Memory systems, data invalidation methods, and recording media that perform them

Abstract

The present invention relates to a memory system comprising: a host; and a flash memory that communicates with the host via a PCIe (Peripheral Component Interconnect Express) interface to store data, and includes a mapping table provided by mapping a physical page number, which is a physical address where the data is stored, to a virtual address managed by the host. The host transmits a data invalidation command, which is provided in advance for deleting data stored in the flash memory, to the flash memory depending on whether the invalidation condition is satisfied. Through this, the host and the memory device share page invalidation information to efficiently select the deletion target, and the amount of data that must be moved to a new page before the block is deleted is reduced, thereby reducing the amount of writing and improving the durability and performance of the flash memory.

Description

Technology Field

[0001] The present invention relates to a memory system for solving the problem of write amplification that may occur in a flash memory, a data invalidation method, and a recording medium for performing the same. Background Technology

[0002] Recently, CXL (Compute Express Link) interconnect technology, which connects memory in an expandable form to efficiently handle the high memory usage of ultra-large AI models, has been gaining attention.

[0003] CLX interconnect technology is a technology that enables memory devices attached to the PCIe (Peripheral Component Interconnect Express) bus to execute memory access instructions from the CPU (Central Processing Unit) through the CXL protocol.

[0004] Here, unlike CIMM slots, PCIe offers the advantage of high scalability, allowing multiple memory devices to be connected and enabling the implementation of high-capacity memory. Additionally, as long as the CXL protocol is supported, the type of internal physical memory can be configured independently, making it possible to use high-capacity memory semiconductors such as NAND Flash.

[0005] However, since these NAND flashes do not allow overwriting, to update data after it has been written, an erase operation must be performed on the corresponding area before rewriting it.

[0006] At this time, write operations are performed in page units (e.g., 4KB to 16KB), but delete operations are performed in block units (e.g., consisting of 128 pages). Therefore, valid data remaining in the block targeted for deletion is copied to a new block before the deletion operation is performed, and this is called garbage collection (hereinafter GC).

[0007] During this GC process, write amplification can occur, leading to problems that degrade performance and durability; the efficiency of GC is determined by the number of valid pages that must be copied within the blocks to be deleted. In other words, the more pages that are copied, the more severe the write amplification becomes.

[0008] Therefore, within the CXL memory device, it is very important to determine the validity of the data currently written to the flash.

[0009] However, since current computing systems primarily use DRAM, which has no durability constraints, as main memory, there is a problem in that there is no mechanism to share validity information of data in memory with lower-level memory devices.

[0010] In other words, CXL-Flash recognizes data that has been effectively deleted or expired in the upper layers as valid data, so it copies it when performing GC operations.

[0011] Since this can lead to severe write amplification, a mechanism is required to share data validity information between the CPU and CXL-Flash. Prior art literature

[0012] Korean Patent Publication No. 10-2012-0039166 The problem to be solved

[0013] The present invention has been devised to solve the above-mentioned problems. The objective of the present invention is to provide a memory system, a data invalidation method, and a recording medium for performing the same, which can improve the durability and performance of a flash memory by allowing a host and a memory device to share page invalidation information to efficiently select deletion targets, as well as by reducing the amount of data that must be moved to a new page before a block is deleted, thereby reducing the amount of writing. means of solving the problem

[0014] A memory system according to one embodiment of the present invention for achieving the above objective comprises: a host including a CPU (Central Processing Unit), a user program and a kernel operating on the CPU; and a flash memory including a mapping table provided by communicating with the host through a PCIe (Peripheral Component Interconnect Express) interface to store data and mapping a physical page number, which is a physical address where the data is stored, to a virtual address managed by the host, wherein the host transmits a data invalidation command, which is provided in advance for deleting data stored in the flash memory, to the flash memory depending on whether the invalidation condition is satisfied.

[0015] And the kernel above manages the memory space corresponding to the physical page number as a virtual page, provides the virtual address to which a logical page number is assigned to each page, and manages unused pages, such as free pages, by including them in a free list.

[0016] Additionally, the data invalidation command may include a command code for deleting the data, the logical page number corresponding to the starting point of the invalidation area, and the length.

[0017] And the above invalidation condition may be when a preset period is reached or when the above free page is added to the above free list.

[0018] In addition, the flash memory may further include a flash manager that interprets the received data invalidation command and changes the state of the physical page corresponding to the invalidation area to an invalid state.

[0019] And the above invalidation condition may be a case where data included in the memory space allocated by the kernel to the user program is deleted or changed, making the memory space unnecessary.

[0020] In addition, when the above invalidation condition is satisfied, the user program may directly insert the data invalidation instruction into the code or call the invalidation instruction by extending the compiler.

[0021] And the above host can interpret the called data invalidation command through the CPU and transmit the interpreted data invalidation command to the flash memory.

[0022] In addition, upon receiving the interpreted data invalidation command, the flash memory can identify the data invalidation area and change the state of the physical page corresponding to the invalidation area to an invalid state.

[0023] Meanwhile, a data invalidation method according to an embodiment of the present invention for achieving the above objective includes: a step in which a flash memory communicates with a host through a PCIe (Peripheral Component Interconnect Express) interface; a step in which the flash memory prepares a mapping table by mapping a physical page number, which is a physical address where data is stored, to a virtual address of the host; a step in which the host determines whether an invalidation condition for deleting the data is satisfied; and a step in which, if the invalidation condition is satisfied, the host transmits a data invalidation command to the flash memory.

[0024] And after the above communication step, the host further includes a step of managing memory space corresponding to the physical page number as a virtual page, and in the managing step, a virtual address is provided with a logical page number assigned to each page, and unused pages, such as free pages, can be managed by including them in a free list.

[0025] Additionally, the data invalidation command may include a command code for deleting the data, the logical page number corresponding to the starting point of the invalidation area, and the length.

[0026] And the above invalidation condition may be when a preset period is reached or when the above free page is added to the above free list.

[0027] In addition, the flash memory may further include a step of interpreting the received data invalidation command and changing the state of the physical page corresponding to the invalidation area to an invalid state.

[0028] And the above invalidation condition may be a case where data included in the memory space allocated by the kernel of the host to the user program of the host is deleted or changed, so that the memory space becomes unnecessary.

[0029] In addition, in the step of transmitting the invalidation command, the host may directly insert the data invalidation command into the code or extend the compiler to call the invalidation command.

[0030] And in the step of transmitting the above-mentioned invalidation command, the called data invalidation command can be interpreted through the CPU provided in the host, and the interpreted data invalidation command can be transmitted to the flash memory.

[0031] In addition, the method may further include the step of identifying the invalidation area of ​​the data according to the interpreted data invalidation command received by the flash memory, and changing the state of the physical page corresponding to the invalidation area to an invalid state.

[0032] Meanwhile, a recording medium according to one embodiment of the present invention for achieving the above objective is a computer-readable recording medium on which a computer program for performing the data invalidation method is recorded. Effects of the invention

[0033] According to one aspect of the present invention described above, by providing a memory system, a data invalidation method, and a recording medium for performing the same, the host and the memory device can share page invalidation information to efficiently select a deletion target, and furthermore, the amount of data that must be moved to a new page before a block is deleted is reduced, thereby reducing the amount of writing and improving the durability and performance of the flash memory. Brief explanation of the drawing

[0034] FIG. 1 is a block diagram for explaining the configuration of a memory system according to an embodiment of the present invention, FIG. 2 is a diagram illustrating communication between a host and a flash memory of a memory system according to an embodiment of the present invention. FIG. 3 is a diagram for specifically explaining the process of sharing data validity information in a memory system according to an embodiment of the present invention, and, FIG. 4 is a flowchart illustrating a data invalidation method according to an embodiment of the present invention. Specific details for implementing the invention

[0035] The following detailed description of the invention refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that various embodiments of the invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in relation to one embodiment. It should also be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the following detailed description is not intended to be limiting, and the scope of the invention is limited only by the appended claims, including all equivalents to those claimed therein, provided appropriately described. Similar reference numerals in the drawings refer to the same or similar functions across various aspects.

[0036] The components according to the present invention are defined by functional distinction rather than physical distinction, and can be defined by the functions each performs. Each component may be implemented as hardware or as program code and processing units that perform each function, and the functions of two or more components may be included and implemented in a single component. Therefore, it should be noted that the names assigned to the components in the following embodiments are not intended to physically distinguish each component but are assigned to imply the representative function performed by each component, and that the technical concept of the present invention is not limited by the names of the components.

[0037] Preferred embodiments of the present invention will be described in more detail below with reference to the drawings.

[0038] FIG. 1 is a block diagram for explaining the configuration of a memory system (10) according to one embodiment of the present invention.

[0039] The memory system (10, hereinafter the system) according to the present embodiment is a space that is not actually used by the upper software layer, but is determined to be in use by the lower memory device, and is provided to prevent writes from being amplified during GC execution.

[0040] To this end, a memory system (10) according to one embodiment of the present invention includes a host (100) and a flash memory (200), and software (application) for performing a data invalidation method may be installed and executed on the system (10). In addition, the host (100) and the flash memory (200) may be controlled by software (application) for performing a data invalidation method.

[0041] A host (100) according to the present embodiment communicates with a flash memory (200) and can transmit a data invalidation command to the flash memory (200) for deleting data stored in the flash memory (200).

[0042] The flash memory (200) is provided to communicate with the host (100) and to store data.

[0043] And the flash memory (200) can change the state of the physical page number, which is the physical address where data is stored, to an invalid state based on the data invalidation command received from the host (100).

[0044] FIG. 2 is a diagram for explaining communication between a host (100) and a flash memory (200) of a memory system (10) according to an embodiment of the present invention, and FIG. 3 is a diagram for specifically explaining the process of sharing data validity information in a memory system (10) according to an embodiment of the present invention.

[0045] The host (100) can be connected to the flash memory (200) through the Root Complex.

[0046] And the host (100) can transmit a data invalidation command (C), which is prepared in advance for deleting data stored in the flash memory (200), to the flash memory (200) depending on whether the invalidation condition is satisfied.

[0047] Such a host (100) may include a CPU (110), a kernel (130), and a user program (150).

[0048] The CPU (110) can be a hardware device.

[0049] The kernel (130) and user program (150) can operate on the CPU (110).

[0050] The kernel (130) manages the memory space provided by the lower layer flash memory (200) by abstracting it into an array of logical pages and can assign a Logical Page Number (LPN) to each page.

[0051] In other words, the kernel (130) can manage a memory space corresponding to a physical page number, which is a physical address of the flash memory (200) where data is stored, as a virtual page.

[0052] And the kernel (130) can provide a virtual address with a logical page number assigned to each page.

[0053] Additionally, the kernel (130) can manage unused pages, such as free pages, by including them in a free list (FL).

[0054] Here, the size of the page may be, for example, 4KB, and such pages may be allocated and used when needed at the request of a user program (150) or within the kernel (130).

[0055] And the kernel (130) can reclaim space that is no longer needed, i.e., free pages, if data has been deleted or the program has terminated execution, and add it to the free list (FL).

[0056] Meanwhile, the user program (150) can be allocated as much memory space as is needed from the kernel (130).

[0057] Meanwhile, the flash memory (200) can store actual data by communicating with the host (100) through a PCIe (Peripheral Component Interconnect Express) interface.

[0058] And the flash memory (200) may include a mapping table (210), a flash manager (CXL-Flash Manager) (230), a controller (250), and an internal buffer (DRAM) (270).

[0059] The mapping table (210) according to the present embodiment can be provided by mapping a physical page number, which is a physical address where data is stored, to a virtual address managed by the host (100).

[0060] This mapping table (210) is provided to match the logical page number (LPN) with the physical page number due to the characteristics of the flash memory (200) which does not allow overwriting.

[0061] The flash manager (230) may be software responsible for the overall management of the flash memory (200).

[0062] A controller (250) may be provided to run the flash manager (230).

[0063] Meanwhile, the internal buffer (270) can be used for transmitting and receiving data, caching, buffering, and storing the mapping table (210).

[0064] Below, with reference to FIG. 3, we will specifically describe the process in which the host (100) determines whether the invalidation condition is satisfied and transmits a data invalidation command to the flash memory (200), and the flash memory (200) changes the state of the physical page to an invalid state.

[0065] First, the data invalidation command (C) transmitted by the host (100) to the flash memory (200) may include a command code for deleting data (e.g., INV), a logical page number (LPN) corresponding to the start point of the invalidation area, and a length (N), as shown in FIG. 3.

[0066] And the invalidation condition determined by the host (100) can be one of two.

[0067] First, the first invalidation condition may be when a preset period is reached or when the kernel (130) adds a free page to the free list (FL).

[0068] When this first invalidation condition is satisfied, a data invalidation command (C), such as ① INV(LPN, N) of FIG. 3, can be transmitted asynchronously from the kernel layer (130) of the host (100) to the flash memory (200).

[0069] Specifically, when the kernel (130) reaches a preset period or when a free page is added to the free list (FL), it can send an invalidation command (C) for the added free page to the flash memory (200), which is a lower device.

[0070] These invalidation commands (C) can be implemented through PCIe interface extensions, and the kernel (130) can configure the invalidation commands (C) and transmit them to the flash memory (200) through the PCIe interface.

[0071] And the flash memory (200) can interpret the received data invalidation command (C). That is, the flash memory (200) can interpret the data invalidation command (C) to identify the invalidated area, which is a series of areas corresponding to length (N) starting from the logical page number (LPN), which is the starting logical page address.

[0072] Afterwards, the flash memory (200) can change the state of the physical page mapped to the invalidation area to an invalid state through the flash manager (230).

[0073] The status information of the flash memory (200) can be indicated by maintaining an invalid bit in the Out Of Band (OOB) area, which is reserved for storing additional information for each page.

[0074] Therefore, the data invalidation command transmitted from the host (100) is interpreted by the flash manager (230), and the invalidation bit of the page corresponding to the invalidation area can be set to 1.

[0075] And the invalid bits of the set page are referenced when performing GC operations inside the flash memory (200).

[0076] Accordingly, the flash memory (200) can improve write volume and performance by not copying pages with invalid bits set to new pages, but by deleting them.

[0077] Meanwhile, the second invalidation condition may be when data contained within the memory space allocated to the user program (150) by the kernel (130) is deleted or changed, making the memory space unnecessary.

[0078] As described above, the user program (150) is structured to allocate and use physical memory from the kernel (130) layer and return it when it is not needed.

[0079] These memory allocation and deallocation processes are operations that require context switching between the user program (150) and the kernel (130) layer, and can cause performance degradation.

[0080] Accordingly, some user programs (150) often pre-allocate sufficient memory and use it in the form of a memory pool, but the kernel (130) does not recognize whether the user program (150) actually uses the memory space. Therefore, there may be a difference between the free pages recognized by the kernel (130) and the pages that are not used by the actual user program (150) (actually invalid pages).

[0081] In other words, the space allocated to the user program (150) may also be an empty page that is not actually used.

[0082] Accordingly, the system (10) according to the present embodiment can send a physical memory invalidation command (C) directly to the flash memory (200) when necessary to reduce this difference.

[0083] That is, when the system (10) according to the present embodiment satisfies the second invalidation condition above, the user program (150) of the host (100) can synchronously transmit a data invalidation command (C), such as ② INV(LPN, N) of FIG. 3, to the flash memory (200).

[0084] This can be implemented by extending the Instruction Set Architecture (ISA) of the CPU (110) to add an Invalid Instruction. Thus, it can be converted into a CXL protocol message by the CPU (110) that supports the CXL protocol and delivered to the flash memory (200).

[0085] Therefore, when the user program (150) reaches a point where memory data in a specific area is deleted or changed due to data deletion, etc., and is no longer needed, that is, when the second invalidation condition is satisfied, the user program (150) can directly insert the data invalidation instruction (C) into the code or call the data invalidation instruction by extending the compiler.

[0086] When a user program (150) directly inserts a data invalidation command (C) or calls a data invalidation command, the host (100) can interpret the data invalidation command (C) called through the CPU (110).

[0087] And the host (100) can transmit the interpreted data invalidation command (C) to the flash memory (200).

[0088] The interpreted data invalidation instruction (C) can also be composed of an instruction code (INV), a logical page number (LPN) corresponding to the start point of the invalidation area, and a length (N).

[0089] Meanwhile, when the flash memory (200) receives an interpreted data invalidation command (C), it can set the invalidation bit of the page corresponding to the invalidation area to 1, just as in the case of the first invalidation condition.

[0090] Accordingly, the system (10) according to the present embodiment can share information about invalidated data, which is data that has been deleted or expired from the host, with the flash memory (200).

[0091] Through this, the system (10) can efficiently perform deletion target selection by having the host (100) and the flash memory (200) share invalid page information, and also improve the durability and performance of the flash memory (200) by reducing the amount of data that needs to be moved to a new page before the block is deleted, thereby reducing the amount of writing.

[0092] In addition, the system (10) according to the present embodiment can reduce severe write amplification phenomena during the process of performing GC operations.

[0094] FIG. 4 is a flowchart for explaining a data invalidation method according to an embodiment of the present invention. Since the data invalidation method according to an embodiment of the present invention is carried out on a configuration substantially identical to that of the memory system (10) shown in FIG. 3, the same reference numerals are assigned to the same components as those of the memory system (10) in FIG. 3, and repetitive descriptions are omitted.

[0095] The data invalidation method according to the present embodiment includes the steps of: communicating between a flash memory (200) and a host (100) (S110); the flash memory (200) preparing a mapping table (S130); the host (100) determining whether an invalidation condition is satisfied (S150); and the host (100) transmitting a data invalidation command (S170).

[0096] In the communication step (S110), the flash memory (200) can communicate with the host (100) through a PCIe (Peripheral Component Interconnect Express) interface.

[0097] And the data invalidation method according to the present embodiment may further include the step of the host (100) managing a memory space corresponding to a physical page number as a virtual page after the communication step (S110).

[0098] In this management step, the host (100) may provide the virtual address to which a logical page number is assigned to each page, and manage unused pages, such as free pages, by including them in a free list (FL).

[0099] Meanwhile, in the step of preparing a mapping table (S130), a mapping table (210) can be prepared by mapping a physical page number, which is a physical address where data is stored in the flash memory (200), to a virtual address of the host (100).

[0100] In the step (S150) of determining whether the invalidation condition is satisfied, the host (100) can determine whether the invalidation condition for deleting data is satisfied.

[0101] Here, the invalidation condition can be one of two.

[0102] First, the first invalidation condition may be when a preset period is reached or when a free page is added to the free list (FL).

[0103] The second invalidation condition may be a case where data included in the memory space allocated by the kernel (130) to the user program (150) provided in the host (100) is deleted or changed, making the memory space unnecessary.

[0104] Meanwhile, in the step of transmitting a data invalidation command (S170), if the invalidation condition is satisfied, the host (100) can transmit a data invalidation command (C) to the flash memory (200).

[0105] The data invalidation command (C) according to the present embodiment may include a command code (INV) for deleting data, a logical page number (LPN) corresponding to the start point of the invalidation area, and a length (N).

[0106] And in the step of transmitting the data invalidation command (S170), if the second invalidation condition among the aforementioned invalidation conditions is satisfied, the host (100) can directly insert the data invalidation command (C) into the code or call the invalidation command by extending the compiler.

[0107] In addition, in the step (S170) of transmitting a data invalidation command, the data invalidation command called through the CPU (110) provided in the host (100) can be interpreted, and the interpreted data invalidation command (C) can be transmitted to the flash memory (200).

[0108] And the data invalidation method according to the present embodiment may further include the step of interpreting the data invalidation command (C) received by the flash memory (200) and changing the state of the physical page corresponding to the invalidation area to an invalid state when the first invalidation condition among the above-described invalidation conditions is satisfied.

[0109] In addition, the data invalidation method according to the present embodiment may further include the step of, when the second invalidation condition among the aforementioned invalidation conditions is satisfied, checking the data invalidation area according to the interpreted data invalidation command received by the flash memory (200) and changing the state of the physical page corresponding to the invalidation area to an invalid state.

[0110] The data invalidation method of the present invention as described above may be implemented in the form of program instructions that can be executed through various computer components and recorded on a computer-readable recording medium. The computer-readable recording medium may include program instructions, data files, data structures, etc., either individually or in combination.

[0111] The program instructions recorded on the above-mentioned computer-readable recording medium may be those specifically designed and configured for the present invention, or they may be those known and available to those skilled in the art of computer software.

[0112] Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, and flash memory.

[0113] Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc. The hardware device may be configured to operate as one or more software modules to perform processing according to the present invention, and vice versa.

[0114] Although various embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above. It is understood that various modifications can be made by those skilled in the art without departing from the essence of the invention as claimed in the claims, and such modifications should not be understood individually from the technical spirit or perspective of the present invention. Explanation of the symbols

[0115] 10 : Memory System 100 : Host 110 : CPU 130 : Kernel 150 : User Program 200 : Flash Memory 210 : Mapping Table 230 : Flash Manager 250: Controller 270: Internal buffer C: Data invalidation instruction LPN: Logical page number FL : Free List

Claims

Claim 1 A host comprising a CPU (Central Processing Unit), a user program operating on the CPU, and a kernel; A memory system comprising a flash memory that stores data by communicating with the host via a PCIe (Peripheral Component Interconnect Express) interface, and includes a mapping table provided by mapping a physical page number, which is a physical address where the data is stored, to a virtual address managed by the host; wherein the host transmits a data invalidation command, which is provided in advance for deleting data stored in the flash memory, to the flash memory depending on whether an invalidation condition is satisfied; wherein the kernel manages a memory space corresponding to the physical page number as a virtual page, provides the virtual address in which a logical page number is assigned to each page, and manages unused pages, such as free pages, by including them in a free list; wherein the data invalidation command includes a command code for deleting the data, the logical page number corresponding to the starting point of the invalidation area, and a length; and wherein the invalidation condition includes an invalidation condition in which a preset period is reached or the free page is added to the free list. Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 A memory system according to claim 1, wherein the flash memory further comprises a flash manager that interprets the received data invalidation command and changes the state of the physical page corresponding to the invalidation area to an invalid state. Claim 6 A memory system according to claim 1, wherein the invalidation condition further includes an invalidation condition in which data contained within the memory space allocated by the user program from the kernel is deleted or changed, thereby making the memory space unnecessary. Claim 7 A memory system according to claim 6, wherein when the invalidation condition in which the memory space becomes unnecessary is satisfied, the user program directly inserts the data invalidation instruction into the code or extends the compiler to call the invalidation instruction. Claim 8 In claim 7, the memory system wherein the host interprets the called data invalidation command through the CPU and transmits the interpreted data invalidation command to the flash memory. Claim 9 A memory system according to claim 8, wherein upon receiving the interpreted data invalidation command, the flash memory identifies the data invalidation area and changes the state of the physical page corresponding to the invalidation area to an invalid state. Claim 10 A method for invalidating data, comprising: a step in which a flash memory communicates with a host via a PCIe (Peripheral Component Interconnect Express) interface; a step in which the flash memory prepares a mapping table by mapping a physical page number, which is a physical address where data is stored, to a virtual address of the host; a step in which the host determines whether an invalidation condition for deleting the data is satisfied; and a step in which, if the invalidation condition is satisfied, the host transmits a data invalidation command to the flash memory; and further comprising, after the communication step, a step in which the host manages a memory space corresponding to the physical page number as a virtual page, wherein in the managing step, the virtual address is prepared by assigning a logical page number to each page, and unused pages, which are free pages, are managed by including them in a free list; wherein the data invalidation command includes a command code for deleting the data, the logical page number corresponding to the starting point of the invalidation area, and a length; and wherein the invalidation condition includes an invalidation condition in which a preset period is reached or the free page is added to the free list. Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 A data invalidation method according to claim 10, wherein the flash memory further comprises the step of interpreting the received data invalidation command and changing the state of the physical page corresponding to the invalidation area to an invalid state. Claim 15 A data invalidation method according to claim 10, wherein the invalidation condition further includes an invalidation condition in which data contained within the memory space allocated by a user program provided in the host from a kernel provided in the host is deleted or changed, thereby making the memory space unnecessary. Claim 16 A data invalidation method according to claim 15, wherein in the step of transmitting an invalidation command, when the invalidation condition in which the memory space becomes unnecessary is satisfied, the host directly inserts the data invalidation command into the code or extends the compiler to call the invalidation command. Claim 17 A data invalidation method according to claim 16, wherein in the step of transmitting the invalidation command, the called data invalidation command is interpreted through a CPU provided in the host, and the interpreted data invalidation command is transmitted to the flash memory. Claim 18 A data invalidation method according to claim 17, further comprising the step of identifying the data invalidation area according to the interpreted data invalidation command received by the flash memory and changing the state of the physical page corresponding to the invalidation area to an invalid state. Claim 19 A computer-readable recording medium having a computer program for performing the above-mentioned data invalidation method according to paragraph 10.

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