A joining structure having an interconnection structure

Abstract

A bonding structure is disclosed. The bonding structure may include an interconnection structure. The bonding structure may also include a first die directly bonded to the interconnection structure. The bonding structure may also include a second die mounted on the interconnection structure. The second die is laterally spaced from the first die along the upper surface of the interconnection structure. The second die is electrically connected to the first die at least partially through the interconnection structure. The bonding structure may further include a dielectric layer disposed over the upper surface of the interconnection structure between the first die and the second die.

Description

Technology Field

[0001] This application claims priority to U.S. provisional patent application No. 63 / 074,928 ('joint structure having interconnected structure'), filed on September 4, 2020, the entire contents of which are incorporated herein by reference.

[0002] This field generally relates to bonded structures, and specifically, to bonded structures having an interconnect structure. Background Technology

[0003] The bonding structure may include electronic components mounted on a carrier or substrate. The bonding structure may include a molding material placed over the electronic components to provide additional mechanical support and / or protection for the bonding structure. During the manufacture (and / or operation) of the bonding structure, heat may be applied to the bonding structure. Applying heat (e.g., an annealing process) may apply stress to the electronic components. The problem to be solved

[0004] Therefore, there is a continuous demand for improved structures and methods for manufacturing bonded structures. Brief explanation of the drawing

[0005] A specific implementation will now be described with reference to the following drawings, which are provided as examples and are not limited thereto. Figure 1a illustrates the step of forming a bonded structure. Figure 1b illustrates another step of forming a bonded structure. Fig. 1c illustrates another step of forming a bonded structure. FIG. 1d is a schematic side cross-sectional view of a bonded structure according to an embodiment. FIG. 1e is a flowchart illustrating the steps of forming a bonded structure according to an embodiment. FIG. 2 is a schematic side cross-sectional view of a bonded structure according to another embodiment. FIG. 3 is a schematic side cross-sectional view of a bonded structure according to another embodiment. FIG. 4 is a schematic diagram of a system comprising one or more microelectronic assemblies according to various embodiments. Specific details for implementing the invention

[0006] FIGS. 1a through 1d illustrate a manufacturing process for forming a bonded structure (1) according to various embodiments. The resulting bonded structure (1) (see FIG. 1d) may include electronic components (e.g., integrated element dies) mounted on an interconnected structure (10). For example, a first integrated element die (12) and a second integrated element die (14) may be mounted on the interconnected structure (10). The interconnected structure (10) (e.g., a redistribution layer (RDL)) may route input / output (IO) pads of the electrical components (first integrated element die (12) and / or second integrated element die (14)) to other locations on the bonded structure (1). For example, in some embodiments, the interconnect structure (10) may include a fan-out structure in which a signal from a relatively fine pitch contact pad of an electrical component is routed to a pad outside the footprint of the component. In some applications, the interconnect structure (10) may allow electrical communication between two or more dies (e.g., a first integrated element die (12) and a second integrated element die (14)) mounted on the interconnect structure (10). A molding material (16) or sealing material may be provided between two or more dies (the first integrated element die (12) and the second integrated element die (14)) for mechanical support and / or protection. During the manufacture (and / or operation) of the bonding structure (1), the material may be heated, which may cause reliability issues and / or defects due to a mismatch in the coefficient of thermal expansion. For example, during the manufacture (and / or operation) of the bonding structure (1), heating of the bonding structure may apply stress near the interface (e.g., edge) between the integrated element die (first integrated element die (12) or second integrated element die (14)), the interconnect structure (10), and the molding material (16).In some embodiments, the width of the molding material is less than about 20% of the width of the first integrated die (12) or the second integrated die (14), and preferably less than about 10% of the width of the die. For example, the width of the molding material is 3% to 20%, 5% to 20%, 3% to 10%, or 5% to 10% of the width of the first integrated die (12) or the second integrated die (14).

[0007] Various embodiments disclosed herein relate to a bonding structure having enhanced reliability when heated, for example, during manufacturing and / or bonding. The bonding structure may comprise an interconnection structure (e.g., RDL), a first die bonded to the interconnection structure, a second die bonded to the interconnection structure, and a low coefficient of thermal expansion (CTE) layer disposed between the first die and the second die. The bonding structure may also comprise a molding material disposed between the first die and the second die. The first die and / or the second die may be directly bonded to the interconnection structure without an intermediate adhesive.

[0008] Two or more semiconductor elements (e.g., integrated device dies, wafers, etc.) may be stacked or bonded together to form a bond structure. A conductive contact pad of one element may be electrically connected to a corresponding conductive contact pad of another element. Any appropriate number of elements may be stacked on the bond structure.

[0009] In some embodiments, elements (e.g., a first integrated device die (12) and an interconnect structure (10)) are directly bonded to each other without adhesive. In various embodiments, a dielectric field region (e.g., a non-conductive material (32)) (also referred to as a non-conductive bonding region) of a first element (e.g., a first semiconductor device die having an active circuit or a first integrated device die (12)) may be directly bonded to a corresponding dielectric field region (e.g., a non-conductive material (20)) of a second element (e.g., a second semiconductor device die having an active circuit or an interconnect structure (10)) without adhesive (e.g., using dielectric-to-dielectric bonding techniques). For example, dielectric-to-dielectric bonding may be formed without adhesive using direct bonding techniques disclosed in at least U.S. Patents No. 9,564,414; No. 9,391,143; and No. 10,434,749, the entire contents of each of which are incorporated herein by reference and for all purposes.

[0010] In various embodiments, the hybrid direct bond can be formed without an intermediate adhesive. For example, the dielectric bond surface can be polished to a very smooth finish. The bond surface can be cleaned and exposed to plasma and / or an etchant to activate the surface. In some embodiments, the surface can be terminated by species after or during activation (e.g., during the plasma and / or etching process). Without being limited by theory, in some embodiments, the activation process may be performed to break chemical bonds at the bond surface, and the termination process may provide additional chemical species at the bond surface to enhance bond energy during direct bonding. In some embodiments, activation and termination are performed in the same step, for example, with a plasma or wet etchant to activate and terminate the surface. In other embodiments, the bond surface may be terminated by a separate treatment to provide additional species for direct bonding. In various embodiments, the termination species may include nitrogen. Additionally, in some embodiments, the bond surface may be exposed to fluorine. For example, there may be one or more fluorine peaks near the layer and / or bonding interface. Thus, in a directly bonded structure, the bonding interface between two dielectric materials may include a very smooth interface having a higher nitrogen content and / or fluorine peak at the bonding interface. Additional examples of activation and / or termination treatments can be found in U.S. Patents No. 9,564,414; No. 9,391,143; and No. 10,434,749, the full contents of each of which are incorporated herein by reference and for all purposes.

[0011] In various embodiments, the conductive contact pad of the first element may be directly bonded to the corresponding conductive contact pad of the second element. For example, hybrid bonding techniques may be used to provide direct bonding between conductors along a bonding interface comprising a covalently directly bonded dielectric inter-surface prepared as described above. In various embodiments, the direct bonding between conductors (e.g., between contact pads) and the total hybrid bonding between dielectrics may be formed using direct bonding techniques disclosed in at least U.S. Patents No. 9,716,033 and No. 9,852,988, the full contents of each of which are incorporated herein by reference and for all purposes.

[0012] For example, dielectric junction interfaces may be prepared and can be directly bonded to each other without an intermediate adhesive as described above. Conductive contact pads (which may be surrounded by a non-conductive dielectric field region) can also be directly bonded to each other without an intermediate adhesive. In some embodiments, each contact pad may be recessed below the outer (e.g., upper) surface of the dielectric field or non-conductive junction region, for example, to less than 20 nm, less than 15 nm, or less than 10 nm, or to a range of, for example, 2 nm to 20 nm, or 4 nm to 10 nm. In some embodiments, the non-conductive junction regions may be directly bonded to each other without an adhesive at room temperature, and the bonded structure may then be annealed. Upon annealing, the contact pads may expand and come into contact with each other to form a direct metal-to-metal bond. Benefitably, using direct bond interconnects, or DBI® technology, can enable a high density of connected pads across the direct bond interface (e.g., small or fine pitch of a general array). In some embodiments, the pitch of the bond pads may be less than 40 microns, less than 10 microns, or even less than 2 microns. For some applications, the ratio of the pitch of the bond pads to one of the dimensions of the bond pads is less than 5, or less than 3, and sometimes preferably less than 2. In various embodiments, the contact pads may comprise copper, but other metals may also be suitable.

[0013] Accordingly, in a direct bonding process, the first element can be directly bonded to the second element without an intermediate adhesive. In some arrangements, the first element may include an individualized element, such as a unified integrated device die. In other arrangements, the first element may include a carrier or substrate (e.g., a wafer) comprising a plurality (e.g., tens, hundreds, or more) of device regions that form a plurality of integrated device dies when individualized. Similarly, the second element may include an individualized element, such as a unified direct device die. In other arrangements, the second element may include a carrier or substrate (e.g., a wafer).

[0014] As described herein, the first and second elements can be directly bonded to each other without an adhesive, which differs from a deposition process. Thus, the first and second elements may include undeposited elements. Additionally, the directly bonded structure may include defect regions along the bonding interface where nanopores exist, unlike the deposited layer. Nanopores may be formed due to the activation of the bonding surface (e.g., exposure to plasma). As described above, the bonding interface may include a concentration of material from the activation and / or final chemical treatment process. For example, in an embodiment utilizing nitrogen plasma for activation, a nitrogen peak may be formed at the bonding interface. In an embodiment utilizing oxygen plasma for activation, an oxygen peak may be formed at the bonding interface. In some embodiments, the bonding interface may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. The bonding layer may also include a polished surface flattened to a high degree of smoothness.

[0015] In various embodiments, the intermetallic bond between the contact pads may be bonded so that copper particles grow together across the bonding interface. In some embodiments, the copper may have grains oriented along the 111 crystal plane for improved copper diffusion across the bonding interface. The bonding interface may extend substantially completely to at least a portion of the bonded contact pad so that there is substantially no gap between the bonded contact pad or a non-conductive bonding region nearby. In some embodiments, a barrier layer may be provided beneath the contact pad (e.g., may contain copper). However, in other embodiments, as described, for example, in U.S. Application No. 2019 / 0096741, there may be no barrier layer beneath the contact pad, the entirety of which is incorporated herein by reference and for all purposes.

[0016] FIG. 1a illustrates the step of forming a junction structure (1). In FIG. 1a, an interconnect structure (10) is formed on a carrier (11). The carrier (11) may include a wafer in various embodiments. The step in FIG. 1a illustrates a first integrated device die (12) and a second integrated device die (14) before being mounted on the interconnect structure (10). The dies (12, 14) may include any suitable type of device die, such as a processor die, a memory die, a sensor die, etc. A dielectric field region (e.g., a non-conductive material (32)) may be provided on a bulk semiconductor region (e.g., silicon) of the dies (12, 14).

[0017] FIG. 1b illustrates another step of forming a bonded structure (1). A first integrated element die (12) and a second integrated element die (14) are mounted on an interconnect structure (10) (e.g., directly bonded without an intermediate adhesive). Also in FIG. 1b, a dielectric layer (18) with a low coefficient of thermal expansion (CTE) is provided. As illustrated, the dielectric layer (18) may be deposited on the upper surface of the dies (12, 14) and on the interconnect structure (10) in the space between the dies (12, 14). In some embodiments, the dielectric layer (18) may include a conformal coating. In some embodiments, the CTE of the dielectric layer (18) may be less than 10 ppm / °C and less than 6 ppm / °C, preferably less than 2 ppm / °C. For example, the CTE of the dielectric layer (18) may be in the range of 1 ppm / °C to 10 ppm / °C, in the range of 2 ppm / °C to 6 ppm / °C, or within the range of 1 ppm / °C to 2 ppm / °C. The dielectric layer (18) may include multiple dielectric layers. Each dielectric layer of the multiple dielectric layers may have a different CTE. In some embodiments, the thickness of the dielectric layer (18) may be thinner than the thickness of the integrated device die (12, 14). For example, the thickness of the dielectric layer (18) may be less than 50% of the thickness of the integrated device die (12, 14), or the thickness of the dielectric layer (18) may be less than 20% of the thickness of the die (12, 14).

[0018] FIG. 1c illustrates another step of forming a bonded structure (1). In the step of FIG. 1c, a molding material (16) is provided over a dielectric layer (18), including a location on the dies (12, 14) and a space between the dies (12, 14). The structure (1) illustrated in FIG. 1c may comprise a reconstructed wafer comprising a plurality of dies (12, 14) mounted on a carrier (11) and at least partially encapsulated by the molding material (16). At least a portion of the CTE dielectric layer (18) over the first integrated element die (12) and / or the second integrated element die may be removed or thinned (e.g., etched or ground). At least a portion of the molding material (16) over the first integrated element die (12) and / or the second integrated element may be removed or thinned (e.g., etched or ground). The structure illustrated in FIG. 1c may be individualized at a unification line (37) to define a bonded structure (1) as illustrated in FIG. 1d. In some embodiments, the unification line (37) may include a saw street. The side edge of the bonded structure (1) may include features indicating a unification process, such as a saw marking, an etching line, etc.

[0019] In some embodiments, the carrier (11) may remain with the interconnect structure until after the application of the molding material (16). However, in some other processes, the carrier (11) may be removed from the interconnect structure (10) at an appropriate time, for example, before the application of the molding material (16) or before the application of the dielectric layer (18). For example, the carrier may be removed from the interconnect structure after the step shown in FIG. 1a and before the step shown in FIG. 1b, after the step shown in FIG. 1b and before the step shown in FIG. 1c, or after the step shown in FIG. 1c and before the step shown in FIG. 1d. In the illustrated embodiment, the carrier (11) is removed after the step shown in FIG. 1c, for example, after the partial removal of the molding material (16) and the dielectric layer (18). In some embodiments, the carrier (11) may comprise an optically transparent carrier or plate. An optically transparent carrier can be mechanically bonded to the lower surface of an interconnect structure (10), for example, with a UV light-emitting layer (not shown).

[0020] FIG. 1d illustrates a schematic side cross-sectional view of a bonding structure (1) according to an embodiment. In some embodiments, the bonding structure (1) may include individualized reconfiguration elements unified from a reconfigured wafer. The bonding structure may include an interconnecting structure (10), a first integrated element die (12) mounted on the interconnecting structure (10), and a second integrated element die (14) mounted on the interconnecting structure (10). The interconnecting structure (10) may be provided by a transfer process. For example, in some embodiments, the interconnecting structure (10) (e.g., RDL) may be formed on a carrier (such as a semiconductor or glass carrier) and directly bonded to the dies (12, 14). The carrier may be removed from the interconnecting structure (10) to transfer the RDL to the dies (12, 14). Thus, in some embodiments, the interconnecting structure (10) may include a transfer RDL. The first and second dies (12, 14) may be spaced apart from each other along the interconnect structure (10). For example, the first and second dies (12, 14) may be aligned in the design of the interconnect structure. The bonding structure (1) may also include a molding material (16) and a low coefficient of thermal expansion (CTE) dielectric layer (18) disposed between the first die (12) and the second die (14). Although only two dies (12) are shown in FIG. 1, the bonding structure (1) may include three or more dies in other embodiments.

[0021] In some embodiments, the interconnect structure (10) may include a redistribution layer (RDL). In some embodiments, the interconnect structure (10) may serve as an alignment layer by fixing the relative lateral positions of the dies (12, 14) and aligning them relative to each other. The interconnect structure (10) may include a non-conductive material (20), a plurality of conductive lines (22) formed in the non-conductive material (20), and a plurality of conductive vias (23) formed in the non-conductive material (20). In some embodiments, the conductive vias (23) may extend through the thickness of the non-conductive material (20). The non-conductive material (20) may include any suitable material. For example, the non-conductive material (20) may include a dielectric material such as an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), or amorphous silicon. In some embodiments, the interconnect structure (10) may have an upper contact surface (10a) comprising a plurality of conductive pads (e.g., a first conductive pad (24a), a second conductive pad (24b)), and a non-conductive region (26) between at least the first conductive pad (24a) and the second conductive pad (24b).

[0022] The first integrated device die (12) and / or the second integrated device die (14) may include any suitable type of device die. For example, the first integrated device die (12) and / or the second integrated device die (14) may include electronic components such as a processor die, a memory die, a microelectromechanical system (MEMS) die, an optical device, or other suitable type of device die. In some embodiments, the first integrated device die (12) and / or the second integrated device die (14) may include a stack of multiple dies. In other embodiments, the electronic components may include passive components such as capacitors, inductors, or other surface-mounted components. Circuits (such as active components like transistors) may be patterned on or near the active surface(s) of the first integrated device die (12) and / or the second integrated device die (14) in various embodiments. The active surface may be on the side of the first integrated element die (12) and / or the second integrated element die (14) facing the respective rear surface of the first integrated element die (12) and / or the second integrated element die (12). The rear surface may include or may not include any active circuit or passive component. The first integrated element die (12) and the second integrated element die (14) may be the same type of integrated element die or a different type of component die.

[0023] The first die (12) may include a bonding surface (12a) and an upper surface (12b) facing the bonding surface (12a). The bonding surface (12a) may have a conductive bonding pad (30) and a non-conductive material (32) adjacent to the conductive bonding pad (30). In some embodiments, the conductive bonding pad (30) may be bonded to the first conductive pad (24a), and the non-conductive material (32) may be bonded to a portion of the non-conductive region (26). In some embodiments, the conductive bonding pad (30) may be bonded directly to the first conductive pad (24a) without an intermediate adhesive, and the non-conductive material (32) may be bonded directly to a portion of the non-conductive region (26) without an intermediate adhesive. The non-conductive material (32, 36) and the conductive bonding pad (30, 24) may be bonded directly without an adhesive as described below.

[0024] The second die (14) may include a bonding surface (14a) and a rear surface (14b) facing the bonding surface (14a). The bonding surface (14a) may have a conductive bonding pad (34) and a non-conductive material (36) adjacent to the conductive bonding pad (34). In some embodiments, the conductive bonding pad (34) may be bonded to the second conductive pad (24b), and the non-conductive material (36) may be bonded to a portion of the non-conductive region (24). In some embodiments, the conductive bonding pad (34) may be bonded directly to the second conductive pad (24b) without an intermediate adhesive, and the non-conductive material (36) may be bonded directly to a portion of the non-conductive region (26) without an intermediate adhesive.

[0025] In some embodiments, the first integrated element die (12) and / or the second integrated element die (14) may be joined to the interconnection structure (10) such that the active surface(s) of the first integrated element die (12) and / or the second integrated element die (14) face the interconnection structure (10). In some embodiments, the first integrated element die (12) and / or the second integrated element die (14) may be joined to the interconnection structure (10) such that the active surface(s) of the first integrated element die (12) and / or the second integrated element die (14) do not face the interconnection structure (10). In some embodiments, the active surface of one of the first integrated element die (12) and the second integrated element die (14) faces the interconnect structure (10), and the active surface of the other of the first integrated element die (12) and the second integrated element die (14) does not face the interconnect structure (10). In the illustrated embodiment, the dielectric layer (18) and the non-conductive material (32) may be coplanar with the upper surface of the interconnect structure (10). The non-conductive material (32) may extend along the side of the bulk portion of the die (12, 14) and along the side of the non-conductive material (32).

[0026] The molding material (16) may include materials such as polymers, epoxy, and resins. In some embodiments, the molding material (16) provides mechanical support for the first integrated device die (12) and / or the second integrated device die (14). In some embodiments, the molding material (16) may at least partially fill the gap (40) between the first integrated device die (12) and the second integrated device die (14). The CTE of the molding material (16) may be relatively high so that the molding material (16) can expand when heated, which may cause stress on the dies (12, 14) and / or interconnection structure (10).

[0027] The low CTE layer (18) may comprise any suitable material. In some embodiments, the low CTE layer (18) may have a CTE equal to or less than that of the non-conductive material (20) of the interconnect structure (10), the non-conductive material (32) of the first die (12), or the non-conductive material (36) of the second die (14). In some embodiments, the low CTE layer (18) may have a lower CTE than that of the molding material (16). In some embodiments, the low CTE layer (18) may comprise a dielectric layer. For example, the low CTE layer (18) may comprise a silicon oxide layer. The use of the low CTE layer (18) can reduce the overall thermal mismatch between the molding material (16) and the components of the other structure. The layer (18) may comprise a material different from or the same as the conductive material (32). The layer (18) may be a material different from the molding material (16). The low CTE layer (18) can advantageously reduce and / or eliminate stress in the first die (12), interconnect structure (10), and molding material (16) during manufacturing (or operation) compared to a similar bonding structure without the low CTE layer. In some embodiments, the low CTE layer (18) may have a thickness in the range of, for example, 1 µm to 10 µm, for example, 1 µm to 5 µm, for example, 3 µm to 10 µm, for example, 5 µm to 10 µm, or for example, 3 µm to 5 µm.

[0028] In some embodiments, the low CTE layer (18) may be placed along at least a portion of the sidewall (12c) of the first integrated device die (12). In the illustrated embodiment, the layer (18) may be placed only along the sidewall (12c). For example, it may not be placed along the top surface (12b) of the integrated device die (12). In some embodiments, the low CTE layer (18) may not be present on most of the top surface (12b) of the integrated device die (12). In some embodiments, the low CTE layer (18) may be placed along at least a portion of the sidewall (14c) of the second integrated device die (14). In some embodiments, the low CTE layer (18) may be applied to the top surface (12b) and the sidewall (12c) of the die (12), and the low CTE layer (18) may be removed from the top surface (12b), for example, by lapping. In the illustrated embodiments, the layer (18) may be positioned only along the sidewall (14c). For example, it may not be positioned along the upper surface of the die (14). In some embodiments, the low CTE layer (18) may be positioned along at least a portion of the upper contact surface (10a) of the interconnect structure (10). In some embodiments, the low CTE layer (18) may include a conformal layer that matches the surfaces of the first die (12), the second die (14), and the interconnect structure (10). In some embodiments, the low CTE layer (18) may separate the molding material (16) from the surfaces of the first die (12), the second die (14), and the interconnect structure (10). In some embodiments, the low CTE layer (18) completely separates the molding material (16) from the interconnect structure (10) so that no part of the molding material comes into direct contact with the interconnect structure (10). In some embodiments, the low CTE layer (18) may have a CTE in the range of, for example, 3 ppm to 7 ppm, for example, 3 ppm to 5 ppm, for example, 5 ppm to 7 ppm.

[0029] In some embodiments, the low CTE layer (18) can improve the stiffness of the bonded structure (1). In some embodiments, the low CTE layer (18) can provide more reliability during the manufacture (and / or operation) of the bonded structure (1) than a similar bonded structure without the low CTE layer. A similar bonded structure without the low CTE layer may have a high stress zone at the three-point coer or edge between the die, the interconnect structure, and the molding material. In the bonded structure (1), the low CTE layer (18) can reduce the stress applied to the first die (12) or the second die (14) by moving or transitioning the high stress zone from the three-point coer to an area near the coer between the CTE layer (18) and the interconnect structure (10). For example, the low CTE layer (18) can reduce the stress applied to the first and second dies (12, 14) during the manufacture (and / or operation) of the bonded structure.

[0030] The bonding surfaces (e.g., upper contact surface (10a), bonding surface (12a), and bonding surface (14a)) may be polished or flattened, activated, and terminated into a suitable species. For example, in various embodiments, one or more of the non-conductive region (26), the non-conductive material (32) of the bonding surface (12a), and the conductive bonding pad (34) of the bonding surface (14a) (e.g., non-conductive material) may comprise an inorganic dielectric material, e.g., silicon oxide. The bonding surfaces may be polished to a root-mean-square (rms) surface roughness of less than 2 nm, e.g., less than 1 nm, less than 0.5 nm, etc. The polished bonding surfaces may be activated by a process including, for example, an atmospheric or vacuum plasma method. In various embodiments, the bonding surface may be terminated with nitrogen by, for example, wet or dry etching using a nitrogen-containing solution (e.g., very slight etching (VSE)) or by using nitrogen-based plasma etching. In some embodiments, a portion of the non-conductive region (26) and the non-conductive material (32) of the bonding surface (12a) may be brought into contact to form a direct bond at room temperature without the application of external pressure and without adhesive. In some embodiments, the non-conductive region (26) and the conductive bonding pad (34) of the bonding surface (14a) may be brought into contact to form a direct bond at room temperature without the application of external pressure and without adhesive.

[0031] In some embodiments, the bonding structure (1) may be further heated to improve the bonding strength between the opposing bonding surfaces of the interconnecting structure (10) and the first die (12) and / or the second die (14), and to form reliable electrical and mechanical contact at the interface between the interconnecting structure (10) and the first die (12) or the second die (14). For example, in some embodiments, each contact pad (24a, 24b) and the conductive bonding pad (30, 34) may be coplanar with the surface of each non-conductive region (26) and non-conductive material (32, 36), or may be recessed below the non-conductive region (26) and non-conductive material (32, 36), for example, within the range of 0nm to 20nm or within the range of 4nm to 10nm. A portion of the non-conductive region (26) and the non-conductive material (32, 36) can be directly bonded to each other without adhesive at room temperature, and then the bonded structure (I) can be annealed. During annealing, the contact pads (24a, 24b) and the conductive bonding pads (30, 34) can be extended to come into contact with each other to form a direct metal-to-metal bond. The direct metal-to-metal bond can provide an electrical and mechanical connection between the opposing bonding surfaces of the interconnected structure (10) and the first die (12) and / or the second die (14).Further details of the direct bonding process used in connection with each disclosed embodiment are U.S. Patents No. 7,126,212; No. 8,153,505; No. 7,622,324; No. 7,602,070; No. 8,163,373; No. 8,389,378; No. 7,485,968; No. 8,735,219; No. 9,385,024; No. 9,391,143; No. 9,431,368; No. 9,953,941; No. 9,716,033; No. 9,852,988; No. 10,032,068; No. 10,204,893; No. 10,434,749; and can be found in No. 10,446,532, the contents of each of which are incorporated herein by reference and for all purposes.

[0032] FIG. 1e is a flowchart illustrating the steps for forming a bonded structure according to an embodiment. In step 39a (see FIG. 1a), an interconnect structure (10) may be formed and provided. The interconnect structure (10) may be provided through a transfer process. For example, in some embodiments, the interconnect structure (10) (e.g., RDL) may be formed on a carrier (11) (such as a semiconductor or glass carrier). In step 39b (see FIG. 1b), an electronic component (e.g., an integrated device die (12, 14)) may be mounted on the interconnect structure (10). In step 39c (see FIG. 1b), a low coefficient of thermal expansion (CTE) dielectric layer (18) may be provided. In some embodiments, the low CTE dielectric layer (18) may comprise an inorganic dielectric material such as a silicon oxide layer. In some embodiments, the low CTE dielectric layer (18) may be provided by deposition. In step 39d (see also FIG. 1c), a molding material (16) may be provided. In some embodiments, the molding material (16) may include materials such as polymers, epoxy, resins, liquid crystal polymers, etc. The low CTE dielectric layer (18) may include a material having a CTE lower than the CTE of the molding material (16). In step 39e, at least a portion of the CTE dielectric layer (18) on the electronic component may be removed or thinned (e.g., etched or ground). In step 39e, at least a portion of the molding material (16) on the electronic component may be removed or thinned (e.g., etched or ground). In step 39f (see also FIG. 1c and 1d), the resulting structure may be individualized to define an individualized bonded structure (1). As described above, in some embodiments, the width of the molding material is less than 20% of the width of the first integration die (12) or the second integration die (14), and preferably less than 10% of the die width.

[0033] The carrier (11) may be removed from the interconnect structure (10) at any appropriate time in the manufacturing process to transfer the RDL to an electronic component (e.g., a first integrated device die (12)). For example, the carrier (11) may be removed from the interconnect structure (10) after step 39a and before step 39b, after step 39b and before step 39c, after step 39c and before step 39d, after step 39d and before step 39e, after step 39e and before step 39f, or after step 39f.

[0034] FIG. 2 illustrates a schematic side cross-sectional view of a bonding structure (2) according to an embodiment. Unless otherwise noted, the components of FIG. 2 may be identical or generally similar to the components of the same number in FIG. 1. The bonding structure may include an interconnection structure (10), a first integrated element die (12) mounted on the interconnection structure (10), and a second integrated element die (14) mounted on the interconnection structure (10). The bonding structure (2) may also include a molding material (16) disposed between the first die (12) and the second die (14), and a low coefficient of thermal expansion (CTE) layer (18). The bonding structure (2) may further include a support structure (50).

[0035] The support structure (50) may comprise any suitable material for supporting the first integrated element die (12) and / or the second integrated element die (14), such as a silicon handle wafer or other structure. The support structure (50) may be positioned so that the first integrated element die (12) and the second integrated element die (14) are located between the support structure (50) and the interconnection structure (10).

[0036] In some embodiments, the support structure (50) may include a third integrated element die. In these embodiments, the support structure may provide an electrical connection between the first integrated element die (12) and the second integrated element die (14). Additionally, the third integrated element die may be electrically connected to the interconnect structure (10) through vias (not shown) formed within the first integrated element die (12), the second integrated element die (14), or the molding material (16).

[0037] FIG. 3 illustrates a schematic side cross-sectional view of a bonding structure (3) according to an embodiment. Unless otherwise noted, the components of FIG. 3 may be identical or generally similar to the components of the same number in FIG. 1a-2. The bonding structure may include an interconnection structure (10), a first integrated element die (12) mounted on the interconnection structure (10), and a second integrated element die (14) mounted on the interconnection structure (10). A support structure (50) may be removed from the structure of FIG. 2 to form the structure of FIG. 3. The bonding structure (2) may also include a molding material (16) and a low coefficient of thermal expansion (CTE) layer (18) disposed between the first die (12) and the second die (14). The bonding structure (2) may further include a substrate (54).

[0038] The substrate (54) may include a conductive via (56) that extends at least partially through the substrate. In some embodiments, the via (56) may be electrically coupled to a first integrated device die (12) and / or a second integrated device die (14) through an interconnection structure (10). The substrate (54) may include any suitable material. In some embodiments, the substrate (54) may include a semiconductor die.

[0039] FIG. 4 is a schematic diagram of a system (80) comprising one or more bonding structures (5) according to various embodiments. The system (80) may include any suitable type of electronic device, such as a mobile electronic device (e.g., a smartphone, a tablet computing device, a laptop computer, etc.), a desktop computer, an automobile or its components, a stereo system, a medical device, a camera, or other suitable type of system. In some embodiments, the electronic device may include a microprocessor, a graphics processor, an electronic recording device, or a digital memory. The system (80) may include one or more component packages (82) that are mechanically and electrically connected to the system (80), for example, through one or more motherboards. Each package (82) may include one or more bonding structures (5). The bonding structure (5) illustrated in FIG. 4 may include any of the bonding structures disclosed herein. The bonding structure (5) may include one or more integrated device dies that perform various functions for the system (80).

[0040] In one embodiment, a bonding structure is disclosed. The bonding structure may include an interconnection structure having a non-conductive material and a conductor at least partially embedded in an upper surface. The upper surface includes a first conductive pad, a second conductive pad, and a non-conductive region. The bonding structure may also include a first integrated device die having a first bonding surface. The first bonding surface includes a first conductive bonding pad and a first non-conductive material. The first conductive bonding pad is directly bonded to the first conductive pad without an intermediate adhesive. The first non-conductive material may be directly bonded to a first portion of the non-conductive region. The bonding structure may further include a second integrated device die mounted on the interconnection structure. The second integrated device die may be laterally spaced from the first integrated device die along the upper surface of the interconnection structure. The second integrated device die may be electrically connected to the first integrated device die through at least the interconnection structure. The bonding structure may further include a dielectric layer disposed on the upper surface of the interconnection structure between the first integrated device die and the second integrated device die.

[0041] In one embodiment, the bonding structure further includes a molding material positioned on a dielectric layer between a first integrated device die and a second integrated device die.

[0042] In one embodiment, the dielectric layer has a coefficient of thermal expansion (CTE) lower than the coefficient of thermal expansion (CTE) of the molding material.

[0043] In one embodiment, the interconnect structure includes a transfer redistribution layer (transfer RDL).

[0044] In one embodiment, the dielectric layer includes a silicon oxide layer.

[0045] In one embodiment, the dielectric layer is disposed between the molding material and the first integrated device die and between the molding material and a portion of the upper surface of the interconnect structure.

[0046] In one embodiment, the dielectric layer is disposed along the sidewall of the first integrated device die, a portion of the upper surface of the interconnect structure, and the sidewall of the second integrated device die.

[0047] In one embodiment, the first junction surface of the first integrated device die includes the active surface of the first integrated device die.

[0048] The second integrated device die may include a rear surface facing the second junction surface. The rear surface of the second integrated device die includes the active surface of the second integrated device die.

[0049] In one embodiment, the bonding structure further includes a support structure coupled between the first integrated element die and the second integrated element die such that the first integrated element die and the second integrated element die are positioned between the interconnect structure and the support structure.

[0050] In one embodiment, the interconnection structure includes a first conductive line connected to a first conductive pad through a first conductive via, and a second conductive line connected to a second conductive pad through a second conductive via.

[0051] In one embodiment, the second integrated device die includes a second junction surface. The second junction surface may include a second conductive junction pad and a second non-conductive material. The second conductive junction pad may be bonded to the second conductive pad. The second non-conductive material may be bonded to a second portion of a non-conductive region that is different from the first portion.

[0052] In one embodiment, the second conductive bonding pad is directly bonded to the second conductive pad without an intermediate adhesive, and the second non-conductive material is directly bonded to the second portion of a non-conductive region different from the first portion without an intermediate adhesive.

[0053] In one aspect, a bonding structure is disclosed. The bonding structure may include an interconnection structure having a non-conductive material and a conductor at least partially embedded in an upper surface. The upper surface includes a first conductive pad, a second conductive pad electrically communicating with the first conductive pad, and a non-conductive region. The bonding structure may also include a first integrated device die having a first bonding surface. The first bonding surface may include a first conductive bonding pad and a first non-conductive material. The first conductive bonding pad may be directly bonded to the first conductive pad without an intermediate adhesive. The first non-conductive material may be directly bonded to a first portion of the non-conductive region. The bonding structure may also include a second integrated device die mounted on the interconnection structure. The second die may be laterally spaced from the first integrated device die along the upper surface of the interconnection structure. The bonding structure may also include a molding material disposed between the first integrated device die and the second integrated device die. The bonding structure may further include a dielectric layer disposed between at least the molding material and the first integrated element die or between the molding material and the upper surface of the interconnection structure.

[0054] In one embodiment, the dielectric layer has a coefficient of thermal expansion (CTE) lower than the coefficient of thermal expansion (CTE) of the molding material.

[0055] In one embodiment, the interconnect structure includes a transfer redistribution layer (RDL).

[0056] In one embodiment, the dielectric layer includes a silicon oxide layer.

[0057] In one embodiment, the dielectric layer is disposed between the molding material and the first integrated device die and between the molding material and a portion of the upper surface of the interconnection structure. The dielectric layer may be disposed along the sidewall of the first integrated device die, a portion of the upper surface of the interconnection structure, and the sidewall of the second integrated device die.

[0058] In one embodiment, the first junction surface of the first integrated device die includes the active surface of the first integrated device die. The second integrated device die may include a rear surface facing the second junction surface. The rear surface of the second integrated device die may include the active surface of the second integrated device die.

[0059] In one embodiment, the bonding structure further includes a support structure coupled to the first integrated element die and the second integrated element die such that the first integrated element die and the second integrated element die are positioned between the interconnect structure and the support structure.

[0060] In one embodiment, the interconnection structure includes a first conductive line connected to a first conductive pad through a first conductive via, and a second conductive line connected to a second conductive pad through a second conductive via.

[0061] In one embodiment, the second die includes a second bonding surface. The second bonding surface may include a second conductive bonding pad and a second non-conductive material. The second conductive bonding pad may be bonded to the second conductive pad, and the second non-conductive material may be bonded to a second portion of a non-conductive region different from the first portion. The second conductive bonding pad may be directly bonded to the second conductive pad without an intermediate adhesive, and the second non-conductive material may be directly bonded to a second portion of a non-conductive region different from the first portion without an intermediate adhesive.

[0062] In one embodiment, the second integrated device die is electrically connected to the first integrated device die at least partially through an interconnection structure.

[0063] In one embodiment, a method for manufacturing a bonding structure is disclosed. The method may include the step of providing an interconnection structure having a non-conductive material and a conductor at least partially embedded in an upper surface. The upper surface includes a first conductive pad, a second conductive pad, and a non-conductive region. The method may also include the step of directly bonding a first integrated device die to the interconnection structure. The first integrated device die has a first bonding surface. The first bonding surface may include a first conductive bonding pad and a first non-conductive material. The first conductive bonding pad may be directly bonded to the first conductive pad without an intermediate adhesive, and the first non-conductive material may be directly bonded to a first portion of the non-conductive region. The method may also include the step of directly bonding a second integrated device die to the interconnection structure. The second integrated device die may be laterally spaced from the first integrated device die along the upper surface of the interconnection structure. The second integrated device die may be electrically connected to the first integrated device die at least through the interconnection structure. This method may also include the step of forming a dielectric layer on at least a portion of the upper surface of the interconnect structure. This method may further include the step of placing a molding material on at least a portion of the dielectric layer.

[0064] In one embodiment, forming an interconnect structure includes forming an interconnect structure on a carrier. This method may further include the step of removing the carrier from the interconnect structure after mounting the first integrated element die.

[0065] In one embodiment, the step of forming a dielectric layer includes forming a dielectric layer along the sidewall of the first die, a portion of the upper surface, and the sidewall of the second die.

[0066] In one aspect, a bonding structure is disclosed. The bonding structure may include an interconnection structure having a non-conductive material and a conductor at least partially embedded in an upper surface. The upper surface includes a first conductive pad, a second conductive pad, and a non-conductive region between the first conductive pad and the second conductive pad. The bonding structure may also include a first die having a first bonding surface. The first bonding surface may include a first conductive bonding pad and a first non-conductive material. The first bonding surface of the first die may include an active surface of the first die. The first conductive bonding pad may be directly bonded to the first conductive pad without an intermediate adhesive, and the first non-conductive material may be directly bonded to a first portion of the non-conductive region. The bonding structure may also include a second die having a second bonding surface facing the interconnection structure. The second die may be mounted on the interconnection structure. The second die may be laterally spaced from the first die along the upper surface of the interconnection structure. The second die includes a rear surface facing the second bonding surface. The rear surface of the second die may include the active surface of the second die. The bonding structure may also include a molding material disposed between the first die and the second die. The bonding structure may further include a silicon oxide layer disposed between the molding material and the first die, or between the molding material and the upper surface of the interconnection structure.

[0067] In one embodiment, the interconnection structure includes a redistribution layer, and the first die and the second die are electrically connected to each other at least partially through the interconnection structure.

[0068] In one embodiment, a silicon oxide layer is disposed between the molding material and the first die and between the molding material and a portion of the upper surface of the interconnect structure.

[0069] In one embodiment, the silicon oxide layer is disposed along the sidewall of the first die, a portion of the upper surface, and the sidewall of the second die.

[0070] In one embodiment, the interconnection structure includes a first conductive line connected to a first conductive pad through a first conductive via, and a second conductive line connected to a second conductive pad through a second conductive via.

[0071] In one embodiment, the second bonding surface comprises a second conductive bonding pad and a second non-conductive material, the second conductive bonding pad is bonded to the second conductive pad, and the second non-conductive material is bonded to a second portion of a non-conductive region different from the first portion.

[0072] In one aspect, a bonding structure is disclosed. The bonding structure may include an interconnect structure having a non-conductive material and a conductor at least partially embedded in an upper surface. The upper surface may include a first conductive pad, a second conductive pad, and a non-conductive region surrounding the first conductive pad and the second conductive pad. The bonding structure may also include a first die having a first bonding surface. The first bonding surface may include a first conductive bonding pad and a first non-conductive material surrounding the first conductive bonding pad. The first bonding surface of the first die may include an active surface of the first die. The first conductive bonding pad may be directly bonded to the first conductive pad, and the first non-conductive material may be directly bonded to a first portion of the non-conductive region. The bonding structure may also include a second die having a second bonding surface facing the interconnect structure. The second die may be mounted on the interconnect structure. The second die may be laterally spaced from the first die along the upper surface of the interconnect structure. The bonding structure may further include a molding material disposed between the first die and the second die. The width of the molding material is less than 20% of the width of the first die or the second die.

[0073] In one aspect, a bonding structure is disclosed. The bonding structure may include an interconnect structure having a non-conductive material and a conductor at least partially embedded in an upper surface. The upper surface includes a first conductive pad, a second conductive pad, and a non-conductive region surrounding the first conductive pad and the second conductive pad. The bonding structure may also include a first die having a first bonding surface. The first bonding surface may include a first conductive bonding pad and a first non-conductive material surrounding the first conductive bonding pad. The first bonding surface of the first die may include an active surface of the first die. The first conductive bonding pad may be directly bonded to the first conductive pad, and the first non-conductive material may be directly bonded to a first portion of the non-conductive region. The bonding structure may further include a second die having a second bonding surface facing the interconnect structure. The second die may be mounted on the interconnect structure. The second die may be laterally spaced from the first die along the upper surface of the interconnect structure. The thickness of the interconnect structure is thinner than the thickness of the first die or the second die. The thickness of the interconnect structure may be less than 50% of the thickness of the first die or the second die.

[0074] Unless otherwise clearly required by the context, throughout the specification and claims, terms such as “comprise,” “comprising,” “include,” and “including” should be interpreted in a comprehensive sense, not in an exclusive or complete sense. That is, they mean “include, but not limited thereto.” As used herein, the word “comprised” refers to two or more elements that are directly connected or may be connected by one or more intermediate elements. Likewise, as used herein, the word “connected” refers to two or more elements that are directly connected or may be connected through one or more intermediate elements. Additionally, as used herein, the words “here,” “above,” “below,” and similar terms refer to the application as a whole rather than a specific part thereof. Where the context permits, words in the above detailed description using the singular or plural may each include the plural or singular form. In relation to a list of two or more items, the word "or" includes the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0075] Additionally, conditional language used herein, such as “can,” “could,” “might,” “may,” “eg,” “for example,” “for example,” and “like,” is generally intended to convey that a particular embodiment includes a particular feature, element, and / or state, but that other embodiments do not, unless otherwise specifically stated or otherwise understood within the context in which it is used. Accordingly, such conditional language is generally not intended to imply that a feature, element, and / or state is required in any way for one or more embodiments.

[0076] Although specific embodiments have been described, these embodiments are presented merely as examples and are not intended to limit the scope of the disclosure. In practice, the novel devices, methods, and systems described herein may be implemented in various other forms, and various omissions, substitutions, and modifications to the forms of methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in various ways. Any suitable combination of elements and operations of the various embodiments described above may be combined to provide additional embodiments. The appended claims and their equivalents are intended to include such forms or modifications that fall within the scope and spirit of the disclosure.

Claims

Claim 1 As a bonding structure, an interconnection structure having a non-conductive material and a conductor at least partially embedded in an upper surface — said upper surface comprises a first conductive pad, a second conductive pad, and a non-conductive region —; a first integrated device die having a first bonding surface — said first bonding surface comprises a first conductive bonding pad and a first non-conductive material, said first conductive bonding pad is directly bonded to said first conductive pad without an intermediate adhesive, and said first non-conductive material is directly bonded to a first portion of said non-conductive region —; a second integrated device die mounted on said interconnection structure — said second integrated device die is laterally spaced from said first integrated device die along the upper surface of said interconnection structure, and said second integrated device die is electrically connected to said first integrated device die at least through said interconnection structure —; A bonding structure comprising a dielectric layer disposed on an upper surface of the interconnection structure between the first integrated element die and the second integrated element die, wherein the interconnection structure comprises a redistribution layer (RDL), and the lower surface of the interconnection structure facing the upper surface comprises a direct hybrid bonding surface. Claim 2 A bonding structure according to claim 1, further comprising a sealing material on a dielectric layer between the first integrated element die and the second integrated element die. Claim 3 In paragraph 2, the dielectric layer is a bonded structure having a coefficient of thermal expansion (CTE) lower than the coefficient of thermal expansion (CTE) of the sealant. Claim 4 A bonding structure according to paragraph 2, wherein the dielectric layer is disposed between the sealing material and the first integrated device die and between the sealing material and a portion of the upper surface of the interconnection structure, and the dielectric layer is disposed along the sidewall of the first integrated device die, a portion of the upper surface of the interconnection structure, and the sidewall of the second integrated device die. Claim 5 In claim 1, the lower surface of the interconnection structure is directly hybrid-bonded to a carrier, forming a bonding structure. Claim 6 A bonding structure according to claim 1, wherein the first bonding surface of the first integrated element die comprises an active surface of the first integrated element die. Claim 7 A bonding structure according to claim 1, further comprising a support structure coupled to the first integrated element die and the second integrated element die such that the first integrated element die and the second integrated element die are positioned between the interconnection structure and the support structure. Claim 8 In claim 1, the interconnection structure comprises a first conductive line connected to the first conductive pad through a first conductive via, and a second conductive line connected to the second conductive pad through a second conductive via, forming a bonding structure. Claim 9 A bonding structure according to claim 1, wherein the second integrated device die comprises a second bonding surface, and the second bonding surface comprises a second conductive bonding pad and a second non-conductive material, wherein the second conductive bonding pad is bonded to the second conductive pad, and the second non-conductive material is bonded to a second portion of the non-conductive region that is different from the first portion, and the second conductive bonding pad is directly bonded to the second conductive pad without an intermediate adhesive, and the second non-conductive material is directly bonded to a second portion of the non-conductive region that is different from the first portion without an intermediate adhesive. Claim 10 An interconnection structure having an upper surface, a lower surface facing the upper surface, and a conductor at least partially embedded in a non-conductive material — the upper surface comprises a first conductive pad, a second conductive pad electrically communicating with the first conductive pad, and a non-conductive region, and the lower surface comprises a direct hybrid bonding surface —; a first integrated device die having a first bonding surface — the first bonding surface comprises a first conductive bonding pad and a first non-conductive material, the first conductive bonding pad is directly bonded to the first conductive pad without an intermediate adhesive, and the first non-conductive material is directly bonded to a first portion of the non-conductive region —; a second integrated device die mounted on the interconnection structure — the second integrated device die is laterally spaced from the first integrated device die along the upper surface of the interconnection structure —; a sealant disposed between the first integrated device die and the second integrated device die; A bonding structure comprising: a dielectric layer disposed between at least the sealing material and the first integrated element die or between the sealing material and the upper surface of the interconnection structure; and a carrier - the direct hybrid bonding surface of the lower surface of the interconnection structure is directly hybrid bonded to the carrier. Claim 11 In claim 10, the dielectric layer is a bonded structure having a coefficient of thermal expansion (CTE) lower than the coefficient of thermal expansion (CTE) of the sealant. Claim 12 In claim 10, the dielectric layer is disposed between the sealant and the first integrated element die and between the sealant and a portion of the upper surface of the interconnect structure, forming a bonding structure. Claim 13 A bonding structure according to claim 10, further comprising a support structure coupled to the first integrated element die and the second integrated element die such that the first integrated element die and the second integrated element die are positioned between the interconnection structure and the support structure. Claim 14 A method for manufacturing a bonding structure, comprising the steps of: providing an interconnecting structure having a non-conductive material and a conductor at least partially embedded in an upper surface — wherein the upper surface comprises a first conductive pad, a second conductive pad, and a non-conductive region, and the step of providing the interconnecting structure comprises forming the interconnecting structure on a carrier —; directly bonding a first integrated element die to the interconnecting structure — wherein the first integrated element die has a first bonding surface, the first bonding surface comprises a first conductive bonding pad and a first non-conductive material, the first conductive bonding pad is directly bonded to the first conductive pad without an intermediate adhesive, and the first non-conductive material is directly bonded to a first portion of the non-conductive region —; removing the carrier from the interconnecting structure after directly bonding the first integrated element die to the interconnecting structure; and directly bonding a second integrated element die to the interconnecting structure — wherein the second integrated element die is laterally removed from the first integrated element die along the upper surface of the interconnecting structure A method for manufacturing a bonded structure comprising: being spaced apart, wherein the second integrated element die is electrically connected to the first integrated element die through at least the interconnection structure; forming a dielectric layer on at least a portion of the upper surface of the interconnection structure; placing a sealant on at least a portion of the dielectric layer; and providing a support structure on the sealant, the first integrated element die, and the second integrated element die. Claim 15 A method for manufacturing a bonded structure according to claim 14, wherein the step of forming the dielectric layer comprises forming the dielectric layer along the sidewall of the first integrated device die, a portion of the upper surface, and the sidewall of the second integrated device die. Claim 16 As a bonding structure, an interconnection structure having an upper surface and a lower surface facing the upper surface and a conductor at least partially embedded in a non-conductive material ― the upper surface comprises a first conductive pad, a second conductive pad, and a non-conductive region between the first conductive pad and the second conductive pad, and the lower surface comprises a direct hybrid bonding surface ―; a first die having a first bonding surface ― the first bonding surface comprises a first conductive bonding pad and a first non-conductive material, and the first bonding surface of the first die comprises an active surface of the first die, the first conductive bonding pad is directly bonded to the first conductive pad without an intermediate adhesive, and the first non-conductive material is directly bonded to a first portion of the non-conductive region ―; a second die having a second bonding surface facing the interconnection structure ― the second die is mounted on the interconnection structure, the second die is laterally spaced from the first die along the upper surface of the interconnection structure, and the second die faces the second bonding surface A bonding structure comprising: a rear surface, wherein the rear surface of the second die comprises an active surface of the second die; a sealant disposed between the first die and the second die; and a silicon oxide layer disposed between the sealant and the first die or between the sealant and the upper surface of the interconnection structure—the interconnection structure comprises a redistribution layer (RDL). Claim 17 In claim 16, the lower surface of the interconnection structure is directly hybrid-bonded to a carrier, and the first die and the second die are electrically connected to each other at least partially through the interconnection structure, forming a bonding structure. Claim 18 In claim 16, the silicon oxide layer is disposed between the sealant and the first die and between the sealant and a portion of the upper surface of the interconnect structure, forming a bonding structure. Claim 19 In claim 16, the silicon oxide layer is a bonding structure disposed along the sidewall of the first die, a portion of the upper surface, and the sidewall of the second die. Claim 20 In claim 16, the interconnection structure comprises a first conductive line connected to the first conductive pad through a first conductive via, and a second conductive line connected to the second conductive pad through a second conductive via, forming a bonding structure. Claim 21 A bonding structure according to claim 16, wherein the second bonding surface comprises a second conductive bonding pad and a second non-conductive material, the second conductive bonding pad is bonded to the second conductive pad, and the second non-conductive material is bonded to a second portion of the non-conductive region that is different from the first portion. Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete

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