Display device

Abstract

A display device is provided. The display device comprises a first electrode and a second electrode disposed on a substrate, a spacing region formed to space the first electrode and the second electrode apart, a first insulating layer disposed on the first electrode and the second electrode and disposed to fill the spacing region, a light-emitting element disposed on the first insulating layer and having a first end disposed on the first electrode and a second end facing the first end, and a first opening adjacent to the first end and exposing the first insulating layer, wherein the spacing region is disposed adjacent to the second end.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display device may be a flat panel display device such as a Liquid Crystal Display, a Field Emission Display, or a Light Emitting Display. The light emitting display device may include an organic light emitting display device comprising an organic light emitting diode as a light emitting element, an inorganic light emitting display device comprising an inorganic semiconductor as a light emitting element, or a micro light emitting diode (or micro light emitting diode) as a light emitting element. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a display device with improved light emission efficiency.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device according to one embodiment for solving the above problem comprises a first electrode and a second electrode disposed on a substrate, a spacing area formed to be spaced apart from the first electrode and the second electrode, a first insulating layer disposed on the first electrode and the second electrode and disposed to fill the spacing area, a light-emitting element disposed on the first insulating layer and having a first end disposed on the first electrode and a second end facing the first end, and a first opening adjacent to the first end and exposing the first insulating layer, wherein the spacing area is disposed adjacent to the second end.

[0006] The display device may include a floating electrode that is disposed between the substrate and the first electrode in the thickness direction of the substrate and is electrically floating.

[0007] The floating electrode can overlap the spacing region and the thickness direction of the substrate.

[0008] The light-emitting element comprises an N-type semiconductor layer, a P-type semiconductor layer, and a light-emitting layer disposed between the N-type semiconductor layer and the P-type semiconductor layer, and the second end may include one surface of the N-type semiconductor layer.

[0009] The first electrode can overlap the center of the light-emitting element and the thickness direction of the substrate.

[0010] The second end of the light-emitting element can be non-overlapping with the second electrode.

[0011] The second end of the light-emitting element can overlap the first electrode and the substrate in the thickness direction.

[0012] The second end of the light-emitting element can overlap the spacing region and the thickness direction of the substrate.

[0013] The first opening may be formed to expose the upper surface of the first insulating layer.

[0014] The first opening may be formed to expose the side of the first insulating layer and the first electrode.

[0015] The display device further includes a first bank pattern disposed between the substrate and the first electrode and a second bank pattern disposed between the substrate and the second electrode, wherein the spacing area is formed to expose the second bank pattern and the first insulating layer can contact the exposed second bank pattern.

[0016] One end of the second electrode may be placed on the second bank pattern.

[0017] The display device may further include a first connecting electrode in contact with a first end of the light-emitting element on the first insulating layer, and a second connecting electrode in contact with a second end of the light-emitting element on the first insulating layer.

[0018] The second connecting electrode can overlap the first electrode and the substrate in the thickness direction.

[0019] The first insulating layer further includes a second opening that exposes the upper surface of the second electrode, and the second connecting electrode can contact the exposed upper surface of the second electrode.

[0020] The first insulating layer further includes a third opening that exposes the upper surface of the first electrode, and the first connecting electrode can contact the exposed upper surface of the first electrode.

[0021] The first electrode can overlap the second electrode and the substrate in the thickness direction.

[0022] A display device according to another embodiment for solving the above problem comprises a first electrode and a second electrode spaced apart from each other on a substrate, a first insulating layer disposed on the first electrode and the second electrode, a light-emitting element disposed on the first insulating layer and having a first end disposed on the first electrode and a second end facing the first end, and a first opening adjacent to the first end and exposing the first insulating layer, wherein the first distance between the first end and one end of the first electrode is longer than the second distance between the second end and one end of the first electrode.

[0023] The display device further includes a first bank pattern disposed between the substrate and the first electrode and a second bank pattern disposed between the substrate and the second electrode, and one end of the second electrode may be disposed on the second bank pattern.

[0024] The minimum distance of the first electrode from the substrate may be shorter than the minimum distance of the second electrode from the substrate. Effects of the invention

[0025] A display device according to the embodiments includes a first electrode and a second electrode for forming an electric field that aligns a light-emitting element. Since the first electrode and the second electrode are spaced apart and offset to one side, the loss of light emitted in the downward direction of the light-emitting element can be reduced, and the light emission efficiency in the upward direction can be improved.

[0026] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0027] FIG. 1 is a schematic plan view of a display device according to one embodiment. FIG. 2 is a plan view showing one pixel of a display device according to one embodiment. Figure 3 is a cross-sectional view taken along the line E1-E1' of Figure 2. Figure 4 is a cross-sectional view taken along the line E2-E2' of Figure 2. FIG. 5 is a schematic diagram of a light-emitting element according to one embodiment. FIG. 6 is an example of an enlarged cross-sectional view of a portion in which a light-emitting element is placed in one embodiment. FIG. 7 is another example of an enlarged cross-sectional view of a portion in which a light-emitting element is placed in one embodiment. FIG. 8 is a conceptual diagram showing the light emission direction of a light-emitting element in one embodiment. FIG. 9 is another example of an enlarged cross-sectional view of a portion in which a light-emitting element is placed in one embodiment. FIG. 10 is a conceptual diagram showing the alignment process of the electric field formed on the first electrode and the second electrode and the light-emitting element in one embodiment. FIG. 11 is a cross-sectional view of a display device according to another embodiment. FIG. 12 is an enlarged cross-sectional view of a portion in which a light-emitting element is placed in another embodiment. FIG. 13 is a cross-sectional view of a display device according to another embodiment. FIG. 14 is an enlarged cross-sectional view of a portion in which a light-emitting element is placed in another embodiment. FIG. 15 is a cross-sectional view of a display device according to another embodiment. FIG. 16 is an enlarged cross-sectional view of a portion in which a light-emitting element is placed in another embodiment. Specific details for implementing the invention

[0028] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0029] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0030] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0031] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0032] Specific embodiments will be described below with reference to the attached drawings.

[0033] FIG. 1 is a schematic plan view of a display device according to one embodiment.

[0034] Referring to FIG. 1, the display device (10) displays a video or a still image. The display device (10) may refer to any electronic device that provides a display screen. For example, a television, laptop, monitor, billboard, Internet of Things, mobile phone, smartphone, tablet PC (Personal Computer), electronic watch, smart watch, watch phone, head-mounted display, mobile communication terminal, electronic notebook, electronic book, PMP (Portable Multimedia Player), navigation, game console, digital camera, camcorder, etc. that provide a display screen may be included in the display device (10).

[0035] The display device (10) includes a display panel that provides a display screen. Examples of display panels include an inorganic light-emitting diode display panel, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a plasma display panel, a field emission display panel, etc. In the following examples, an inorganic light-emitting diode display panel is used as an example of a display panel, but it is not limited thereto, and if the same technical concept is applicable, it can be applied to other display panels.

[0036] The shape of the display device (10) can be varied in many ways. For example, the display device (10) may have a shape such as a horizontally elongated rectangle, a vertically elongated rectangle, a square, a rectangle with rounded corners (vertices), other polygons, or a circle. The shape of the display area (DPA) of the display device (10) may also be similar to the overall shape of the display device (10). In FIG. 1, a display device (10) in the shape of a rectangle with a long length in the second direction (DR2) is illustrated.

[0037] The display device (10) may include a display area (DPA) and a non-display area (NDA). The display area (DPA) is an area where the screen can be displayed, and the non-display area (NDA) is an area where the screen is not displayed. The display area (DPA) may also be referred to as an active area, and the non-display area (NDA) as an inactive area. The display area (DPA) may generally occupy the center of the display device (10).

[0038] The display area (DPA) may include a plurality of pixels (PX). The plurality of pixels (PX) may be arranged in a matrix direction. The shape of each pixel (PX) may be a planar rectangle or a square, but is not limited thereto, and may be a rhombus shape with each side tilted toward one direction. Each pixel (PX) may be arranged in a stripe type or an island type. Additionally, each of the pixels (PX) may include one or more light-emitting elements that emit light of a specific wavelength range to display a specific color.

[0039] A non-display area (NDA) may be placed around a display area (DPA). The non-display area (NDA) may surround the display area (DPA) in whole or in part. The display area (DPA) is rectangular in shape, and the non-display area (NDA) may be placed adjacent to the four sides of the display area (DPA). The non-display area (NDA) may form the bezel of the display device (10). In each non-display area (NDA), wiring or circuit drivers included in the display device (10) may be placed, or external devices may be mounted.

[0040] FIG. 2 is a plan view showing one pixel of a display device according to one embodiment.

[0041] FIG. 2 illustrates the planar arrangement of electrodes (RME: RME1, RME2), bank patterns (BP1, BP2), bank layer (BNL), a plurality of light-emitting elements (ED), and connecting electrodes (CNE: CNE1, CNE2) placed in one pixel (PX) of a display device (10).

[0042] Referring to FIG. 2, each of the pixels (PX) of the display device (10) may include a plurality of subpixels (SPXn). For example, one pixel (PX) may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3). The first subpixel (SPX1) may emit light of a first color, the second subpixel (SPX2) may emit light of a second color, and the third subpixel (SPX3) may emit light of a third color. As an example, the first color may be blue, the second color may be green, and the third color may be red. However, not limited thereto, each subpixel (SPXn) may emit light of the same color. FIG. 2 illustrates that one pixel (PX) includes three subpixels (SPXn), but is not limited thereto, and the pixel (PX) may include a larger number of subpixels.

[0043] Each subpixel (SPXn) of the display device (10) may include a light-emitting region (EMA) and a non-light-emitting region. The light-emitting region (EMA) may be an area where a light-emitting element (ED) is placed and light of a specific wavelength range is emitted. The non-light-emitting region may be an area where a light-emitting element (ED) is not placed and light emitted from the light-emitting element (ED) does not reach and is not emitted.

[0044] The light-emitting region (EMA) may include an area where a light-emitting element (ED) is placed and an area adjacent to the light-emitting element (ED) through which light emitted from the light-emitting element (ED) is emitted. For example, the light-emitting region (EMA) may also include an area where light emitted from the light-emitting element (ED) is reflected or refracted by another component and emitted. A plurality of light-emitting elements (ED) are placed in each subpixel (SPXn), and a light-emitting region may be formed by including the area where they are placed and an area adjacent thereto.

[0045] In the drawings, the light-emitting regions (EMAs) of each subpixel (SPXn) are illustrated as having uniform areas, but are not limited thereto. In some embodiments, each light-emitting region (EMA) of each subpixel (SPXn) may have different areas depending on the color or wavelength of light emitted from the light-emitting element (ED) placed in the corresponding subpixel.

[0046] Each subpixel (SPXn) may further include a sub-region (SA) placed in a non-emissive region. The sub-region (SA) of the corresponding subpixel (SPXn) may be placed on the lower side, which is the other side of the first direction (DR1) of the emitting region (EMA). The emitting region (EMA) and the sub-region (SA) are arranged alternately along the first direction (DR1), and the sub-region (SA) may be placed between the emitting regions (EMA) of different subpixels (SPXn) that are spaced apart in the first direction (DR1). For example, the emitting region (EMA) and the sub-region (SA) may be arranged alternately with each other in the first direction (DR1), and each of the emitting region (EMA) and the sub-region (SA) may be arranged repeatedly in the second direction (DR2). However, this is not limited thereto, and the emitting regions (EMA) and sub-regions (SA) in a plurality of pixels (PX) may have an arrangement different from that of FIG. 2.

[0047] In the sub-region (SA), light is not emitted because no light-emitting element (ED) is placed, but a portion of the electrode (RME) placed in each sub-pixel (SPXn) may be placed therein. The electrodes (RME) placed in different sub-pixels (SPXn) may be separated from each other in the separation section (ROP) of the sub-region (SA).

[0048] The display device (10) may include a plurality of electrodes (RME: RME1, RME2), bank patterns (BP1, BP2), a bank layer (BNL), light-emitting elements (ED), and connecting electrodes (CNE: CNE1, CNE2).

[0049] Multiple bank patterns (BP1, BP2) can be placed in the light-emitting region (EMA) of each subpixel (SPXn). The bank patterns (BP1, BP2) may have a shape that has a certain width in the second direction (DR2) and extends in the first direction (DR1).

[0050] For example, bank patterns (BP1, BP2) may include a first bank pattern (BP1) and a second bank pattern (BP2) spaced apart from each other in a second direction (DR2) within the light-emitting region (EMA) of each subpixel (SPXn). The first bank pattern (BP1) may be positioned on the left side, which is one side of the second direction (DR2) from the center of the light-emitting region (EMA), and the second bank patterns (BP2) may be spaced apart from the first bank pattern (BP1) and positioned on the right side, which is the other side of the second direction (DR2) from the center of the light-emitting region (EMA). The first bank pattern (BP1) and the second bank pattern (BP2) may be arranged alternately along the second direction (DR2) and may be arranged as an island pattern in the display region (DPA). A plurality of light-emitting elements (ED) may be arranged between the first bank pattern (BP1) and the second bank pattern (BP2).

[0051] The first direction (DR1) lengths of the first bank pattern (BP1) and the second bank pattern (BP2) are equal to each other, but may be smaller than the first direction (DR1) length of the light-emitting region (EMA) surrounded by the bank layer (BNL). The first bank pattern (BP1) and the second bank pattern (BP2) may be spaced apart from the portion of the bank layer (BNL) that extends in the second direction (DR2). However, not limited thereto, the bank patterns (BP1, BP2) may be integrated with the bank layer (BNL) or partially overlap with the portion of the bank layer (BNL) that extends in the second direction (DR2). In this case, the first direction (DR1) lengths of the bank patterns (BP1, BP2) may be equal to or greater than the first direction (DR1) length of the light-emitting region (EMA) surrounded by the bank layer (BNL).

[0052] The first bank pattern (BP1) and the second bank pattern (BP2) may have the same width in the second direction (DR2). However, they are not limited thereto and may have different widths. For example, one bank pattern may have a larger width than the other bank pattern, and the bank pattern with the larger width may be placed across the light-emitting regions (EMA) of other subpixels (SPXn) adjacent in the second direction (DR2). In this case, the bank pattern placed across multiple light-emitting regions (EMA) may overlap with the portion of the bank layer (BNL) extended in the first direction (DR1) in the thickness direction. In the drawing, it is illustrated that two bank patterns (BP1, BP2) are placed with the same width for each subpixel (SPXn), but this is not limited thereto. The number and shape of the bank patterns (BP1, BP2) may vary depending on the number or arrangement structure of the electrodes (RME).

[0053] Multiple electrodes (RME: RME1, RME2) are arranged in a shape extending in one direction for each subpixel (SPXn). The multiple electrodes (RME) may extend in a first direction (DR1) and be placed in the light-emitting region (EMA) and sub-region (SA) of the subpixel (SPXn), and may be arranged spaced apart from each other in a second direction (DR2). The multiple electrodes (RME) may be electrically connected to a light-emitting element (ED) described later. However, they are not limited thereto, and the electrodes (RME) may not be electrically connected to the light-emitting element (ED).

[0054] In one embodiment, the display device (10) may include a first electrode (RME1) and a second electrode (RME2) disposed in each subpixel (SPXn). The second electrode (RME2) may be disposed to the right of the center of the light-emitting region (EMA), and the first electrode (RME1) may be spaced apart from the second electrode (RME2) in a second direction (DR2). A portion of the first electrode (RME1) may be disposed to the left of the center of the light-emitting region (EMA), and another portion may be disposed to the right of the center of the light-emitting region (EMA). The width of the first electrode (RME1) may be greater than the width of the second electrode (RME2). Accordingly, the spaced-apart area between the first electrode (RME1) and the second electrode (RME2) may be disposed to the right of the center of the light-emitting region (EMA).

[0055] A first electrode (RME1) may be placed on a first bank pattern (BP1), and a second electrode (RME2) may be placed on a second bank pattern (BP2). The first electrode (RME1) and the second electrode (RME2) may be partially placed in the corresponding subpixel (SPXn) and sub-region (SA) beyond the bank layer (BNL). The first electrode (RME1) and the second electrode (RME2) of different subpixels (SPXn) may be spaced apart from each other based on a separation portion (ROP) located within the sub-region (SA) of one subpixel (SPXn).

[0056] As will be described later, when the light-emitting element (ED) is placed at the center of the light-emitting region (EMA), the first electrode (RME1) overlaps with the light-emitting element (ED), but the second electrode (RME2) may not overlap with the light-emitting element (ED).

[0057] In the drawing, it is illustrated that each subpixel (SPXn) has two electrodes (RME) extending in a first direction (DR1), but is not limited thereto. For example, the display device (10) may have a larger number of electrodes (RME) arranged in one subpixel (SPXn), or the electrodes (RME) may be partially bent.

[0058] A bank layer (BNL) may be arranged to surround a plurality of subpixels (SPXn) and the light-emitting region (EMA) and sub-region (SA) of each subpixel (SPXn). The bank layer (BNL) may be arranged at the boundary of subpixels (SPXn) adjacent in a first direction (DR1) and a second direction (DR2), and may also be arranged at the boundary of the light-emitting region (EMA) and sub-region (SA). The subpixels (SPXn), light-emitting region (EMA), and sub-region (SA) of the display device (10) may be regions separated by the arrangement of the bank layer (BNL). The spacing between the plurality of subpixels (SPXn), the light-emitting regions (EMA), and the sub-regions (SA) may vary depending on the width of the bank layer (BNL).

[0059] The bank layer (BNL) may be arranged in a grid pattern across the entire front of the display area (DPA), including portions extending in the first direction (DR1) and the second direction (DR2) on the plane. The bank layer (BNL) may be arranged across the boundaries of each subpixel (SPXn) to distinguish neighboring subpixels (SPXn). Additionally, the bank layer (BNL) may be arranged to surround the light-emitting area (EMA) and sub-area (SA) arranged for each subpixel (SPXn) to distinguish them.

[0060] A plurality of light-emitting elements (EDs) may be placed in a light-emitting region (EMA). The light-emitting elements (EDs) may be placed between bank patterns (BP1, BP2) and arranged spaced apart from each other in a first direction (DR1). In one embodiment, the plurality of light-emitting elements (EDs) may have a shape that extends in one direction. The light-emitting elements (EDs) may have a first end corresponding to the left side, which is one side of the second direction (DR2), and a second end corresponding to the right side, which is the other side of the second direction (DR2). The first end is placed on the first electrode (RME1), but the second end is not placed on the second electrode (RME2). The second end may be placed on the first electrode (RME1) or on the spaced-away region ('SP' in FIG. 3) between the first electrode (RME1) and the second electrode (RME2).

[0061] The light-emitting elements (ED) may generally be arranged such that their extended direction is perpendicular to the first direction (DR1) in which the electrodes (RME) are extended. However, this is not limited thereto, and the extended direction of the light-emitting elements (ED) may be the second direction (DR2) or a direction inclined obliquely thereto.

[0062] A plurality of connecting electrodes (CNE; CNE1, CNE2) may be disposed on a plurality of electrodes (RME) and bank patterns (BP1, BP2). Each of the plurality of connecting electrodes (CNE) may have a shape extending in one direction and may be disposed spaced apart from each other. Each connecting electrode (CNE) may be in contact with a light-emitting element (ED) and may be electrically connected to an electrode (RME) or a conductive layer underneath it.

[0063] The connecting electrodes (CNE) may include a first connecting electrode (CNE1) and a second connecting electrode (CNE2) disposed in each subpixel (SPXn). The first connecting electrode (CNE1) may have a shape extending in a first direction (DR1) and may be disposed on a first electrode (RME1) or a first bank pattern (BP1). The first connecting electrode (CNE1) may completely overlap with the first electrode (RME1) and may be disposed from the light-emitting region (EMA) beyond the bank layer (BNL) to a sub-region (SA). The second connecting electrode (CNE2) may have a shape extending in a first direction (DR1) and may be disposed on a second electrode (RME1) or a second bank pattern (BP). The second connecting electrode (CNE2) may partially overlap with the second electrode (RME2) and may be disposed from the light-emitting region (EMA) beyond the bank layer (BNL) to a sub-region (SA).

[0064] FIG. 3 is a cross-sectional view taken along the line E1-E1' of FIG. 2. FIG. 4 is a cross-sectional view taken along the line E2-E2' of FIG. 2. FIG. 3 illustrates a cross-section across both ends of a light-emitting element (ED) placed in a first subpixel (SPX1) and electrode contact holes (CTD, CTS), and FIG. 4 illustrates a cross-sectional view across both ends of a light-emitting element (ED) placed in a first subpixel (SPX1) and contact portions (CT1, CT2).

[0065] Referring to FIGS. 2 to 4, the cross-sectional structure of the display device (10) is described as follows: the display device (10) may include a first substrate (SUB), a semiconductor layer disposed thereon, a plurality of conductive layers, and a plurality of insulating layers. Additionally, the display device (10) may include a plurality of electrodes (RME: RME1, RME2), a light-emitting element (ED), and a connecting electrode (CNE: CNE1, CNE2). The semiconductor layer, the conductive layer, and the insulating layer may each constitute a circuit layer of the display device (10).

[0066] The first substrate (SUB) may be an insulating substrate. The first substrate (SUB) may be made of an insulating material such as glass, quartz, or a polymer resin. Additionally, the first substrate (SUB) may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc. The first substrate (SUB) includes a display area (DPA) and a non-display area (NDA) surrounding it, and the display area (DPA) may include a light-emitting area (EMA) and a sub-area (SA) which is a part of the non-light-emitting area.

[0067] The first conductive layer may be disposed on the first substrate (SUB). The first conductive layer may include a lower metal layer (BML), a first voltage line (VL1), and a second voltage line (VL2). The lower metal layer (BML) is disposed to overlap with the active layer (ACT1) of the first transistor (T1). The lower metal layer (BML) may perform the function of preventing light from being incident on the first active layer (ACT1) of the first transistor, or electrically connecting to the first active layer (ACT1) to stabilize the electrical characteristics of the first transistor (T1). However, the lower metal layer (BML) may be omitted.

[0068] A high potential voltage (or a first power supply voltage) delivered to the first electrode (RME1) may be applied to the first voltage wiring (VL1), and a low potential voltage (or a second power supply voltage) delivered to the second electrode (RME2) may be applied to the second voltage wiring (VL2). The first voltage wiring (VL1) may be electrically connected to the first transistor (T1) through a conductive pattern of the third conductive layer (e.g., a third conductive pattern (CDP)). The second voltage wiring (VL2) may be electrically connected to the second electrode (RME2) through a conductive pattern of the third conductive layer (e.g., a second conductive pattern (CDP)).

[0069] In the drawings, the first voltage line (VL1) and the second voltage line (VL2) are illustrated as being disposed in the first conductive layer, but are not limited thereto. In some embodiments, the first voltage line (VL1) and the second voltage line (VL2) may be disposed in the third conductive layer and directly electrically connected to the first transistor (T1) and the second electrode (RME2), respectively.

[0070] A buffer layer (BL) may be disposed on a first conductive layer and a first substrate (SUB). The buffer layer (BL) is formed on the first substrate (SUB) to protect the transistors of the pixel (PX) from moisture penetrating through the first substrate (SUB), which is susceptible to moisture permeability, and can perform a surface planarization function.

[0071] The semiconductor layer is disposed on the buffer layer (BL). The semiconductor layer may include a first active layer (ACT1) of the first transistor (T1) and a second active layer (ACT2) of the second transistor (T2). The first active layer (ACT1) and the second active layer (ACT2) may be disposed to partially overlap with the first gate electrode (G1) and the second gate electrode (G2) of the second conductive layer, respectively, which will be described later.

[0072] The semiconductor layer may include polycrystalline silicon, single-crystal silicon, oxide semiconductors, etc. In another embodiment, the semiconductor layer may include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium tin oxide (IGTO), indium gallium zinc oxide (IGZO), and indium gallium zinc tin oxide (IGZTO).

[0073] In the drawing, a first transistor (T1) is illustrated in the subpixel (SPXn) of the display device (10), but the display device (10) is not limited thereto and may include a larger number of transistors.

[0074] The first gate insulating layer (GI) is disposed on the semiconductor layer in the display area (DPA). The first gate insulating layer (GI) can serve as the gate insulating film for each transistor (T1, T2). In the drawings, the first gate insulating layer (GI) is illustrated as being patterned together with the gate electrodes (G1, G2) of the second conductive layer described later and partially disposed between the second conductive layer and the active layer (ACT1, ACT2) of the semiconductor layer, but is not limited thereto. In some embodiments, the first gate insulating layer (GI) may be disposed entirely on the buffer layer (BL).

[0075] The second conductive layer is disposed on the first gate insulating layer (GI). The second conductive layer may include a first gate electrode (G1) of the first transistor (T1) and a second gate electrode (G2) of the second transistor (T2). The first gate electrode (G1) may be disposed to overlap the channel region of the first active layer (ACT1) in the third direction (DR3), which is the thickness direction, and the second gate electrode (G2) may be disposed to overlap the channel region of the second active layer (ACT2) in the third direction (DR3), which is the thickness direction. Although not shown in the drawing, the second conductive layer may further include one electrode of the storage capacitor.

[0076] The first interlayer insulating layer (IL1) is disposed on the second conductive layer. The first interlayer insulating layer (IL1) functions as an insulating film between the second conductive layer and other layers disposed thereon, and can protect the second conductive layer.

[0077] A third conductive layer is disposed on the first interlayer insulating layer (IL1). The third conductive layer may include a plurality of conductive patterns (CDP1, CDP2, CDP3) and source electrodes (S1, S2) and drain electrodes (D1, D2) of each transistor (T1, T2). Some of the conductive patterns (CDP1, CDP2, CDP3) electrically connect conductive layers or semiconductor layers of different layers to each other and may serve as source / drain electrodes of transistors (T1, T2).

[0078] The first conductive pattern (CDP1) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The first conductive pattern (CDP1) can contact the lower metal layer (BML) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The first conductive pattern (CDP1) can serve as the first source electrode (S1) of the first transistor (T1). The first conductive pattern (CDP1) can be electrically connected to the first electrode (RME1) or the first connection electrode (CNE1). The first transistor (T1) can transmit the first power supply voltage applied from the first voltage wiring (VL1) to the first electrode (RME1) or the first connection electrode (CNE1).

[0079] The second conductive pattern (CDP2) can contact the second voltage wiring (VL2) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). The second conductive pattern (CDP2) can be electrically connected to the first electrode (RME1) or the first connecting electrode (CNE1). The second voltage wiring (VL2) can transmit the second power supply voltage to the second electrode (RME2) or the second connecting electrode (CNE2).

[0080] The third conductive pattern (CDP3) can contact the first voltage wiring (VL1) through a contact hole penetrating the first interlayer insulating layer (IL1) and the buffer layer (BL). Additionally, the third conductive pattern (CDP3) can contact the first active layer (ACT1) of the first transistor (T1) through a contact hole penetrating the first interlayer insulating layer (IL1). The third conductive pattern (CDP3) electrically connects the first voltage wiring (VL1) to the first transistor (T1) and can serve as the first drain electrode (D1) of the first transistor (T1).

[0081] The second source electrode (S2) and the second drain electrode (D2) can each contact the second active layer (ACT2) of the second transistor (T2) through a contact hole penetrating the first interlayer insulating layer (IL1). The second transistor (T2) can transmit a data signal to the first transistor (T1) or transmit an initialization signal.

[0082] The first protective layer (PV1) is disposed on the third conductive layer. The first protective layer (PV1) functions as an insulating film between the third conductive layer and other layers and can protect the third conductive layer.

[0083] The above-described buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be composed of a plurality of inorganic layers stacked alternately. For example, the buffer layer (BL), first gate insulating layer (GI), first interlayer insulating layer (IL1), and first protective layer (PV1) may be silicon oxide (SiO₂). x ), Silicon Nitride (SiN x ), Silicon Oxynitride (SiO₂ x N y It may be formed into a double layer in which an inorganic layer comprising at least one of ) is stacked, or a multilayer in which the same is stacked alternately. However, it is not limited thereto, and the buffer layer (BL), the first gate insulating layer (GI), the first interlayer insulating layer (IL1), and the first protective layer (PV1) may be formed into a single inorganic layer including the insulating material described above. In addition, in some embodiments, the first interlayer insulating layer (IL1) may be made of an organic insulating material such as polyimide (PI).

[0084] The fourth conductive layer may be disposed on the first protective layer (PV1). The fourth conductive layer may include a floating electrode (FE). The floating electrode (FE) may be an electrode with an island pattern to which no voltage is applied. That is, the floating electrode (FE) may be electrically floating.

[0085] In the drawings, the floating electrode (FE) is illustrated as being disposed in the fourth conductive layer, but is not limited thereto. In some embodiments, the floating electrode (FE) may be disposed in any one of the first to third conductive layers.

[0086] A via layer (VIA) is disposed on the fourth conductive layer in the display area (DPA). The via layer (VIA) may include an organic insulating material, such as polyimide (PI), to compensate for the step difference caused by the underlying conductive layers and to form a flat upper surface. However, in some embodiments, the via layer (VIA) may be omitted.

[0087] A display device (10) may include a display element layer disposed on a via layer (VIA), bank patterns (BP1, BP2), a plurality of electrodes (RME: RME1, RME2), a bank layer (BNL), a plurality of light-emitting elements (ED), and a plurality of connecting electrodes (CNE: CNE1, CNE2). Additionally, the display device (10) may include insulating layers (PAS1, PAS2, PAS3) disposed on the via layer (VIA).

[0088] Multiple bank patterns (BP1, BP2) may be disposed on a via layer (VIA). For example, bank patterns (BP1, BP2) may be disposed directly on the via layer (VIA) and may have a structure in which at least a portion protrudes with respect to the upper surface of the via layer (VIA). The protruding portion of the bank patterns (BP1, BP2) may have a side that is inclined or bent with a certain curvature, and light emitted from the light-emitting element (ED) may be reflected from the electrode (RME) disposed on the bank patterns (BP1, BP2) and emitted in the direction of the upper side of the via layer (VIA). Unlike as illustrated in the drawings, the bank patterns (BP1, BP2) may have a shape in which the outer surface in the cross-sectional view is bent with a certain curvature, such as a semicircle or a semi-ellipse. The bank patterns (BP1, BP2) may include an organic insulating material such as polyimide (PI), but are not limited thereto.

[0089] A plurality of electrodes (RME: RME1, RME2) may be disposed on bank patterns (BP1, BP2) and via layers (VIA). For example, the first electrode (RME1) and the second electrode (RME2) may be disposed on at least the inclined side of the bank patterns (BP1, BP2). The first electrode (RME1) may be disposed on a via layer (VIA) located between the bank patterns (BP1, BP2). The second electrode (RME2) may not be disposed on a via layer (VIA) located between the bank patterns (BP1, BP2). The width of the plurality of electrodes (RME) measured in the second direction (DR2) may be smaller than the width of the bank pattern (BP1, BP2) measured in the second direction (DR2), and the spacing between the first electrode (RME1) and the second electrode (RME2) in the second direction (DR2) may be narrower than the spacing between the bank patterns (BP1, BP2). At least some regions of the first electrode (RME1) and the second electrode (RME2) may be placed directly on the via layer (VIA) so that they may be placed on the same plane.

[0090] According to one embodiment, a separation region (SP) (or separation space) separating the first electrode (RME1) and the second electrode (RME2) may be disposed between them. The separation region (SP) may be formed by removing or penetrating at least a portion of the electrodes (RME1, RME2). For example, the electrodes (RME1, RME2) may be separated into the first electrode (RME1) and the second electrode (RME2) by etching the electrode disposed in the separation region (SP) after they have been deposited on the bank pattern (BP1, BP2) and the via layer (VIA). A portion of the via layer (VIA) and the bank pattern (BP1, BP2) may be exposed by the separation region (SP).

[0091] For example, a spacing region (SP) may be formed to the right of the light-emitting element (ED). The spacing region (SP) may be positioned closer to the second bank pattern (BP2) than to the first bank pattern (BP1). The spacing region (SP) may expose at least a portion of the side of the via layer (VIA) and the second bank pattern (BP2).

[0092] A light-emitting element (ED) placed between bank patterns (BP1, BP2) emits light in both end directions, and the emitted light can be directed toward an electrode (RME) placed on the bank patterns (BP1, BP2). Each electrode (RME) may have a structure in which the portion placed on the bank patterns (BP1, BP2) can reflect the light emitted from the light-emitting element (ED). The first electrode (RME1) and the second electrode (RME2) are placed to cover at least the sides of the bank patterns (BP1, BP2) so as to reflect the light emitted from the light-emitting element (ED).

[0093] Each electrode (RME) can directly contact the third conductive layer through electrode contact holes (CTD, CTS) in the portion overlapping with the bank layer (BNL) between the light-emitting region (EMA) and the sub-region (SA). The first electrode contact hole (CTD) may be formed in the area where the bank layer (BNL) and the first electrode (RME1) overlap, and the second electrode contact hole (CTS) may be formed in the area where the bank layer (BNL) and the second electrode (RME2) overlap. The first electrode (RME1) can contact the first conductive pattern (CDP1) through the first electrode contact hole (CTD) penetrating the via layer (VIA) and the first protective layer (PV1). The second electrode (RME2) can contact the second voltage wiring (VL2) through the second electrode contact hole (CTS) penetrating the via layer (VIA) and the first protective layer (PV1). The first electrode (RME1) may be electrically connected to the first transistor (T1) through the first conductive pattern (CDP1) to apply the first power supply voltage, and the second electrode (RME2) may be electrically connected to the second voltage wiring (VL2) to apply the second power supply voltage. However, it is not limited thereto. In other embodiments, each electrode (RME1, RME2) may not be electrically connected to the voltage wiring (VL1, VL2) of the third conductive layer, and the connecting electrode (CNE) described below may be directly connected to the third conductive layer.

[0094] Multiple electrodes (RMEs) may include a highly reflective conductive material. For example, the electrodes (RMEs) may include a metal such as silver (Ag), copper (Cu), aluminum (Al), an alloy such as aluminum (Al), nickel (Ni), lanthanum (La), or a structure in which a metal layer such as titanium (Ti), molybdenum (Mo), and niobium (Nb) is stacked with said alloy. In some embodiments, the electrodes (RMEs) may be composed of a double layer or a multilayer structure in which an alloy containing aluminum (Al) and at least one metal layer consisting of titanium (Ti), molybdenum (Mo), and niobium (Nb) are stacked.

[0095] Each electrode (RME) may further include a transparent conductive material, without being limited thereto. For example, each electrode (RME) may include a material such as ITO, IZO, ITZO, etc. In some embodiments, each electrode (RME) may have a structure in which a transparent conductive material and a highly reflective metal layer are each stacked one or more times, or may be formed as a single layer including these. For example, each electrode (RME) may have a stacked structure such as ITO / Ag / ITO / , ITO / Ag / IZO, or ITO / Ag / ITZO / IZO. The electrodes (RME) are electrically connected to a light-emitting element (ED) and may reflect some of the light emitted from the light-emitting element (ED) toward the upper direction of the first substrate (SUB).

[0096] According to one embodiment, the separation region (SP) separating the electrodes (RME) is not positioned at the center between the bank patterns (BP1, BP2) but is positioned off-center, thereby minimizing the proportion of light directed downward among the light emitted from the light-emitting element (ED). For example, the separation region (SP) is positioned off-center to the second bank pattern (BP2) and adjacent to one end of the light-emitting element (ED), and the first electrode (RME1) overlaps the center of the light-emitting element (ED), so that the light directed downward among the light emitted from the light-emitting element (ED) can be reflected upward. A detailed explanation regarding this will be provided later with reference to other drawings.

[0097] The first insulating layer (PAS1) is disposed on the front surface of the display area (DPA) and may be disposed on a via layer (VIA) and a plurality of electrodes (RME). The first insulating layer (PAS1) may be disposed to fill a spaced area (SP) formed by the plurality of electrodes (RME). The first insulating layer (PAS1) may include an insulating material to protect the plurality of electrodes (RME) while simultaneously insulating different electrodes (RME) from each other. Since the first insulating layer (PAS1) is disposed to cover the electrodes (RME) before the bank layer (BNL) is formed, the electrodes (RME) may be prevented from being damaged during the process of forming the bank layer (BNL). Additionally, the first insulating layer (PAS1) may prevent the light-emitting element (ED) disposed thereon from being damaged by direct contact with other components.

[0098] The first insulating layer (PAS1) may include contact portions (CT1, CT2) disposed in a sub-region (SA). The contact portions (CT1, CT2) may each be disposed to overlap with different electrodes (RME). For example, the contact portions (CT1, CT2) may include first contact portions (CT1) disposed to overlap with the first electrode (RME1), and second contact portions (CT2) disposed to overlap with the second electrode (RME2). The first contact portions (CT1) and the second contact portions (CT2) may penetrate the first insulating layer (PAS1) to expose a portion of the upper surface of the first electrode (RME1) or the second electrode (RME2) below it. The first contact portions (CT1) and the second contact portions (CT2) may each further penetrate some of the other insulating layers disposed on the first insulating layer (PAS1). The electrode (RME) exposed by each contact part (CT1, CT2) can come into contact with the connecting electrode (CNE).

[0099] As will be described later, the first insulating layer (PAS1) may have a step formed so that a portion of its upper surface is sunken in the part overlapping with the first electrode (RME1), or the entire upper surface may be removed. The area where all or part of the first insulating layer (PAS1) is exposed may form a strong electric field in response to an electrical signal.

[0100] A bank layer (BNL) may be disposed on a first insulating layer (PAS1). The bank layer (BNL) may include a portion extending in a first direction (DR1) and a second direction (DR2) and may surround each subpixel (SPXn). The bank layer (BNL) may surround and distinguish the light-emitting region (EMA) and sub-region (SA) of each subpixel (SPXn), and may surround the outermost edge of the display region (DPA) and distinguish the display region (DPA) from the non-display region (NDA).

[0101] The bank layer (BNL) may have a certain height similar to the bank pattern (BP1, BP2). In some embodiments, the height of the upper surface of the bank layer (BNL) may be higher than that of the bank pattern (BP1, BP2), and its thickness may be equal to or greater than that of the bank pattern (BP1, BP2). The bank layer (BNL) can prevent ink from overflowing into adjacent subpixels (SPXn) during the inkjet printing process in the manufacturing process of the display device (10). The bank layer (BNL) may include an organic insulating material such as polyimide, similar to the bank pattern (BP1, BP2).

[0102] A plurality of light-emitting elements (EDs) may be disposed in a light-emitting region (EMA). The light-emitting elements (EDs) may be disposed on a first insulating layer (PAS1) between bank patterns (BP1, BP2). The light-emitting elements (EDs) may be disposed such that one extended direction is parallel to the upper surface of the first substrate (SUB). As described below, the light-emitting elements (EDs) may include a plurality of semiconductor layers disposed along the one extended direction, and the plurality of semiconductor layers may be sequentially disposed along a direction parallel to the upper surface of the first substrate (SUB). However, not limited thereto, if the light-emitting elements (EDs) have a different structure, the plurality of semiconductor layers may be disposed in a direction perpendicular to the first substrate (SUB).

[0103] The light-emitting elements (EDs) placed in each subpixel (SPXn) can emit light of different wavelengths depending on the material of the semiconductor layer described above. However, not limited thereto, the light-emitting elements (EDs) placed in each subpixel (SPXn) may include a semiconductor layer of the same material and emit light of the same color.

[0104] The light-emitting elements (EDs) can be electrically connected to the conductive layers under the electrode (RME) and via layer (VIA) by contacting the connecting electrodes (CNE), and can emit light of a specific wavelength range when an electrical signal is applied.

[0105] A second insulating layer (PAS2) may be disposed on a plurality of light-emitting elements (ED), a first insulating layer (PAS1), and a bank layer (BNL). The second insulating layer (PAS2) includes a pattern portion that extends in a first direction (DR1) between bank patterns (BP1, BP2) and is disposed on a plurality of light-emitting elements (ED). The pattern portion is disposed to partially cover the outer surface of the light-emitting element (ED), and may not cover both sides or both ends of the light-emitting element (ED). The pattern portion may form a linear or island pattern within each subpixel (SPXn) in a planar view. The pattern portion of the second insulating layer (PAS2) can protect the light-emitting element (ED) and, at the same time, fix the light-emitting element (ED) during the manufacturing process of the display device (10). Additionally, a portion of the second insulating layer (PAS2) may be disposed on the upper part of the bank layer (BNL) and in sub-regions (SA).

[0106] The second insulating layer (PAS2) may include contact portions (CT1, CT2) disposed in a sub-region (SA). The second insulating layer (PAS2) may include a first contact portion (CT1) disposed to overlap with the first electrode (RME1), and a second contact portion (CT2) disposed to overlap with the second electrode (RME2). The contact portions (CT1, CT2) may penetrate the second insulating layer (PAS2) in addition to the first insulating layer (PAS1). A plurality of first contact portions (CT1) and second contact portions (CT2) may each expose a portion of the upper surface of the first electrode (RME1) or the second electrode (RME2) below them.

[0107] A plurality of connecting electrodes (CNE: CNE1, CNE2) may be disposed on a plurality of electrodes (RME) and bank patterns (BP1, BP2). A first connecting electrode (CNE1) may be disposed on a first electrode (RME1) and a first bank pattern (BP1). The first connecting electrode (CNE1) may partially overlap with the first electrode (RME1) and may be disposed from the light-emitting region (EMA) beyond the bank layer (BNL) to a sub-region (SA). In one embodiment, a second connecting electrode (CNE2) may be disposed on a second electrode (RME2), a second bank pattern (BP2), and a first electrode (RME1). The second connecting electrode (CNE2) may partially overlap with the first electrode (RME1) and the second electrode (RME2) and may be disposed from the light-emitting region (EMA) beyond the bank layer (BNL) to a sub-region (SA). In addition, the second connecting electrode (CNE2) can overlap with the separation area (SP).

[0108] The first connecting electrode (CNE1) and the second connecting electrode (CNE2) are each disposed on the second insulating layer (PAS2) and can come into contact with light-emitting elements (EDs). The first connecting electrode (CNE1) partially overlaps with the first electrode (RME1) and can come into contact with the first end of the light-emitting elements (EDs). The second connecting electrode (CNE2) partially overlaps with the second electrode (RME2) and can come into contact with the second end of the light-emitting elements (EDs). A plurality of connecting electrodes (CNEs) are disposed across the light-emitting region (EMA) and the sub-region (SA). The connecting electrodes (CNEs) can come into contact with the light-emitting elements (EDs) in the portion disposed in the light-emitting region (EMA) and can be electrically connected to the third conductive layer in the portion disposed in the sub-region (SA).

[0109] According to one embodiment, the display device (10) may have each connecting electrode (CNE) in contact with an electrode (RME) through contact portions (CT1, CT2) disposed in a sub-region (SA). The first connecting electrode (CNE1) may be in contact with the first electrode (RME1) through a first contact portion (CT1) that penetrates the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) in the sub-region (SA). The second connecting electrode (CNE2) may be in contact with the second electrode (RME2) through a second contact portion (CT2) that penetrates the first insulating layer (PAS1) and the second insulating layer (PAS2) in the sub-region (SA). Each connecting electrode (CNE) may be electrically connected to the third conductive layer through each electrode (RME). The first connecting electrode (CNE1) is electrically connected to the first transistor (T1) so that the first power supply voltage is applied, and the second connecting electrode (CNE2) is electrically connected to the second voltage wiring (VL2) so that the second power supply voltage can be applied. Each connecting electrode (CNE) can contact the light-emitting element (ED) in the light-emitting region (EMA) to transmit the power supply voltage to the light-emitting element (ED).

[0110] However, it is not limited thereto. In some embodiments, a plurality of connecting electrodes (CNE) may be in direct contact with the third conductive layer, or may be electrically connected to the third conductive layer through patterns other than the electrodes (RME).

[0111] Connecting electrodes (CNEs) may include a conductive material. For example, they may include ITO, IZO, ITZO, aluminum (Al), etc. As an example, the connecting electrode (CNE) may include a transparent conductive material, and light emitted from the light-emitting element (ED) may pass through the connecting electrode (CNE) and be emitted.

[0112] A third insulating layer (PAS3) is disposed on the second connecting electrode (CNE2) of the first connecting electrode layer and on the second insulating layer (PAS2). The third insulating layer (PAS3) is disposed entirely on the second insulating layer (PAS2) to cover the second connecting electrode (CNE2), and the first connecting electrode (CNE1) of the second connecting electrode layer may be disposed on the third insulating layer (PAS3). The third insulating layer (PAS3) can insulate the first connecting electrode (CNE1) from the second connecting electrode (CNE2) so that they do not come into direct contact with each other.

[0113] The third insulating layer (PAS3) may include first contact portions (CT1) disposed in a sub-region (SA). The first contact portions (CT1) may penetrate the third insulating layer (PAS3) in addition to the first insulating layer (PAS1) and the second insulating layer (PAS2). A plurality of first contact portions (CT1) may expose a portion of the upper surface of the first electrode (RME1) below them.

[0114] Although not illustrated in the drawings, other insulating layers may be disposed on the third insulating layer (PAS3) and the first connecting electrode (CNE1). The insulating layers may function to protect the members disposed on the first substrate (SUB) from the external environment.

[0115] The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) described above may each comprise an inorganic insulating material or an organic insulating material. For example, the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each comprise an inorganic insulating material, or the first insulating layer (PAS1) and the third insulating layer (PAS3) may comprise an inorganic insulating material, while the second insulating layer (PAS2) may comprise an organic insulating material. The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each, or at least one of them, be formed in a structure in which a plurality of insulating layers are stacked alternately or repeatedly. In an exemplary embodiment, the first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may each be silicon oxide (SiO₂). x ), silicon nitride (SiN x ), and silicon oxynitride (SiO₂ x N y It may be any one of the following. The first insulating layer (PAS1), the second insulating layer (PAS2), and the third insulating layer (PAS3) may be made of the same material, some of which may be made of the same material and some of which may be made of different material, or each of which may be made of different material.

[0116] FIG. 5 is a schematic diagram of a light-emitting element according to one embodiment.

[0117] Referring to FIG. 5, the light-emitting element (ED) may be a light-emitting diode, and specifically, the light-emitting element (ED) may be an inorganic light-emitting diode made of inorganic material having a size in the nanometer to micrometer range. The light-emitting element (ED) may be aligned between two electrodes that form polarity when an electric field is formed in a specific direction between the two electrodes facing each other.

[0118] A light-emitting element (ED) according to one embodiment may have a shape that extends in one direction. The light-emitting element (ED) may have a shape such as a cylinder, a rod, a wire, or a tube. However, the shape of the light-emitting element (ED) is not limited thereto, and the light-emitting element (ED) may have various shapes, such as a polygonal prism shape like a cube, a rectangular prism, or a hexagonal prism, or a shape that extends in one direction but has a partially inclined outer surface.

[0119] The light-emitting element (ED) may include a semiconductor layer doped with any conductivity type (e.g., p-type or n-type) dopant. The semiconductor layer may emit light of a specific wavelength range when an electrical signal applied from an external power source is transmitted. The light-emitting element (ED) may include a first semiconductor layer (31), a second semiconductor layer (32), a light-emitting layer (36), an electrode layer (37), and an insulating film (38).

[0120] The first semiconductor layer (31) may be an n-type semiconductor. The first semiconductor layer (31) is Al x Ga y In 1-x-y It may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the first semiconductor layer (31) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer (31) may be Si, Ge, Sn, Se, etc.

[0121] The second semiconductor layer (32) is disposed on the first semiconductor layer (31) with the light-emitting layer (36) in between. The second semiconductor layer (32) may be a p-type semiconductor, and the second semiconductor layer (32) is Al x Ga y In 1-x-yIt may include a semiconductor material having the chemical formula N (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the second semiconductor layer (32) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer (32) may be Mg, Zn, Ca, Ba, etc.

[0122] Meanwhile, the drawing shows the first semiconductor layer (31) and the second semiconductor layer (32) as being composed of a single layer, but is not limited thereto. Depending on the material of the light-emitting layer (36), the first semiconductor layer (31) and the second semiconductor layer (32) may further include a greater number of layers, such as a clad layer or a TSBR (Tensile strain barrier reducing) layer. For example, the light-emitting device (ED) may further include other semiconductor layers disposed between the first semiconductor layer (31) and the light-emitting layer (36), or between the second semiconductor layer (32) and the light-emitting layer (36). The semiconductor layer disposed between the first semiconductor layer (31) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN, InN and SLs doped with an n-type dopant, and the semiconductor layer disposed between the second semiconductor layer (32) and the light-emitting layer (36) may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with a p-type dopant.

[0123] The light-emitting layer (36) is disposed between the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include a material having a single or multiple quantum well structure. If the light-emitting layer (36) includes a material having a multiple quantum well structure, it may have a structure in which a quantum layer and a well layer are alternately stacked in multiple layers. The light-emitting layer (36) can emit light by the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (31) and the second semiconductor layer (32). The light-emitting layer (36) may include materials such as AlGaN, AlGaInN, InGaN, etc. In particular, if the light-emitting layer (36) has a structure in which quantum layers and well layers are alternately stacked in a multiple quantum well structure, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN.

[0124] The light-emitting layer (36) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, and may include different group 3 to group 5 semiconductor materials depending on the wavelength range of the light emitted. The light emitted by the light-emitting layer (36) is not limited to light in the blue wavelength range, and may emit light in the red or green wavelength range depending on the case.

[0125] The electrode layer (37) may be an ohmic connection electrode. However, it is not limited thereto and may be a Schottky connection electrode. The light-emitting element (ED) may include at least one electrode layer (37). The light-emitting element (ED) may include one or more electrode layers (37), but is not limited thereto and the electrode layer (37) may be omitted.

[0126] The electrode layer (37) can reduce the resistance between the light-emitting element (ED) and the electrode or connecting electrode when the light-emitting element (ED) in the display device (10) is electrically connected to the electrode or connecting electrode. The electrode layer (37) may include a conductive metal. For example, the electrode layer (37) may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0127] The insulating film (38) is arranged to surround the outer surface of the plurality of semiconductor layers and electrode layers described above. For example, the insulating film (38) may be arranged to surround the outer surface of at least the light-emitting layer (36), but may be formed so that both ends in the longitudinal direction of the light-emitting element (ED) are exposed. Additionally, in the region adjacent to at least one end of the light-emitting element (ED), the upper surface of the insulating film (38) may have a cross-sectional shape that is round, semicircular, or semi-elliptical.

[0128] The insulating film (38) is made of materials having insulating properties, for example, silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon oxynitride (SiO₂ x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ), and titanium oxide (TiO₂ x It may include at least one of ). In the drawings, the insulating film (38) is illustrated as being formed as a single layer, but is not limited thereto, and in some embodiments, the insulating film (38) may be formed as a multilayer structure in which a plurality of layers are stacked.

[0129] The insulating film (38) can perform the function of protecting the semiconductor layers and electrode layers of the light-emitting element (ED). The insulating film (38) can prevent an electrical short circuit that may occur in the light-emitting layer (36) when in direct contact with the electrode through which an electrical signal is transmitted to the light-emitting element (ED). In addition, the insulating film (38) can prevent a decrease in the light-emitting efficiency of the light-emitting element (ED).

[0130] In one embodiment, the light-emitting element (ED) may have a first end (E1) in which an electrode layer (37) is disposed, and a second end (E2) in which a first semiconductor layer (31) is disposed and which faces the first end (E1) in a third direction (DR3).

[0131] FIG. 6 is an example of an enlarged cross-sectional view of a portion in which a light-emitting element is placed in one embodiment. FIG. 7 is another example of an enlarged cross-sectional view of a portion in which a light-emitting element is placed in one embodiment.

[0132] Referring to FIGS. 6 and 7, a first end (E1) of a light-emitting element (ED) may be positioned adjacent to a first bank pattern (BP1), and a second end (E2) may be positioned adjacent to a second bank pattern (BP2). The light-emitting element (ED) may be positioned in a shape extending in a second direction (DR2) in a display device (10). In the display device (10), a first electrode (RME1) and a second electrode (RME2) may be positioned spaced apart in a second direction (DR2) with a spaced-out area (SP) in between, and the semiconductor layer (31, 32), light-emitting layer (36), and electrode layer (37) of the light-emitting element (ED) may be positioned sequentially in the second direction (DR2). More specifically, the light-emitting element (ED) may have an electrode layer (37), a second semiconductor layer (32), a light-emitting layer (36), and a first semiconductor layer (31) formed sequentially in a second direction (DR2).

[0133] A separation region (SP) may be formed to separate the first electrode (RME1) and the second electrode (RME2). The separation region (SP) may be positioned offset to one side of the bank patterns (BP1, BP2). For example, the separation region (SP) may be positioned offset to the side of the second bank pattern (BP2). The separation region (SP) may expose at least a portion of the side of the second bank pattern (BP2) and the upper surface of the via layer (VIA). The separation region (SP) may be positioned to the right of the center of the light-emitting element (ED).

[0134] Among the electrodes (RME1, RME2) separated by a separation region (SP), the first electrode (RME1) may have one end disposed on the upper surface of the via layer (VIA), and the second electrode (RME2) may have one end disposed on the side of the second bank pattern (BP2). According to one embodiment, the minimum distance (H1) between one end of the first electrode (RME1) and the lower surface of the via layer (VIA) (or the first substrate (SUB)) may be shorter than the minimum distance (H2) between one end of the second electrode (RME2) and the lower surface of the via layer (VIA) (or the first substrate (SUB)).

[0135] The first insulating layer (PAS1) is disposed on a via layer (VIA) and a plurality of electrodes (RME), and may be disposed to fill a spaced-out area (SP) formed by the plurality of electrodes (RME). The first insulating layer (PAS1) may be in direct contact with the side of the second bank pattern (BP2) and the upper surface of the via layer (VIA). In the drawings, the first insulating layer (PAS1) is illustrated as having no step in the spaced-out area (SP), but is not limited thereto. In some embodiments, the first insulating layer (PAS1) may have a step formed such that a portion of the upper surface is recessed in the spaced-out area (SP).

[0136] The first insulating layer (PAS1) may include an opening formed in an area where part or all of the upper surface is removed in a portion overlapping with the first electrode (RME1). For example, the first insulating layer (PAS1) may include a first opening (OP1) in which a portion of the upper surface of the first insulating layer (PAS1) is removed and the side and upper surfaces are exposed. The first opening (OP1) is positioned offset from the first bank pattern (BP1) and, unlike the spaced-out area (SP), may be positioned to the left of the center of the light-emitting element (ED). Accordingly, during the alignment process of the light-emitting element (ED) described later, the electric field of the first electrode (RME1) portion overlapping with the exposed first opening (OP1) of the first insulating layer (PAS1) may be strengthened. The light-emitting element (ED) can be aligned to the center of the light-emitting region (EMA) by the enhanced electric field of the first electrode (RME1) portion and the electric field of one end of the second electrode (RME1) near the separation region (SP).

[0137] A first end (E1) of a light-emitting element (ED) is positioned adjacent to a first opening (OP1) and may be positioned on a first electrode (RME1). The first end (E1) of the light-emitting element (ED) may be positioned adjacent to a first electrode (RME1) to which a high potential voltage (or a first power supply voltage) is applied, and a second end (E2) may be positioned adjacent to a second electrode (RME2) to which a low potential voltage (or a second power supply voltage) is applied. For example, referring to FIG. 6, the first end (E1) may overlap with the first electrode (RME1) and the first opening (OP1). An electrode layer (37) corresponding to the first end (E1) may overlap with the first opening (OP1). As another example, referring to FIG. 7, the first end (E1) may overlap with the first electrode (RME1) without overlapping with the first opening (OP1).

[0138] The second end (E2) of the light-emitting element (ED) may be positioned adjacent to the spacing region (SP). The second end (E2) may not overlap with the first electrode (RME1) and the second electrode (RME2). For example, referring to FIG. 6, the second end (E2) may be positioned in the spacing region (SP). That is, the first semiconductor layer (31) corresponding to the second end (E2) may be positioned in the spacing region (SP). For another example, referring to FIG. 7, the second end (E2) may be positioned on the first electrode (RME1).

[0139] Most of the semiconductor layers of the light-emitting element (ED) can overlap with the first electrode (RME1). The second semiconductor layer (32) and the light-emitting layer (36) of the light-emitting element (ED), and a portion of the first semiconductor layer (31) can overlap with the first electrode (RME1). The center of the light-emitting element (ED) can overlap with the first electrode (RME1). In one embodiment, the first distance (L1) between the first end (E1) of the light-emitting element (ED) and one end of the first electrode (RME1) may be longer than the second distance (L2) between the second end (E2) and one end of the first electrode (RME1).

[0140] A floating electrode (FE) disposed on the first protective layer (PV1) can be formed in an area that overlaps at least partially with the separation area (SP). The floating electrode (FE) can prevent the light-emitting element (ED) from being misaligned to the right rather than centered due to a strong electric field formed between one end of the first electrode (RME1) and one end of the second electrode (RME2). That is, the floating electrode (FE) can weaken the electric field formed between one end of the first electrode (RME1) and one end of the second electrode (RME2).

[0141] The first connecting electrode (CNE1) contacts the first end (E1) of the light-emitting element (ED) on the first insulating layer (PAS1), and the second connecting electrode (CNE2) can contact the second end (E2) of the light-emitting element (ED). The first connecting electrode (CNE1) can overlap with the first electrode (RME1) and can be placed within the first opening (OP1). The second connecting electrode (CNE2) can overlap with the first electrode (RME1) and the second electrode (RME2), and can overlap with the spaced-out region (SP).

[0142] FIG. 8 is a conceptual diagram showing the direction of light emission of a light-emitting element in one embodiment. FIG. 8 schematically illustrates light being emitted from a light-emitting element (ED) of a display device (10).

[0143] Referring to FIG. 8, the emitted light emitted from the light-emitting element (ED) can be generated in the light-emitting layer (36) of the light-emitting element (ED) and emitted in random directions. Among the emitted light, the first emitted light (EL1) can pass through the insulating film (38), the second insulating layer (PAS2), the connecting electrode (CNE1, CNE2), and the third insulating layer (PAS3) from the light-emitting layer (36) and be directed upward. Another portion of the emitted light can be emitted from both ends of the light-emitting element (ED) and directed toward the electrodes (RME1, RME2) on the bank pattern (BP1, BP2).

[0144] Among the emitted light, the second emitted light (EL2) and the third emitted light (EL3) can be emitted to the bottom of the light-emitting element (ED). The second emitted light (EL2) can pass through the insulating film (38) from the light-emitting layer (36) of the light-emitting element (ED) and be directed toward the first substrate (SUB). In one embodiment, since the separation region (SP) is positioned far away from the light-emitting layer (36) of the light-emitting element (ED), the amount of light from the second emitted light (EL2) emitted from the light-emitting element (ED) and directed toward the first substrate (SUB) through the separation region (SP) can be reduced. That is, the proportion of light emitted downward can be minimized.

[0145] The third emitted light (EL3) can be emitted downward from the light-emitting element (ED) and reflected from the first electrode (RME1). Since the first electrode (RME1) functions as a reflective electrode that reflects incident light, the third emitted light (EL3) incident on the first electrode (RME1) can be reflected from the first electrode (RME1) and emitted upward. That is, as the first electrode (RME1) placed in the center of the bank patterns (BP1, BP2) performs the function of a reflective electrode, a recycling effect of the light emitted downward can be achieved.

[0146] The closer the distance between the light-emitting element (ED) and the reflective electrode, the higher the light emission efficiency due to the recycling effect can be. For example, when the distance between the light-emitting element (ED) and the reflective electrode is within 1 μm, the light emission efficiency due to the recycling effect can be increased by approximately 10% or more compared to when the distance is greater than 1 μm. In an exemplary embodiment, the distance between the light-emitting element (ED) and the first electrode (RME1) can be within 1 μm, so the light emission efficiency in the upward direction can be increased.

[0147] In summary, the separation region (SP) separating the electrodes (RME1, RME2) is not positioned at the center of the light-emitting element (ED) but is positioned offset to one end, thereby minimizing the proportion of light directed downward among the light emitted from the light-emitting element (ED). For example, the separation region (SP) may be positioned adjacent to the second end (E2) of the light-emitting element (ED) and positioned far away from the light-emitting layer (36). The first electrode (RME1) may overlap with most of the area of ​​the light-emitting element (ED), including the light-emitting layer (36) of the light-emitting element (ED). Accordingly, the amount of light emitted downward from the light-emitting element (ED) that is emitted downward can be reduced, and the light emitted downward can be reflected upward through the first electrode (RME1). The display device (10) can reduce the loss of light emitted downward and improve the light emission efficiency in the upward direction.

[0148] FIG. 9 is another example of an enlarged cross-sectional view of a portion in which a light-emitting element is placed in one embodiment.

[0149] In a display device (10) according to one embodiment, a first opening (OP1) may be formed to completely remove the upper surface of a first insulating layer (PAS1) in a portion of the area. The first opening (OP1) may expose the side of the first insulating layer (PAS1) and the upper surface of a first electrode (RME1). A first connecting electrode (CNE1) may come into direct contact with the first electrode (RME1) whose upper surface is exposed.

[0150] FIG. 10 is a conceptual diagram illustrating the alignment process of the electric field formed on the first electrode and the second electrode and the light-emitting element in one embodiment. FIG. 10 conceptually illustrates the electric field formed between the first electrode (RME1) and the second electrode (RME2) by applying an electric signal to the first electrode (RME1) and the second electrode (RME2).

[0151] Generally, the electric field density may be highest at the ends (or edges) of the electrodes. For example, the electric field with the highest density may be formed at one end of the first electrode (RME1) and the second electrode (RME2).

[0152] The floating electrode (FE) can weaken the electric field generated at one end of the electrodes (RME1, RME2). The floating electrode (FE) is formed in a portion that overlaps with the spacing region (SP) in the thickness direction and can weaken the strong electric field formed between one end of the first electrode (RME1) and one end of the second electrode (RME2). Accordingly, it is possible to prevent the light-emitting element (ED) from being aligned to one side (e.g., the right) rather than being settled in the center between the bank patterns (BP1, BP2) by the electric field.

[0153] A first opening (OP1) that exposes all or part of the first insulating layer (PAS1) can strengthen the electric field of the first electrode (RME1) that overlaps therewith. Since the first opening (OP1) can form a thinner thickness of the first insulating layer (PAS1) or remove the first insulating layer (PAS1), the electric field of the first electrode (RME1) can be increased in that area. A centrally aligned electric field can be stably formed by the strengthened electric field on the upper surface of the first electrode (RME1) covered by the thin first insulating layer (PAS1) and the weakened electric field on one end of the second electrode (RME1). The light-emitting element (ED) is seated in the center between the bank patterns (BP1, BP2) by the electric field and can prevent alignment off-center.

[0154] Hereinafter, display devices (10_1, 10_2, 10_3) according to other embodiments will be described. In the following embodiments, components identical to those in the previously described embodiments will be referred to by the same reference numerals, and redundant descriptions will be omitted or simplified, with the focus on the differences.

[0155] FIG. 11 is a cross-sectional view of a display device according to another embodiment. FIG. 12 is an enlarged cross-sectional view of a portion in which a light-emitting element is placed in another embodiment.

[0156] Referring to FIGS. 11 and 12, the display device (10_1) according to the present embodiment differs from the previous embodiment in that the spacing region (SP) is formed only in the second bank pattern (BP2), and the first insulating layer (PAS1) further includes a second opening (OP2) that exposes the upper surface of the second electrode (RME2).

[0157] The spacing region (SP) may not be formed on the upper surface of the via layer (VIA) but may be formed on the side of the second bank pattern (BP2). The distance between the spacing region (SP) and the first opening (OP1) may be longer than in the previous embodiment. The first insulating layer (PAS1) arranged to fill the spacing region (SP) may not be in contact with the upper surface of the via layer (VIA) but may be in contact with the side of the second bank pattern (BP2).

[0158] The electrodes (RME1, RME2) may be spaced apart from the side of the second bank pattern (BP2). The first electrode (RME1) may be positioned to cover the entire upper surface of the via layer (VIA) so as to contact the second bank pattern (BP2). The second electrode (RME2) may contact the second bank pattern (BP2) but may not be positioned on the upper surface of the via layer (VIA).

[0159] The first insulating layer (PAS1) may include a first opening (OP1) and a second opening (OP2). The first opening (OP1) is adjacent to the first end (E1) of the light-emitting element (ED) as in the previous embodiment and may expose a portion of the upper surface and side of the first insulating layer (PAS1). The second opening (OP2) may penetrate the first insulating layer (PAS1) and partially expose a second electrode (RME2) disposed on a second bank pattern (BP2). A second connecting electrode (CNE2) may come into contact with the second electrode (RME2) exposed within the second opening (OP2).

[0160] The light-emitting element (ED) can completely overlap with the first electrode (RME1). The electrode layer (37), the second semiconductor layer (32), the light-emitting layer (36), and the first semiconductor layer (31) of the light-emitting element (ED) can completely overlap with the first electrode (RME1). The light-emitting element (ED) can not overlap with the second electrode (RME2).

[0161] The connecting electrodes (CNE1, CNE2) can be in contact with both ends of the light-emitting element (ED) in the same manner as in the previous embodiment. For example, the first connecting electrode (CNE1) can be in contact with the first end (E1), and the second connecting electrode (CNE2) can be in contact with the second end (E2).

[0162] The floating electrode (FE) may partially overlap with the separation region (SP) and may partially overlap with the first electrode (RME1). The floating electrode (FE) may weaken the electric field formed between the first electrode (RME1) and one end of the second electrode (RME1). In one embodiment, the floating electrode (FE) may weaken the electric field between the upper surface of the first electrode (RME1) and one end of the second electrode (RME2) for aligning the light-emitting element (ED) to the center.

[0163] In this embodiment, to prevent the light-emitting element (ED) from being placed in the center of the light-emitting region (EMA) while the electric field between the upper surface of the first electrode (RME1) and one end of the second electrode (RME2) is weakened by the floating electrode (FE), a second opening (OP2) that exposes the upper surface of the second electrode (RME2) may be included. The electric field of the upper surface of the second electrode (RME2) exposed by the second opening (OP2) is strengthened, and a centrally aligned electric field of the light-emitting element (ED) can be formed between the upper surface of the second electrode (RME2) and the upper surface of the first electrode (RME1).

[0164] The display device (10_1) according to the present embodiment can reduce the loss of light emitted in the downward direction of the first substrate (SUB) and improve the light emission efficiency in the upward direction by positioning the spacing region (SP) to be offset to one side of the light-emitting element (ED). In addition, by adjusting the electric field between the first electrode (RME1) and the second electrode (RME2), the light-emitting element (ED) of the display device (10_1) can be aligned to the center of the light-emitting region (EMA) (or the central part between the bank patterns (BP1, BP2).

[0165] FIG. 13 is a cross-sectional view of a display device according to another embodiment. FIG. 14 is an enlarged cross-sectional view of a portion in which a light-emitting element is placed in another embodiment.

[0166] Referring to FIGS. 13 and 14, in the display device (10_2) according to the present embodiment, the separation region (SP) is formed in the via layer (VIA) and the second bank pattern (BP2), and one end of the first electrode (RME1) is disposed on the upper surface of the via layer (VIA), and one end of the second electrode (RME2) is disposed on the side of the second bank pattern (BP2), which is the same as the embodiment of FIGS. 6 to 9. The first insulating layer (PAS2) may further include a third opening (OP3) that exposes a portion of the upper surface of the first electrode (RME1), in addition to a second opening (OP2) that exposes a portion of the upper surface of the second electrode (RME2).

[0167] The first insulating layer (PAS1) may include a first opening (OP1), a second opening (OP2), and a third opening (OP3). The first opening (OP1) is adjacent to the first end (E1) of the light-emitting element (ED) as in the previous embodiment and may expose a portion of the upper surface and side of the first insulating layer (PAS1). The second opening (OP2) may penetrate the first insulating layer (PAS1) and partially expose a second electrode (RME2) placed on the second bank pattern (BP2). The second connecting electrode (CNE2) may contact the second electrode (RME2) exposed within the second opening (OP2). The third opening (OP3) may penetrate the first insulating layer (PAS1) and partially expose a first electrode (RME1) placed on the first bank pattern (BP1). The first connecting electrode (CNE1) can come into contact with the first electrode (RME1) exposed within the third opening (OP3).

[0168] The display device (10_2) according to the present embodiment can reduce the loss of light emitted in the downward direction of the first substrate (SUB) and improve the light emission efficiency in the upward direction by positioning the spacing region (SP) to be offset to one side of the light-emitting element (ED). In addition, by adjusting the electric field between the first electrode (RME1) and the second electrode (RME2), the light-emitting element (ED) of the display device (10) can be aligned to the center of the light-emitting region (EMA) (or the central part between the bank patterns (BP1, BP2).

[0169] FIG. 15 is a cross-sectional view of a display device according to another embodiment. FIG. 16 is an enlarged cross-sectional view of a portion in which a light-emitting element is placed in another embodiment.

[0170] Referring to FIGS. 15 and 16, the display device (10_3) according to the present embodiment differs from the previous embodiment in that the spacing region (SP) is formed only on the second bank pattern (BP2), and a part of the first electrode (RME1) is placed between the via layer (VIA) (or the first substrate (SUB)) and the second bank pattern (BP2). In the present embodiment, instead of the floating electrode (FE), a part of the first electrode (RME1) can function to weaken the electric field.

[0171] The spacing region (SP) may not be formed on the upper surface of the via layer (VIA) but may be formed on the side of the second bank pattern (BP2). The first insulating layer (PAS1) arranged to fill the spacing region (SP) may not be in contact with the upper surface of the via layer (VIA) but may be in contact with the side of the second bank pattern (BP2).

[0172] The first electrode (RME1) may include a portion disposed between the via layer (VIA) and the second bank pattern (BP2). A portion of the first electrode (RME1) may be in contact with the lower surface of the second bank pattern (BP2). The first electrode (RME1) may overlap the second electrode (RME2) and the first substrate (SUB) in the thickness direction.

[0173] In one embodiment, the first electrode (RME1) can weaken the electric field formed in the spacing region (SP). Accordingly, the light-emitting element (ED) is not aligned off-center to one side but can be aligned in the center of the bank patterns (BP1, BP2).

[0174] The display device (10_3) according to the present embodiment can reduce the loss of light emitted in the lower direction of the first substrate (SUB) and improve the light emission efficiency in the upper direction by positioning the spacing region (SP) to be offset to one side of the light-emitting element (ED).

[0175] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0177] 10: Display device ED: Light-emitting element RME1, RME2: Electrodes CNE1, CNE2: Connecting electrodes BP1, BP2: Bank pattern PAS1, PAS2, PAS3: Insulation layer FE: Floating electrode SP: Separation area E1: 1st end E2: 2nd end OP1, OP2, OP3: Apertures PX: Pixel EMA: Emission region BNL: Bank layer

Claims

Claim 1 A display device comprising: a first electrode and a second electrode disposed on a substrate; a spacing region formed to space the first electrode and the second electrode apart; a first insulating layer disposed on the first electrode and the second electrode and disposed to fill the spacing region; a light-emitting element disposed on the first insulating layer and having a first end disposed on the first electrode and a second end facing the first end; and a first opening adjacent to the first end and exposing the first insulating layer, wherein the spacing region is disposed adjacent to the second end, and the light-emitting element comprises at least a light-emitting layer, wherein the light-emitting layer overlaps with either the first electrode or the second electrode. Claim 2 A display device according to claim 1, comprising an electrically floating floating electrode disposed between the substrate and the first electrode in the thickness direction of the substrate. Claim 3 In claim 2, the floating electrode is a display device that overlaps the spacing region and the thickness direction of the substrate. Claim 4 A display device according to claim 1, wherein the light-emitting element comprises an N-type semiconductor layer and a P-type semiconductor layer spaced apart from each other with the light-emitting layer in between, and the second end comprises one surface of the N-type semiconductor layer. Claim 5 In claim 1, the first electrode is a display device that overlaps the center of the light-emitting element and the thickness direction of the substrate. Claim 6 In claim 1, the second end of the light-emitting element is a display device that does not overlap with the second electrode. Claim 7 In claim 6, the second end of the light-emitting element is a display device that overlaps the first electrode and the substrate in the thickness direction. Claim 8 In claim 6, the second end of the light-emitting element is a display device that overlaps the thickness direction of the above-mentioned spaced region and the above-mentioned substrate. Claim 9 In claim 1, the first opening is formed to expose the upper surface of the first insulating layer. Claim 10 A display device according to claim 1, wherein the first opening is formed to expose the side of the first insulating layer and the first electrode. Claim 11 A display device according to claim 1, further comprising a first bank pattern disposed between the substrate and the first electrode and a second bank pattern disposed between the substrate and the second electrode, wherein the spacing region is formed to expose the second bank pattern and the first insulating layer contacts the exposed second bank pattern. Claim 12 In claim 11, one end of the second electrode is a display device disposed on the second bank pattern. Claim 13 A display device according to claim 1, further comprising: a first connecting electrode in contact with a first end of the light-emitting element on the first insulating layer; and a second connecting electrode in contact with a second end of the light-emitting element on the first insulating layer. Claim 14 In claim 13, the second connecting electrode is a display device that overlaps the first electrode and the substrate in the thickness direction. Claim 15 In claim 13, the first insulating layer further comprises a second opening that exposes the upper surface of the second electrode, and the second connecting electrode is a display device that contacts the exposed upper surface of the second electrode. Claim 16 In claim 15, the first insulating layer further comprises a third opening that exposes the upper surface of the first electrode, and the first connecting electrode is a display device that contacts the exposed upper surface of the first electrode. Claim 17 In claim 1, the first electrode is a display device that overlaps the second electrode and the substrate in the thickness direction. Claim 18 A display device comprising: a first electrode and a second electrode spaced apart from each other on a substrate; a first insulating layer disposed on the first electrode and the second electrode; a light-emitting element disposed on the first insulating layer and having a first end disposed on the first electrode and a second end facing the first end; and a first opening adjacent to the first end and exposing the first insulating layer, wherein a first distance between the first end and one end of the first electrode is longer than a second distance between the second end and one end of the first electrode, and the light-emitting element comprises at least a light-emitting layer, wherein the light-emitting layer overlaps with either the first electrode or the second electrode. Claim 19 A display device according to claim 18, further comprising a first bank pattern disposed between the substrate and the first electrode and a second bank pattern disposed between the substrate and the second electrode, wherein one end of the second electrode is disposed on the second bank pattern. Claim 20 In claim 18, a display device in which the minimum distance of the first electrode from the substrate is shorter than the minimum distance of the second electrode from the substrate.

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