Signal acquisition circuit and wearable device

Abstract

An embodiment of the present application discloses a signal acquisition circuit. The signal acquisition circuit comprises a differential amplifier, a first electrode, a second electrode, a first negative capacitance circuit, and a second negative capacitance circuit. Here, the first electrode is connected to the first input terminal of the differential amplifier through a first lead wire, and the second electrode is connected to the second input terminal of the differential amplifier through the second lead wire. The first negative capacitance circuit electrically connects the first lead wire to a ground wire, and the second negative capacitance circuit electrically connects the second lead wire to a ground wire, and both the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect.

Description

Technology Field The present application relates to the field of circuit design, and in particular, to signal acquisition circuits and wearable devices. Background Technology In most conventional bioelectric (electrocardiography, myoelectricism, etc.) signal acquisition circuits, a signal at common-mode power frequency is converted into noise at differential-mode power frequency and input into an amplifier, thereby degrading the signal-to-noise ratio and potentially causing the circuit to saturate and fail. In light of this, it is necessary to reduce power frequency interference by using a relatively large input impedance. However, in actual circuits, parasitic capacitance often lowers the input impedance of the electrical circuit, thereby increasing power frequency interference. In other words, the presence of parasitic capacitance limits the effectiveness of bioelectric signal acquisition. The background technology of the present invention is disclosed in Chinese Patent Publication No. 109981060 (July 5, 2019). The problem to be solved Therefore, it is desirable to provide a signal acquisition circuit and a wearable device capable of reducing the effect of parasitic capacity on signal acquisition. means of solving the problem One embodiment of the present application includes a signal acquisition circuit, wherein the signal acquisition circuit includes a differential amplifier, a first electrode and a second electrode, and a first negative capacitance circuit and a second negative capacitance circuit, wherein the first electrode is connected to a first input terminal of the differential amplifier through a first lead wire, and the second electrode is connected to a second input terminal of the differential amplifier through a second lead wire, wherein the first negative capacitance circuit electrically connects the first lead wire to a ground wire, and the second negative capacitance circuit electrically connects the second lead wire to a ground wire, and wherein both the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect. In some embodiments, the absolute value of the equivalent capacitance value of the first negative capacitance circuit and the relative error of the ground parasitic capacitance value of the first lead wire is less than 50%, and the absolute value of the equivalent capacitance value of the second negative capacitance circuit and the relative error of the ground parasitic capacitance value of the second lead wire is less than 50%. In some embodiments, a first equivalent input capacitance exists at the first input terminal of the differential amplifier, and a second equivalent input capacitance exists at the second input terminal of the differential amplifier, and the absolute value of the equivalent capacitance value of the first negative capacitance circuit and the relative error of the sum of the ground parasitic capacitance of the first lead wire and the first equivalent input capacitance is less than 50%, and the absolute value of the equivalent capacitance value of the second negative capacitance circuit and the relative error of the sum of the ground parasitic capacitance of the second lead wire and the second equivalent input capacitance is less than 50%. In some embodiments, the circuit further comprises a third negative capacitance circuit, the third negative capacitance circuit electrically connects the first lead wire and the second lead wire, and the third negative capacitance circuit has a negative capacitance effect. In some embodiments, the absolute value of the equivalent capacitance value of the third negative capacitance circuit and the relative error between the parasitic capacitance value between the first lead wire and the second lead wire is less than 50%. In some embodiments, the first negative capacitance circuit comprises a first operational amplifier, a first electrical resistor, a second electrical resistor, and a first capacitance, and the second negative capacitance circuit comprises a second operational amplifier, a third electrical resistor, a fourth electrical resistor, and a second capacitance, wherein the opposite input terminal of the first operational amplifier is grounded through the first electrical resistor and simultaneously connects the second electrical resistor to the output terminal of the first operational amplifier, and the same input terminal of the first operational amplifier is connected through the first capacitance and the output terminal of the first operational amplifier, and the opposite input terminal of the second operational amplifier is grounded through the third electrical resistor and simultaneously connects the fourth electrical resistor to the output terminal of the second operational amplifier, and the same input terminal of the second operational amplifier is connected through the second capacitance and the output terminal of the second operational amplifier. In some embodiments, the co-direction input terminal of the first operational amplifier and the first lead wire are connected, and the co-direction input terminal of the second operational amplifier and the second lead wire are connected. In some embodiments, the circuit further includes a feedback control circuit for adjusting the equivalent capacitance values ​​of the first negative capacitance circuit and the second negative capacitance circuit. In some embodiments, the input impedance of the differential amplifier is greater than 100 MΩ. In some embodiments, the differential amplifier is a positive / negative dual-terminal voltage power supply type. In some embodiments, the differential amplifier is a single-terminal power supply type. One embodiment of the present application provides a signal acquisition circuit, wherein the signal acquisition circuit comprises a differential amplifier, a first electrode and a second electrode, and a fourth negative capacitance circuit, wherein the first electrode is connected to a first input terminal of the fourth negative capacitance circuit through a first lead wire, the second electrode is connected to a second input terminal of the fourth negative capacitance circuit through a second lead wire, the first output terminal of the fourth negative capacitance circuit is connected to a first input terminal of the differential amplifier, the second output terminal of the fourth negative capacitance circuit is connected to a second input terminal of the differential amplifier, and the fourth negative capacitance circuit has a negative capacitance effect. In some embodiments, the fourth negative capacitance circuit includes a dual-terminal differential amplifier, a first negative feedback capacitance, and a second negative feedback capacitance, wherein the first negative feedback capacitance is connected between the first input terminal of the dual-terminal differential amplifier and the first output terminal of the dual-terminal differential amplifier, and the second negative feedback capacitance is connected between the second input terminal of the dual-terminal differential amplifier and the second output terminal of the dual-terminal differential amplifier. In some embodiments, the dual-terminal differential amplifier is a fixed-gain amplifier. In some embodiments, the fourth negative capacitance circuit comprises a first unit and a second unit, wherein the first unit comprises a first amplifier and a third negative feedback capacitance, and the second unit comprises a second amplifier and a fourth negative feedback capacitance, wherein the third negative feedback capacitance is connected between the input terminal of the first amplifier and the output terminal of the first amplifier, and the fourth negative feedback capacitance is connected between the input terminal of the second amplifier and the output terminal of the second amplifier. In some embodiments, the absolute value of the equivalent capacitance value of the first unit of the fourth negative capacitance circuit and the relative error of the ground parasitic capacitance value of the first lead wire is less than 50%, and the absolute value of the equivalent capacitance value of the second unit of the fourth negative capacitance circuit and the relative error of the ground parasitic capacitance value of the second lead wire is less than 50%. In some embodiments, the first amplifier and the second amplifier are fixed amplifiers with the same gain. In some embodiments, the circuit includes a feedback control circuit for adjusting the equivalent capacitance value of the fourth negative capacitance circuit. In some embodiments, the input impedance of the differential amplifier is greater than 100 MΩ. In some embodiments, the differential amplifier is a positive / negative dual-terminal voltage power supply type. In some embodiments, the differential amplifier is a single-terminal power supply type. One embodiment of the present application provides a wearable device comprising the signal acquisition circuit. Effects of the invention The signal collection circuit provided in the embodiment of the present application connects a first negative capacitance circuit and a second negative capacitance circuit to the lead wire of the collection unit, so that the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect, and thus cancels out the ground parasitic capacitance of the lead wire, thereby reducing the influence of parasitic capacitance on signal collection and further improving the performance and signal collection effect of the signal collection circuit. Brief explanation of the drawing The present application is further described in terms of exemplary embodiments, which are described in detail through the drawings. These embodiments are not limiting, and like reference numerals in these embodiments denote like structures. FIG. 1 is a schematic diagram of the principle of power frequency interference according to some embodiments of the present application. FIGS. 2a and 2b are schematic diagrams of a power supply method for a differential amplifier according to some embodiments of the present application. FIG. 3 is a schematic diagram of a signal acquisition circuit according to some embodiments of the present application. FIG. 4 is a schematic diagram of the structure of a negative capacitance circuit in a signal collection circuit according to some embodiments of the present application. FIG. 5 is a schematic diagram of a signal acquisition circuit according to some embodiments of the present application. FIG. 6a is a schematic diagram of one structure of a fourth negative capacitance circuit in a signal acquisition circuit according to some embodiments of the present application. FIG. 6b is a schematic diagram of another structure of a fourth negative capacitance circuit in a signal acquisition circuit according to some embodiments of the present application. FIG. 7a is a schematic diagram of an effective electrical circuit before removing power frequency interference according to some embodiments of the present application. FIG. 7b is a schematic diagram of an effective electrical circuit after removing power frequency interference according to some embodiments of the present application. Specific details for implementing the invention To more clearly explain the technical solutions of the embodiments of the present application, the drawings to be used in the description of the embodiments are briefly introduced below. Of course, the accompanying drawings in the description below are merely some examples or embodiments of the present application, and those skilled in the art can apply the present application to other similar situations based on these drawings without creative labor. Unless readily available in the preceding or following text or described separately, the same reference numerals in the drawings denote the same structure or operation It should be understood that as used herein, the terms “system,” “device,” “unit,” and / or “module” are one method for distinguishing different assemblies, elements, components, parts, or assemblies at different levels. However, where other words can achieve the same purpose, said words may be replaced by other expressions. As described in this application and claims, unless otherwise clearly indicated by the context, words such as “one,” “one,” and / or “above” do not specifically refer only to the singular but may include the plural. Generally, the terms “include” and “comprehensively” mean merely including the specified procedures and elements, and such procedures and elements do not form an exclusive enumeration, and the method or apparatus may include other procedures or elements. The signal collection circuit described in the embodiments of the present application may be applied to various signal monitoring devices that require signal collection, particularly monitoring devices for physiological signals, such as smart wearable devices. In some embodiments, the wearable device (e.g., clothing, wristband, shoulder strap, etc.) is placed on various parts of the human body (e.g., calves, thighs, waist, back, chest, shoulders, neck, etc.) and is used to collect physiological signals from each part of the user's body when the user is in a different state, and may subsequently process the collected signals. In some embodiments, the physiological signals are signals that can indicate the user's physical condition to be detected and may include various signals such as respiration signals, electrocardiograph (ECG), electromyograph (EMG), electroencephalograph (EEG), blood pressure signals, temperature signals, etc. In some embodiments, the wearable device for collecting physiological signals may be applied to cross-emerging industries such as medical, gaming entertainment, and health education. For example, when combined with technologies such as virtual reality (VR) and EMG acquisition, it promotes the development of immersive entertainment and education, and when combined with technologies such as mechanical electronics and exoskeletons, it can achieve the goal of reducing medical technology costs and promoting the development of medical health. FIG. 1 is a schematic diagram of the principle of power frequency interference according to some embodiments of the present application. In some embodiments, the signal collection circuit (100) shown in FIG. 1 includes one or more sensor units that come into contact with the user's body (e.g., a first electrode (110) and a second electrode (120)), a differential amplifier (130), and one or more lead wires (e.g., a first lead wire (L1), a second lead wire (L2)) that connect the sensor units and the differential amplifier (130). In some embodiments, the sensor unit may be used to acquire one or more physiological signals from a user. The sensor unit may include, but is not limited to, one or more of the following: a myoelectric sensor, a posture sensor, an electrocardiographic sensor, a respiration sensor, a temperature sensor, a humidity sensor, an inertial sensor, a blood oxygen saturation sensor, a Hall sensor, a skin electroelectric sensor, a rotation sensor, etc. In some embodiments, the physiological signal may include one or more of the following: an myoelectric signal, a posture signal, an electrocardiographic signal, a respiration frequency, a temperature signal, a humidity signal, etc. The sensor unit may be placed at different locations on the wearable device depending on the type of motion signal acquired. In some embodiments, different signal acquisition circuits may be placed at different locations on the user's body and used to collect the same or different types of physiological signals from the user. For example, signal acquisition circuits placed on different sides of the user's thigh may all be used to collect electromyographic signals from the thigh location. Also, for example, a signal acquisition circuit placed at the user's forearm location may be used to collect electromyographic signals from the forearm location, and a signal acquisition circuit placed at the user's heart location may be used to collect electrocardiographic signals from the user. In some embodiments, the sensor unit may include one or more electrode elements that come into contact with the user's body, and may collect myoelectric signals from the surface of the user's body through the electrode elements. The electrode elements may be dry electrodes or wet electrodes. Here, the dry electrode is a metal structure electrode formed by weaving a metal plate or a metal wire, and the contact strength with the human body can be increased by forming a wet electrode by applying an electrically conductive gel between the human skin and the electrode elements. Since the human body is not an absolute conductor, contact impedance exists between the dry electrode and the wet electrode and the human body, and the resistance differs under different physiological conditions, allowing different electrode types to be selected and used in different situations. In some embodiments, the electrode element includes a first electrode (110) and a second electrode (120). The first electrode (110) is connected to point A of the first input terminal of the differential amplifier (130) via a first lead wire (L1), and the second electrode (120) is connected to point B of the second input terminal of the differential amplifier (130) via a second lead wire (L2), and the first lead wire (L1) and the second lead wire (L2) transmit a physiological signal collected by the electrode element to the differential amplifier to perform appropriate processing (e.g., noise reduction, amplification, etc.). In some embodiments, the differential amplifier (130) performs differential amplification processing on the physiological signal acquired by the electrode element. In some embodiments, the physiological signal after processing by the differential amplifier (130), i.e., Vout output by the output terminal, is transmitted to other elements in the wearable device for subsequent processing. For example, the physiological signal after processing is converted from an analog signal to a digital signal through an analog-to-digital converter (ADC), and then subsequent processing, for example, signal analysis, is performed through a processor. In some embodiments, the differential amplifier (130) may include two power supply modes, namely a single-terminal power supply mode and a dual-terminal power supply mode. As shown in FIG. 2a, the first power supply terminal (111) of the differential amplifier (130) is connected to a positive power supply (+Vcc) and the second power supply terminal (112) is connected to a negative power supply (-Vcc), and at the same time, the end portion (113) receiving the bias voltage is grounded. As shown in FIG. 2a, the first power supply terminal (114) of the differential amplifier (130) is connected to a positive power supply (+Vcc) and the second power supply terminal (116) is grounded, and at the same time, the voltage value received by the end portion (117) receiving the bias voltage is a bias voltage of +Vcc / 2. In some embodiments, when the contact impedance between the first electrode (110) and the second electrode (120) and the user's body is mismatched, that is, when the impedances of the two input terminals of the differential amplifier (130) are mismatched (the impedances lose equilibrium), the common mode power frequency signal of the human body surface is converted into differential mode power frequency noise and input to the amplifier, thereby reducing the signal-to-noise ratio and, in severe cases, even causing a saturation failure of the electrical circuit. In the environment where the human body is located, there are various types of 50 / 60 Hz power frequency lines (50 Hz lines in China, 60 Hz lines in other countries). Since these power frequency lines emit electromagnetic waves, they couple with the human body, causing a change in the body's potential. The amplitude of this change is generally in the millivolt range, ranging from a few mV to several hundred mV, and this is related to the position of the human body and the power frequency lines. To aid understanding, if environmental interference is treated as equivalent to the capacitance coupling model C0 and the impedance between the human body and the ground is denoted as Z0, the model of power frequency interference can be equivalent to the left half of Figure 1; that is, the power frequency lines are grounded by connecting the capacitance C0, the human body, and the ground impedance in series. When the human body moves, the distance of the power frequency lines changes, and the value of the equivalent capacitance C0 changes accordingly. In some embodiments, if the power frequency current coupled to the human body is Icm, the common mode power frequency potential Vcm on the surface of the human body can be expressed as follows. (1) If the ground impedance of the first input terminal (A) is Zin1 and the ground impedance of the second input terminal (B) is Zin2, then in a general situation The common mode input impedance can be expressed as follows. (2) In some embodiments, when the contact impedance between the first electrode (110) and the second electrode (120) and the user's body is mismatched, the potentials of the first input terminal (A) and the second input terminal (B) of the differential amplifier (130) are not the same, and the differential amplifier (130) also amplifies the potential difference between the two points AB, thereby causing saturation or failure of the electrical circuit. When a common mode power frequency potential Vcm is present in the human body, the potential difference VAB between the first input terminal (A) and the second input terminal (B) of the differential amplifier (130) can be expressed through the following formula (3). (3) Here, Z1 is the contact impedance value of the first electrode (110), and Z2 is the contact impedance value of the second electrode (120). From the above formula, it can be seen that the differential mode power frequency signal strength between the first input terminal (A) and the second input terminal (B) of the differential amplifier (130) and the common mode input impedance of the differential amplifier (130) are inversely proportional, and that the lower the common mode input impedance, the greater the power frequency interference. In some embodiments, to reduce the effect of power frequency interference on signal acquisition, the potential difference between the two input terminals of the differential amplifier can be reduced by using a method that reduces the contact impedance of the electrode element, and the common mode power frequency potential can be lowered by adding a ground electrode to the human body, thereby reducing the potential difference between the two input terminals of the differential amplifier, for example, by contacting one end of the electrode with the human body and connecting the other end to the GND of the electrical circuit. However, since contact impedance always exists in the electrode element, the common mode power frequency potential may not be completely eliminated. In some embodiments, to reduce the effect of power frequency interference on signal acquisition, a method of increasing the (common mode) input impedance of the differential amplifier may be used. For example, a differential amplifier having a high (common mode) input impedance (e.g., both the first input terminal (A) and the second input terminal (B) have high ground impedance) may be used as the input stage of the signal acquisition circuit. In some embodiments, the (common mode) input impedance of the differential amplifier (130) is greater than 100 MΩ, and preferably, the (common mode) input impedance of the differential amplifier (130) is greater than 1 GΩ. However, when applying the signal collection circuit (100) to a wearable device, if parasitic capacitance exists in the actual electrical circuit, the input impedance of the differential amplifier is reduced. In the actual application process, parasitic capacitance exists not only between the lead wires but also between the lead wires and the ground. In particular, when collecting physiological signals, the signals of some physiological signals (e.g., myoelectric signals, electrocardiographic signals, etc.) are relatively weak, and the influence of such parasitic capacitance is particularly significant. In some embodiments, such parasitic capacitance and each type of equivalent impedance in the signal collection circuit are connected in parallel, which drastically reduces the input impedance of the entire electrical circuit and also rapidly increases interference of power frequency, which cannot be resolved by a differential amplifier with a higher input impedance. Therefore, it can be seen that the presence of such parasitic capacitance limits the performance and collection effect of the signal collection circuit. FIG. 3 is a schematic diagram of a signal collection circuit (200) according to some embodiments of the present application. In some embodiments, the signal collection circuit (200) shown in FIG. 3 may include a first electrode (210), a second electrode (220), a differential amplifier (230), a first lead wire (L1), a second lead wire (L2), a first negative capacitance circuit (C10), and a second negative capacitance circuit (C20). In some embodiments, the first electrode (210) is connected to the first input terminal (A) of the differential amplifier (230) through the first lead wire (L1), and the second electrode (220) is connected to the second input terminal (B) of the differential amplifier (230) through the second lead wire (L2). Here, for the relevant description regarding the first electrode (210), the second electrode (220), the differential amplifier (230), the first lead wire (L1), and the second lead wire (L2), please refer to the relevant description in FIG. 1, and will not be described redundantly here. In some embodiments, a first ground parasitic capacitance (C1) exists between the first lead wire (L1) and the ground wire, a second ground parasitic capacitance (C2) exists between the second lead wire (L2) and the ground wire, and a parasitic capacitance (C3) exists between the lead wires between the first lead wire (L1) and the second lead wire (L2). As shown in FIG. 3, the first ground parasitic capacitance (C1) is equivalently connected between the first lead wire (L1) and the ground wire, and the ground impedance (Zin1) of the first input terminal (A) of the differential amplifier (230) can be considered to be connected in parallel with the first ground parasitic capacitance (C1), and the second ground parasitic capacitance (C2) is equivalently connected between the second lead wire (L2) and the ground wire, and the ground impedance (Zin2) of the second input terminal (B) of the differential amplifier (230) can be considered to be connected in parallel with the second ground parasitic capacitance (C2), and the parasitic capacitance (C3) between the lead wires can be considered to be equivalently connected between the first lead wire (L1) and the second lead wire (L2). Here, the first ground parasitic capacitance (C1) and the second ground parasitic capacitance (C2) are each connected in parallel with the ground impedance (Zin1) and ground impedance (Zin2) of the differential amplifier, respectively, thereby maximally reducing the input impedance of the entire electrical circuit and increasing the effect of power frequency interference on signal acquisition. In some embodiments, changes in parasitic capacitance values ​​cannot be measured in real time, but since they are related to the design of the electrical circuit, the parasitic capacitance values ​​can be measured after the electrical circuit is designed. That is, after designing the electrical circuit of the signal collection circuit, the first ground parasitic capacitance (C1), the second ground parasitic capacitance (C2), and the parasitic capacitance between the lead wires (C3) can be measured. In the actual application process, the parasitic capacitance value between the human body and the device cannot be measured accurately, but a reference value for the parasitic capacitance can be determined by measuring it when the human body is not moving. When the human body is in motion, the parasitic capacitance value between the human body and the device changes, and an approximate range of variation can be determined based on the reference value for the parasitic capacitance. In some embodiments, a first negative capacitance circuit (C10) and a second negative capacitance circuit (C20) are placed in the signal collection circuit (200) to increase the input impedance of the differential amplifier by reducing the effect of parasitic capacitance. The first negative capacitance circuit (C10) electrically connects the first lead wire (L1) to the ground wire, and the second negative capacitance circuit (C20) electrically connects the second lead wire (L2) to the ground wire. Since the first negative capacitance circuit (C10) and the second negative capacitance circuit (C20) have a negative capacitance effect, they cancel out the ground parasitic capacitance of the lead wire, thereby reducing the effect of parasitic capacitance on the input impedance of the circuit and signal collection, and thus can improve the performance and signal collection effect of the signal collection circuit. The negative capacitance effect referred to here can be understood as the change trend of the quantity of charge in the first negative capacitance circuit (C10) and the second negative capacitance circuit (C20) being opposite to the change trend of the voltage applied thereto, that is, as the voltage decreases, the quantity of charge in the first negative capacitance circuit (C10) and the second negative capacitance circuit (C20) increases correspondingly. In some embodiments, the method of electrically connecting the first negative capacitance circuit (C10) and / or the second negative capacitance circuit (C20) to a ground wire may include connecting the first negative capacitance circuit (C10) and / or the second negative capacitance circuit (C20) to a shared ground terminal among one or more printed circuit boards (PCBs). In some embodiments, the first negative capacitance circuit (C10) can be considered to be connected in parallel with the first ground parasitic capacitance (C1), and the second negative capacitance circuit (C20) can be considered to be connected in parallel with the second ground parasitic capacitance (C2). The first negative capacitance circuit (C10) and the second negative capacitance circuit (C20) each cancel out the parasitic capacitance of the input terminals of the two differential amplifiers, thereby reducing the capacitance value of the input terminals of the differential amplifiers and improving the input impedance. In some embodiments, when the equivalent capacitance value of the first negative capacitance circuit (C10) and the equivalent capacitance value of the second negative capacitance circuit (C20) are expressed by the following formulas (4) and (5), (4) (5) The total ground capacitance of the first lead wire (L1) and the total ground capacitance of the second lead wire (L2) are both zero. At this time, the ground parasitic capacitance of the input terminal of the differential amplifier is completely canceled out, and the overall input impedance of the signal collection circuit is significantly improved, thereby improving the ability to prevent power frequency interference. In some embodiments, because there is a possibility that the parasitic capacitance may vary slightly depending on the movement of the lead wire in an actual working environment, the absolute value of the negative capacitance circuit may not be exactly the same as the parasitic capacitance. In some embodiments, in order to effectively offset the ground parasitic capacitance of the input terminal of the differential amplifier, the absolute value of the equivalent capacitance value of the first negative capacitance circuit (C10) and the ground parasitic capacitance of the first lead wire (L1) Value (C1)The relative error is less than 50%, and the relative error between the absolute value of the equivalent capacitance value of the second negative capacitance circuit (C20) and the ground parasitic capacitance value (C2) of the second lead wire (L2) is less than 50%. In some embodiments, in order to have the input terminal of the differential amplifier have a larger input impedance, the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit (C10) and the ground parasitic capacitance value (C1) of the first lead wire (L1) is less than 30%, and the relative error between the absolute value of the equivalent capacitance value of the second negative capacitance circuit (C20) and the ground parasitic capacitance value (C2) of the second lead wire (L2) is less than 30%. It must be understood that, in the actual application process, the smaller the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit (C10) and the ground parasitic capacitance (C1) of the first lead wire (L1), the greater the ground parasitic capacitance (C1) of the first lead wire (L1) canceled out by the first negative capacitance circuit (C10), the greater the input impedance of the overall signal collection circuit, and ultimately, the better the signal collection effect. The same applies to the second negative capacitance circuit (C20), so it is not explained redundantly here. In some embodiments, the absolute value of the equivalent capacitance value of the first negative capacitance circuit (C10) and the relative error of the ground parasitic capacitance value of the first lead wire (L1) represent the ratio value of the absolute value of the equivalent capacitance value of the first negative capacitance circuit (C10), the differential value of the ground parasitic capacitance value of the first lead wire (L1), and the ground parasitic capacitance value of the first lead wire (L1).

[0032] In some embodiments, the equivalent input impedance (Zin1) of the first input terminal (A) of the differential amplifier (230) may be equivalent to a parallel connection of one capacitance (Rin1) and one capacitance (Cin1), and the equivalent input impedance (Zin2) of the second input terminal (B) of the differential amplifier (230) may be equivalent to a parallel connection of one capacitance (Rin2) and one capacitance (Cin2). In some embodiments, to further improve the performance of the input impedance of the signal collection circuit (200), the first negative capacitance circuit (C10) and the second negative capacitance circuit (C20) may be adjusted to further offset the influence of the equivalent input capacitance of the differential amplifier (230). In some embodiments, the equivalent capacitance value of the first negative capacitance circuit (C10) and the equivalent capacitance value of the second negative capacitance circuit (C20) can be adjusted using the following formulas (6) and (7). (6) (7) In some embodiments, to effectively offset the equivalent input capacitance of the input terminal of the differential amplifier, the relative error of the sum of the absolute value of the equivalent capacitance value of the first negative capacitance circuit (C10), the ground parasitic capacitance value (C1) of the first lead wire (L1), and the equivalent input capacitance value Cin1 of the first input terminal (A) of the differential amplifier (230) is less than 50%, and the relative error of the sum of the absolute value of the equivalent capacitance value of the second negative capacitance circuit (C20), the ground parasitic capacitance value (C2) of the second lead wire (L2), and the equivalent input capacitance value Cin2 of the second input terminal (B) of the differential amplifier (230) is less than 50%. In some embodiments, to have the input terminal of the differential amplifier have a larger input impedance, the relative error of the sum of the absolute value of the equivalent capacitance value of the first negative capacitance circuit (C10), the ground parasitic capacitance value (C1) of the first lead wire (L1), and the equivalent capacitance value Cin1 of the first input terminal (A) of the differential amplifier (230) is less than 30%, and the relative error of the sum of the absolute value of the equivalent capacitance value of the second negative capacitance circuit (C20), the ground parasitic capacitance value (C2) of the second lead wire (L2), and the equivalent capacitance value Cin2 of the second input terminal (B) of the differential amplifier (230) is less than 30%. It must be understood that, in the actual application process, the smaller the relative error between the absolute value of the equivalent capacitance of the first negative capacitance circuit (C10), the sum of the ground parasitic capacitance of the first lead wire (L1) and the first equivalent input capacitance (Cin1) of the differential amplifier, and the greater the ground parasitic capacitance of the first lead wire (L1) and the first equivalent input capacitance (Cin1) of the differential amplifier canceled by the first negative capacitance circuit (C10), the greater the input impedance of the overall signal collection circuit and, ultimately, the better the signal collection effect. The same applies to the second negative capacitance circuit (C20), so it is not explained redundantly here. Accordingly, the first negative capacitance circuit (C10) and the second negative capacitance circuit (C20) each cancel out the ground parasitic capacitance of the first lead wire (L1) and the first equivalent input capacitance (Cin1) of the differential amplifier, and the ground parasitic capacitance of the second lead wire (L2) and the second equivalent input capacitance (Cin2) of the differential amplifier, thereby further increasing the input impedance of the overall signal collection circuit. In some embodiments, the signal collection circuit (200) may further include a third negative capacitance circuit (C30). The third negative capacitance circuit (C30) is electrically connected between the first lead wire (L1) and the second lead wire (L2) and is connected in parallel with the parasitic capacitance (C3) between the lead wires. In some embodiments, since the presence of the parasitic capacitance (C3) between the lead wires has a relatively small effect on the performance of the electrical circuit, it is not necessary to place the third negative capacitance circuit (C30) in the signal collection circuit (200). In some embodiments, when the demand for the signal collection circuit (200) is relatively high, the third negative capacitance circuit (C30) may be placed in the signal collection circuit (200). In some embodiments, the value of the third negative capacitance circuit (C30) can be expressed by the following formula (8). (8) In some embodiments, the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit (C30) and the parasitic capacitance value (C3) between the two lead wires is less than 50%. In some embodiments, the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit (C30) and the parasitic capacitance value (C3) between the two lead wires is less than 30%. It should be understood that in actual application, the smaller the relative error between the absolute value of the equivalent capacitance of the third negative capacitance circuit (C30) and the ground parasitic capacitance value (C3) between the two lead wires, the greater the parasitic capacitance (C3) between the lead wires that the third negative capacitance circuit (C30) cancels, the greater the input impedance of the overall signal collection circuit, and ultimately the better the signal collection effect.

[0038] In some embodiments, the signal collection circuit may include a feedback control circuit to adjust the equivalent capacitance values ​​of the first negative capacitance circuit (C10) and the second negative capacitance circuit (C20), for example, by changing the electrical resistance value of the negative capacitance circuit. For the specific structure of the first negative capacitance circuit (C10), the second negative capacitance circuit (C20), and the third negative capacitance circuit (C30), refer to the relevant content of FIGS. 4a and 4b. FIG. 4 is a schematic diagram of the structure of a negative capacitance circuit in a signal collection circuit (200) according to some embodiments of the present application. In some embodiments, the first negative capacitance circuit (C10) may be the structure of FIG. 4, and as shown in FIG. 4, the first negative capacitance circuit (C10) may include a first operational amplifier (410), a first electrical resistor (R1), a second electrical resistor (R2), and a first capacitance (C401). In some embodiments, the opposite input terminal of the first operational amplifier (410) is grounded through the first electrical resistor (R1), the opposite input terminal of the first operational amplifier (410) is connected through the second electrical resistor (R2) and the output terminal of the first operational amplifier (410), and the same input terminal of the first operational amplifier (410) is connected through the first capacitance (C401) and the output terminal of the first operational amplifier (410). In some embodiments, point m in FIG. 4 and point a in FIG. 3 are two equipotential points, and points a and m can be electrically connected using a lead wire. In some embodiments, the second negative capacitance circuit (C20) may have the structure of FIG. 4, wherein point m in FIG. 4 and point b in FIG. 3 are two equipotential points, and these two points m and b can be electrically connected using a lead wire. It should be noted that the negative capacitance circuit shown in FIG. 4 is an equivalent circuit having a negative capacitance effect. Specifically, in the negative capacitance circuit shown in FIG. 4, the equivalent impedance of the negative capacitance circuit is, that is, the impedance between point m and GND. The impedance between point m and GND If you say that, The impedance of can be expressed by the following formula (9). (9) That is, the impedance between point m and GND can include a negative capacitance or be equivalent to what is generated by a negative capacitance. The negative capacitance between point m and GND If you say that, The equivalent capacitance value can be expressed by the following formula (10). (10) What can be understood is, That is, it is the equivalent capacitance of the negative capacitance circuit shown in Fig. 4. In some embodiments, electrical resistors R1 and R2 may be electrical resistors with adjustable resistance values ​​(e.g., sliding resistors, electrical resistor boxes, and potentiometers), or they may be electrical resistors with fixed resistance values. In some embodiments, the resistance values ​​of electrical resistors R1 and R2 may be the same or different. It is understood that in some embodiments, by adjusting the resistance values ​​of electrical resistors R1 and R2, the equivalent capacitance The size of can be adjusted. In some embodiments, the capacitance (C401) may be a paper dielectric capacitance, a metallized paper dielectric capacitance, a ceramic capacitance, a thin film capacitance, an oil-immersed paper dielectric capacitance, an aluminum electrolytic capacitance, a semi-variable capacitance, a variable capacitance, etc. In some embodiments, by adjusting the capacitance value of the capacitance (C401), an equivalent capacitance The size of can be adjusted. In some embodiments, the operational amplifier (410) may use a dual power supply, for example, with voltage +Vcc (411) as the positive power and voltage -Vcc (412) as the negative power, and output the amplified signal generated by the operational amplifier (410) at 413. In some embodiments, the operational amplifier (410) may use a single power supply, which is not described redundantly here. In some embodiments, the first negative capacitance circuit (C10) and the second negative capacitance circuit (C20) may be structures other than those in FIG. 4. In some embodiments, the signal collection circuit (200) may further include a third negative capacitance circuit (C30), wherein the third negative capacitance circuit (C30) is electrically connected to the first lead wire (L1) and the second lead wire (L2), and the third negative capacitance circuit (C30) has a negative capacitance effect. In some embodiments, the third negative capacitance circuit (C30) may have the structure of FIG. 4, wherein point m in FIG. 4 and point c in FIG. 3 are two equipotential points, and point GND in FIG. 4 and point d in FIG. 3 are two equipotential points, and point c in FIG. 3 and point m in FIG. 4 can be electrically connected using lead wires, and point d in FIG. 3 and point GND in FIG. 4 can be electrically connected. In some embodiments, the third negative capacitance circuit (C30) may be a structure other than that shown in the drawing, and any structure that can offset the parasitic capacitance (C3) between the lead wires is sufficient to meet the requirements. It should be noted that the description of the signal collection circuit (100), the signal collection circuit (200), and the structure thereof described above is for convenience of explanation only and does not limit the present application to the scope of the embodiments described above. FIG. 5 is a schematic diagram of a signal collection circuit (300) according to some embodiments of the present application. The signal collection circuit (300) shown in FIG. 5 may include a first electrode (210), a second electrode (220), a differential amplifier (230), a first lead wire (L1), a second lead wire (L2), and a fourth negative capacitance circuit (C40). For related descriptions regarding the first electrode (210), the second electrode (220), the differential amplifier (230), the first lead wire (L1), and the second lead wire (L2), refer to the related descriptions of FIG. 1 to 4 described above, which are not duplicated here. Combining the description of the above-described embodiment, a first ground parasitic capacitance (C1) exists between the first lead wire (L1) and the ground wire, and a second ground parasitic capacitance (C2) exists between the second lead wire (L2) and the ground wire. Since the first ground parasitic capacitance (C1) and the second ground parasitic capacitance (C2) are each connected in parallel with the ground impedance (Zin1) and ground impedance (Zin2) of the differential amplifier, the input impedance of the entire electrical circuit is reduced to the maximum extent, and the influence of power frequency interference on signal collection is increased. Accordingly, in some embodiments, a fourth negative capacitance circuit (C40) is placed in the signal collection circuit (300) to increase the input impedance of the differential amplifier (230) by reducing the effect of parasitic capacitance. In some embodiments, the first electrode (210) is connected to the first input terminal (P) of the fourth negative capacitance circuit (C40) via the first lead wire (L1), the second electrode (220) is connected to the second input terminal (Q) of the fourth negative capacitance circuit (C40) via the second lead wire (L2), the first output terminal (M) of the fourth negative capacitance circuit (C40) is connected to the first input terminal (A) of the differential amplifier (230), and the second output terminal (N) of the fourth negative capacitance circuit (C40) is connected to the second input terminal (B) of the differential amplifier (230). The fourth negative capacitance circuit (C40) is equipped with a negative capacitance effect, thereby canceling out the ground parasitic capacitance of the lead wire, reducing the influence of parasitic capacitance on the electrical circuit input impedance and signal collection, and further improving the performance and signal collection effect of the signal collection circuit. In some embodiments, the negative capacitance circuit (C40) is implemented using an amplifier having a fixed gain and a feedback capacitance to achieve the effect of simultaneously canceling out the first ground parasitic capacitance (C1) and the second ground parasitic capacitance (C2). For specific implementation forms of the negative capacitance circuit (C40), refer to the relevant descriptions in FIGS. 6a and 6b. In some embodiments, the signal collection circuit (300) may further include a third negative capacitance circuit (C30). The third negative capacitance circuit (C30) is electrically connected between the first lead wire (L1) and the second lead wire (L2) and is connected in parallel with the parasitic capacitance (C3) between the lead wires. In some embodiments, since the presence of the parasitic capacitance (C3) between the lead wires has a relatively low impact on the performance of the electrical circuit, it may not be necessary to place the third negative capacitance circuit (C30) in the signal collection circuit (200). In some embodiments, if the requirements of the signal collection circuit (200) are relatively high, the third negative capacitance circuit (C30) may be placed in the signal collection circuit (200). Regarding specific implementation forms of the third negative capacitance circuit (C30), reference may be made to the relevant descriptions in FIGS. 3 and FIGS. 4, which are not described redundantly here. In some embodiments, the signal collection circuit may include a feedback control circuit to adjust the equivalent capacitance value of the fourth negative capacitance circuit (C40), for example, by changing the resistance value or capacitance value in the negative capacitance circuit. FIG. 6a is a schematic diagram of the structure of one of the fourth negative capacitance circuits (C40) of the signal collection circuit (300) according to some embodiments of the present application. In some embodiments, the fourth negative capacitance circuit (C40) includes a first unit (C402) and a second unit (C404), the first unit (C402) includes a first amplifier (G2) and a third negative feedback capacitance (C46), and the second unit (C404) includes a second amplifier (G3) and a fourth negative feedback capacitance (C48). In some embodiments, both the first amplifier (G2) and the second amplifier (G3) are fixed-gain amplifiers. In some embodiments, the input terminal of the first amplifier (G2) is the first input terminal (P) of the fourth negative capacitance circuit (C40), and the input terminal of the second amplifier (G3) is the second input terminal (Q) of the fourth negative capacitance circuit (C40); similarly, the output terminal of the first amplifier (G2) is the first output terminal (M) of the fourth negative capacitance circuit (C40), and the output terminal of the second amplifier (G3) is the second output terminal (N) of the fourth negative capacitance circuit (C40). In some embodiments, the input terminal (P) of the first amplifier (G2) and the output terminal (M) of the first amplifier (G2) are connected in series through a third negative feedback capacitance (C46), and the input terminal (Q) of the second amplifier (G3) and the output terminal (N) of the second amplifier (G3) are connected in series through a fourth negative feedback capacitance (C48). In some embodiments, if the gain of the first amplifier (G2) is constant g1, the gain of the second amplifier (G3) is also constant g1, and the equivalent capacitance value of the first unit (C402) of the fourth negative capacitance circuit (C40) can be expressed by the following formula (11). (11) The equivalent capacitance value of the second unit (C404) of the fourth negative capacitance circuit (C40) can be expressed by the following formula (12). (12) In some embodiments, the first amplifier (G2) and the second amplifier (G3) may be amplifiers with the same and fixed gain, for example, if the gain of the first amplifier (G2) is constant g1, the gain of the second amplifier (G3) is also constant g1. In some embodiments, the gain range of the first amplifier (G2) and the second amplifier (G3) may be 0 to 100 dB, and preferably, the gain range of the first amplifier (G2) and the second amplifier (G3) may be 0 to 10 dB. In some embodiments, the values ​​of the third negative feedback capacitance (C46) and the fourth negative feedback capacitance (C48) are the same. Therefore, the first unit (C402) and the second unit (C404) of the fourth negative capacitance circuit (C40) form a structure with symmetrical heights, so that the entire signal collection circuit (300) can obtain a relatively large common-mode rejection ratio. In some embodiments, if the gains of the first amplifier (G2) and the second amplifier (G3) are not the same, the common-mode rejection ratio of the electrical circuit is reduced, and the effect of reducing power frequency interference cannot be achieved. In some embodiments, each of the first amplifier (G2) and the second amplifier (G3) may form a cascade configuration by multi-stage fixed-gain amplifiers. In some embodiments, the first unit (C402) of the fourth negative capacitance circuit (C40) may be used to offset the first ground parasitic capacitance (C1), and the second unit (C404) of the fourth negative capacitance circuit (C40) may be used to offset the second ground parasitic capacitance (C2). Thus, the fourth negative capacitance circuit (C40) may be used to offset both the first ground parasitic capacitance (C1) and the second ground parasitic capacitance (C2) simultaneously. In some embodiments, the equivalent capacitance value of the first unit (C402) and the equivalent capacitance value of the second unit (C404) may be expressed as follows. (13) (14) As described above, the total grounding capacitance of the first lead wire (L1) and the total grounding capacitance of the second lead wire (L2) are both zero. At this time, the grounding parasitic capacitance of the input terminal of the differential amplifier (230) is completely canceled out, and the total input impedance of the signal collection circuit (300) is greatly increased, thereby improving the ability to prevent interference with power frequency. In some embodiments, considering that in an actual working environment the parasitic capacitance may vary slightly depending on the movement of the lead wire, correspondingly, the absolute value of the equivalent capacitance value of the first unit (C402) of the fourth negative capacitance circuit (C40) and the relative error of the ground parasitic capacitance value (C1) of the first lead wire (L1) is less than 50%, and the relative error of the equivalent capacitance value of the second unit (C404) of the fourth negative capacitance circuit (C40) and the ground parasitic capacitance value (C2) of the second lead wire (L2) is less than 50%. In some embodiments, the absolute value of the equivalent capacitance value of the first unit (C402) of the fourth negative capacitance circuit (C40) and the relative error of the ground parasitic capacitance value (C1) of the first lead wire (L1) is less than 30%, and the relative error of the equivalent capacitance value of the second unit (C404) of the fourth negative capacitance circuit (C40) and the ground parasitic capacitance value (C2) of the second lead wire (L2) is less than 30%. FIG. 6b is a schematic diagram of another structure of a fourth negative capacitance circuit (C40) in a signal collection circuit (300) according to some embodiments of the present application. In some embodiments, the fourth negative capacitance circuit (C40) may include a dual-terminal differential amplifier (G1), a first negative feedback capacitance (C42), and a second negative feedback capacitance (C44). In some embodiments, the first input terminal of the dual-terminal differential amplifier (G1) is the first input terminal (P) of the fourth negative capacitance circuit (C40), and the second input terminal of the dual-terminal differential amplifier (G1) is the second input terminal (Q) of the fourth negative capacitance circuit (C40); similarly, the first output terminal of the dual-terminal differential amplifier (G1) is the first output terminal (M) of the fourth negative capacitance circuit (C40), and the second output terminal of the dual-terminal differential amplifier (G1) is the second output terminal (N) of the fourth negative capacitance circuit (C40). The first input terminal (P) of the dual-terminal differential amplifier (G1) and the first output terminal (M) of the dual-terminal differential amplifier (G1) are connected in series through a first negative feedback capacitance (C42), and the second input terminal (Q) of the dual-terminal differential amplifier (G1) and the second output terminal (N) of the dual-terminal differential amplifier (G1) are connected in series through a second negative feedback capacitance (C44). In some embodiments, the dual-terminal differential amplifier (G1) is a single fixed-gain amplifier. In some embodiments, the gain g0 of the dual-terminal differential amplifier (G1) may be in the range of 0 to 100 dB, and preferably, the range of g0 is in the range of 0 to 10 dB. In some embodiments, the fourth negative capacitance circuit (C40) may be used to simultaneously cancel out the first ground parasitic capacitance (C1) and the second ground parasitic capacitance (C2). In some embodiments, the dual-terminal differential amplifier (G1) is composed of a combination of multiple fixed-gain amplifiers, for example, the dual-terminal differential amplifier (G1) is composed of two amplifiers (G11 and G12) with a gain of g0, wherein the amplifiers (G11 and G12) are fixed-gain amplifiers with the same gain and have completely identical structures. In some embodiments, the input terminal of the amplifier (G11) is point P and the output terminal is point M, and the first negative feedback capacitance (C42) connects point P and point M in series, and the electrical circuit structure composed of the amplifier (G11) and the first negative feedback capacitance (C42) may be used to cancel out the first ground parasitic capacitance (C1). In some embodiments, the input terminal of the amplifier (G12) is point Q and the output terminal is point N, and a second negative feedback capacitance (C44) connects point Q and point N in series, and the electrical circuit structure formed by the amplifier (G12) and the second negative feedback capacitance (C44) can be used to cancel out the first ground parasitic capacitance (C1). In some embodiments, the equivalent capacitance value (C11) of the electrical circuit structure formed by the amplifier (G11) and the first negative feedback capacitance (C42) and the equivalent capacitance value (C12) of the electrical circuit structure formed by the amplifier (G12) and the second negative feedback capacitance (C44) can be expressed as follows. (15) (16) At this time, an electrical circuit structure composed of an amplifier (G11) and a first negative feedback capacitance (C42) can be used to offset the first ground parasitic capacitance (C1), and an electrical circuit structure composed of an amplifier (G12) and a second negative feedback capacitance (C44) can be used to offset the second ground parasitic capacitance (C2). At this time, the ground parasitic capacitance of the input terminal of the differential amplifier is offset, and the overall input impedance of the signal collection circuit is greatly increased, thereby improving the ability to prevent power frequency interference. In some embodiments, to effectively offset the input terminal ground parasitic capacitance of the differential amplifier, the absolute value of the equivalent capacitance value (C11) of the electrical circuit structure composed of the amplifier (G11) and the first negative feedback capacitance (C42) and the relative error of the ground parasitic capacitance value (C1) of the first lead wire (L1) is less than 50%, and the absolute value of the equivalent capacitance value (C12) of the electrical circuit structure composed of the amplifier (G12) and the second negative feedback capacitance (C44) and the relative error of the ground parasitic capacitance value (C2) of the second lead wire (L2) is less than 50%. In some embodiments, to have the input terminal of the differential amplifier have a larger input impedance, the absolute value of the equivalent capacitance value (C11) of the electrical circuit structure composed of the amplifier (G11) and the first negative feedback capacitance (C42) and the relative error of the ground parasitic capacitance value (C1) of the first lead wire (L1) is less than 30%, and the absolute value of the equivalent capacitance value (C12) of the electrical circuit structure composed of the amplifier (G12) and the second negative feedback capacitance (C44) and the relative error of the ground parasitic capacitance value (C2) of the second lead wire (L2) is less than 30%.

[0080] It must be understood that, in the actual application process, the smaller the relative error between the absolute value of the equivalent capacitance value (C11) of the electrical circuit structure composed of the amplifier (G11) and the first negative feedback capacitance (C42) and the ground parasitic capacitance value (C1) of the first lead wire (L1), and the smaller the relative error between the equivalent capacitance value (C12) of the electrical circuit structure composed of the amplifier (G12) and the second negative feedback capacitance (C44) and the ground parasitic capacitance value (C2) of the second lead wire (L2), the greater the ground parasitic capacitance (C1) of the first lead wire (L1) and the ground parasitic capacitance value (C2) of the second lead wire (L2) canceled by the fourth negative capacitance circuit (C40), the greater the input impedance of the overall signal collection circuit, and ultimately, the better the signal collection effect. In some embodiments, the structure of the fourth negative capacitance circuit (C40) may be a structure other than that shown in FIG. 6a and FIG. 6b, and it is sufficient that the equivalent capacitance value of C40 can offset the first ground parasitic capacitance value (C1) of the first lead wire (L1) and the ground parasitic capacitance value (C2) of the second lead wire (L2), and no excessive limitations are imposed here. FIG. 7a is a schematic diagram of an effective electrical circuit before removing power frequency interference according to some embodiments of the present application. FIG. 7b is a schematic diagram of an effective electrical circuit after removing power frequency interference according to some embodiments of the present application. In some embodiments, as shown in FIG. 7a, an analog signal acquisition circuit (400) is provided, the signal acquisition circuit (400) comprises a common mode power frequency source (501), a differential amplifier (530), an electrical resistor (R5) with a resistance value of 10 MΩ, an electrical resistor (R6) with a resistance value of 100 KΩ, and electrical capacitances (C5 and C6) with a capacitance value of 6 PF each, wherein the electrical resistor (R5) is connected to the first input terminal (A1) of the differential amplifier (530) through a first lead wire (L11), the electrical resistor (R6) is connected to the second input terminal (B1) of the differential amplifier (530) through a second lead wire (L12), and one end of the electrical capacitance (C5) is connected to the first input terminal (A1) of the differential amplifier (530) and simultaneously connected to the first lead wire (L11). The other end of the electrical capacitance (C5) is grounded, and one end of the electrical capacitance (C6) is connected to the second input terminal (B1) of the differential amplifier (530) and simultaneously connected to the second lead wire (L22), and the other end of the electrical capacitance (C6) is grounded.

[0084] It should be noted that the common mode power frequency source (501) is an AC power source with a single voltage peak of 300 mV and a frequency of 50 Hz, and is used to simulate the common mode power frequency signal generated by the human body. The resistance values ​​of R5 and R6 may differ and are used to simulate the impedance formed between the two electrodes not joining when the analog actual wearable device collects the human body signal. The electrical capacitance (C5 and C6) is used to simulate the parasitic capacitance formed by the two lead wires on the ground when the actual wearable device collects the human body signal. In some embodiments, the differential amplifier (530) uses a dual-terminal power supply method, and the first power supply terminal (511) of the differential amplifier (530) is connected to a positive power supply (+Vcc), the second power supply terminal (512) is connected to a negative power supply (-Vcc), and at the same time, the end portion (513) receiving the bias voltage is grounded. In some embodiments, the positive power supply (+Vcc) provides a voltage of 3.3V, and the negative power supply (-Vcc) provides a voltage of -3.3V. In some embodiments, the signal acquisition circuit (400) includes a first probe (T1) and a second probe (T2), the first probe (T1) is positioned at the input side of the signal and connected to the first input terminal (A1) of the differential amplifier (530), and the second probe (T2) is positioned at the output side of the signal and connected to the output terminal (514) of the differential amplifier (530). The first probe (T1) and the second probe (T2) are each used to measure voltage peaks, effective values, frequencies, etc., before and after the voltage signal is input to the differential amplifier (530). The data obtained through testing is as shown in Table 1 below. Voltage peak Effective voltage DC voltage Voltage frequency 1st probe (T1) 11.4mV 196mV 196mV 50Hz 2nd probe (T2) 11.4mV 195mV 195mV 50.2Hz FIG. 7b is a schematic diagram of an effective electrical circuit after removing power frequency interference according to some embodiment of the present application. FIG. 7b adds a negative capacitance circuit (C510) and a negative capacitance circuit (C520) based on FIG. 7a. Here, the structures of the negative capacitance circuit (C510) and the negative capacitance circuit (C520) both utilize the structure of FIG. 4, and the x-point of the negative capacitance circuit (C510) and the X-point on the first lead wire (L11) are electrically connected, and the y-point of the negative capacitance circuit (C520) and the Y-point on the second lead wire (L22) are electrically connected.

[0088] In some embodiments, the first power supply terminal (521) of the operational amplifier (502) of the negative capacitance circuit (C510) is connected to a positive power supply (+Vcc), the second power supply terminal (522) is connected to a negative power supply (-Vcc), and the output terminal (523) of the operational amplifier (502) outputs an amplified voltage. In some embodiments, the positive power supply (+Vcc) provides a voltage of 3.3V, the negative power supply (-Vcc) provides a voltage of -3.3V, the magnitude of the capacitance (C501) is 6PF, and the magnitude of the electrical resistance (R51) and the electrical resistance (R51) are both 10KΩ. Based on the above formula (10), the capacitance value of the negative capacitance circuit (C510) of size 6PF can be obtained. By using a component of the same structure and value as the negative capacitance circuit (C520) as the negative capacitance circuit (C510), the magnitude of the capacitance value of the negative capacitance circuit (C520) is also -6PF. After adding two negative capacitance circuits, the data obtained using the first probe (T1) and the second probe (T2) again to verify that the power frequency interference of the entire signal collection circuit (400) has been significantly reduced is as shown in Table 2 below. Voltage peak Effective voltage DC voltage Voltage frequency 1st probe (T1) 1.17mV 196mV 196mV 50Hz 2nd probe (T2) 1.10mV 195mV 195mV 50.2Hz By comparing the data in Table 1 and Table 2, it can be seen that before adding the negative capacitance circuit (C510) and the negative capacitance circuit (C520), the voltage peaks measured by the first probe (T1) and the second probe (T2) are both 11.4 mV, and after adding the negative capacitance circuit (C510) and the negative capacitance circuit (C520), the voltage peak measured by the first probe (T1) is 1.17 mV and the voltage peak measured by the second probe (T2) is 1.10 mV. Therefore, it can be seen that after adding the negative capacitance circuit (C510) and the negative capacitance circuit (C520), the power frequency interference of the overall electrical circuit has been reduced by more than 10 times.

[0093] This result significantly reduces the risk of the electrical circuit becoming saturated by introducing a negative capacitance circuit at the input of the differential amplifier, thereby increasing the input impedance and thus reducing interference caused by the switching of the power frequency common mode to differential mode due to the electrode impedance becoming unsuitable. In some embodiments, the signal collection circuit (200) and the signal collection circuit (300) described above may be applied to a wearable device. The wearable device (e.g., clothing, wristband, shoulder strap, etc.) may be placed on various parts of the human body (e.g., calf, thigh, waist, back, chest, shoulder, neck, back) and used to collect physiological signals from each part of the user's body when the user is in a different state, and may also subsequently process the collected signals. It should be noted that the signal acquisition circuit described above may be used in situations where it is necessary to detect signals indicating the user's physical condition. For example, the physiological signals may include various signals such as respiration signals, electrocardiogram signals, myocardial signals, electroencephalogram signals, blood pressure signals, and temperature signals. In some embodiments, the wearable device for collecting physiological signals may be applied to cross-emerging industries such as medical, entertainment, and health education. For example, by combining it with technologies such as virtual reality and EMG acquisition, it can promote the development of immersive entertainment and education, and by combining it with technologies such as mechanical electronics and exoskeleton devices, it can achieve the objective of reducing the cost of medical technology and promoting the development of medical health. This application does not limit specific application scenarios of the signal acquisition circuit and the wearable device. The beneficial effects according to the embodiments of the present application include, but are not limited to, arranging a negative capacitance circuit to offset parasitic capacitance within the signal acquisition circuit, thereby effectively increasing the input impedance of the entire signal acquisition circuit and ultimately significantly reducing interference from parasitic capacitance with respect to the entire signal acquisition circuit, thereby improving the effectiveness of the collected signal of the signal acquisition circuit. It should be noted that the beneficial effects produced by different embodiments are different, and the beneficial effects that can be produced in different embodiments may be any one or a combination of several of the beneficial effects described above, or any other beneficial effects that can be obtained. The basic concepts have been explained above. Of course, to those skilled in the art, the foregoing specification is merely an example and does not constitute a limitation to this application. Although not specified herein, those skilled in the art may make various changes, improvements, and modifications to this application. Such changes, improvements, and modifications are proposed in this application, and therefore, such changes, improvements, and modifications still fall within the essence and scope of the preferred embodiments of this application. At the same time, the present application describes embodiments of the present application using specific words. For example, “one embodiment,” “one embodiment,” and / or “some embodiments” refer to a particular feature, structure, or characteristic associated with at least one embodiment of the present application. Accordingly, it should be emphasized and noted herein that “one embodiment,” “one embodiment,” or “one alternative embodiment” mentioned two or more times at different locations in the specification do not need to refer to the same embodiment. Furthermore, any feature, structure, or characteristic of one or more embodiments of the present application may be appropriately combined. Furthermore, as will be understood by those skilled in the art, each aspect of this application may describe and explain several patentable classes or situations, including any new and useful combination of processes, machines, products or materials, or any new and useful improvements thereto. Correspondingly, each aspect of this application may be performed entirely in hardware, entirely in software (ware, resident software, microcode, etc.), or implemented in combination of software and hardware. The aforementioned hardware or software may be referred to as a "data block," "module," "engine," "unit," "assembly," or "system." Additionally, each aspect of this application may be embodied in a computer product comprising computer-readable program code located on one or more computer-readable media. A computer storage medium may contain radio data signals, such as a baseband or a portion of a carrier wave, containing computer program code. The radio signals may have various representation formats, such as electromagnetic, optical, or a suitable combination of formats. The computer storage medium may be any computer-readable medium, excluding computer-readable storage media, and may implement a program used in communication, radio, or transmission when connected to a single instruction execution system, device, or facility. Program code located on the computer storage medium may be propagated via any suitable medium, such as wireless, cable, optical cable, RF, or similar media, or any combination of the above media. Furthermore, unless explicitly stated in the claims, the order of processing elements and sequences, the use of data characters, or the use of other names in this application are not intended to limit the flow and method sequence of this application. Although the foregoing specification discusses embodiments of the invention that are currently considered useful in this specification using various examples, it should be understood that such detailed description is for illustrative purposes only, and the appended claims are not limited to the embodiments for which the foregoing is described. On the contrary, the essence of the claims covers all modifications and equivalent combinations that conform to the substance and scope of the embodiments of this application. For example, the system components described above may be implemented by hardware devices, but the system components may be implemented solely by software solutions, such as mounting the system described above on a current processing unit or mobile device. Likewise, it should be noted that, in order to simplify the expressions disclosed in the specification of this application and thus aid in understanding one or more embodiments of this specification, in the description of the embodiments of this application, multiple features may, in some cases, be combined into a single example, drawing, or description. However, this method of specification does not imply that the features required for the subject of this application are greater than the features mentioned in the claims. In fact, the features of the above embodiments are fewer than the entirety of the single embodiment described above. In some embodiments, numbers are used to denote components and properties, and it should be understood that the numbers used to describe these embodiments are modified in some exemplary examples by the modifiers “about,” “similar,” or “generally.” Unless otherwise noted, “about,” “similar,” or “generally” may indicate that a variation of ±20% is permitted for the described value. Correspondingly, in some embodiments, the numerical parameters used in the specification and claims are all approximations, and such approximations may vary depending on the features required in individual embodiments. In some embodiments, numerical parameters must take into account the defined significant figures and adopt a general method of retaining digits. While the ranges and parameters of the numbers used to determine the ranges in some embodiments of this application are approximations, in specific embodiments, the setting of these numbers is as accurate as possible within the possible range. All patents, patent applications, disclosures and texts of patent applications, books, specifications, publications, documents, and other materials cited in this application are incorporated herein by reference. Any application history that is inconsistent with or conflicts with the contents of this application is excluded, as are any documents (currently or subsequently attached to this application) that limit the broadest scope of the claims of this application. It must be noted that any parts of the descriptions, definitions, and / or use of terms in the attached materials of this application that are inconsistent with or conflict with the contents of this application shall be based on the descriptions, definitions, and / or use of terms in this application. Finally, it should be understood that the above embodiments in this application are merely for illustrating the principles of the embodiments of this application. Other variations may also fall within the scope of this application. Accordingly, alternative arrangements of the embodiments of this application may be considered consistent with the teachings of this application as a non-limiting example. Accordingly, the embodiments of this application are not limited to the embodiments explicitly introduced and described in this application.

Claims

Claim 1 A signal collection circuit comprising a differential amplifier, a first electrode and a second electrode, a first negative capacitance circuit and a second negative capacitance circuit, and a third negative capacitance circuit, wherein the first electrode is connected to a first input terminal of the differential amplifier through a first lead wire, and the second electrode is connected to a second input terminal of the differential amplifier through a second lead wire, wherein the first negative capacitance circuit electrically connects the first lead wire to a ground wire, and the second negative capacitance circuit electrically connects the second lead wire to a ground wire, and wherein both the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect, and the third negative capacitance circuit electrically connects the first lead wire to the second lead wire, and the third negative capacitance circuit has a negative capacitance effect. Claim 2 A signal collection circuit according to claim 1, wherein the absolute value of the equivalent capacitance value of the first negative capacitance circuit and the relative error between the ground parasitic capacitance value of the first lead wire is less than 50%, and the absolute value of the equivalent capacitance value of the second negative capacitance circuit and the relative error between the ground parasitic capacitance value of the second lead wire is less than 50%. Claim 3 A signal collection circuit according to claim 1, wherein a first equivalent input capacitance exists at the first input terminal of the differential amplifier and a second equivalent input capacitance exists at the second input terminal of the differential amplifier, wherein the relative error between the absolute value of the equivalent capacitance value of the first negative capacitance circuit and the first sum is less than 50%, wherein the first sum is the sum of the ground parasitic capacitance of the first lead wire and the first equivalent input capacitance, and the relative error between the absolute value of the equivalent capacitance value of the second negative capacitance circuit and the second sum is less than 50%, wherein the second sum is the sum of the ground parasitic capacitance of the second lead wire and the second equivalent input capacitance. Claim 4 A signal collection circuit according to claim 1, wherein the absolute value of the equivalent capacitance value of the third negative capacitance circuit and the relative error between the parasitic capacitance value between the first lead wire and the second lead wire is less than 50%. Claim 5 In claim 1, the first negative capacitance circuit comprises a first operational amplifier, a first electrical resistor, a second electrical resistor, and a first capacitance, and the second negative capacitance circuit comprises a second operational amplifier, a third electrical resistor, a fourth electrical resistor, and a second capacitance, wherein the opposite input terminal of the first operational amplifier is grounded through the first electrical resistor and simultaneously connects the second electrical resistor to the output terminal of the first operational amplifier, and the same input terminal of the first operational amplifier is connected through the first capacitance and the output terminal of the first operational amplifier, and the opposite input terminal of the second operational amplifier is grounded through the third electrical resistor and simultaneously connects the fourth electrical resistor to the output terminal of the second operational amplifier, and the same input terminal of the second operational amplifier is connected through the second capacitance and the output terminal of the second operational amplifier. Claim 6 A signal collection circuit according to claim 5, wherein the same-direction input terminal of the first operational amplifier and the first lead wire are connected, and the same-direction input terminal of the second operational amplifier and the second lead wire are connected. Claim 7 In claim 1, the signal acquisition circuit further comprises a feedback control circuit for adjusting the equivalent capacitance value of the first negative capacitance circuit and the second negative capacitance circuit. Claim 8 As a signal acquisition circuit, the differential amplifier, a first electrode and a second electrode, a first negative capacitance circuit and a second negative capacitance circuit, a third negative capacitance circuit, and a fourth negative capacitance circuit are included, wherein the first electrode is connected to the first input terminal of the differential amplifier through a first lead wire, and the second electrode is connected to the second input terminal of the differential amplifier through a second lead wire, the first negative capacitance circuit electrically connects the first lead wire and a ground wire, and the second negative capacitance circuit electrically connects the second lead wire and a ground wire, and both the first negative capacitance circuit and the second negative capacitance circuit have a negative capacitance effect, the third negative capacitance circuit electrically connects the first lead wire and the second lead wire, and the third negative capacitance circuit has a negative capacitance effect, and in the fourth negative capacitance circuit, the first electrode through the first lead wire the fourth negative A signal collection circuit connected to a first input terminal of a capacitance circuit, wherein the second electrode is connected to a second input terminal of a fourth negative capacitance circuit through the second lead wire, wherein the first output terminal of the fourth negative capacitance circuit is connected to a first input terminal of a differential amplifier, and the second output terminal of the fourth negative capacitance circuit is connected to a second input terminal of a differential amplifier, and wherein the fourth negative capacitance circuit has a negative capacitance effect. Claim 9 In claim 8, the fourth negative capacitance circuit comprises a dual-terminal differential amplifier, a first negative feedback capacitance, and a second negative feedback capacitance, wherein the first negative feedback capacitance is connected between the first input terminal of the dual-terminal differential amplifier and the first output terminal of the dual-terminal differential amplifier, and the second negative feedback capacitance is connected between the second input terminal of the dual-terminal differential amplifier and the second output terminal of the dual-terminal differential amplifier, thereby forming a signal collection circuit. Claim 10 In paragraph 9, the above dual-terminal differential amplifier is a signal collection circuit that is a fixed-gain amplifier. Claim 11 In claim 8, the fourth negative capacitance circuit comprises a first unit and a second unit, wherein the first unit comprises a first amplifier and a third negative feedback capacitance, and the second unit comprises a second amplifier and a fourth negative feedback capacitance, wherein the third negative feedback capacitance is connected between the input terminal of the first amplifier and the output terminal of the first amplifier, and the fourth negative feedback capacitance is connected between the input terminal of the second amplifier and the output terminal of the second amplifier. Claim 12 A signal collection circuit according to claim 11, wherein the absolute value of the equivalent capacitance value of the first unit of the fourth negative capacitance circuit and the relative error between the ground parasitic capacitance value of the first lead wire is less than 50%, and the absolute value of the equivalent capacitance value of the second unit of the fourth negative capacitance circuit and the relative error between the ground parasitic capacitance value of the second lead wire is less than 50%. Claim 13 In claim 8, the signal collection circuit comprises a feedback control circuit for adjusting the equivalent capacitance value of the fourth negative capacitance circuit. Claim 14 A wearable device comprising a signal collection circuit according to any one of claims 1 to 13. Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete

Images