High speed flip flop circuitincluding delay circuit

Abstract

A flip-flop according to the technical concept of the present disclosure includes a delay circuit that receives a clock signal and generates a first internal signal, a master latch that generates an internal output signal by latching a data signal based on the first internal signal, and a slave latch that generates a final signal by latching the internal output signal. The delay circuit generates the first internal signal by delaying the clock signal by a delay time when the clock signal is at a first logic level, and generates the first internal signal based on the data signal when the clock signal is at a second logic level.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to a flip-flop circuit, and more specifically, to a high-speed flip-flop circuit including a delay circuit. Background Technology

[0002] As semiconductor integrated circuits become higher in performance and more highly integrated, the number of flip-flops included in them is increasing. Flip-flops are used as data storage devices, and these data storage devices are used to store state. Flip-flops are electronic circuits capable of storing and maintaining 1-bit information and are a fundamental element of sequential logic circuits. Since flip-flops can transmit data based on the active edge of a clock signal, the frequency of the clock signal can be used as a measure of the performance of the semiconductor integrated circuit. The problem to be solved

[0003] The technical concept of the present disclosure relates to a flip-flop circuit including a delay circuit, and can provide a flip-flop circuit capable of increasing the frequency of a clock signal by latching a data signal according to a first internal signal. means of solving the problem

[0004] To achieve the above objectives, a flip-flop according to one aspect of the present disclosure comprises a delay circuit that receives a clock signal and generates a first internal signal, a master latch that generates an internal output signal by latching a data signal based on the first internal signal, and a slave latch that generates a final signal by latching the internal output signal. The delay circuit generates the first internal signal by delaying the clock signal by a delay time when the clock signal is at a first logic level, and generates the first internal signal based on the data signal when the clock signal is at a second logic level.

[0005] A flip-flop according to another aspect of the present disclosure comprises a first latch that receives a data signal and a clock signal and outputs an internal output signal, and a second latch that outputs a final signal by latching the internal output signal according to the clock signal. The first latch comprises a delay circuit that generates a first internal signal by delaying the clock signal by a delay time, and generates an internal output signal by latching the data signal according to the first internal signal.

[0006] A flip-flop according to another aspect of the present disclosure comprises: a first OAI21 logic circuit that receives a scan input signal, an inverted scan enable signal, and an inverted clock signal and outputs an intermediate signal; a second OAI21 logic circuit that receives an internal output signal, an inverted clock signal, and an intermediate signal and outputs a first internal signal; an OAI31 logic circuit that receives a second internal signal, an inverted scan enable signal, a data signal, and a first internal signal and outputs an internal output signal; a NOR2 logic circuit that receives an inverted clock signal and an internal output signal and outputs a second internal signal; an AOI21 logic circuit that receives an inverted signal, an inverted clock signal, and a second internal signal and outputs an inverted final signal; a first inverter that outputs an inverted signal by inverting the inverted final signal; and a second inverter that generates a final signal by inverting the inverted final signal. Effects of the invention

[0007] According to an exemplary embodiment of the present disclosure, a flip-flop circuit capable of increasing the frequency of a clock signal by latching a data signal according to a first internal signal can be provided. Brief explanation of the drawing

[0008] FIG. 1 is a drawing for illustrating a flip-flop according to an exemplary embodiment of the present disclosure. Figure 2 is a diagram illustrating an integrated circuit operating in normal operation mode and scan test mode. FIG. 3 is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 4 is a drawing illustrating an example of a delay circuit according to an exemplary embodiment of the present disclosure. FIG. 5 is a drawing illustrating an AOI31 logic circuit according to an exemplary embodiment of the present disclosure. FIG. 6 is a diagram showing a circuit diagram of a second AOI21 logic circuit according to an exemplary embodiment of the present disclosure. FIG. 7a is a circuit diagram illustrating an example of an AOI31 logic circuit according to an exemplary embodiment of the present disclosure. FIG. 7b is a circuit diagram illustrating an example of an AOI31 logic circuit according to an exemplary embodiment of the present disclosure. FIG. 8 is a drawing illustrating an example of a slave latch according to an exemplary embodiment of the present disclosure. FIG. 9a is a circuit diagram for illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 9b is a circuit diagram for illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 9c is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 10a is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 10b is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 10c is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 10d is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 10e is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 11 is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 12a is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 12b is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIGS. 13a and FIGS. 13b are circuit diagrams for illustrating the normal operation mode of a flip-flop according to an exemplary embodiment of the present disclosure. FIGS. 14a and FIGS. 14b are circuit diagrams for illustrating the normal operation mode of a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 15 is a timing diagram for a flip-flop according to an exemplary embodiment of the present disclosure. Specific details for implementing the invention

[0009] Hereinafter, various embodiments of the present invention are described with reference to the accompanying drawings.

[0010] FIG. 1 is a drawing for illustrating a flip-flop according to an exemplary embodiment of the present disclosure. Referring to FIG. 1, a flip-flop (10) according to an exemplary embodiment of the present disclosure may be a scan flip-flop that receives a data signal (D), a scan input signal (SI), or a scan enable signal (SE) and outputs a final signal (Q) according to a clock signal (CK).

[0011] The scan enable signal (SE) may indicate a first operation mode or a second operation mode depending on the logic level. Specifically, the scan enable signal (SE) may indicate a first operation mode when it is at a first logic level (e.g., a logic low level), and the scan enable signal (SE) may indicate a second operation mode when it is at a second logic level (e.g., a logic high level). For example, the first operation mode may be a normal operation mode that performs data transfer, and the second operation mode may be a scan test mode that performs a test operation. However, this is merely one embodiment of the present invention, and in some embodiments, the first operation mode may be a scan test mode and the second operation mode may be a normal operation mode.

[0012] When the scan enable signal (SE) indicates a normal operation mode, the flip-flop (10) can perform a normal operation by latching the data signal (D) to provide a final signal (Q). When the scan enable signal (SE) indicates a scan test mode, the flip-flop (10) can perform a scan test operation by latching the scan input signal (SI) to provide a final signal (Q).

[0013] A flip-flop (10) according to an exemplary embodiment of the present disclosure may include a master latch (200) and a slave latch (300). The master latch (200) may receive a data signal (D) or a scan input signal (SI) according to a scan enable signal (SE) and output an internal output signal (Qm). The slave latch (300) may receive the internal output signal (Qm) and output a final signal (Q).

[0014] A master latch (200) according to an exemplary embodiment of the present disclosure may include a delay circuit (100). As described below through FIG. 3, the delay circuit (100) may receive a clock signal (CK) and output a first internal signal (DCK). The master latch (200) may obtain a reduced setup time for latching a data signal (D) by latching the data signal (D) based on the first internal signal (DCK). The setup time may mean a minimum time during which the value of the data signal (D) must be maintained constant before the active edge of the clock signal (CK) so that the data signal (D) is output as a final signal (Q).

[0015] The slave latch (300) receives a clock signal (CK) and can output a second internal signal (CKb) representing an inverted value of the clock signal (CK). For example, as described below with reference to FIG. 14a, when the clock signal (CK) is at a logic low level, the second internal signal (CKb) may be at a logic high level. The second internal signal (CKb) may be a signal generated at an internal node of the slave latch (300). The flip-flop (10a) according to an exemplary embodiment of the present disclosure can obtain the second internal signal (CKb) from an internal node of the slave latch (300) without having a separate clock inverter for inverting the clock signal (CK), thereby reducing the power consumed by the clock inverter.

[0016] Figure 2 is a diagram illustrating an integrated circuit operating in normal operation mode and scan test mode. Referring to FIG. 2, the integrated circuit (100) may include a combinational logic circuit (1) and a plurality of scan flip-flops (10-1, 10-2, 10-3). The combinational logic circuit (1) may be a circuit that outputs the same output data for the same input data. The plurality of scan flip-flops (10-1, 10-2, 10-3) may be sequential logic circuits. The sequential logic circuit may be a circuit that includes a memory element. The sequential logic circuit may be a circuit that outputs different output data depending on the memory state, even if the same input data is input.

[0017] When the scan enable signal (SE) indicates a normal operation mode, data can be transmitted along the data path, and the original function of the integrated circuit (100) can be performed. When the scan enable signal (SE) indicates a scan test mode, a scan test operation can be performed by transmitting data along the scan test path. In the scan test operation, errors occurring in the sequential logic circuit can be identified by comparing the scan test pattern (STP) and the output pattern (OP). The scan test pattern (STP) is an input bit sequence, and the output pattern (OP) may be an output bit sequence corresponding to the scan test pattern (STP).

[0018] FIG. 3 is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. FIG. 4 is a drawing illustrating an example of a delay circuit according to an exemplary embodiment of the present disclosure. FIG. 5 is a drawing illustrating an AOI31 logic circuit according to an exemplary embodiment of the present disclosure. Referring to FIG. 3, the flip-flop (10a) may include a master latch (200a) and a slave latch (300a).

[0019] The master latch (200a) may include a delay circuit (100a). The delay circuit (110a) receives a scan input signal (SI), a scan enable signal (SE), a clock signal (CK), and an internal output signal (Qm) which is an output signal of the master latch (200), and may output a first internal signal (DCK).

[0020] The delay circuit (100a) may include two AOI (AND-OR-INVERTER) 21 logic circuits (110, 120). An AOI 21 logic circuit may be a logic circuit in which an AND gate having two signals as inputs, the output of the AND gate, an OR gate having another signal as input, and an inverter are connected sequentially.

[0021] Specifically, the first AOI21 logic circuit (110) can receive a scan input signal (SI), a scan enable signal (SE), and a clock signal (CK) as inputs and output an intermediate signal (F). Referring to FIG. 4, in an exemplary embodiment, the first AOI21 logic circuit (110) may include an AND gate (111) that receives the scan input signal (SI) and the scan enable signal (SE) as inputs. The first AOI21 logic circuit (110) may include a NOR gate (112) that receives the output signal of the AND gate (111) and the clock signal (CK) as inputs and outputs an intermediate signal (F).

[0022] Referring to FIG. 3, the second AOI21 logic circuit (120) receives an internal output signal (Qm), a clock signal (CK), and an intermediate signal (F), which are output signals of the master latch (200a), as inputs, and can output a first internal signal (DCK). Referring to FIG. 4, the second AOI21 logic circuit (120) may include an AND gate (121) that receives the internal output signal (Qm) and the clock signal (CK) as inputs. The second AOI21 logic circuit (120) may include a NOR gate (122) that receives the output signal of the AND gate (121) and the intermediate signal (F) as inputs and outputs a first internal signal (DCK).

[0023] Referring to FIG. 3, the master latch (200a) may include a first inverter (400). The first inverter (400) may receive a scan enable signal (SE) as an input and output an inverted scan enable signal (nSE). The embodiment is not limited thereto, and the first inverter (400) may be located outside the master latch (200a).

[0024] The master latch (200a) may include an AOI31 logic circuit (220a). In an exemplary embodiment, the AOI31 logic circuit may be a logic circuit in which an AND gate having three signals as inputs, an OR gate having the output of the AND gate and another signal as inputs, and an inverter are connected sequentially.

[0025] The AOI31 logic circuit (220a) receives a second internal signal (CKb), a data signal (D), an inverted scan enable signal (nSE), and a first internal signal (DCK) as inputs from a slave latch (300a), and can output an internal output signal (Qm). Referring to FIG. 5, in an exemplary embodiment, the AOI31 logic circuit (220a) may include an AND gate (221) that receives the second internal signal (CKb), the data signal (D), and the inverted scan enable signal (nSE) as inputs. The AOI31 logic circuit (220a) may include a NOR gate (222) that receives the output signal of the AND gate (221) and the first internal signal (DCK) as inputs and outputs an internal output signal (Qm).

[0026] Referring to FIG. 3, the slave latch (300a) may include a 2-input NAND gate (310a). The 2-input NAND gate (310a) receives an internal output signal (Qm) and a clock signal (CK) as inputs and may output a second internal signal (CKb). When the clock signal (CK) is at a first logic level, the second internal signal (CKb) may have a second logic level in which the first logic level is inverted by the 2-input NAND gate (310a). For example, when the clock signal (CK) is at a logic low level, the second internal signal (CKb) may be at a logic high level by the 2-input NAND gate (310a). A flip-flop (10a) according to an exemplary embodiment of the present disclosure may provide a second internal signal (CKb) that inverts a specific logic level of the clock signal (CK) even without having a clock inverter dedicated to inverting the clock signal (CK). Therefore, the power consumed by the clock inverter can be reduced.

[0027] The slave latch (300a) may include an OAI21 logic circuit (320). In an exemplary embodiment, the OAI21 logic circuit may be a logic circuit in which an OR gate having three signals as inputs, an AND gate having the output of the OR gate and another signal as inputs, and an inverter are sequentially connected. The OAI21 logic circuit (320) may receive an inverted signal (Qi) obtained by inverting the output signal (QN) of the OAI21 logic circuit (320), a clock signal (CK), and a second internal signal (CKb), and output the output signal (QN).

[0028] The slave latch (300a) may include a second inverter (330) and a third inverter (340). The second inverter (330) may receive an output signal (QN) and provide an inverted signal (Qi), which is the output signal (QN) inverted, to the OAI21 logic circuit (320). The third inverter (340) may receive an output signal (QN) and output a final signal (Q), which is the output signal (QN) inverted.

[0029] FIG. 6 is a diagram showing a circuit diagram of a second AOI21 circuit according to an exemplary embodiment of the present disclosure. Referring to FIG. 6, the second AOI21 circuit (120) may include a pull-up section (123) and a pull-down section (124). The pull-up section (123) may generate a first internal signal (DCK) of a logic high level, and the pull-down section (124) may generate a first internal signal (DCK) of a logic low level.

[0030] In this specification, the transistor may be a transistor comprising an active pattern. The active pattern may be, for example, a fin-shaped active pattern, and the transistor formed by the active pattern and the gate electrode may be referred to as a fin field effect transistor (FinFET). However, the embodiments are not limited thereto, and the active pattern may include nanosheets. The transistor formed by the nanosheets and the gate electrode may be referred to as a multi-bridge channel FET (MBCFET). Additionally, it may include a ForkFET in which the N-type transistor and the P-type transistor have a structure in which the nanosheets for the P-type transistor and the nanosheets for the N-type transistor are separated by a dielectric wall. Furthermore, the cell may include a vertical FET (VFET) having a structure in which the source / drain regions are spaced apart from each other with the channel region in between, and the gate electrode surrounds the channel region. Additionally, the transistor may be one of a field effect transistor (FET), such as a complementary FET (CFET), a negative FET (NCFET), or a carbon nanotube (CNT) FET. In this specification, the transistor may be one of a bipolar junction transistor or other three-dimensional transistors. In this specification, a P-type transistor may refer to a transistor formed in a P-type active region, and an N-type transistor may refer to a transistor formed in an N-type active region.

[0031] The pull-up unit (123) may include a plurality of P-type transistors (P1 to P4). An intermediate signal (F) may be input to the gate terminal of the first P-type transistor (P1), a clock signal (CK) may be input to the gate terminal of the second P-type transistor (P2), an internal output signal (Qm) may be input to the gate terminal of the third P-type transistor (P3), and an intermediate signal (F) may be input to the gate terminal of the fourth P-type transistor (P4).

[0032] A first P-type transistor (P1) and a second P-type transistor (P2) can be connected in series to form a series structure. For example, as shown in FIG. 6, the drain terminal of the first P-type transistor (P1) can be connected to the source terminal of the second P-type transistor (P2). However, the embodiment is not limited thereto, and the source terminal of the first P-type transistor (P1) can also be connected to the drain terminal of the second P-type transistor (P2). One end of the series structure can be connected to a supply power (VDD) node, and the other end can be connected to a first node (M1) where a first internal signal (DCK) is output.

[0033] The third P-type transistor (P3) and the fourth P-type transistor (P4) can form a series structure by being connected in series. For example, as shown in FIG. 6, the drain terminal of the third P-type transistor (P3) can be connected to the source terminal of the fourth P-type transistor (P4). However, the embodiment is not limited thereto, and the source terminal of the third P-type transistor (P3) can also be connected to the drain terminal of the fourth P-type transistor (P4). One end of the series structure can be connected to the supply power (VDD) node, and the other end can be connected to the first node (M1).

[0034] The pull-down section (124) may include N-type transistors (N1 to N3). An intermediate signal (F) may be input to the gate terminal of the first N-type transistor (N1), a clock signal (CK) may be input to the gate terminal of the second N-type transistor (N2), and an internal output signal (Qm) may be input to the gate terminal of the third N-type transistor (N3).

[0035] The source terminal of the first N-type transistor (N1) can be connected to a ground node, and the drain terminal can be connected to the first node (M1).

[0036] The second N-type transistor (N2) and the third N-type transistor (N3) can form a series structure by being connected in series. For example, as shown in FIG. 6, the source terminal of the second N-type transistor (N2) can be connected to the drain terminal of the third N-type transistor (N3). However, the embodiment is not limited thereto, and the drain terminal of the second N-type transistor (N2) can also be connected to the source terminal of the third N-type transistor (N3). One end of the series structure can be connected to a ground node, and the other end can be connected to a first node (M1).

[0037] An AOI21 logic circuit (120) according to an exemplary embodiment of the present disclosure is provided with a plurality of P-type transistors (P1, P4) that receive an intermediate signal (F) at a pull-up section (123), so that a serial structure including a second P-type transistor (P2) and a serial structure including a third P-type transistor (P3) can be connected to separate supply power nodes. Thus, the degree of routing freedom can be improved.

[0038] FIG. 7a is a circuit diagram illustrating an example of an AOI31 logic circuit according to an exemplary embodiment of the present disclosure. Referring to FIG. 7a, the AOI31 logic circuit (220a-1) may include a pull-up section (223-1) and a pull-down section (224-1). The pull-up section (223-1) may generate an internal output signal (Qm) of a logic high level, and the pull-down section (224-1) may generate an internal output signal (Qm) of a logic low level.

[0039] The pull-up section (223-1) may include P-type transistors (P5a to P8a). A first internal signal (DCK) may be input to the gate terminal of the fifth P-type transistor (P5a), the source terminal may be connected to a supply power (VDD) node, and the drain terminal may be connected to a second node (M2). An inverted scan enable signal (nSE) may be input to the gate terminal of the sixth P-type transistor (P6a), the source terminal may be connected to a second node (M2), and the drain terminal may be connected to a third node (M3). A data signal (D) may be input to the gate terminal of the seventh P-type transistor (P7a), the source terminal may be connected to a second node (M2), and the drain terminal may be connected to a third node (M3). The gate terminal of the eighth P-type transistor (P8a) can receive the second internal signal (CKb), the source terminal can be connected to the supply power (VDD) node, and the drain terminal can be connected to the third node (M3). The third node (M3) can be the node where the internal output signal (Qm) is output.

[0040] The pull-down section (224-1) may include N-type transistors (N4a to N7a). A first internal signal (DCK) may be input to the gate terminal of the fourth N-type transistor (N4a). A data signal (D) may be input to the gate terminal of the fifth N-type transistor (N5a). A second internal signal (CKb) may be input to the gate terminal of the sixth N-type transistor (N6a). An inverted scan enable signal (nSE) may be input to the gate terminal of the seventh N-type transistor (N7a). The fifth to seventh N-type transistors (N5a to N7a) may form a series structure by being connected in series. For example, as shown in FIG. 7, the drain terminal of the fifth N-type transistor (N5a) may be connected to the sixth node (M6), and the source terminal may be connected to the drain terminal of the sixth N-type transistor (N6a). The source terminal of the sixth N-type transistor (N6a) may be connected to the drain terminal of the seventh N-type transistor (N7a). The source terminal of the seventh N-type transistor (N7a) may be connected to a ground node. The embodiments are not limited thereto, and the order in which the fifth to seventh N-type transistors (N5a to N7a) are connected in series may vary.

[0041] As described below in FIGS. 13b and 14b, in a flip-flop according to an exemplary embodiment of the present disclosure, if the clock signal (CK) is at a logic high level, the first internal signal (DCK) and the second internal signal (CKb) may be at the same logic level as the data signal (D). On the other hand, if the clock signal (CK) is at a logic low level, the first internal signal (DCK) may be at a logic low level and the second internal signal (CKb) may be at a logic high level. That is, in the AOI31 logic circuit (220a-1), a situation in which the first internal signal (DCK) is at a logic high level and the second internal signal (CKb) is at a logic low level may not occur. Accordingly, it can operate as an AOI31 logic circuit even if the source terminal of the eighth P-type transistor (P8a) is not connected to the second node (M2). Therefore, by connecting the source terminal of the 8th P-type transistor (P8a) to a separate power supply node, the overall routing freedom of the flip-flop can be increased.

[0042] FIG. 7b is a circuit diagram illustrating an example of an AOI31 logic circuit according to an exemplary embodiment of the present disclosure. Referring to FIG. 7b, the AOI31 logic circuit (220a-2) may include a pull-up section (223-2) and a pull-down section (224-2).

[0043] Unlike the AOI logic circuit (220a-1) of FIG. 7a, the source terminal of the eighth P-type transistor (P8b) of the AOI31 logic circuit (220a-2) can be connected to the second node (M2) in common with the source terminals of the sixth and seventh P-type transistors (P6b, P7b).

[0044] Additionally, the drain terminal of the sixth N-type transistor (N6b) of the AOI31 logic circuit (220a-2) can be connected to the third node (M3) where the internal output signal (Qm) is output, and the source terminal can be connected to the fourth node (M4). The drain terminal of the fourth N-type transistor (N4b) can be connected to the fourth node (M4), and the source terminal can be connected to the ground node. The fifth N-type transistor (N5b) and the seventh N-type transistor (N7b) can be connected in series to form a series structure. One end of the series structure can be connected to the fourth node (M4), and the other end can be connected to the ground node.

[0045] As described below in FIGS. 13b and 14b, in a flip-flop according to an exemplary embodiment of the present disclosure, when the clock signal (CK) is at a logic high level, the first internal signal (DCK) and the second internal signal (CKb) may be at the same logic level as the data signal (D). Meanwhile, when the clock signal (CK) is at a logic low level, the first internal signal (DCK) may be at a logic low level and the second internal signal (CKb) may be at a logic high level. That is, in the AOI31 logic circuit (220a-2), when the first internal signal (DCK) is at a logic high level, the second internal signal (CKb) may also be at a logic high level.

[0046] Therefore, even if the drain terminal of the fourth N-type transistor (N4b) is not connected to the third node (M3) but to the fourth node (M4), the AOI31 logic circuit (220a-1) can operate normally. Thus, since the drain terminal of the fourth N-type transistor (P4b) can be selectively connected to the third node (M3) or the fourth node (M7), the routing freedom of the flip-flop can be increased.

[0047] FIG. 8 is a drawing illustrating an example of a slave latch according to an exemplary embodiment of the present disclosure. Referring to FIG. 8, the slave latch (300a) receives an internal output signal (Qm) and a clock signal (CK) as inputs and can output a final signal (Q).

[0048] The slave latch (300a) may include a NAND gate (310a). The NAND gate (310a) may receive an internal output signal (Qm) and a clock signal (CK) as inputs and output a second internal signal (CKb). The second internal signal (CKb) may have a logic level opposite to the level of the clock signal (CK) when the clock signal (CK) is at a specific logic level. For example, when the clock signal (CK) is at a logic low level, the second internal signal (CKb) may be at a logic high level regardless of the internal output signal (Qm). Thus, the flip-flop according to the exemplary embodiment of the present disclosure may generate a second internal signal that inverts the clock signal when the clock signal is at a specific level, even without a clock inverter.

[0049] The slave latch (300a) may include an OAI21 logic circuit (320). The OAI21 logic circuit (320) may include an OR gate (321) and a NAND gate (322). The OR gate (321) may receive an inverted signal (Qi) obtained by inverting the output signal (QN) of the OAI21 logic circuit (320) and a clock signal (CK) as inputs. The NAND gate (322) may receive the output signal of the OR gate (321) and a second internal signal (CKb) as inputs, and output an output signal (QN).

[0050] The slave latch (300a) may include two inverters (330, 340). The second inverter (330) may receive an output signal (QN) and provide an inverted signal (Qi) obtained by inverting the output signal (QN) to the OAI21 logic circuit (320). The third inverter (340) may receive an output signal (QN) and output a final signal (Q) obtained by inverting the output signal (QN).

[0051] FIG. 9a is a circuit diagram for illustrating a flip-flop according to an exemplary embodiment of the present disclosure.Referring to FIG. 9a, the flip-flop (10a-2) may further include a clock buffer (500). The clock buffer (500) may include two inverters. The clock buffer (500) may receive a clock signal (CK) and output a buffered clock signal (bCK). Unlike the flip-flop (10a) disclosed in FIG. 3, the flip-flop (10a-2) according to an exemplary embodiment of the present disclosure may receive a buffered clock signal (bCK) instead of a clock signal (CK).

[0052] The buffered clock signal (bCK) may have a predetermined buffer delay time (tb) compared with the clock signal (CK). As shown in FIG. 2, among the flip-flops (10-1, 10-2, 10-3) included in the integrated circuit (100), the flip-flop receiving the relatively delayed data signal can coordinate the data latching timing with the other flip-flops by receiving the buffered clock signal (bCK).

[0053] Meanwhile, the slew rate of the buffered clock signal (bCK) may be greater than the slew rate of the clock signal (CK). Since the data signal is latched according to the active edge, the reliability of the flip-flop can be improved as the slew rate increases. According to an exemplary embodiment of the present disclosure, the reliability of data latching can be increased by applying a buffered clock signal (bCK) having a relatively high slew rate to the flip-flop instead of the clock signal (CK).

[0054] FIG. 9b is a circuit diagram for illustrating a flip-flop according to an exemplary embodiment of the present disclosure.Referring to FIG. 9b, the flip-flop (10a-3) may include a slave latch (300a-2). Unlike the slave latch (300a) of FIG. 3, the slave latch (300a-2) may include an AND gate (350) and a NOR gate (360). The AND gate (350) may receive an internal output signal (Qm) and a clock signal (CK), as in the NAND gate (310a) of FIG. 3. The NOR gate (360) may receive the output of the AND gate (350) and a reset signal (RST).

[0055] If the reset signal (RST) is at a logic high level, the output of the NOR gate (360) becomes a logic low level, and the final signal (Q) can be reset to a logic low level.

[0056] When the reset signal (RST) is at a logic low level, the NOR gate (360) can operate as an inverter. Thus, the AND gate (350) and the NOR gate (360) can be connected in series to operate like the NAND gate (310a) of FIG. 3.

[0057] FIG. 9c is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. Referring to FIG. 9c, the flip-flop (10a-4) may include a 12th P-type transistor (P12). The slave latch (300a-3) may include a glitch protection circuit (370) and an inverter (380).

[0058] An internal output signal (Qm) can be input to the gate terminal of the 12th P-type transistor (P12), the source terminal can be connected to a supply power node, and the drain terminal can be connected to the 6th node (M6).

[0059] Referring to FIGS. 13b and 14b, when the clock signal (CK) is at a logic high level, the internal output signal (Qm) has a logic level that is the inverted version of the data signal (D), and the second internal signal (CKb) may have the same logic level as the data signal (D).

[0060] Referring to FIG. 9c, when the clock signal (CK) is at a logic high level, the eighth N-type transistor (N8) is turned on, and the second internal signal (CKb) of the fifth node (M5) can be input to the source terminal of the second N-type transistor (N2) through the sixth node (M6). Meanwhile, since the second N-type transistor (N2) can be turned on by the clock signal (CK), the second internal signal (CKb) transmitted from the source terminal can be applied to the first node (M1). When the clock signal (CK) is at a logic high level, the second internal signal (CKb) can have the same logic level as the data signal (D), so the first internal signal (DCK) representing the signal of the first node (M1) can have the same logic level as the data signal (D).

[0061] However, when the data signal (D) is at a logic high level, the logic level of the 6th node (M6) may be lower than the level of the data signal (D) due to the threshold voltage of the 8th N-type transistor (N8). Since the logic level of the 6th node (M6) may be lowered when the level of the 6th node (M6) is lowered, the logic level of the 1st internal signal (DCK) may also be lowered, so an error may occur in the overall operation of the flip-flop (10a-4). That is, since a low voltage may be applied to the AOI31 logic circuit (220a) due to the threshold voltage of the 8th N-type transistor (N8), the flip-flop (10a-4) may perform a low-voltage operation.

[0062] The 12th P-type transistor (P12) is turned on when the data signal (D) is at a logic high level, so the logic level of the 6th node (M6) can be raised. Accordingly, the logic level of the 1st internal signal (DCK) can also be maintained at a logic high level, so the low-voltage operation of the flip-flop (10a-4) can be improved.

[0063] The glitch protection circuit (370) may include a 14th P-type transistor (P14), a 12th N-type transistor (N12), and a 13th N-type transistor (N13).

[0064] As described below through FIGS. 13b and 14b, when the clock signal (CK) is at a logic high level, the second internal signal (CKb) may be the same as the logic level of the data signal (D). That is, when the clock signal (CK) is at a logic high level, the data signal (D) may be input to the gate terminal of the 14th P-type transistor (P14). Also, when the clock signal (CK) is at a logic high level, the 8th N-type transistor (N8) is turned on, so the data signal (D) may be input to the gate terminal of the 12th N-type transistor (N12). When the clock signal (CK) is at a logic high level, the 13th N-type transistor (N13) is turned on, so the glitch protection circuit (370) may operate as an inverter in which the data signal (D) is received by the 12th N-type transistor (N12) and the 14th P-type transistor (P14).

[0065] However, when the data signal (D) is at a logic high level, the logic level of the 6th node (M6) may be lower than the level of the data signal (D) due to the threshold voltage of the 8th N-type transistor (N8). When the level of the 6th node (M6) is lowered, the 12th N-type transistor (N12) may not be turned on, and the glitch protection circuit (370) may not operate as an inverter. If the glitch protection circuit (370) does not operate as an inverter, the output signal (QN) may differ from the inverted value of the data signal (D), so a glitch may occur in the final signal (Q).

[0066] As described above, the 12th P-type transistor (P12) is turned on when the data signal (D) is at a logic high level, so the logic level of the 6th node (M6) can be raised. Accordingly, the 12th N-type transistor (N12) can be turned on normally, and the glitch protection circuit (370) can operate as an inverter. That is, by the 12th P-type transistor (P12) providing a stable logic high signal to the glitch protection circuit (370), glitches that may occur in the final signal (Q) can be prevented.

[0067] Meanwhile, when the clock signal (CK) is at a logic low level, the second internal signal (CKb) is at a logic high level, so the 13th N-type transistor (N13) and the 14th P-type transistor (P14) can be turned off. Also, since the inverter (380) is enabled when the clock signal (CK) is at a logic low level, the final signal (Q) can be maintained at a constant value when the clock signal (CK) is at a logic low level.

[0068] FIG. 10a is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. Referring to FIG. 10a, the flip-flop (10b) may include a master latch (200b) and a slave latch (300b).

[0069] The slave latch (300b) may include a NAND gate (310b). The NAND gate (310b) may include ninth and tenth P-type transistors (P9, P10) and eighth and ninth N-type transistors (N8, N9).

[0070] An internal output signal (Qm) can be input to the gate terminal of the ninth P-type transistor (P9), the source terminal can be connected to the supply power (VDD) node, and the drain terminal can be connected to the fifth node (M5). A clock signal (CK) can be input to the gate terminal of the tenth P-type transistor (P10), the source terminal can be connected to the supply power (VDD) node, and the drain terminal can be connected to the fifth node (M5).

[0071] A clock signal (CK) can be input to the gate terminal of the eighth N-type transistor (N8), the source terminal can be connected to the sixth node (M6), and the drain terminal can be connected to the fifth node (M5). An internal output signal (Qm) can be input to the gate terminal of the ninth N-type transistor (N9), the source terminal can be connected to the ground node, and the drain terminal can be connected to the sixth node (M6).

[0072] Unlike the NAND gate (310a) of Fig. 3, the logic level of the sixth node (M6), which is an internal node of the NAND gate (310b), can be fed back to the master latch (200b).

[0073] The master latch (200b) may include a delay circuit (100b). Unlike the delay circuit (100a) of FIG. 3, the delay circuit (100b) may include a NAND gate (130), a circuit section (140), and an inverter (150). The NAND gate (130) receives a scan enable signal (SE) and a scan input signal (SI), and may be enabled according to a clock signal (CK). The output of the NAND gate (130) may be output to a seventh node (M7). The circuit section (140) may include a plurality of transistors (P11, N10, N11). A second internal signal (CKb) may be input to the gate terminal of the eleventh P-type transistor (P11), the source terminal may be connected to a supply power (VDD) node, and the drain terminal may be connected to the seventh node (M7). A clock signal (CK) can be input to the gate terminal of the 10th N-type transistor (N10). The gate terminal of the 11th N-type transistor (N11) can be connected to the 6th node (M6), which is an internal node of the slave latch (300b). Referring to FIGS. 13b and 14b, when the clock signal (CK) is at a logic high level, the logic level of the 6th node (M6) may be the same logic level as the data signal (D). Additionally, when the clock signal (CK) is at a logic high level, the second internal signal (CKb) may also be at the same logic level as the data signal (D), so the circuit (140) can operate as an inverter. Accordingly, the circuit (140) can output a value obtained by inverting the data signal (D). As a result, the first internal signal (DCK) may have the same logic level as the data signal (D) by means of the inverter (150).

[0074] FIG. 10b is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure.Referring to FIG. 10b, unlike the flip-flop (10b) of FIG. 10a, the flip-flop (10b-2) may further include a 12th P-type transistor (P12). An internal output signal ((Qm) may be input to the gate terminal of the 12th P-type transistor (P12), the source terminal may be connected to a supply power node, and the drain terminal may be connected to a 10th node (M10).

[0075] Referring to FIGS. 13b and 14b, when the clock signal (CK) is at a logic high level, the internal output signal (Qm) has a logic level that is the inverted version of the data signal (D), and the second internal signal (CKb) may have the same logic level as the data signal (D).

[0076] Referring to FIG. 10b, when the clock signal (CK) is at a logic high level, the eighth N-type transistor (N8) is turned on, and the second internal signal (CKb) of the fifth node (M5) can be input to the gate terminal of the eleventh N-type transistor (N11) through the sixth node (M6). However, when the data signal (D) is at a logic high level, the logic level of the sixth node (M6) may be lower than the level of the data signal (D) due to the threshold voltage of the eighth N-type transistor (N8). If the level of the sixth node (M6) is lowered, the eleventh N-type transistor (N11) may not be turned on, and the circuit (140) may not operate as an inverter.

[0077] The 12th P-type transistor (P12) is turned on when the data signal (D) is at a logic high level, so the logic level of the 6th node (M6) can be raised. Accordingly, the 11th N-type transistor (N11) can be turned on normally, and the circuit (140) can operate as an inverter. That is, by the 12th P-type transistor (P2) providing a stable logic high signal to the circuit (140), the circuit (140) can operate as a normal inverter.

[0078] FIG. 10c is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure.Referring to FIG. 10c, the flip-flop (10b-3) may include a slave latch (300b-2), and the slave latch (300b-2) may include a NAND gate (310b-2) that is reset by a reset signal (RST). The NAND gate (310b-2) may include reset transistors (P13, N12).

[0079] A reset signal (RST) may be input to the gate terminal of the 13th P-type transistor (P13), the source terminal may be connected to the supply power (VDD) node, and the drain terminal may be connected to the 8th node (M8). The source terminal of the 9th P-type transistor (P9) may be connected to the 8th node (M8), and the drain terminal may be connected to the 5th node (M5). The source terminal of the 10th P-type transistor (P10) may be connected to the 8th node (M8), and the drain terminal may be connected to the 5th node (M5). When the reset signal (RST) is at a logic high level, the 13th P-type transistor (P13) is turned on, so the 9th node (M9) may not be pulled up regardless of the signal applied to the gate terminals of the 9th and 10th P-type transistors (P9, P10). When the reset signal (RST) is at a logic low level, the pull-up portion of the NAND gate (310b-2) can operate substantially the same as the pull-up portion of the NAND gate (310b) of FIG. 10a and 10b.

[0080] A reset signal (RST) can be input to the gate terminal of the 12th N-type transistor (N12). When the reset signal (RST) is at a logic low level, the 5th node (M5) is discharged by the turned-on 12th N-type transistor (N12), so the 2nd internal signal (CKb) can become a logic low level. When the 2nd internal signal (CKb) is at a logic low level, the final signal (Q) becomes a logic high level by the OAI32 logic circuit (320), so the flip-flop (10b-3) can be reset. When the reset signal (RST) is at a logic low level, the pull-down portion of the NAND gate (310b-2) can operate substantially the same as the pull-down portion of the NAND gate (310b) of FIG. 10a and 10b.

[0081] FIG. 10d is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. Referring to FIG. 10d, the flip-flop (10b-4) may include a slave latch (300b-3), and the slave latch (300b-3) may include a glitch protection circuit (370) and an inverter (380).

[0082] The glitch protection circuit (370) may include a 14th P-type transistor (P14), a 12th N-type transistor (N12), and a 13th N-type transistor (N13).

[0083] As described below through FIGS. 13b and FIGS. 14b, when the clock signal (CK) is at a logic high level, the second internal signal (CKb) may be the same as the logic level of the data signal (D). That is, when the clock signal (CK) is at a logic high level, the data signal (D) may be input to the gate terminal of the 14th P-type transistor (P14). Also, when the clock signal (CK) is at a logic high level, the 8th N-type transistor (N8) is turned on, so the data signal (D) may be input to the gate terminal of the 12th N-type transistor (N12). When the clock signal (CK) is at a logic high level, the 13th N-type transistor (N13) is turned on, so the glitch protection circuit (370) may operate as an inverter in which the data signal (D) is received by the 12th N-type transistor (N12) and the 14th P-type transistor (P14).

[0084] However, when the data signal (D) is at a logic high level, the logic level of the 6th node (M6) may be lower than the level of the data signal (D) due to the threshold voltage of the 8th N-type transistor (N8). When the level of the 6th node (M6) is lowered, the 12th N-type transistor (N12) may not be turned on, and the glitch protection circuit (370) may not operate as an inverter. If the glitch protection circuit (370) does not operate as an inverter, the output signal (QN) may differ from the inverted value of the data signal (D), so a glitch may occur in the final signal (Q).

[0085] As described above with reference to FIG. 10b, the 12th P-type transistor (P12) is turned on when the data signal (D) is at a logic high level, so the logic level of the 6th node (M6) can be raised. Accordingly, the 12th N-type transistor (N12) can be turned on normally, and the glitch protection circuit (370) can operate as an inverter. That is, by the 12th P-type transistor (P2) providing a stable logic high signal to the glitch protection circuit (370), glitches that may occur in the final signal (Q) can be prevented.

[0086] Meanwhile, when the clock signal (CK) is at a logic low level, the second internal signal (CKb) is at a logic high level, so the 13th N-type transistor (N13) and the 14th P-type transistor (P14) can be turned off. Also, since the inverter (380) is enabled when the clock signal (CK) is at a logic low level, the final signal (Q) can be maintained at a constant value when the clock signal (CK) is at a logic low level.

[0087] FIG. 10e is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. Referring to FIG. 10e, the flip-flop (10b-5) may include a slave latch (300b-4), and the slave latch (300b-4) may include a NAND gate (310b-2) that is reset by the reset signal (RST) described above with reference to FIG. 10c. The NAND gate (310b-2) may include reset transistors (P13, N12).

[0088] FIG. 10e includes the glitch protection circuit (370) and the 12th P-type transistor (P12) described in FIG. 10d, so that glitches occurring in the final signal (Q) can be prevented, and FIG. 10c includes the NAND gate (310b-2) described in FIG. 10c, so that the final signal (Q) can be reset according to the reset signal (RST).

[0089] FIG. 11 is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure.Referring to FIG. 11, the flip-flop (10d) may include a clock inverter (600). The clock inverter (600) may receive a clock signal (CK) and output an inverted clock signal (nCK). The flip-flop (10d) may include a master latch (200d) and a slave latch (300d), and the master latch (200d) may include a delay circuit (100d).

[0090] Unlike the delay circuit (100a) of FIG. 3, the delay circuit (100d) may include a first OAI21 logic circuit (110d) and a second OAI21 logic circuit (120d). The first OAI21 logic circuit (110d) may include an OR gate (111d) and a NAND gate (112d). The OR gate (111d) may receive a scan input signal (SI) and an inverted scan enable signal (nSE). The NAND gate (112d) may receive the output signal of the OR gate (111d) and an inverted clock signal (nCK), and output an intermediate signal (F). The second OAI21 logic circuit (120d) may include an OR gate (121d) and a NAND gate (122d). The OR gate (121d) can receive an internal output signal (Qm) and an inverted clock signal (nCK). The NAND gate (122d) can receive the output signal and intermediate signal (F) of the OR gate (121d) and output a first internal signal (DCK).

[0091] Unlike the master latch (200a) of FIG. 3, the master latch (200d) may include an OAI31 logic circuit (220d). The OAI31 logic circuit (220d) may include an OR gate (221d) and a NAND gate (222d). The OR gate (221d) may receive a second internal signal (CKb), an inverted scan enable signal (nSE), and a data signal (D). The NAND gate (222d) may receive the output signal of the OR gate (221d) and the first internal signal (DCK), and output an internal output signal (Qm).

[0092] Unlike the slave latch (300a) of FIG. 3, the slave latch (300d) may include a NOR gate (310d) that outputs a second internal signal (CKb). The NOR gate (310d) may receive an inverted clock signal (nCK) and an internal output signal (Qm) and output the second internal signal (CKb). Unlike the slave latch (300a) of FIG. 3, the slave latch (300d) may include an AOI21 logic circuit (320d). The AOI logic circuit (320d) may include an AND gate (321d) and a NOR gate (322d). The AND gate (321d) may receive an inverted clock signal (nCK) and an inverted signal (Qi). The NOR gate (322d) receives the output signal of the AND gate (321d) and the second internal signal (CKb) and can output an output signal (QN). The third inverter (340) receives the output signal (QN) and can output a final signal (Q) by inverting the output signal (QN).

[0093] FIG. 12a is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. Specifically, FIG. 12a is a diagram illustrating a flip-flop (10d-2) using an inverted clock signal (nCK). The description in FIG. 12a may be omitted if it is described with reference to FIG. 1 through FIG. 11. Referring to FIG. 12a, the flip-flop (10d-2) may include a master latch (200d-2) and a slave latch (300d-2).

[0094] The master latch (200d-2) may include a delay circuit (100d-2). Unlike the delay circuit (100d) of FIG. 11, the delay circuit (100d-2) may include a NOR gate (130d), a circuit section (140d), and an inverter (150). The NOR gate (130d) receives an inverted scan enable signal (nSE) and a scan input signal (SI), and may be enabled according to an inverted clock signal (nCK). The output of the NOR gate (130d) may be output to a first node (M1d). The circuit section (140d) may include a plurality of transistors (P1d, P2d, N1d). A second internal signal (CKb) may be input to the gate terminal of the first N-type transistor (N1d), the source terminal may be connected to a ground node, and the drain terminal may be connected to the first node (M1d). An inverted clock signal (nCK) can be input to the gate terminal of the first P-type transistor (P1d). The gate terminal of the second P-type transistor (P2d) is connected to the second node (M2d), which is an internal node of the slave latch (300d-2), so that a glitch protection signal (GP) of the second node (M2d) can be applied. As described below with reference to FIG. 12a, when the clock signal (CK) is at a logic low level, the second internal signal (CKb) may be the same as the logic level of the data signal (D). Also, when the clock signal (CK) is at a logic low level, the third P-type transistor (P3d) is turned on so that the glitch signal (GP) of the second node (M2d) may be the same as the logic level of the data signal (D). Thus, the circuit section (140d) can operate as an inverter. That is, the circuit section (140d) can output a value obtained by inverting the data signal (D). Consequently, the first internal signal (DCK) can have the same logic level as the data signal (D) by the delay circuit (100d-2).

[0095] The slave latch (300d-2) may include a NOR gate (310d), a glitch protection circuit (350d), and a fifth N-type transistor (N5d). An internal output signal (Qm) may be input to the gate terminal of the fifth N-type transistor (N5d), the source terminal may be connected to a ground node, and the drain terminal may be connected to a second node (M2d).

[0096] When the clock signal (CK) is at a logic high level, the second internal signal (CKb) may be at a logic low level by the third N-type transistor (N3d). When the second internal signal (CKb) is at a logic low level, in normal operation mode (SE=0), the internal output signal (Qm) may have a logic level that is the inverted version of the data signal (D) by the OAI31 logic circuit (220d). That is, when the clock signal (CK) is at a logic high level, the inverted logic level of the data signal (D) may be latched to the internal output signal (Qm).

[0097] When the clock signal (CK) transitions to a logic low level, the NOR gate (310d) can operate as an inverter with the internal output signal (Qm) as input. Thus, the second internal signal (CKb) can be the same as the logic level of the data signal (D). Additionally, when the clock signal (CK) is at a logic low level, the second node (M2d) can be the same as the logic level of the third node (M3d) by the third P-type transistor (P3d). That is, when the clock signal (CK) is at a logic low level, the second node (M2d) can be the same as the logic level of the data signal (D).

[0098] Meanwhile, when the data signal (D) is at a logic low level, the logic level of the second node (M2d) can be higher than the level of the data signal (D) due to the threshold voltage of the fourth P-type transistor (P4d). When the level of the second node (M2d) is higher, the second P-type transistor (P2d) may not be turned on, and the circuit part (140d) may not operate as an inverter.

[0099] According to an exemplary embodiment of the present disclosure, the fifth N-type transistor (N5d) is turned on when the clock signal (CK) is at a logic high level and the data signal (D) is at a logic low level (i.e., the internal output signal Qm is at a logic high level), so that the logic level of the second node (M2d) can be lowered. Accordingly, the second P-type transistor (P2d) can be turned on normally, and the circuit section (140d) can operate as an inverter. That is, by the fifth N-type transistor (N5d) providing a stable logic low signal to the circuit section (140d), the circuit section (140d) can operate as a normal inverter.

[0100] Meanwhile, the glitch protection circuit (350d) may include a fourth N-type transistor (N4d), a fifth P-type transistor (P5d), and a sixth P-type transistor (P6d).

[0101] When the clock signal (CK) is at a logic high level, the second internal signal (CKb) is the same as the logic level of the data signal (D), so the glitch protection circuit (350d) can operate as an inverter that receives the data signal (D).

[0102] However, when the data signal (D) is at a logic low level, the logic level of the second node (M2d) may be higher than the level of the data signal (D) due to the threshold voltage of the fourth P-type transistor (N4d). When the level of the second node (M2d) is higher, the sixth P-type transistor (P6d) may not be turned on, and the glitch protection circuit (350d) may not operate as an inverter. If the glitch protection circuit (350d) does not operate as an inverter, the output signal (QN) may differ from the inverted value of the data signal (D), so a glitch may occur in the final signal (Q).

[0103] As described above, the fifth N-type transistor (N5d) is turned on when the data signal (D) is at a logic low level, so the logic level of the second node (M2d) can be lowered. Accordingly, the sixth P-type transistor (P6d) can be turned on normally, and the glitch protection circuit (350d) can operate as an inverter. That is, by the fifth N-type transistor (N5d) providing a stable logic low signal to the glitch protection circuit (350d), glitches that may occur in the final signal (Q) can be prevented.

[0104] FIG. 12b is a drawing illustrating a flip-flop according to an exemplary embodiment of the present disclosure. Referring to FIG. 12b, the flip-flop (10d-3) may include a first NOR gate (150d-2) and a second NOR gate (330d-2).

[0105] The first NOR gate (150d-2) receives the output and reset signal (RST) of the circuit section (140d) and can output the first internal signal (DCK). When the reset signal (RST) is at a logic high level, the internal output signal (Qm) can be reset to a logic high level.

[0106] The second NOR gate (330d-2) receives an output signal (QN) and a reset signal (RST) and can output an inverted output signal (QM). When the reset signal (RST) is at a logic high level, the final signal (Q) can be reset to a logic low level.

[0107] FIGS. 13a and FIGS. 13b are circuit diagrams for illustrating the normal operation mode of a flip-flop according to an exemplary embodiment of the present disclosure. Specifically, FIG. 13a is a diagram illustrating the normal operation mode of a flip-flop (10a) when the clock signal (CK) is at a logic low level. FIG. 13b is a diagram illustrating the normal operation mode of a flip-flop (10a) when the clock signal (CK) is at a logic high level.

[0108] Referring to FIGS. 13a and 13b, when the scan enable signal (SE) is at a logic low level, the flip-flop may operate in a normal operation mode. It is assumed that the clock signal (CK) transitions from a logic low level to a logic high level. Specifically, in FIG. 13a, it is assumed that a first data signal (D1) is applied to the master latch (200) when the clock signal (CK) is at a logic low level, and in FIG. 13b, it is assumed that a second data signal (D2) is applied to the master latch (200) when the clock signal (CK) is at a logic high level. Specifically, it is assumed that the second data signal (D2) is applied to the master latch (200) after the setup time has elapsed from the point at which the clock signal (CK) transitions. In this specification, a logic low level may be represented as 0, and a logic high level may be represented as 1.

[0109] Referring to FIG. 13a, when the clock signal (CK) is at a logic low level, the first internal signal (DCK) may be at a logic low level by the delay circuit (100). The first internal signal (DCK) may be a signal that is delayed by a delay time (td) compared to the clock signal (CK).

[0110] Referring to FIG. 13a, when the clock signal (CK) is at a logic low level, the second internal signal (CKb) may be at a logic high level by the NAND gate (310).

[0111] Since the first internal signal (DCK) is at a logic low level and the second internal signal (CKb) is at a logic high level, the AOI31 logic circuit (220) can operate as an inverter that receives the first data signal (D1) and outputs an internal output signal (Qm) by inverting the first data signal (D1). That is, while the first internal signal (DCK) is maintained at a logic low level, the master latch (200) can receive the first data signal (D1) and output the inverted first data signal (D1N) as an internal output signal (Qm).

[0112] Referring to FIG. 13a, when the clock signal (CK) is at a logic low level, the second internal signal (CKb) is at a logic high level, so the OAI21 logic circuit (320) can operate as an inverter receiving an inverted signal (Qi). That is, when the clock signal (CK) is at a logic low level, the slave latch (300) can maintain the existing final signal (Q-).

[0113] In conclusion, when the clock signal (CK) is at a logic low level, the master latch (200) outputs the input first data signal (D1) as an internal output signal (Qm), and the slave latch (300) can maintain the existing final signal (Q-).

[0114] Referring to FIG. 13b, when the clock signal (CK) is at a logic high level, the AOI21 logic circuit (120a) can operate as an inverter receiving an internal output signal (Qm). When the clock signal (CK) transitions, the internal output signal (Qm) is identical to the inverted first data signal (D1N), so the first internal signal (DCK) can be identical to the first data signal (D1). According to an exemplary embodiment of the present disclosure, the time during which the first internal signal (DCK) remains at a logic low level may be delayed compared to the clock signal (CK). Thus, even when the clock signal (CK) transitions to a logic high level, the first internal signal (DCK) may remain at a logic low level during the delay time.

[0115] Referring to FIG. 13b, when the clock signal (CK) is at a logic high level, the NAND gate (310) can operate as an inverter. When the clock signal (CK) transitions, the internal output signal (Qm) is identical to the inverted first data signal (D1N), so the second internal signal (CKb) can be identical to the first data signal (D1) by the NAND gate (310). Even when the clock signal (CK) transitions to a logic high level, the first internal signal (DCK) maintains a logic low level for a delay time, so if the data signal applied to the AND gate (221) changes within a predetermined setup time, the internal output signal (Qm) can be identical to the inverted value of the changed data signal.

[0116] The AOI31 logic circuit (220) can operate as a logic circuit comprising an AND gate (221) that receives a first data signal (D1) and a second data signal (D2), and a NOR gate (222) that receives the output value of the AND gate (221) and the first data signal (D1). That is, Qm, which is the output value of the AOI31 logic circuit (220), can be the first data signal (D1N) inverted by [Equation 1].

[0117]

[0118] That is, when the clock signal (CK) is at a logic high level, the master latch (200) can maintain the first data signal (D1) as an internal output signal (Qm).

[0119] Referring to FIG. 13b, when the clock signal (CK) is at a logic high level, the OAI21 logic circuit (320) can operate as an inverter that receives a second internal signal (CKb). Thus, the output signal (QN) can be an inverted first data signal (D1N). The third inverter (340) receives the output signal (QN) and outputs the inverted output signal (QN) as a final signal (Q), so the final signal (Q) can be a first data signal (D1).

[0120] That is, when the clock signal (CK) is at a logic high level, the slave latch (300) can output the first data signal (D1) input to the master latch (200) as the final signal (Q) when the clock signal (CK) is at a logic low level.

[0121] FIGS. 14a and FIGS. 14b are circuit diagrams for illustrating the normal operation mode of a flip-flop according to an exemplary embodiment of the present disclosure. Specifically, FIG. 14a is a diagram illustrating the normal operation mode of a flip-flop (10b) when the clock signal (CK) is at a logic low level. FIG. 14b is a diagram illustrating the normal operation mode of a flip-flop (10b) when the clock signal (CK) is at a logic high level. FIG. 14a and FIG. 14b illustrate the flip-flop (10b) of FIG. 10a, but the description of FIG. 14a and FIG. 14b may also be applied to the flip-flops (10b-2 to 10b-5) of FIG. 10b to 10e.

[0122] Referring to FIGS. 14a and 14b, when the scan enable signal (SE) is at a logic low level, the flip-flop can operate in a normal operation mode. It is assumed that the clock signal (CK) transitions from a logic low level to a logic high level. In FIG. 14a, it is assumed that a first data signal (D1) is applied to the master latch (200) when the clock signal (CK) is 0, and in FIG. 14b, it is assumed that a second data signal (D2) is applied to the master latch (200) when the clock signal (CK) is 1.

[0123] Similar to the flip-flop (10a) of FIG. 13a and 13b, when the clock signal (CK) is at a logic low level, the first internal signal (DCK) is at a logic low level, the internal output signal (Qm) is at the same logic level as the inverted first data signal (D1N), the second internal signal (CKb) is at a logic high level, and the final signal (Q) can maintain the previous final signal (Q-).

[0124] Similar to the flip-flop (10a) of FIG. 13a and 13b, when the clock signal (CK) is at a logic high level, the first internal signal (DCK) is at the same logic level as the first data signal (D1), the internal output signal (Qm) is at the same logic level as the inverted first data signal (D1N), the second internal signal (CKb) is at the same logic level as the first data signal (D1), and the final signal (Q) may be at the same logic level as the first data signal (D1).

[0125] FIG. 15 is a timing diagram for a flip-flop according to an exemplary embodiment of the present disclosure.The timing diagram of FIG. 15 may be a timing diagram describing the operation of at least one of the flip-flops described through FIGS. 1 to 14. The clock signal (CK) may transition from a logic low level to a logic high level at a first time (t1). The first internal signal (DCK) may maintain a logic low level from the first time (t1) until a third time (t3) which is delayed by a delay time (td). The delay time (td) may be, for example, a delay that occurs as the clock signal (CK) passes through the delay circuit (100) of FIG. 1. Although the clock signal (CK) has been described as an example, parts of the timing diagram of FIG. 15 may also be applied to a buffered clock signal (bCK) or an inverted clock signal (CK) by modifying them. Accordingly, the operation of at least one of the flip-flops (10a-2, 10a-3, 10d, 10d-2, 10d-3) illustrated in FIG. 9a, 9b, 11, 12a, and 12b can be explained through FIG. 15.

[0126] The data signal (D) may transition to a logic high level after a setup time (ts) has elapsed from a first time (t1). The setup time (ts) may be shorter than the delay time (td). According to an exemplary embodiment of the present disclosure, the data signal (D) may be reflected in the internal output signal (Qm) when the first internal signal (DCK) is maintained at a logic low level. Thus, even after the clock signal (CK) has transitioned to a logic high level, if the data signal is changed within a predetermined setup time (ts), the changed data signal may be reflected in the final signal (Q).

[0127] For example, referring to FIG. 15, if the data signal (D) changes from a logic low level to a logic high level within a setup time (ts) from a first time (t1) when the clock signal (CK) transitions to a logic high level, the changed data signal (D) can be reflected in the internal output signal (Qm) and the final signal (Q).

[0128] That is, the flip-flop according to the exemplary embodiment of the present disclosure includes a delay circuit, thereby enabling a data signal (D) latching operation having a negative setup time. Since the maximum frequency of the clock signal (CK) increases as the setup time decreases, the flip-flop according to the exemplary embodiment of the present disclosure can provide an improved clock frequency.

[0129] As described above, exemplary embodiments have been disclosed in the drawings and specification. Although specific terms have been used to describe the embodiments in this specification, they are used only for the purpose of explaining the technical concept of this disclosure and are not intended to limit the meaning or the scope of this disclosure as defined in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of this disclosure should be determined by the technical concept of the appended claims.

Claims

Claim 1 A flip-flop comprising: a master latch that includes a delay circuit for receiving a clock signal and generating a first internal signal, and generates an internal output signal by latching a data signal based on the first internal signal of a first logic level; and a slave latch that generates a final signal by latching the internal output signal, wherein the delay circuit generates the first internal signal by delaying the clock signal by a delay time when the clock signal is at the first logic level, and generates the first internal signal based on the internal output signal when the clock signal is at the second logic level. Claim 2 A flip-flop according to claim 1, wherein the slave latch comprises a logic circuit that generates a second internal signal based on the clock signal, and the logic circuit generates the second internal signal having the second logic level when the clock signal is the first logic level, and generates the second internal signal having the logic level of the internal output signal inverted when the clock signal is the second logic level. Claim 3 A flip-flop according to claim 2, wherein the master latch generates an internal output signal having a logic level in which the logic level of the data signal is inverted during a time interval in which the clock signal is at the first logic level and during a time interval in which the clock signal is transitioned to the second logic level and the setup time is elapsed, and during a time interval after the setup time has elapsed, the logic level of the internal output signal is maintained at a logic level determined based on the logic level of the data signal received before the setup time has elapsed, and the setup time is shorter than the delay time. Claim 4 A flip-flop according to claim 3, wherein the slave latch maintains the logic level of the final signal at the logic level of the final signal before the clock signal transitions to the first logic level when the clock signal is at the first logic level, and outputs the final signal having a logic level inverted from the logic level of the internal output signal when the clock signal is at the second logic level. Claim 5 A flip-flop according to claim 4, wherein the delay circuit comprises: a first logic circuit that receives a scan input signal, a scan enable signal, and the clock signal; and a second logic circuit that receives the internal output signal, the clock signal, and the output signal of the first logic circuit and outputs the first internal signal. Claim 6 In paragraph 4, the flip-flop is characterized in that the logic circuit receives the internal output signal and the clock signal, and generates the second internal signal. Claim 7 delete Claim 8 delete Claim 9 A flip-flop comprising: a first latch that receives a data signal and a clock signal and outputs an internal output signal; and a second latch that outputs a final signal by latching the internal output signal according to the clock signal, wherein the first latch includes a delay circuit that generates a first internal signal by delaying the clock signal by a delay time when the clock signal is at a first logic level, and generates the first internal signal based on the internal output signal when the clock signal is at a second logic level, and generates the internal output signal by latching the data signal according to the first internal signal of the first logic level. Claim 10 A flip-flop according to claim 9, wherein the delay circuit comprises: a first logic circuit that receives a scan enable signal, a scan input signal, and the clock signal, generates a first signal by ANDing the scan enable signal and the scan input signal, and outputs a second signal by NORing the first signal and the clock signal; and a second logic circuit that receives the internal output signal, the clock signal, and the second signal, generates a third signal by ANDing the internal output signal and the clock signal, and outputs the first internal signal by NORing the third signal and the second signal. Claim 11 A flip-flop according to claim 9, wherein the second latch comprises: a third logic circuit that receives the internal output signal and the clock signal and outputs a second internal signal; a fourth logic circuit that receives the inverted signal, the clock signal and the second internal signal and outputs an inverted final signal; a first inverter that receives the inverted final signal and outputs the inverted signal generated by inverting the inverted final signal; and a second inverter that receives the inverted final signal and outputs the final signal generated by inverting the inverted final signal. Claim 12 A flip-flop according to claim 11, wherein the first latch further comprises a fifth logic circuit that receives the second internal signal, the data signal, the inverted scan enable signal, and the first internal signal, and outputs the internal output signal. Claim 13 A flip-flop according to claim 12, wherein the fifth logic circuit comprises: a fifth P-type transistor having a gate terminal that receives the first internal signal, a first terminal connected to a supply power node, and a second terminal connected to a second node; a sixth P-type transistor having a gate terminal that receives the inverted scan enable signal, a first terminal connected to the second node, and a second terminal connected to a third node that outputs the internal output signal; a seventh P-type transistor having a gate terminal that receives the data signal, a first terminal connected to the second node, and a second terminal connected to the third node; and an eighth P-type transistor having a gate terminal that receives the second internal signal, a first terminal connected to a supply power node, and a second terminal connected to the third node. Claim 14 In claim 12, the flip-flop is characterized in that the fifth logic circuit comprises: a fourth N-type transistor that receives the first internal signal at its gate terminal, with its first terminal connected to a fourth node and its second terminal connected to a ground node; a fifth N-type transistor that receives the data signal at its gate terminal; a seventh N-type transistor that receives the inverted scan enable signal at its gate terminal; and a sixth N-type transistor that receives the second internal signal at its gate terminal, with its first terminal connected to a third node that outputs the internal output signal and its second terminal connected to the fourth node, wherein the fifth N-type transistor and the seventh N-type transistor are connected in series to form a second series structure, and the first terminal of the second series structure is connected to the fourth node and the second terminal is connected to a ground node. Claim 15 A flip-flop according to claim 11, wherein the third logic circuit comprises: a sixth logic circuit that receives the clock signal and the internal output signal and outputs an AND operation value for the clock signal and the internal output signal; and a seventh logic circuit that receives the reset signal and the AND operation value and outputs the second internal signal. Claim 16 A flip-flop according to claim 9, wherein the second latch comprises an eighth logic circuit that receives the internal output signal and the clock signal and outputs a second internal signal. Claim 17 In claim 16, the flip-flop is characterized in that the eighth logic circuit comprises: a ninth P-type transistor that receives the internal output signal at its gate terminal, with its first terminal connected to a supply power node and its second terminal connected to a fifth node; a tenth P-type transistor that receives the clock signal at its gate terminal, with its first terminal connected to a supply power node and its second terminal connected to the fifth node; an eighth N-type transistor that receives the clock signal at its gate terminal, with its first terminal connected to the fifth node and its second terminal connected to a sixth node; and a ninth N-type transistor that receives the internal output signal at its gate terminal, with its first terminal connected to the sixth node and its second terminal connected to a ground node. Claim 18 A flip-flop according to claim 17, wherein the delay circuit further comprises a circuit portion that is connected to the sixth node and operates as an inverter that receives the data signal as an input when the clock signal is at a logic high level. Claim 19 In claim 18, the delay circuit further includes a ninth logic circuit that receives a scan enable signal and a scan input signal, is enabled according to the clock signal, and has an output terminal connected to a seventh node; the circuit part includes: a first P-type transistor in which the second internal signal is input to the gate terminal, is connected to a supply power node at the first terminal, and is connected to the seventh node at the second terminal; a tenth N-type transistor in which the clock signal is input to the gate terminal; a tenth N-type transistor in which the gate terminal is connected to the sixth node; and a tenth logic circuit in which the input terminal is connected to the seventh node and generates the first internal signal by inverting the signal of the seventh node, wherein the tenth N-type transistor and the tenth N-type transistor are connected in series to form a third series structure, and the first terminal of the third series structure is connected to a ground node and the second terminal is connected to the seventh node. Claim 20 A flip-flop according to claim 19, further comprising a 12th P-type transistor in which the internal output signal is input to the gate terminal, the first terminal is connected to a supply power node, and the second terminal is connected to the 6th node.

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