Integrated circuit device

Abstract

An integrated circuit device according to the present invention comprises: a substrate, a peripheral circuit wiring structure disposed on the substrate and including bypass vias, and an interlayer insulating film covering at least a portion of the peripheral circuit wiring structure; a cell array structure overlapping perpendicularly with the peripheral circuit structure on the peripheral circuit structure and comprising a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channel structures penetrating the plurality of gate lines; and a barrier layer interposed between the peripheral circuit structure and the cell array structure and having a bypass hole that fills the bypass vias and penetrates from the upper surface to the lower surface; wherein at least a portion of the barrier layer and at least a portion of the base substrate form a structure in which a conductive material layer, an insulating material layer, a semiconductor material layer, an insulating material layer having an ONO structure, and a semiconductor material layer are sequentially stacked.

Description

Technology Field

[0001] The technical concept of the present invention relates to an integrated circuit device, and more specifically, to an integrated circuit device comprising a non-volatile memory device having a COP (Cell Over Periphery) structure. Background Technology

[0002] With the increasing multifunctionality of information and communication devices, integrated circuit devices including memory elements are becoming larger in capacity and more highly integrated. Furthermore, the size of memory cells is gradually shrinking, and the operating circuits and wiring structures included in memory devices are becoming more complex to facilitate operation and electrical connections. Consequently, there is a demand for integrated circuit devices that include memory elements with structures possessing excellent electrical characteristics while maintaining enhanced integration density. The problem to be solved

[0003] The technical problem that the technical concept of the present invention aims to solve is to provide an integrated circuit element having structural reliability. means of solving the problem

[0004] To achieve the above technical objectives, the present invention provides an integrated circuit device as follows. An integrated circuit device according to the present invention comprises: a peripheral circuit structure comprising a substrate, a peripheral circuit wiring structure disposed on the substrate and including bypass vias, and an interlayer insulating film covering at least a portion of the peripheral circuit wiring structure; a cell array structure overlapping perpendicularly with the peripheral circuit structure on the peripheral circuit structure and comprising a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channel structures penetrating the plurality of gate lines; and a barrier layer interposed between the peripheral circuit structure and the cell array structure and having a bypass hole that fills the bypass vias and penetrates from the upper surface to the lower surface; wherein at least a portion of the barrier layer and at least a portion of the base substrate form a structure in which a conductive material layer, an insulating material layer, a semiconductor material layer, an insulating material layer having an ONO structure, and a semiconductor material layer are sequentially stacked.

[0005] An integrated circuit device according to the present invention comprises: a substrate; a peripheral circuit structure disposed on the substrate and comprising a peripheral circuit contact, a peripheral circuit wiring layer, and a bypass via, and an interlayer insulating film covering the peripheral circuit contact and the peripheral circuit wiring layer; a cell array structure overlapping vertically with the peripheral circuit structure on the peripheral circuit structure and comprising a substrate layer, a plurality of gate lines disposed on the substrate layer, and a plurality of channel structures through which the plurality of gate lines penetrate; a barrier layer interposed between the peripheral circuit structure and the cell array structure and having a stacked structure of a first barrier layer covering the interlayer insulating film and a second barrier layer covering the first barrier layer, wherein the peripheral circuit wiring layer is exposed on the bottom surface and a bypass hole filled with the bypass via is provided; and a cover layer interposed between the first barrier layer and the bypass via.

[0006] An integrated circuit device according to the present invention comprises: a peripheral circuit transistor disposed on a substrate; a peripheral circuit wiring structure electrically connected to the peripheral circuit transistor and comprising a peripheral circuit contact, a peripheral circuit wiring layer, and a bypass via; and an interlayer insulating film surrounding the peripheral circuit contact and the peripheral circuit wiring layer; a cell array structure comprising a substrate layer, a lower base layer, and an upper base layer sequentially stacked and overlapping in a vertical direction with respect to the peripheral circuit structure, a plurality of gate lines disposed on the upper base layer, and a plurality of channel structures filling a plurality of channel holes penetrating the plurality of gate lines; a barrier layer interposed between the peripheral circuit structure and the cell array structure and having a stacked structure of a first barrier layer covering the interlayer insulating film and a second barrier layer covering the first barrier layer, wherein the peripheral circuit wiring layer is exposed on the bottom surface and the barrier layer has a bypass hole filled with the bypass via, which is integrally formed with the same material as the substrate layer; and a cover layer interposed between the bypass via and the first barrier layer. It includes: a plurality of base insulating layers filling a plurality of openings penetrating the base substrate and the barrier layer; a plurality of conductive lines disposed on the cell array structure; and a plurality of through electrodes penetrating the cell array structure and the plurality of base insulating layers, connecting the plurality of conductive lines to the peripheral circuit wiring structure, and spaced apart from the barrier layer with the plurality of base insulating layers in between. Effects of the invention

[0007] The integrated circuit device according to the present invention can have structural reliability because the barrier layer acts as a structural support layer during the manufacturing process. Brief explanation of the drawing

[0008] FIG. 1 is a block diagram of an integrated circuit element according to exemplary embodiments of the present invention. FIG. 2 is a schematic perspective view of an integrated circuit element according to exemplary embodiments of the present invention. FIG. 3 is an equivalent circuit diagram of a memory cell array of an integrated circuit element according to exemplary embodiments of the present invention. FIGS. 4a to 4c are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. FIGS. 5a to 6c are plan views showing through-electrode regions of an integrated circuit element according to exemplary embodiments of the present invention. FIGS. 7a and 7b are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. FIGS. 8a and FIGS. 8b are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. FIGS. 9a and 9b are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. FIGS. 10a to 10f are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to exemplary embodiments of the present invention. FIGS. 11a and FIGS. 11b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to exemplary embodiments of the present invention. FIGS. 12a and FIGS. 12b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to exemplary embodiments of the present invention. FIGS. 13 and FIGS. 14 are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. FIG. 15 is a schematic diagram showing an electronic system including an integrated circuit element according to exemplary embodiments of the present invention. FIG. 16 is a schematic perspective view of an electronic system including an integrated circuit element according to exemplary embodiments of the present invention. FIG. 17 is a cross-sectional view schematically showing a semiconductor package according to exemplary embodiments of the present invention. Specific details for implementing the invention

[0009] FIG. 1 is a block diagram of an integrated circuit element according to exemplary embodiments of the present invention.

[0010] Referring to FIG. 1, an integrated circuit device (10) may include a memory cell array (20) and a peripheral circuit (30). The memory cell array (20) includes a plurality of memory cell blocks (BLK1, BLK2, ..., BLKn). Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) may include a plurality of memory cells. The memory cell blocks (BLK1, BLK2, ..., BLKn) may be connected to the peripheral circuit (30) through a bit line (BL), a word line (WL), a string select line (SSL), and a ground select line (GSL).

[0011] The peripheral circuit (30) may include a row decoder (32), a page buffer (34), a data input / output circuit (36), and control logic (38). Although not shown in FIG. 1, the peripheral circuit (30) may further include an input / output interface, column logic, a voltage generator, a pre-decoder, a temperature sensor, a command decoder, an address decoder, an amplifier circuit, etc.

[0012] A memory cell array (20) can be connected to a page buffer (34) via a bit line (BL) and to a row decoder (32) via a word line (WL), a string select line (SSL), and a ground select line (GSL). In the memory cell array (20), a plurality of memory cells included in a plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) may each be a flash memory cell. The memory cell array (20) may include a three-dimensional memory cell array. The three-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include a plurality of memory cells connected to a plurality of word lines (WL) stacked vertically on a substrate.

[0013] The peripheral circuit (30) can receive an address (ADDR), a command (CMD), and a control signal (CTRL) from outside the integrated circuit device (10), and can transmit and receive data (DATA) with a device outside the integrated circuit device (10).

[0014] The row decoder (32) can select at least one of a plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) in response to an external address (ADDR), and can select the word line (WL), string select line (SSL), and ground select line (GSL) of the selected memory cell block. The row decoder (32) can transmit a voltage for performing memory operations to the word line (WL) of the selected memory cell block.

[0015] The page buffer (34) can be connected to the memory cell array (20) via a bit line (BL). During a program operation, the page buffer (34) can operate as a write driver to apply a voltage to the bit line (BL) according to the data (DATA) to be stored in the memory cell array (20), and during a read operation, it can operate as a detection amplifier to detect the data (DATA) stored in the memory cell array (20). The page buffer (34) can operate according to a control signal (PCTL) provided by the control logic (38).

[0016] The data input / output circuit (36) can be connected to the page buffer (34) via data lines (DLs). The data input / output circuit (36) can receive data (DATA) from a memory controller (not shown) during a program operation and provide program data (DATA) to the page buffer (34) based on a column address (C_ADDR) provided by the control logic (38). During a read operation, the data input / output circuit (36) can provide read data (DATA) stored in the page buffer (34) to the memory controller based on a column address (C_ADDR) provided by the control logic (38).

[0017] The data input / output circuit (36) can transmit the input address or command to the control logic (38) or row decoder (32). The peripheral circuit (30) may further include an Electro Static Discharge (ESD) circuit and a pull-up / pull-down driver.

[0018] The control logic (38) can receive a command (CMD) and a control signal (CTRL) from the memory controller. The control logic (38) can provide a row address (R_ADDR) to the row decoder (32) and provide a column address (C_ADDR) to the data input / output circuit (36). The control logic (38) can generate various internal control signals used within the integrated circuit device (10) in response to the control signal (CTRL). For example, the control logic (38) can adjust the voltage levels provided to the word line (WL) and bit line (BL) when performing memory operations such as program operation or erase operation.

[0019] FIG. 2 is a schematic perspective view of an integrated circuit element according to exemplary embodiments of the present invention.

[0020] Referring to FIG. 2, the integrated circuit device (10) includes a cell array structure (CS) and a peripheral circuit structure (PS) that overlap each other in a vertical direction (Z direction). The cell array structure (CS) may include a memory cell array (20) described with reference to FIG. 1. The peripheral circuit structure (PS) may include a peripheral circuit (30) described with reference to FIG. 1.

[0021] The cell array structure (CS) may include a plurality of memory cell blocks (BLK1, BLK2, ..., BLKn). Each of the plurality of memory cell blocks (BLK1, BLK2, ..., BLKn) may include memory cells arranged in three dimensions.

[0022] FIG. 3 is an equivalent circuit diagram of a memory cell array of an integrated circuit element according to exemplary embodiments of the present invention.

[0023] Referring to FIG. 3, a memory cell array (MCA) may include a plurality of memory cell strings (MS). The memory cell array (MCA) may include a plurality of bit lines (BL: BL1, BL2, …, BLm), a plurality of word lines (WL: WL1, WL2, …, WLn-1, WLn), at least one string select line (SSL), at least one ground select line (GSL), and a common source line (CSL). A plurality of memory cell strings (MS) may be formed between the plurality of bit lines (BL: BL1, BL2, …, BLm) and the common source line (CSL). FIG. 3 illustrates a case where each of the plurality of memory cell strings (MS) includes two string select lines (SSL), but the technical concept of the present invention is not limited thereto. For example, each of the plurality of memory cell strings (MS) may include one string select line (SSL).

[0024] Each of the multiple memory cell strings (MS) may include a string select transistor (SST), a ground select transistor (GST), and multiple memory cell transistors (MC1, MC2, …, MCn-1, MCn). The drain region of the string select transistor (SST) is connected to a bit line (BL: BL1, BL2, …, BLm), and the source region of the ground select transistor (GST) may be connected to a common source line (CSL). The common source line (CSL) may be a region in which the source regions of the multiple ground select transistors (GST) are connected in common.

[0025] A string select transistor (SST) can be connected to a string select line (SSL), and a ground select transistor (GST) can be connected to a ground select line (GSL). A plurality of memory cell transistors (MC1, MC2, …, MCn-1, MCn) can each be connected to a plurality of word lines (WL: WL1, WL2, …, WLn-1, WLn).

[0026] FIGS. 4a to 4c are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. Specifically, FIG. 4b is a cross-sectional view showing an enlarged portion of CXA in FIG. 4a, and FIG. 4c is a cross-sectional view showing an enlarged portion of CXB in FIG. 4a. In FIG. 4a, only some components of the integrated circuit element (100) are schematically shown for convenience of illustration and understanding.

[0027] Referring together to FIGS. 4a through 4c, the integrated circuit element (100) may include a peripheral circuit structure (PS) and a cell array structure (CS) positioned at a vertical level higher than the peripheral circuit structure (PS). The cell array structure (CS) includes a memory cell region (MCR), a connection region (CON), and a through-electrode region (TVR), and the peripheral circuit structure (PS) may include a peripheral circuit region (PERI).

[0028] The memory cell region (MCR) may be a region where a vertical channel structure NAND type memory cell array (MCA) (see FIG. 3) is formed, which operates in the manner described with reference to FIG. 3. The connection region (CON) may be a region where pad contacts (CNT) are placed for electrical connection between the memory cell array (MCA) formed in the memory cell region (MCR) and the peripheral circuit region (PERI). The through-electrode region (TVR) may be a region where a plurality of through-electrodes (TVS) are placed for electrical connection between the memory cell region (MCR) and the peripheral circuit region (PERI) located at a lower vertical level.

[0029] A peripheral circuit structure (PS) may include a peripheral circuit transistor (60TR) and a peripheral circuit wiring structure (70) disposed on a substrate (50). An active region (AC) may be defined on the substrate (50) by a device isolation film (52), and a plurality of peripheral circuit transistors (60TR) may be formed on the active region (AC). The plurality of peripheral circuit transistors (60TR) may include a peripheral circuit gate (60G) and a source / drain region (62) disposed on a portion of the substrate (50) on both sides of the peripheral circuit gate (60G).

[0030] The substrate (50) may comprise a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, the group IV semiconductor may comprise silicon (Si), germanium (Ge), or silicon-germanium. In some embodiments, the substrate (50) may be provided as a bulk wafer or an epitaxial layer. In other embodiments, the substrate (50) may comprise a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate.

[0031] The peripheral circuit wiring structure (70) includes a plurality of peripheral circuit contacts (72) and a plurality of peripheral circuit wiring layers (74). An interlayer insulating film (80) covering the peripheral circuit transistor (60TR) and the peripheral circuit wiring structure (70) may be disposed on the substrate (50). The interlayer insulating film (80) may cover the plurality of peripheral circuit contacts (72) and the plurality of peripheral circuit wiring layers (74). The plurality of peripheral circuit wiring layers (74) may have a multilayer structure including a plurality of metal layers disposed at different vertical levels. Although FIG. 4a exemplarily illustrates that the plurality of peripheral circuit wiring layers (74) all have the same height, the peripheral circuit wiring layer (74) disposed at some levels (e.g., at the top level) may have a greater thickness than the peripheral circuit wiring layer (74) disposed at the remaining levels.

[0032] At least one antenna diode (D40) may be further disposed on the substrate (50). The antenna diode (D40) may include a diode ion implantation region (42). In some embodiments, the active region (AC) of the substrate (50) may be composed of an ion implantation region of a first conductivity type, and the diode ion implantation region (42) may be composed of an ion implantation region of a second conductivity type different from the first conductivity type. The first conductivity type ion implantation region and the second conductivity type ion implantation region may form a PN junction diode. In some embodiments, the diode ion implantation region (42) may have the same conductivity type as the source / drain region (62).

[0033] The interlayer insulating film (80) may include a first interlayer insulating layer (82), a passivation layer (84), and a second interlayer insulating layer (86) that are sequentially stacked. The first interlayer insulating layer (82) may cover a peripheral circuit wiring structure (70). In some embodiments, the upper surface of the first interlayer insulating layer (82) and the upper surface of the peripheral circuit wiring layer (74) placed at the top level may be coplanar. The passivation layer (84) may cover the upper surface of the first interlayer insulating layer (82) and the upper surface of the peripheral circuit wiring layer (74) placed at the top level. The second interlayer insulating layer (86) may cover the passivation layer (84). For example, the first interlayer insulating layer (82) and the second interlayer insulating layer (86) may include oxides, and the passivation layer (84) may include nitrides. In some embodiments, for example, the first interlayer insulating layer (82) and the second interlayer insulating layer (86) may be made of silicon oxide, and the passivation layer (84) may be made of silicon nitride.

[0034] A barrier layer (90) may be interposed between the peripheral circuit structure (PS) and the cell array structure (CS). The barrier layer (90) may be disposed on the interlayer insulating film (80). In some embodiments, the barrier layer (90) may be formed as a stacked structure of a first barrier layer (92) covering the interlayer insulating film (80) and a second barrier layer (94) covering the first barrier layer (92). The first barrier layer (92) may be made of the same material as the substrate layer (110S) described later, or may be made of a material having the same or similar etching characteristics. For example, the first barrier layer (92) may be a conductive material layer, and the second barrier layer (92) may be an insulating material layer. In some embodiments, the first barrier layer (92) may be made of a semiconductor material, and the second barrier layer (94) may be made of an oxide or a nitride. For example, the first barrier layer (92) may be made of polysilicon, and the second barrier layer (94) may be made of silicon oxide or silicon nitride. The thickness of the first barrier layer (92) may have a greater value than the thickness of the second barrier layer (94).

[0035] The bypass hole (BPH) penetrates from the upper surface to the lower surface of the barrier layer (90) and can penetrate a portion of the interlayer insulating film (80). The peripheral circuit wiring layer (74) of the peripheral circuit wiring structure (70) may be exposed at the bottom surface of the bypass hole (BPH).

[0036] A base substrate (110) may be disposed on the barrier layer (90). The base substrate (110) may include a substrate layer (110S), a lower base layer (110L), and an upper base layer (110U) sequentially stacked on the interlayer insulating film (80). Each of the substrate layer (110S), the lower base layer (110L), and the upper base layer (110U) may be a semiconductor material layer. The substrate layer (110S) may include a semiconductor material such as silicon. For example, the substrate layer (110S) may be made of polysilicon. The lower base layer (110L) may be made of impurity-doped polysilicon, undoped polysilicon, a metal, or a combination thereof, and the upper base layer (110U) may be made of impurity-doped polysilicon, undoped polysilicon, a metal, or a combination thereof. The lower base layer (110L) can correspond to the common source line (CSL) described with reference to FIG. 3.

[0037] In at least a portion of each of the through-electrode region (TVR) and the connection region (CON), the base substrate (110) may have an insulating plate (112) interposed between the substrate layer (110S) and the upper base layer (110U) instead of the lower base layer (110L). In some embodiments, the insulating plate (112) may be an insulating material layer having an ONO (Oxide / Nitride / Oxide) structure. For example, the insulating plate (112) may be made of an insulating film having a multilayer structure comprising a first insulating film (112A), a second insulating film (112B), and a third insulating film (112C) stacked sequentially on the upper substrate (110). In exemplary embodiments, the first insulating film (112A) and the third insulating film (112C) may be made of silicon oxide, and the second insulating film (112B) may be made of silicon nitride.

[0038] In the memory cell region (MCR), a base substrate (110) in which a substrate layer (110S), a lower base layer (110L), and an upper base layer (110U) are sequentially stacked may be disposed on the barrier layer (90), and in at least a portion of each of the through electrode region (TVR) and the connection region (CON), a base substrate (110) in which a substrate layer (110S), an insulating plate (112), and an upper base layer (110U) are sequentially stacked may be disposed.

[0039] In the memory cell region (MCR), the barrier layer (90) and the base substrate (110) may have a structure in which a first barrier layer (92) which is a conductive material layer, a second barrier layer (94) which is an insulating material layer, a substrate layer (110S) which is a semiconductor material layer, a lower base layer (110L) which is a semiconductor material layer, and an upper base layer (110U) which is a semiconductor material layer are sequentially stacked. In at least a portion of each of the through electrode region (TVR) and the connection region (CON), the barrier layer (90) and the base substrate (110) may have a structure in which a first barrier layer (92) which is a conductive material layer, a second barrier layer (94) which is an insulating material layer, a substrate layer (110S) which is a semiconductor material layer, an insulating plate (112) which is a semiconductor material layer having an ONO structure, and an upper base layer (110U) which is a semiconductor material layer are sequentially stacked.

[0040] A base damper (110C) may be interposed between the insulating plate (112) and the lower base layer (110L). The base damper (110C) may be formed together with the upper base layer (110U) to form an integral unit. The lower surface of the base damper (110C) may be in contact with the upper surface of the substrate layer (110S). The base damper (110C) may be located between the memory cell region (MCR) and the through electrode region (TVR). In some embodiments, the base damper (110C) may be located in the connection region (CON).

[0041] The base dam portion (110C) can be formed by filling the plate recess (112R) together with the upper base layer (110U) after forming a plate recess (112R) that penetrates the insulating plate (112). The lower base layer (110L) can be formed by filling the space where a portion of the insulating plate (112) was removed after removing a portion of the insulating plate (112) through the gate stack separation opening (WLH) to be described later. The base dam portion (110C) can be interposed between the portion of the insulating plate (112) that is removed to form the lower base layer (110L) and the remaining portion of the insulating plate (112) that is not removed, and can perform the function of a barrier to prevent the remaining portion of the insulating plate (112) from being removed during the process of removing the portion of the insulating plate (112) that is removed to form the lower base layer (110L).

[0042] The upper base layer (110U) can serve as a support layer to prevent the mold stack from collapsing or falling over during the process of removing a portion of the insulating plate (112) to form the lower base layer (110L). Since the barrier layer (90) remains intact and is not removed even when a portion of the substrate layer (110S) is removed during the manufacturing process, it can serve as a structural support layer required for subsequent processes.

[0043] The peripheral circuit wiring structure (70) may further include bypass vias (BPVs) that fill bypass holes (BPHs). The bypass vias (BPVs) can electrically connect the substrate layer (110S) and the diode ion implantation region (42) of the substrate (50). In some embodiments, the bypass vias (BPVs) may be formed together with the substrate layer (110S) using the same material. For example, the bypass vias (BPVs) may be formed by filling the bypass holes (BPHs) with a portion of the semiconductor material when forming the semiconductor material on the barrier layer (90) to form the substrate layer (110S). The bypass vias (BPVs) may be electrically connected to the diode ion implantation region (42) through a portion of the peripheral circuit wiring structure (70). FIG. 4a is illustrated as being electrically connected to a bypass via (BPV) through a plurality of peripheral circuit contacts (72) and a plurality of peripheral circuit wiring layers (74) in which the diode ion implantation region (42) is positioned at different vertical levels, but is not limited thereto. In some embodiments, a contact may be interposed between the bypass via (BPV) and the diode ion implantation region (42), having an upper surface in contact with the bypass via (BPV) and a lower surface in contact with the diode ion implantation region (42).

[0044] In some embodiments, a cover layer (92N) may be interposed between the bypass via (BPV) and the first barrier layer (92). The cover layer (92N) may not be interposed between the bypass via (BPV) and the second barrier layer (94). For example, the cover layer (92N) may be a nitride formed by nitriding a portion of the first barrier layer (92) exposed within the bypass hole (BPH) by a plasma nitriding (PN) process, or an oxide formed by oxidizing a portion of the first barrier layer (92) exposed within the bypass hole (BPH). The cover layer (92N) and the second barrier layer (94) may be made of a material different from that of the substrate layer (110S). In some embodiments, the cover layer (92N) and the second barrier layer (94) may be made of a material resistant to etching of the substrate layer (110S). The cover layer (92N) and the second barrier layer (94) can prevent the first barrier layer (92) from being removed together even when a part of the substrate layer (110S) is removed during the manufacturing process.

[0045] In some embodiments, a cover contact layer (74N) may be interposed between the bypass via (BPV) and the peripheral circuit wiring layer (74). For example, the cover contact layer (74N) may be a conductive metal nitride formed by nitriding a portion of the peripheral circuit wiring layer (74) exposed on the bottom surface of the bypass hole (BPH) by a plasma nitriding process to form a cover layer (92N).

[0046] A plurality of openings (120H) may be formed in a portion of a structure in which a substrate layer (110S), an insulating plate (112), and an upper base layer (110U) are sequentially stacked adjacent to a plurality of through electrodes (TVS). The plurality of openings (120H) penetrate the structure in which the substrate layer (110S), the insulating plate (112), and the upper base layer (110U) are sequentially stacked, so that an interlayer insulating film (80) may be exposed on the bottom surface of the plurality of openings (120H). The base insulating layer (120) may fill the inside of the openings (120H).

[0047] A first gate stack (GS1) may be disposed on the base structure (210), and a second gate stack (GS2) may be disposed on the first gate stack (GS1). The first gate stack (GS1) may extend on the base substrate (110) in a first horizontal direction (X direction) and a second horizontal direction (Y direction) parallel to the upper surface of the base substrate (110). The second gate stack (GS2) may extend on the first gate stack (GS2) in a first horizontal direction (X direction) and a second horizontal direction (Y direction) parallel to the upper surface of the base substrate (110).

[0048] A first gate stack (GS1) may include a plurality of first gate lines (130) and a plurality of first insulating layers (140) arranged alternately, and a second gate stack (GS2) may include a plurality of second gate lines (230) and a plurality of second insulating layers (240) arranged alternately. A plurality of first gate lines (130) and a plurality of first insulating layers (140) may be arranged alternately along a vertical direction (Z direction) perpendicular to the upper surface of a base substrate (110), and a plurality of second gate lines (230) and a plurality of second insulating layers (240) may be arranged alternately along a vertical direction (Z direction) perpendicular to the upper surface of a base substrate (110).

[0049] For example, the first gate line (130) and the second gate line (230) may each comprise a metal such as tungsten, nickel, cobalt, tantalum, etc., a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, tantalum silicide, etc., doped polysilicon, or a combination thereof. In some embodiments, the integrated circuit element (100) may further comprise a dielectric liner that surrounds at least a portion of the top surface, bottom surface, and side surface of the first gate line (130) and the second gate line (230). In exemplary embodiments, the dielectric liner may comprise a high dielectric material such as aluminum oxide.

[0050] In exemplary embodiments, a plurality of first gate lines (130) and a plurality of second gate lines (230) may correspond to a ground select line (GSL), a word line (WL: WL1, WL2, …, WLn-1, WLn) and at least one string select line (SSL) constituting a memory cell string (MS) (see FIG. 3). For example, the lowest first gate line (130) may function as a ground select line (GSL), the uppermost second gate line (230) may function as a string select line (SSL), and the remaining first gate line (130) and the remaining second gate line (230) may function as word lines (WL). Accordingly, a memory cell string (MS) may be provided in which a ground select transistor (GST), a select transistor (SST), and memory cell transistors (MC1, MC2, …, MCn-1, MCn) between them are connected in series. In some embodiments, at least one of the first gate line (130) and the second gate line (230) may function as a dummy word line, but is not limited thereto.

[0051] A plurality of channel structures (160) may extend in a vertical direction (Z direction) through the first gate stack (GS1) and the second gate stack (GS2) from the upper surface of the base substrate (110) in the memory cell region (MCR). A plurality of channel structures (160) may be formed inside a first channel hole (160H1) penetrating the first gate stack (GS1) and a second channel hole (160H2) penetrating the second gate stack (GS2).

[0052] In some embodiments, a plurality of first channel holes (160H1) may have a tapered shape extending from the upper side toward the base substrate (110) and generally having a reduced horizontal width and horizontal area, and a plurality of second channel holes (160H2) may have a tapered shape extending from the upper side toward the base substrate (110) and generally having a reduced horizontal width and horizontal area. Among the plurality of first channel holes (160H1) and the plurality of second channel holes (160H2), corresponding first channel holes (160H1) and second channel holes (160H2) may be connected. Each of the plurality of channel structures (160) may have a shape that protrudes outward from the boundary between the first channel hole (160H1) and the second channel hole (160H2).

[0053] A plurality of channel structures (160) may be arranged spaced apart at predetermined intervals along a first horizontal direction (X direction), a second horizontal direction (Y direction), and a third horizontal direction (e.g., diagonal direction). A plurality of channel structures (160) may be arranged in a zigzag shape or a staggered shape.

[0054] Each of the plurality of channel structures (160) may be disposed within a first channel hole (160H1) and a second channel hole (160H2) that communicate with each other. Each of the plurality of channel structures (160) may include a gate insulating layer (162), a channel layer (164), a buried insulating layer (166), and a conductive plug (168). The gate insulating layer (162) and the channel layer (164) may be sequentially disposed on the side walls within the first channel hole (160H1) and the second channel hole (160H2) that communicate with each other. For example, a gate insulating layer (162) may be conformally disposed on the sidewalls within the first channel hole (160H1) and the second channel hole (160H2) communicating with each other, and a channel layer (164) may be conformally disposed on the sidewalls and bottom portions within the first channel hole (160H1) and the second channel hole (160H2) communicating with each other. A buried insulating layer (166) may be disposed on the channel layer (164) to fill the remaining space of the first channel hole (160H1) and the second channel hole (160H2) communicating with each other. A conductive plug (168) may be disposed on the upper side of the first channel hole (160H1) and the second channel hole (160H2) communicating with each other, for example, at the top of the second channel hole (160H2), which is in contact with the channel layer (164) and the entrance of the first channel hole (160H1) and the second channel hole (160H2) communicating with each other. In other embodiments, the buried insulating layer (166) may be omitted, and the channel layer (164) may be formed in a pillar shape that fills the remaining portion of the first channel hole (160H1) and the second channel hole (160H2) communicating with each other.

[0055] A plurality of channel structures (160) may penetrate the upper base layer (110U) and the lower base layer (110L) to come into contact with the substrate layer (110S). In exemplary embodiments, the channel layer (164) may be positioned to come into contact with the base substrate (110) at the bottom of the first channel hole (160H1) and the second channel hole (160H2) communicating with each other, for example, at the bottom of the first channel hole (160H1). In some embodiments, the bottom surface of the channel layer (164) may be positioned at a vertical level lower than the upper surface of the substrate layer (110S).

[0056] As illustrated in FIG. 4b, the gate insulating layer (162) portion is removed at the same level as the lower base layer (110L), and the channel layer (164) can come into contact with the extension (110LE) of the lower base layer (110L). The side wall portion (162S) and bottom portion (162L) of the gate insulating layer (162) are spaced apart from each other with the extension (110LE) of the lower base layer (110L) in between, and since the bottom portion (162L) of the gate insulating layer (162) surrounds the bottom surface of the channel layer (164), the channel layer (164) can be electrically connected to the lower base layer (110L) by coming into contact with it through the space between the side wall portion (162S) and bottom portion (162L) of the gate insulating layer (162) that are spaced apart from each other, instead of coming into direct contact with the substrate layer (110S).

[0057] As illustrated exemplarily in FIG. 4b, the gate insulating layer (162) may have a structure comprising a tunneling dielectric film (162A), a charge storage film (162B), and a blocking dielectric film (162C) sequentially on the outer wall of the channel layer (164). The relative thicknesses of the tunneling dielectric film (162A), the charge storage film (162B), and the blocking dielectric film (162C) forming the gate insulating layer (162) are not limited to those exemplified in FIG. 4b and may vary in many ways.

[0058] The tunneling dielectric film (162A) may include silicon oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, etc. The charge storage film (162B) is a region in which electrons passing through the tunneling dielectric film (162A) from the channel layer (164) can be stored, and may include silicon nitride, boron nitride, silicon boron nitride, or polysilicon doped with impurities. The blocking dielectric film (162C) may be made of silicon oxide, silicon nitride, or a metal oxide with a dielectric constant greater than that of silicon oxide. The metal oxide may be made of hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or a combination thereof.

[0059] Within a single block, the uppermost second gate line (230) can be separated planarly into two parts by a string separation insulating layer (not shown). The two parts can form a string selection line (SSL) as described with reference to FIG. 3.

[0060] As illustrated exemplarily in FIG. 4a, a gate stack separation opening (WLH) may be extended on the base substrate (110) along a first horizontal direction (X direction) parallel to the upper surface of the base substrate (110). The gate stack separation opening (WLH) may penetrate the first gate stack (GS1), the second gate stack (GS2), and the upper insulating layer (174). In some embodiments, the substrate layer (110S) may be exposed on the bottom surface of the gate stack separation opening (WLH). Although not separately illustrated, the first gate stack (GS1) and the second gate stack (GS2) disposed between a pair of gate stack separation openings (WLH) may form a block, and the pair of gate stack separation openings (WLH) may define the width along the second horizontal direction (Y direction) of the first gate stack (GS1) and the second gate stack (GS2).

[0061] A gate stack isolation insulating layer (150) that fills the inside of a gate stack isolation opening (WLH) may be disposed on a base substrate (110). The gate stack isolation insulating layer (150) may be made of silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric material. For example, the gate stack isolation insulating layer (150) may be made of a silicon oxide film, a silicon nitride film, SiON, SiOCN, SiCN, or a combination thereof.

[0062] An upper support layer (TS) may be disposed on the upper insulating layer (174). The upper support layer (TS) may include an opening (TSH), and the opening (TSH) may be disposed to vertically overlap with the gate stack separation opening (WLH). The upper support layer (TS) can provide structural stability to the first gate stack (GS1) and the second gate stack (GS2) during the manufacturing process of the integrated circuit device (100), thereby preventing process defects such as bending or lining of the first gate stack (GS).

[0063] The upper filling layer (176) may fill the interior of the opening (TSH). In some embodiments, the upper filling layer (176) may be formed of the same material as the gate stack isolation insulating layer (150). The upper support layer (TS) and the upper filling layer (176) may comprise silicon oxide or silicon oxynitride.

[0064] A bit line contact (BLC) can penetrate the upper support layer (TS) and the upper insulating layer (174) to contact a conductive plug (168) of the channel structure (160), and a bit line (BL) in contact with the bit line contact (BLC) can be extended on the upper support layer (TS) in a second horizontal direction (Y direction). Additionally, a plurality of conductive lines (ML) can be formed on the upper support layer (TS) in the through electrode region (TVR) and the connection region (CON). An additional insulating layer (not shown) may be further formed between the upper support layer (TS) and the bit line (BL), and between the upper support layer (TS) and the conductive line (ML).

[0065] In the connection area (CON), a first gate stack (GS1) may be extended to form a first pad portion (PAD1), and a first cover insulating layer (172) covering the first pad portion (PAD1) may be disposed. Additionally, a second gate stack (GS2) may be extended to form a second pad portion (PAD2), and a second cover insulating layer (272) covering the second pad portion (PAD2) may be disposed. In the connection area (CON), a plurality of first gate lines (130) and a plurality of second gate lines (230) may be extended to have a shorter length along a first horizontal direction (X direction) as they move away from the upper surface of the base substrate (110). The first pad portion (PAD1) may refer to portions of the first gate line (130) arranged in a stepped shape, and the second pad portion (PAD2) may refer to portions of the second gate line (230) arranged in a stepped shape.

[0066] In the connection area (CON), a plurality of pad contacts (CNT) may be arranged to be connected to a plurality of first gate lines (130) by penetrating the upper support layer (TS), upper insulation layer (174), second cover insulation layer (272), and first cover insulation layer (172), or connected to a plurality of second gate lines (230) by penetrating the upper support layer (TS), upper insulation layer (174), and second cover insulation layer (272). Each of the plurality of first gate lines (130) and the plurality of second gate lines (230) may be referred to as a gate line, and the first cover insulation layer (172), the second cover insulation layer (272), the upper insulation layer (174), and the upper support layer (TS) may be referred to collectively as a cover insulation layer. The plurality of pad contacts (CNT) may be connected to a plurality of conductive lines (ML) and a plurality of gate lines by penetrating the cover insulation layer. A plurality of pad contacts (CNT) can penetrate together the cover insulating layer and a plurality of first insulating layers (140) covering the upper surface of a plurality of first gate lines (130) or a plurality of second insulating layers (140) covering the upper surface of a plurality of second gate lines (230).

[0067] In some embodiments, a common source contact (CSLT) connecting a conductive line (ML) and a substrate layer (110S) may be disposed in the connection region (CON) through the upper support layer (TS), upper insulating layer (174), second cover insulating layer (272), first cover insulating layer (172), upper base layer (110U), and insulating plate (112). In other embodiments, the common source contact (CSLT) may be disposed within the gate stack separation opening (WLH). In this case, a common source region (not shown) may be further formed in the portion of the substrate layer (110S) in contact with the common source contact (CSLT). The common source region may be an impurity region doped with a high concentration of n-type impurities and may function as a source region supplying current to memory cells.

[0068] Although not shown, a plurality of dummy channel structures (not shown) may be further formed in the connection area (CON) that extend vertically (Z direction) through the first gate stack (GS1) and the second gate stack (GS2) from the upper surface of the substrate layer (110S). The dummy channel structures may be formed to prevent leaning or bending of the first gate stack (GS1) and the second gate stack (GS2) and to ensure structural stability during the manufacturing process of the integrated circuit device (100). Each of the plurality of dummy channel structures may have a structure and shape similar to the plurality of channel structures (160). An upper insulating layer (174) may be disposed on the second gate stack (GS2) and the second cover insulating layer (272).

[0069] In the through electrode region (TVR), a plurality of through electrodes (TVS) that fill a plurality of electrode holes (TVH) may be disposed. The plurality of electrode holes (TVH) penetrate the upper support layer (TS), the second cover insulation layer (174), the first cover insulation layer (172), and the base insulation layer (120), so that a peripheral circuit wiring structure (70) may be exposed on the bottom surface. The plurality of through electrodes (TVS) may be connected to the peripheral circuit wiring structure (70) by penetrating the upper support layer (TS), the second cover insulation layer (174), the first cover insulation layer (172), and the base insulation layer (120). In some embodiments, the bottom surface of the plurality of through electrodes (TVS) may be in contact with the peripheral circuit wiring layer (74) disposed at the top level. The plurality of through electrodes (TVS) may connect between the conductive line (ML) and the peripheral circuit wiring structure (70).

[0070] In FIG. 4a, the through electrode region (TVR) is shown positioned opposite to the memory cell region (MCR) with respect to the connection region (CON), but is not limited thereto. In some embodiments, the through electrode region (TVR) may be positioned between the memory cell region (MCR) and the connection region (CON). In other embodiments, the through electrode region (TVR) may be positioned within the connection region (CON). For example, the through electrode region (TVR) may be positioned within the connection region (CON) between the first pad portion (PAD1) and the second pad portion (PAD2).

[0071] The integrated circuit element (100) according to the present invention can have structural reliability because the barrier layer (90) acts as a structural support layer during the manufacturing process.

[0072] FIGS. 5a to 6c are plan views showing through-electrode regions of an integrated circuit element according to exemplary embodiments of the present invention. Specifically, FIGS. 5a to 6c are plan views showing the first barrier layer (92) cut in the horizontal direction (X direction and Y direction) in the region corresponding to the through-electrode region (TVR) shown in FIG. 4a. Descriptions of FIGS. 5a to 6c that overlap with FIGS. 4a to 4c may be omitted.

[0073] Referring to FIG. 5a, the integrated circuit element (100-1a) may include a through electrode region (TVR-1a) in which a plurality of through electrodes (TVS) that fill a plurality of electrode holes (TVH) are disposed. A plurality of openings (120H) may penetrate a barrier layer (90) including a first barrier layer (92). A base insulating layer (120) may fill the interior of the openings (120H). Each of the plurality of electrode holes (TVH) may penetrate the base insulating layer (120) that fills each of the plurality of openings (120H).

[0074] A plurality of through electrodes (TVS) can fill a plurality of electrode holes (TVH). Each of the plurality of through electrodes (TVS) has a base insulating layer (120) between them that fills each of the plurality of openings (120H), and can be spaced apart from a barrier layer (90) including a first barrier layer (92).

[0075] In some embodiments, each of the plurality of openings (120H) may have a circular cross-section in the horizontal direction (X and Y directions). For example, each of the plurality of openings (120H) may surround a corresponding one of the plurality of through electrodes (TVS). The base insulating layer (120) filling the interior of each of the plurality of openings (120H) may have a ring-shaped cross-section in the horizontal direction (X and Y directions).

[0076] Referring to FIG. 5b, the integrated circuit element (100-1b) may include a through electrode region (TVR-1b) in which a plurality of through electrodes (TVS) that fill a plurality of electrode holes (TVH) are arranged.

[0077] In some embodiments, each of the plurality of openings (120H) may have a rectangular cross-section in the horizontal direction (X direction and Y direction). For example, each of the plurality of openings (120H) may surround a corresponding one of the plurality of through electrodes (TVS).

[0078] Referring to FIG. 5c, the integrated circuit element (100-1c) may include a through electrode region (TVR-1c) in which a plurality of through electrodes (TVS) that fill a plurality of electrode holes (TVH) are arranged.

[0079] In some embodiments, each of the plurality of openings (120H) may have a rectangular cross-section with rounded corners in the horizontal direction (X and Y directions). For example, each of the plurality of openings (120H) may surround a corresponding one of the plurality of through electrodes (TVS).

[0080] Referring to FIG. 6a, the integrated circuit element (100-2a) may include a through electrode region (TVR-2a) in which a plurality of through electrodes (TVS) are disposed to fill a plurality of electrode holes (TVH). A plurality of openings (120H) and at least one extended opening (120HE) may penetrate a barrier layer (90) including a first barrier layer (92). A base insulating layer (120) may fill the interior of the openings (120H) and the interior of the extended openings (120H). Each of the plurality of electrode holes (TVH) may penetrate the base insulating layer (120) that fills each of the plurality of openings (120H) and at least one extended opening (120H). In the present specification, an opening (120H) may be referred to as a single opening, and in this case, a plurality of openings (120H) and at least one extended opening (120HE) may be referred to together as a plurality of openings.

[0081] A plurality of through electrodes (TVS) can fill a plurality of electrode holes (TVH). Each of the plurality of through electrodes (TVS) has a base insulating layer (120) between them that fills each of a plurality of openings (120H) and at least one expanded opening (120H), and can be spaced apart from a barrier layer (90) including a first barrier layer (92).

[0082] In some embodiments, each of the plurality of openings (120H) may have a circular cross-section in the horizontal direction (X and Y directions). For example, each of the plurality of openings (120H) may surround a corresponding one of the plurality of through electrodes (TVS). The base insulating layer (120) filling the interior of each of the plurality of openings (120H) may have a ring-shaped cross-section in the horizontal direction (X and Y directions).

[0083] At least one expansion opening (120HE) may have an elliptical shape in the horizontal direction (X direction and Y direction) by connecting two or more openings (120H). The expansion opening (120HE) may surround two or more corresponding through electrodes (TVS).

[0084] Among the plurality of through electrodes (TVS), a through electrode (TVS) that is relatively far apart from other through electrodes (TVS) may be placed alone within the opening (120H), and two or more through electrodes (TVS) that are relatively close together may be placed together within the expanded opening (120HE). That is, the distance between the through electrode (TVS) placed within the opening (120H) and the remaining through electrodes (TVS) among the plurality of through electrodes (TVS) may be greater than the distance between two or more through electrodes placed together within the expanded opening (120HE).

[0085] Referring to FIG. 6b, the integrated circuit element (100-2b) may include a through electrode region (TVR-2b) in which a plurality of through electrodes (TVS) that fill a plurality of electrode holes (TVH) are arranged.

[0086] In some embodiments, each of the plurality of openings (120H) may have a rectangular cross-section in the horizontal direction (X direction and Y direction). For example, each of the plurality of openings (120H) may surround a corresponding one of the plurality of through electrodes (TVS).

[0087] At least one expansion opening (120HE) may have a rectangular shape in the horizontal direction (X direction and Y direction) by connecting two or more openings (120H). In some embodiments, at least one expansion opening (120HE) may have a rectangular shape that extends along any one of the first horizontal direction (X direction), the second horizontal direction (Y direction), and the third horizontal direction (e.g., diagonal direction). The expansion opening (120HE) may surround two or more corresponding through electrodes (TVS).

[0088] Referring to FIG. 5c, the integrated circuit element (100-2c) may include a through electrode region (TVR-2c) in which a plurality of through electrodes (TVS) that fill a plurality of electrode holes (TVH) are disposed.

[0089] In some embodiments, each of the plurality of openings (120H) may have a rectangular cross-section with rounded corners in the horizontal direction (X and Y directions). For example, each of the plurality of openings (120H) may surround a corresponding one of the plurality of through electrodes (TVS).

[0090] At least one expansion opening (120HE) may have a rectangular shape with rounded corners in the horizontal direction (X direction and Y direction) by connecting two or more openings (120H). In some embodiments, at least one expansion opening (120HE) may have a rectangular shape with rounded corners that extends along any one of the first horizontal direction (X direction), the second horizontal direction (Y direction), and the third horizontal direction (e.g., diagonal direction). The expansion opening (120HE) may surround two or more corresponding through electrodes (TVS).

[0091] In FIG. 4a, only two through electrodes (TVS) are exemplarily shown in the through electrode region (TVR), but the through electrode region (TVR) shown in FIG. 4a may be any one of the through electrode regions (TVR-1a, TVR-1b, TVR-1c, TVR-2a, TVR-2b, TVR-2c) shown in FIG. 5a to 6c.

[0092] FIGS. 7a and 7b are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. Specifically, FIG. 7b is a cross-sectional view showing an enlarged view of the CXC portion of FIG. 7a. Descriptions of FIGS. 7a and 7c that overlap with FIGS. 4a through 4c may be omitted.

[0093] Referring to FIG. 7a and FIG. 7b together, the integrated circuit element (200) may include a peripheral circuit structure (PS) and a cell array structure (CS) positioned at a vertical level higher than the peripheral circuit structure (PS). The cell array structure (CS) includes a memory cell region (MCR), a connection region (CON), and a through-electrode region (TVR), and the peripheral circuit structure (PS) may include a peripheral circuit region (PERI).

[0094] A peripheral circuit structure (PS) may include a peripheral circuit transistor (60TR) and a peripheral circuit wiring structure (70) disposed on a substrate (50). The peripheral circuit wiring structure (70) includes a plurality of peripheral circuit contacts (72) and a plurality of peripheral circuit wiring layers (74). An interlayer insulating film (80) covering the peripheral circuit transistor (60TR) and the peripheral circuit wiring structure (70) may be disposed on the substrate (50). At least one antenna diode (D40) may be further disposed on the substrate (50). The antenna diode (D40) may include a diode ion implantation region (42).

[0095] The interlayer insulating film (80) may include a first interlayer insulating layer (82), a passivation layer (84), and a second interlayer insulating layer (86) that are sequentially stacked. A barrier layer (90) may be disposed on the interlayer insulating film (80). In some embodiments, the barrier layer (90) may be formed in a stacked structure of a first barrier layer (92) covering the interlayer insulating film (80) and a second barrier layer (94) covering the first barrier layer (92). A bypass hole (BPH) may penetrate the barrier layer (90) and a portion of the interlayer insulating film (80). A peripheral circuit wiring layer (74) of a peripheral circuit wiring structure (70) may be exposed at the bottom surface of the bypass hole (BPH).

[0096] The cover layer (96) may extend from between the bypass via (BPV) and the first barrier layer (92) to the upper surface of the second barrier layer (94). Specifically, the cover layer (96) may cover the upper surface of the barrier layer (90), i.e., the upper surface of the second barrier layer (94), and the inner surface of the bypass hole (BPH), i.e., the side wall and bottom surface within the bypass hole (BPH). The cover layer (96) may conformally cover the upper surface of the second barrier layer (94) and the inner surface of the bypass hole (BPH). The cover layer (96) may cover the side of the second barrier layer (92), the side of the first barrier layer (92), the side of the second interlayer insulation layer (86), the side of the passivation layer (84), and the upper surface of the peripheral circuit wiring layer (74) within the bypass hole (BPH). In some embodiments, the cover layer (96) may be made of a metal-containing nitride or a metal silicide. For example, the cover layer (96) may be made of TiN, TSN (Ti-Si-N), WN, or WSi, etc.

[0097] A base substrate (110) may be disposed on the cover layer (96). Bypass vias (BPVs) may be disposed in the bypass holes (BPHs). In some embodiments, the bypass vias (BPVs) may be formed together with the substrate layer (110S) to form an integral part. The cover layer (96) may be made of a material different from that of the substrate layer (110S). In some embodiments, the cover layer (96) may be made of a material resistant to etching of the substrate layer (110S). The cover layer (96) can prevent the first barrier layer (92) from being removed together with the substrate layer (110S) even when a portion of the substrate layer (110S) is removed during the manufacturing process.

[0098] FIGS. 8a and 8b are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. Specifically, FIG. 8b is a cross-sectional view showing an enlarged view of the CXD portion of FIG. 8a. Descriptions of FIGS. 8a and 8b that overlap with FIGS. 4a to 4c, FIG. 7a, and FIG. 7b may be omitted.

[0099] Referring to FIG. 8a and FIG. 8b together, the integrated circuit element (300) may include a peripheral circuit structure (PS) and a cell array structure (CS) positioned at a vertical level higher than the peripheral circuit structure (PS). The cell array structure (CS) includes a memory cell region (MCR), a connection region (CON), and a through-electrode region (TVR), and the peripheral circuit structure (PS) may include a peripheral circuit region (PERI).

[0100] A peripheral circuit structure (PS) may include a peripheral circuit transistor (60TR) and a peripheral circuit wiring structure (70) disposed on a substrate (50). The peripheral circuit wiring structure (70) includes a plurality of peripheral circuit contacts (72) and a plurality of peripheral circuit wiring layers (74). An interlayer insulating film (80) covering the peripheral circuit transistor (60TR) and the peripheral circuit wiring structure (70) may be disposed on the substrate (50). At least one antenna diode (D40) may be further disposed on the substrate (50). The antenna diode (D40) may include a diode ion implantation region (42).

[0101] The interlayer insulating film (80) may include a first interlayer insulating layer (82), a passivation layer (84), and a second interlayer insulating layer (86) that are sequentially stacked. A barrier layer (90) may be disposed on the interlayer insulating film (80). In some embodiments, the barrier layer (90) may be formed in a stacked structure of a first barrier layer (92) covering the interlayer insulating film (80) and a second barrier layer (94) covering the first barrier layer (92). A bypass hole (BPH) may penetrate the barrier layer (90) and a portion of the interlayer insulating film (80). A peripheral circuit wiring layer (74) of a peripheral circuit wiring structure (70) may be exposed at the bottom surface of the bypass hole (BPH).

[0102] Bypass vias (BPVa) may be disposed in the bypass hole (BPH). The bypass vias (BPVa) may consist of a bypass barrier layer (BPB) that conformally covers the inner surface of the bypass hole (BPH), i.e., the sidewalls and bottom surface within the bypass hole (BPH), and a bypass conductive layer (BPC) that covers the bypass barrier layer (BPB) and fills the bypass hole (BPH). The bypass barrier layer (BPB) may be made of a metal nitride. For example, the bypass barrier layer (BPB) may be made of TiN or WN, etc. The bypass conductive layer (BPC) may be made of a metal. For example, the bypass conductive layer (BPC) may be made of W, etc.

[0103] A base substrate (110) may be disposed on the barrier layer (90) and the bypass via (BPVa). The second barrier layer (94) and the bypass via (BPVa) may be made of a material different from that of the substrate layer (110S). In some embodiments, the second barrier layer (94) and the bypass via (BPVa) may be made of a material resistant to etching of the substrate layer (110S). Since the second barrier layer (94) and the bypass via (BPVa) fill the bypass hole (BPH) through which the first barrier layer (92) is exposed, the first barrier layer (92) may be prevented from being removed together with the first barrier layer (92) even if a portion of the substrate layer (110S) is removed during the manufacturing process.

[0104] FIGS. 9a and 9b are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. Specifically, FIG. 9b is a cross-sectional view showing an enlarged view of the CXE portion of FIG. 9a. Descriptions of FIGS. 8a and 8c that overlap with FIGS. 4a to 4c, FIG. 8a, and FIG. 8b may be omitted.

[0105] Referring to FIG. 9a and FIG. 9b together, the integrated circuit element (302) may include a peripheral circuit structure (PS) and a cell array structure (CS) positioned at a vertical level higher than the peripheral circuit structure (PS).

[0106] The bypass hole (BPHa) penetrates the base substrate (110) and the barrier layer (90), and can penetrate a portion of the interlayer insulating film (80). The peripheral circuit wiring layer (74) of the peripheral circuit wiring structure (70) may be exposed on the bottom surface of the bypass hole (BPHa).

[0107] A bypass via (BPVb) may be disposed in the bypass hole (BPHa). The bypass via (BPVb) may consist of a bypass barrier layer (BPBa) that conformally covers the inner surface of the bypass hole (BPHa), i.e., the sidewalls and bottom surface within the bypass hole (BPHa), and a bypass conductive layer (BPCa) that covers the bypass barrier layer (BPBa) and fills the bypass hole (BPHa). The bypass barrier layer (BPBa) may be made of a metal nitride. The bypass conductive layer (BPCa) may be made of a metal.

[0108] The upper surface of the bypass via (BPVa) shown in FIGS. 8a and 8b may be located at the same vertical level as the upper surface of the barrier layer (90) and thus form a coplanar plane, whereas the upper surface of the bypass via (BPVb) shown in FIGS. 9a and 9b may be located at the same vertical level as the upper surface of the base substrate (110) and thus form a coplanar plane.

[0109] FIGS. 10a to 10f are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to exemplary embodiments of the present invention. Specifically, FIGS. 10a to 10f are cross-sectional views to explain a method for manufacturing an integrated circuit element (100) shown in FIGS. 4a to 4c, and descriptions of FIGS. 10a to 10f that overlap with FIGS. 4a to 4c may be omitted.

[0110] Referring to FIG. 10a, a peripheral circuit structure (PS) is formed including a peripheral circuit transistor (60TR) placed on a substrate (50) and a peripheral circuit wiring structure (70) surrounded by an interlayer insulating film (80).

[0111] A barrier layer (90) is formed on the interlayer insulating film (80). The barrier layer (90) may be formed to have a stacked structure of a first barrier layer (92) covering the interlayer insulating film (80) and a second barrier layer (94) covering the first barrier layer (92). In some embodiments, the first barrier layer (92) may be formed of a semiconductor material, and the second barrier layer (94) may be formed of an oxide. For example, the first barrier layer (92) may be formed of polysilicon, and the second barrier layer (94) may be formed of silicon oxide. The first barrier layer (92) may be formed thicker than the second barrier layer (94).

[0112] Referring to FIG. 10b, a bypass hole (BPH) is formed that penetrates the barrier layer (90) and exposes a surrounding circuit wiring structure (70) on the bottom surface. The bypass hole (BPH) can be formed by penetrating a portion of the barrier layer (90) and the interlayer insulating film (80). For example, the bypass hole (BPH) can penetrate the second barrier layer (94), the first barrier layer (92), the second interlayer insulating layer (86), and the passivation layer (84).

[0113] Referring to FIG. 10c, a plasma nitriding process is performed on the result of FIG. 10b to form a cover layer (92N) that nitrides a portion of the first barrier layer (92) exposed within the bypass hole (BPH) and a cover contact layer (74N) that nitrides a portion of the peripheral circuit wiring layer (74) exposed on the bottom surface of the bypass hole (BPH).

[0114] Referring to FIG. 10d, a substrate layer (110S) is formed on a barrier layer (90). Bypass vias (BPVs) can be formed together with the substrate layer (110S). When forming a semiconductor material on the barrier layer (90) to form the substrate layer (110S), a portion of the semiconductor material may fill a bypass hole (BPH) so that bypass vias (BPVs) are formed together with the substrate layer (110S).

[0115] Referring to FIG. 10e, an insulating plate (112) and an upper base layer (110U) are sequentially formed on a substrate layer (110S). Afterward, a portion of the insulating plate (112) is removed to form a plate recess (112R) that penetrates the insulating plate (112), and a base dam portion (110C) that fills the plate recess (112R) and an upper base layer (110U) that covers the insulating plate (112) are formed. The base dam portion (110C) can be formed together with the upper base layer (110U) to form an integral unit.

[0116] Referring to FIG. 10f, in the through electrode region (TVR), a plurality of openings (120H) are formed through a structure in which a substrate layer (110S), an insulating plate (112), and an upper base layer (110U) are sequentially stacked. An interlayer insulating film (80) may be exposed on the bottom surface of the plurality of openings (120H). Subsequently, a base insulating layer (120) is formed to fill the plurality of openings (120H).

[0117] Subsequently, as shown in FIGS. 4a to 4c, an integrated circuit element (100) can be formed by forming a first gate stack (GS1), a second gate stack (GS2), a plurality of channel structures (160), a plurality of pad contacts (CNT), a plurality of through electrodes (TVS), and a bit line (BL). The lower base layer (110L) can be formed by removing a portion of an insulating plate (112) located on one side, for example, the side facing the memory cell region (MCR), based on the base damper (110C), and then filling the space where the portion of the insulating plate (112) was removed.

[0118] FIGS. 11a and FIGS. 11b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to exemplary embodiments of the present invention. Specifically, FIGS. 11a and FIGS. 11b are cross-sectional views to explain a method for manufacturing an integrated circuit element (200) shown in FIGS. 7a and FIGS. 7b.

[0119] Referring to FIG. 11a, a cover layer (96) is formed on the result shown in FIG. 10c, covering the upper surface of the barrier layer (90), i.e., the upper surface of the second barrier layer (94), and the inner surface of the bypass hole (BPH), i.e., the side wall and bottom surface inside the bypass hole (BPH). The cover layer (96) can be formed to conformally cover the upper surface of the second barrier layer (94) and the inner surface of the bypass hole (BPH).

[0120] Referring to FIG. 11b, a substrate layer (110S) is formed on a cover layer (96). Bypass vias (BPVs) can be formed together with the substrate layer (110S). When forming a semiconductor material on the cover layer (96) to form the substrate layer (110S), a portion of the semiconductor material may fill a bypass hole (BPH) so that bypass vias (BPVs) are formed together with the substrate layer (110S).

[0121] Afterwards, an integrated circuit element (200) can be formed by referring to the manufacturing method described in FIG. 10e and FIG. 10f and the description in FIG. 7a and FIG. 7b.

[0122] FIGS. 12a and 12b are cross-sectional views illustrated in the order of process to explain a method for manufacturing an integrated circuit element according to exemplary embodiments of the present invention. Specifically, FIGS. 12a and 12b are cross-sectional views to explain a method for manufacturing an integrated circuit element (300) shown in FIGS. 8a and 8b.

[0123] Referring to FIG. 12a, a bypass via (BPVa) is formed to fill the bypass hole (BPH) in the result shown in FIG. 10c. The bypass via (BPVa) may consist of a bypass barrier layer (BPB) and a bypass conductive layer (BPC). The bypass barrier layer (BPB) may be formed to conformally cover the inner surface of the bypass hole (BPH), that is, the sidewalls and bottom surface within the bypass hole (BPH), and the bypass conductive layer (BPC) may be formed to cover the bypass barrier layer (BPB) and fill the bypass hole (BPH).

[0124] Referring to FIG. 12b, a substrate layer (110S) is formed on a barrier layer (90) and a bypass via (BPVa). Subsequently, an integrated circuit element (300) can be formed by referring to the manufacturing method described in FIG. 10e and FIG. 10f and the description in FIG. 8a and FIG. 8b.

[0125] The integrated circuit element (300) shown in FIGS. 9a and 9b can be formed by sequentially forming an insulating plate (112) and an upper base layer (110U) on a substrate layer (110S), and then forming a bypass hole (BPHa) and a bypass via (BPVb) that fills the bypass hole (BPHa).

[0126] FIGS. 13 and 14 are cross-sectional views illustrating integrated circuit elements according to exemplary embodiments of the present invention. Descriptions of FIGS. 13 and 14 that overlap with FIGS. 4a through 12b may be omitted.

[0127] Referring to FIG. 13, the integrated circuit element (400) may include a peripheral circuit structure (PS) and a cell array structure (CS) positioned at a vertical level higher than the peripheral circuit structure (PS). The cell array structure (CS) includes a memory cell region (MCR), a connection region (CON), and a through-electrode region (TVR), and the peripheral circuit structure (PS) may include a peripheral circuit region (PERI).

[0128] A barrier layer (90a) may be disposed on the interlayer insulating film (80). A bypass hole (BPH) may penetrate the barrier layer (90a) and a portion of the interlayer insulating film (80). A peripheral circuit wiring layer (74) of a peripheral circuit wiring structure (70) may be exposed on the bottom surface of the bypass hole (BPH). A bypass via (BPV) may be disposed in the bypass hole (BPH).

[0129] The barrier layer (90a) may be made of a material different from that of the substrate layer (110S). In some embodiments, the barrier layer (90a) may be made of a material resistant to etching of the substrate layer (110S). For example, the barrier layer (90a) may be made of a metal oxide. In some embodiments, the barrier layer (90a) may be made of Al2O3, HfO2, or ZrO2, etc. The barrier layer (90a) may not be removed even if a portion of the substrate layer (110S) is removed during the manufacturing process.

[0130] Referring to FIG. 14, the integrated circuit element (402) may include a peripheral circuit structure (PS) and a cell array structure (CS) positioned at a vertical level higher than the peripheral circuit structure (PS). The cell array structure (CS) includes a memory cell region (MCR), a connection region (CON), and a through-electrode region (TVR), and the peripheral circuit structure (PS) may include a peripheral circuit region (PERI).

[0131] A barrier layer (90b) may be disposed on the interlayer insulating film (80). A bypass hole (BPH) may penetrate the barrier layer (90b) and a portion of the interlayer insulating film (80). A peripheral circuit wiring layer (74) of a peripheral circuit wiring structure (70) may be exposed on the bottom surface of the bypass hole (BPH). A bypass via (BPV) may be disposed in the bypass hole (BPH).

[0132] The barrier layer (90b) may be made of a material different from that of the substrate layer (110S). In some embodiments, the barrier layer (90b) may be made of a material resistant to etching of the substrate layer (110S). For example, the barrier layer (90b) may be made of a metal. It may be made of an oxide. In some embodiments, the barrier layer (90b) may be made of W, etc. The barrier layer (90b) may not be removed even if a portion of the substrate layer (110S) is removed during the manufacturing process.

[0133] FIG. 15 is a schematic diagram showing an electronic system including an integrated circuit element according to exemplary embodiments of the present invention.

[0134] Referring to FIG. 15, an electronic system (1000) according to an exemplary embodiment of the present invention may include an integrated circuit element (1100) and a controller (1200) electrically connected to the integrated circuit element (1100). The electronic system (1000) may be a storage device or an electronic device including a storage device, comprising one or more integrated circuit elements (1100). For example, the electronic system (1000) may be a solid state drive device (SSD), a Universal Serial Bus (USB), a computing system, a medical device, or a communication device, comprising at least one integrated circuit element (1100).

[0135] The integrated circuit element (1100) may be a non-volatile memory element. For example, the integrated circuit element (1100) may be a NAND flash memory element comprising at least one of the structures described above for the integrated circuit elements (10, 100, 100-1a, 100-1b, 100-1c, 100-2a, 100-2b, 100-2c, 200, 300, 302, 400, 402) described with reference to FIGS. 1 to 14. The integrated circuit element (1100) may include a first structure (1100F) and a second structure (1100S) on the first structure (1100F). The first structure (1100F) may be a peripheral circuit structure including a decoder circuit (1110), a page buffer (1120), and a logic circuit (1130). The second structure (1100S) may be a memory cell structure including a bit line (BL), a common source line (CSL), a plurality of word lines (WL), first and second gate upper lines (UL1, UL2), first and second gate lower lines (LL1, LL2), and a plurality of memory cell strings (CSTR) located between the bit line (BL) and the common source line (CSL).

[0136] In the second structure (1100S), a plurality of memory cell strings (CSTR) may each include a lower transistor (LT1, LT2) adjacent to a common source line (CSL), an upper transistor (UT1, UT2) adjacent to a bit line (BL), and a plurality of memory cell transistors (MCT) disposed between the lower transistor (LT1, LT2) and the upper transistor (UT1, UT2). The number of lower transistors (LT1, LT2) and the number of upper transistors (UT1, UT2) may vary depending on the embodiments.

[0137] In exemplary embodiments, the upper transistors (UT1, UT2) may include string select transistors, and the lower transistors (LT1, LT2) may include ground select transistors. A plurality of gate lower lines (LL1, LL2) may each be gate lines of the lower transistors (LT1, LT2). The word line (WL) may be a gate line of the memory cell transistor (MCT), and the gate upper lines (UL1, UL2) may be gate lines of the upper transistors (UT1, UT2).

[0138] A common source line (CSL), a plurality of gate lower lines (LL1, LL2), a plurality of word lines (WL), and a plurality of gate upper lines (UL1, UL2) can be electrically connected to a decoder circuit (1110) through a plurality of first connecting wires (1115) extending from the first structure (1100F) to the second structure (1100S). A plurality of bit lines (BL) can be electrically connected to a page buffer (1120) through a plurality of second connecting wires (1125) extending from the first structure (1100F) to the second structure (1100S).

[0139] In the first structure (1100F), the decoder circuit (1110) and the page buffer (1120) can perform control operations on at least one of a plurality of memory cell transistors (MCT). The decoder circuit (1110) and the page buffer (1120) can be controlled by a logic circuit (1130).

[0140] The integrated circuit element (1100) can communicate with the controller (1200) through an input / output pad (1101) that is electrically connected to the logic circuit (1130). The input / output pad (1101) can be electrically connected to the logic circuit (1130) through an input / output connection wire (1135) that extends from the first structure (1100F) to the second structure (1100S).

[0141] The controller (1200) may include a processor (1210), a NAND controller (1220), and a host interface (1230). According to embodiments, the electronic system (1000) may include a plurality of integrated circuit elements (1100), and in this case, the controller (1200) may control the plurality of integrated circuit elements (1100).

[0142] The processor (1210) can control the overall operation of the electronic system (1000), including the controller (1200). The processor (1210) can operate according to a predetermined firmware and can access the integrated circuit element (1100) by controlling the NAND controller (1220). The NAND controller (1220) may include a NAND interface (1221) that handles communication with the integrated circuit element (1100). Through the NAND interface (1221), control commands for controlling the integrated circuit element (1100), data to be written to a plurality of memory cell transistors (MCTs) of the integrated circuit element (1100), data to be read from a plurality of memory cell transistors (MCTs) of the integrated circuit element (1100), etc., can be transmitted. The host interface (1230) can provide communication functions between the electronic system (1000) and an external host. When a control command is received from an external host through the host interface (1230), the processor (1210) can control the integrated circuit element (1100) in response to the control command.

[0143] FIG. 16 is a schematic perspective view of an electronic system including an integrated circuit element according to exemplary embodiments of the present invention.

[0144] Referring to FIG. 16, an electronic system (2000) according to an exemplary embodiment of the present invention may include a main board (2001), a controller (2002) mounted on the main board (2001), one or more semiconductor packages (2003), and a DRAM (2004). The semiconductor package (2003) and the DRAM (2004) may be connected to the controller (2002) by a plurality of wiring patterns (2005) formed on the main board (2001).

[0145] The main board (2001) may include a connector (2006) comprising a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (2006) may vary depending on the communication interface between the electronic system (2000) and the external host. In exemplary embodiments, the electronic system (2000) may communicate with the external host according to any one of interfaces such as USB (Universal Serial Bus), PCI-Express (Peripheral Component Interconnect Express), SATA (Serial Advanced Technology Attachment), and M-Phy for UFS (Universal Flash Storage). In exemplary embodiments, the electronic system (2000) may operate by power supplied from the external host through the connector (2006). The electronic system (2000) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (2002) and a semiconductor package (2003).

[0146] The controller (2002) can write data to the semiconductor package (2003) or read data from the semiconductor package (2003), and can improve the operating speed of the electronic system (2000).

[0147] The DRAM (2004) may be a buffer memory to mitigate the speed difference between the semiconductor package (2003), which is a data storage space, and an external host. The DRAM (2004) included in the electronic system (2000) may also function as a type of cache memory and may provide a space for temporarily storing data during control operations on the semiconductor package (2003). When the DRAM (2004) is included in the electronic system (2000), the controller (2002) may further include a DRAM controller for controlling the DRAM (2004) in addition to the NAND controller for controlling the semiconductor package (2003).

[0148] A semiconductor package (2003) may include first and second semiconductor packages (2003a, 2003b) spaced apart from each other. The first and second semiconductor packages (2003a, 2003b) may each be a semiconductor package including a plurality of semiconductor chips (2200). Each of the first and second semiconductor packages (2003a, 2003b) may include a package substrate (2100), a plurality of semiconductor chips (2200) on the package substrate (2100), an adhesive layer (2300) disposed on the lower surface of each of the plurality of semiconductor chips (2200), a connecting structure (2400) electrically connecting the plurality of semiconductor chips (2200) and the package substrate (2100), and a molding layer (2500) covering the plurality of semiconductor chips (2200) and the connecting structure (2400) on the package substrate (2100).

[0149] The package substrate (2100) may be a printed circuit board including a plurality of package upper pads (2130). Each of the plurality of semiconductor chips (2200) may include an input / output pad (2210). The input / output pad (2210) may correspond to the input / output pad (1101) of FIG. 13. Each of the plurality of semiconductor chips (2200) may include a plurality of gate stacks (3210) and a plurality of channel structures (3220). Each of the plurality of semiconductor chips (2200) may include at least one of the integrated circuit elements (10, 100, 100-1a, 100-1b, 100-1c, 100-2a, 100-2b, 100-2c, 200, 300, 302, 400, 402) described with reference to FIGS. 1 to 10.

[0150] In exemplary embodiments, the connection structure (2400) may be a bonding wire that electrically connects the input / output pad (2210) and the package upper pad (2130). Thus, in the first and second semiconductor packages (2003a, 2003b), a plurality of semiconductor chips (2200) may be electrically connected to each other by a bonding wire method and may be electrically connected to the package upper pad (2130) of the package substrate (2100). According to embodiments, in the first and second semiconductor packages (2003a, 2003b), a plurality of semiconductor chips (2200) may be electrically connected to each other by a connection structure including a through silicon via (TSV) instead of the bonding wire method connection structure (2400).

[0151] In exemplary embodiments, the controller (2002) and a plurality of semiconductor chips (2200) may be included in a single package. In an exemplary embodiment, the controller (2002) and a plurality of semiconductor chips (2200) may be mounted on a separate interposer substrate different from the main substrate (2001), and the controller (2002) and the plurality of semiconductor chips (2200) may be connected to each other by wiring formed on the interposer substrate.

[0152] FIG. 17 is a schematic cross-sectional view of a semiconductor package according to exemplary embodiments of the present invention. FIG. 17 illustrates in more detail the configuration according to the cross-section along line II-II' of FIG. 16.

[0153] Referring to FIG. 17, in a semiconductor package (2003), the package substrate (2100) may be a printed circuit board. The package substrate (2100) may include a package substrate body portion (2120), a plurality of package upper pads (2130) disposed on the upper surface of the package substrate body portion (2120) (see FIG. 16), a plurality of lower pads (2125) disposed on the lower surface of the package substrate body portion (2120) or exposed through the lower surface, and a plurality of internal wirings (2135) that electrically connect the plurality of upper pads (2130) and the plurality of lower pads (2125) inside the package substrate body portion (2120). The plurality of upper pads (2130) may be electrically connected to a plurality of connection structures (2400). A plurality of lower pads (2125) can be connected to a plurality of wiring patterns (2005) on a main board (2001) of an electronic system (2000) illustrated in FIG. 16 through a plurality of conductive connection parts (2800).

[0154] Each of the plurality of semiconductor chips (2200) may include a semiconductor substrate (3010) and a first structure (3100) and a second structure (3200) that are sequentially stacked on the semiconductor substrate (3010). The first structure (3100) may include a peripheral circuit region that includes a plurality of peripheral wires (3110). The first structure (3100) may include a gate line (200) that is electrically connected to the plurality of peripheral wires (3110). The second structure (3200) may include a common source line (3205), a gate stack (3210) on the common source line (3205), a channel structure (3220) penetrating the gate stack (3210), a bit line (3240) that is electrically connected to the channel structure (3220), and the gate stack (3210).

[0155] A barrier layer (90) may be interposed between the first structure (3100) and the second structure (3200). In some embodiments, the barrier layer (90) may be formed as a laminated structure of a first barrier layer (92) covering an interlayer insulating film (80) and a second barrier layer (94) covering the first barrier layer (92). A bypass via (BPV) may be disposed in a bypass hole (BPH) penetrating the barrier layer (90). In some embodiments, a cover layer (92N) may be interposed between the bypass via (BPV) and the first barrier layer (92). In some embodiments, a cover contact layer (74N) may be interposed between the bypass via (BPV) and the peripheral circuit wiring layer (74).

[0156] FIG. 17 is illustrated as each of a plurality of semiconductor chips (2200) including a barrier layer (90), bypass hole (BPH), bypass via (BPV), cover layer (92N), and cover contact layer (74N) as shown in FIG. 4a to 4c, but is not limited thereto. For example, instead of each of the plurality of semiconductor chips (2200) including the barrier layer (90), bypass hole (BPH), bypass via (BPV), cover layer (92N), and cover contact layer (74N) shown in FIGS. 4a to 4c, each may include the barrier layer (90), bypass hole (BPH), bypass via (BPV), and cover layer (96) shown in FIGS. 7a and 7b, or include the barrier layer (90), bypass hole (BPH), and bypass via (BPVa) shown in FIGS. 8a and 8b, or include the barrier layer (90), bypass hole (BPHa), and bypass via (BPVb) shown in FIGS. 9a and 9b, or include the barrier layer (90a), bypass hole (BPH), and bypass via (BPV) shown in FIG. 13, or include the barrier layer (90b), bypass shown in FIG. 14. It may include a hole (BPH) and a bypass via (BPV).

[0157] Each of the plurality of semiconductor chips (2200) may include a through-wire (3245) that is electrically connected to a plurality of peripheral wires (3110) of the first structure (3100) and extends into the second structure (3200). The through-wire (3245) may be positioned outside the gate stack (3210). In other exemplary embodiments, the semiconductor package (2003) may further include a through-wire that penetrates the gate stack (3210). Each of the plurality of semiconductor chips (2200) may further include an input / output pad (2210 of FIG. 14) that is electrically connected to a plurality of peripheral wires (3110) of the first structure (3100).

[0158] Although the present invention has been described in detail with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications and changes are possible by those skilled in the art within the technical spirit and scope of the present invention. Explanation of the symbols

[0159] 10, 100, 100-1a, 100-1b, 100-1c, 100-2a, 100-2b, 100-2c, 200, 300, 302, 400, 402: Integrated circuit element, PS peripheral circuit structure, PERI: Peripheral circuit region, CS: Cell array structure, MCR: Memory cell region, CON: Connection region, TVR: Through-electrode region, 50: Substrate, 42: Diode ion implantation region, D40: Antenna diode, 62: Source / drain region, 70: Peripheral circuit wiring structure, 72: Peripheral circuit contact, 74: Peripheral circuit wiring layer, 74N: Cover contact layer, 80: Interlayer insulating film, 82: First interlayer insulating layer, 84: Passivation layer, 86: Second interlayer insulating layer, 90, 90a, 90b: Barrier layer, 92: First barrier layer, 94: Second barrier layer, 92N, 96: Cover layer, BPH, BPHa: Bypass hole, BPV, BPVa, BPVb: Bypass via, 110: Base structure, 110S: Base substrate, 110L: Lower base layer, 110U: Upper base layer, 112: Insulating plate, 120: Base insulating layer, 120H: Opening, GS1: First gate stack, GS2: Second gate stack, 160: Channel structure

Claims

Claim 1 An integrated circuit device comprising: a substrate, a peripheral circuit wiring structure disposed on the substrate and including bypass vias, and an interlayer insulating film covering at least a portion of the peripheral circuit wiring structure; a cell array structure overlapping perpendicularly with the peripheral circuit structure on the peripheral circuit structure and comprising a base substrate, a plurality of gate lines disposed on the base substrate, and a plurality of channel structures penetrating the plurality of gate lines; and a barrier layer interposed between the peripheral circuit structure and the cell array structure, having a bypass hole that is filled with the bypass vias and penetrates from the upper surface to the lower surface; wherein at least a portion of the barrier layer and at least a portion of the base substrate form a structure in which a conductive material layer, an insulating material layer, a semiconductor material layer, an insulating material layer having an ONO structure, and a semiconductor material layer are sequentially stacked. Claim 2 An integrated circuit device according to claim 1, comprising: a plurality of conductive lines spaced apart from the barrier layer with the cell array structure in between; a plurality of base insulating layers filling a plurality of openings penetrating the base substrate and the barrier layer; and a plurality of penetrating electrodes penetrating the cell array structure and the plurality of base insulating layers, connecting the plurality of conductive lines and the peripheral circuit wiring structure, and spaced apart from the barrier layer with the plurality of base insulating layers in between. Claim 3 An integrated circuit device according to claim 1, further comprising: a bypass via being integral with at least a portion of the base substrate; a portion of the barrier layer being made of the same material as at least a portion of the base substrate and covering at least a portion of the barrier layer; and a cover layer being interposed between at least a portion of the barrier layer and the bypass via and being made of a nitride, an oxide, a nitride including a metal, or a metal silicide. Claim 4 An integrated circuit device according to claim 3, wherein the barrier layer is characterized by having a stacked structure comprising a first barrier layer covering the interlayer insulating film and comprising a conductive material layer, and a second barrier layer covering the first barrier layer and comprising an insulating material layer. Claim 5 An integrated circuit device according to claim 3, wherein the cover layer covers the upper surface of the barrier layer and the side and bottom surfaces within the bypass hole. Claim 6 An integrated circuit device comprising: a substrate; a peripheral circuit wiring structure disposed on the substrate and including peripheral circuit contacts, a peripheral circuit wiring layer, and bypass vias; and an interlayer insulating film covering the peripheral circuit contacts and the peripheral circuit wiring layer; a cell array structure overlapping vertically with the peripheral circuit structure on the peripheral circuit structure and including a substrate layer, a plurality of gate lines disposed on the substrate layer, and a plurality of channel structures through which the plurality of gate lines penetrate; a barrier layer interposed between the peripheral circuit structure and the cell array structure and having a stacked structure of a first barrier layer covering the interlayer insulating film and a second barrier layer covering the first barrier layer, wherein the peripheral circuit wiring layer is exposed on the bottom surface and a bypass hole filled with the bypass vias is provided; and a cover layer interposed between the first barrier layer and the bypass vias; wherein the substrate layer and the bypass vias are integrally formed from the same material. Claim 7 An integrated circuit device according to claim 6, wherein the cover layer is interposed between the first barrier layer and the bypass via, and is not interposed between the second barrier layer and the bypass via, and wherein the substrate layer, the bypass via, and the first barrier layer are each made of a semiconductor material, and the second barrier layer and the cover layer are each made of a nitride or an oxide. Claim 8 An integrated circuit device according to claim 6, wherein the cover layer extends from between the first barrier layer and the bypass via to the upper surface of the second barrier layer, and the cover layer is composed of a metal-containing nitride or a metal silicide. Claim 9 A peripheral circuit structure comprising a peripheral circuit transistor disposed on a substrate, a peripheral circuit wiring structure electrically connected to the peripheral circuit transistor and including a peripheral circuit contact, a peripheral circuit wiring layer, and a bypass via, and an interlayer insulating film surrounding the peripheral circuit contact and the peripheral circuit wiring layer; a cell array structure comprising a substrate layer, a lower base layer, and an upper base layer sequentially stacked and overlapping vertically with the peripheral circuit structure on the peripheral circuit structure, a plurality of gate lines disposed on the upper base layer, and a plurality of channel structures filling a plurality of channel holes penetrating the plurality of gate lines; and a barrier layer interposed between the peripheral circuit structure and the cell array structure, comprising a stacked structure of a first barrier layer covering the interlayer insulating film and a second barrier layer covering the first barrier layer, wherein the peripheral circuit wiring layer is exposed on the bottom surface and the barrier layer has a bypass hole filled with the bypass via, which is integrally formed with the same material as the substrate layer. An integrated circuit device comprising: a cover layer interposed between the bypass via and the first barrier layer; a plurality of base insulating layers filling a plurality of openings penetrating the substrate layer and the barrier layer; a plurality of conductive lines disposed on the cell array structure; and a plurality of through electrodes penetrating the cell array structure and the plurality of base insulating layers, connecting the plurality of conductive lines and the peripheral circuit wiring structure, and spaced apart from the barrier layer while having the plurality of base insulating layers in between. Claim 10 An integrated circuit device according to claim 9, wherein the plurality of channel structures comprises a gate insulating layer and a channel layer sequentially disposed on the sidewalls within the plurality of channel holes, the gate insulating layer is composed of a sidewall portion and a bottom portion disposed spaced apart from each other, and the channel layer contacts the lower base layer through the sidewall portion and the bottom portion of the gate insulating layer spaced apart from each other.

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