Semiconductor device manufacturing method

Abstract

A method for manufacturing a semiconductor device is provided by embodiments of the technical concept of the present invention. The method for manufacturing a semiconductor device comprises the steps of: providing a first layer having a first surface and a second layer having a second surface perpendicular to the first surface; forming an inhibitor layer conformally on the first surface and the second surface; selectively removing the inhibitor layer on the second surface among the first surface and the second surface to expose the second surface; and forming a layer of interest on the exposed second surface, wherein the step of exposing the second surface may include selectively removing an edge portion of the inhibitor layer on the first surface that contacts the second surface.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a semiconductor device, and specifically to a method for manufacturing a semiconductor device using selective detachment. Background Technology

[0002] Due to the rapid development of the electronics industry and user demands, electronic devices are becoming smaller and lighter. Consequently, there is a demand for semiconductor devices with high integration density used in electronic devices, and design rules for the configuration of semiconductor devices are decreasing. The problem to be solved

[0003] The technical problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor device with improved performance and reliability.

[0004] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0005] A method for manufacturing a semiconductor device is provided by embodiments of the technical concept of the present invention. The method for manufacturing a semiconductor device comprises the steps of: providing a first layer having a first surface and a second layer having a second surface perpendicular to the first surface; forming an inhibitor layer conformally on the first surface and the second surface; selectively removing the inhibitor layer on the second surface among the first surface and the second surface to expose the second surface; and forming a layer of interest on the exposed second surface, wherein the step of exposing the second surface may include selectively removing an edge portion of the inhibitor layer on the first surface that contacts the second surface.

[0006] A method for manufacturing a semiconductor device is provided by embodiments of the technical concept of the present invention. The method for manufacturing a semiconductor device comprises the steps of: performing a pretreatment process on a first surface of a first layer; forming an inhibitor layer on the first surface and a second surface of a second layer; selectively removing the inhibitor layer on the second surface among the first surface and the second surface to expose the second surface; and forming a layer of interest on the exposed second surface, wherein the first layer comprises a metal nitride and the second layer may not comprise a metal nitride.

[0007] A method for manufacturing a semiconductor device is provided by embodiments of the technical concept of the present invention. The method for manufacturing a semiconductor device comprises the steps of: pre-treating a first surface of a metal nitride layer with H2 plasma; forming a first inhibitor layer on the first surface; forming a second inhibitor layer on a second surface of a gap-fill insulating layer that is orthogonal to the first surface in a direction perpendicular to the first surface; selectively removing the second inhibitor layer among the first inhibitor layer and the second inhibitor layer through a heat treatment process to expose a first portion of the second surface and the first surface; and forming a layer of interest on the second surface and the first portion of the first surface, wherein the first portion of the first surface may include a portion of the second inhibitor layer that is in contact with the first surface and the second surface. Effects of the invention

[0008] By embodiments of the technical concept of the present invention, a method for manufacturing a semiconductor device with improved performance and reliability can be provided. Brief explanation of the drawing

[0009] FIGS. 1a to 1c are flowcharts for explaining a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 2 to 8 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 9a, FIGS. 9b, FIGS. 10, and FIGS. 11 are graphs showing experimental data of one embodiment to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 12 and 13 are schematic diagrams relating to a pretreatment process to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 14, FIGS. 15a, FIGS. 15b, FIGS. 15c, and FIGS. 15d are graphs showing experimental data regarding a pretreatment process to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 16a and FIGS. 16b are graphs showing experimental data of one embodiment to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 17 to 24 are schematic diagrams relating to a wet etching process and drawings relating to electron microscope observation results to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. FIGS. 25, FIGS. 26a to 26c are graphs showing experimental data of one embodiment to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. Specific details for implementing the invention

[0010] Hereinafter, embodiments of the technical concept of the present invention will be described in detail with reference to the attached drawings.

[0011] FIGS. 1a to 1c are flowcharts for explaining a method for manufacturing a semiconductor device (S100a, S100b, S100c) according to embodiments of the technical concept of the present invention. FIGS. 2 to 8 are cross-sectional views for explaining a method for manufacturing a semiconductor device (S100a, S100b, S100c) according to embodiments of the technical concept of the present invention.

[0012] Referring to FIG. 1a and FIG. 2, a first layer (100) and a second layer (200) can be provided (S110).

[0013] The first layer (100) may be a metal nitride layer. That is, the first layer (100) may include, for example, titanium nitride (TiN) and / or titanium aluminum nitride (TiAlN). The second layer (200) may be a gap filling insulating film (GFIL). The second layer (200) may be, for example, a dry etch resistance layer, a wet etch resistance layer, or a photoresist layer, but is not limited thereto.

[0014] A second layer (200) is formed on a first surface (100S) of a first layer (100). A portion of the first surface (100S) of the first layer (100) is in contact with the second layer (200), and another portion of the first surface (100S) of the first layer (100) may be exposed by the second layer (200). For example, the second layer (200) may include a first sublayer (210) and a second sublayer (220). Although not illustrated, the first sublayer (210) and the second sublayer (220) may be formed by etching the second layer (200) in a vertical direction (D2). The first sublayer (210) may be a first gap-fill insulation pattern, and the second sublayer (220) may be a second gap-fill insulation pattern.

[0015] The first sublayer (210) and the second sublayer (220) may be spaced apart from each other in the horizontal direction (D1). As the first sublayer (210) and the second sublayer (220) are spaced apart, the first surface (100S) of the first layer (100) may be exposed. The first sublayer (210) includes a second surface (210S). The second surface (210S) of the first sublayer (210) may face the second sublayer (220). The second sublayer (220) includes a second surface (220S). The second surface (220S) of the second sublayer (220) may face the first sublayer (210). That is, the second surface (210S) of the first sublayer (210) and the second surface (220S) of the second sublayer (220) may face each other.

[0016] That is, the first surface (100S) can be extended in a horizontal direction (D1), and the second surface (200S) can be extended in a vertical direction (D2). The first surface (100S) and the second surface (200S) can be orthogonal to each other in a vertical direction.

[0017] The second layer (200) may contain an acid precursor. That is, when a stimulus such as heat, light, or electromagnetic waves is applied to the second layer (200), the second layer (200) may emit acid or hydrogen cations. The second layer (200) may emit a substance containing acid or hydrogen cations.

[0018] Referring to FIG. 1a and FIG. 3, an inhibitor layer (300) can be formed on the first surface (100S) of the first layer (100) and the second surface (200S) of the second layer (200) (S120).

[0019] The inhibitor layer (300) may be formed conformally on the first surface (100S) of the first layer (100) and the second surface (200S) of the second layer (200), but is not limited thereto. The formation of the inhibitor layer (300) may be carried out under temperature conditions of 80°C or higher and 240°C or lower. The time required to form the inhibitor layer (300) may be at least 1 minute and at most 20 minutes. However, the technical concept of the present invention is not limited thereto, and the temperature and the time required to form the inhibitor layer (300) may vary depending on process conditions and circumstances.

[0020] The inhibitor layer (300) may include a first inhibitor layer (310) and a second inhibitor layer (320). The first inhibitor layer (310) may be formed on a first surface (100S). The first inhibitor layer (310) may extend in a horizontal direction (D1) along the first surface (100S). The second inhibitor layer (320) may be formed on a second surface (200S). The second inhibitor layer (320) may extend in a vertical direction (D2) along the second surface (200S).

[0021] In some embodiments, the inhibitor layer (300) may include a first portion (311). The first portion (311) may be a portion that is in contact with both the first surface (100S) and the second surface (200S) at the point where the first surface (100S) and the second surface (200S) intersect. For example, the first portion (311) may include an edge portion of the inhibitor layer formed on the first surface (100S). In some embodiments, the first portion (311) may be formed on the second portion (100S2) of the first surface (100S). That is, the inhibitor layer (300) may include a first inhibitor layer (310) in contact only with the first surface (100S), a second inhibitor layer (320) in contact only with the second surface (200S), and a first portion (311) in contact with both the first surface (100S) and the second surface (200S). The first portion (311) may be a portion of the inhibitor layer formed on the first surface (100S) that is adjacent to the second surface (200S). The first portion (311) may include a portion of the inhibitor layer formed on the second surface (200S) that is adjacent to the first surface (100S).

[0022] In the illustrated embodiments, the boundary line (indicated by a dotted line) between the first inhibitor layer (310) and the second inhibitor layer (320) of the first part (311) is shown to be perpendicular to the first surface (100S) and the second surface (200S), but this is merely illustrative. In other embodiments, the boundary line may be at an angle rather than perpendicular to the first surface (100S) and the second surface (200S). In other embodiments, the boundary line may be curved rather than straight. That is, the shape of the first part (311) is not limited to being a rectangle as illustrated, but can have any shape that simultaneously contacts the first surface (100S) and the second surface (200S). Accordingly, the first inhibitor layer (310) and the second inhibitor layer (320), separated by the boundary line with the first part (311), can also have various shapes not limited to being illustrated.

[0023] The inhibitor layer (300) may include a substance that dissociates by acid or hydrogen cations. The inhibitor layer (300) may include a protecting group that dissociates by acid.

[0024] In some embodiments, the inhibitor layer (300) may include a material that binds strongly to the first layer (100). In some embodiments, the inhibitor layer (300) may include a material that binds with high selectivity to the first layer (100). In some embodiments, the inhibitor layer (300) may include a material that binds strongly to the first layer (100) while binding weakly to the second layer (200).

[0025] Specifically, the inhibitor layer (300) may include a benzene ring. That is, the inhibitor layer (300) may include a substance in which various functional groups are chemically bonded to a benzene ring. For example, the inhibitor layer (300) is 4-trifluoromethyl benzaldehyde (4-TFBA), 3,5-bis(trifluoromethyl)aniline, benzaldehyde, 4-trifluoromethyl aniline, aniline, benzene, 3-trifluoromethyl benzaldehyde, 4-trifluoromethyl acetophenone, 3,5-bis(trifluoromethyl)acetophenone, 3-trifluoromethyl acetophenone, 3-trifluoromethyl benzonitrile, It may include at least one of 4-fluorotoluene, 3-fluorophenylacetylene, 4-trifluoromethyl benzoyl chloride, and 4-methylthioaniline, but is not limited thereto.

[0026] Referring to FIG. 1a and FIG. 4, the inhibitor layer (300) on the second surface (200S) of the second layer (200) can be selectively removed to expose the second surface (200S) (S130).

[0027] In some embodiments, a portion of the inhibitor layer (300) on the second surface (200S) can be selectively removed through a heat treatment process. Specifically, the inhibitor layer (300) in contact with the second surface (200S) can be selectively removed through the heat treatment process. For example, the second inhibitor layer (320) and the first portion (311) in contact with the second surface (200S) can be removed through the heat treatment process.

[0028] In some embodiments, a portion of the inhibitor layer (300) may not be removed through the heat treatment process. Specifically, the first inhibitor layer (310) may not be removed through the heat treatment process. That is, the first inhibitor layer (310) that is in contact only with the first surface (100S) may not be removed through the heat treatment process.

[0029] In some embodiments, the inhibitor layer (300) on the second surface (200S) may be selectively removed through the heat treatment process so that the second surface (200S) is exposed. Specifically, the second surface (200S) may be fully exposed as the second inhibitor layer (320) and the first portion (311) in contact with the second surface (200S) are removed through the heat treatment process.

[0030] In some embodiments, the first inhibitor layer (310) in contact only with the first surface (100S) may not be removed through the heat treatment process, but a portion of the first surface (100S) may be exposed as the first portion (311) in contact with the first surface (100S) and the second surface (200S) is removed. For example, a second portion (100S2) of the first surface (100S) may be exposed.

[0031] In some embodiments, the heat treatment process may be carried out under temperature conditions of 200°C or higher and 250°C or lower. In some embodiments, the heat treatment process may be carried out for a time of at least 1 minute. When the heat treatment process is performed on the inhibitor layer (300), the first inhibitor layer (310) on the first surface (100S) is not removed, and the second inhibitor layer (320) and the first portion (311) on the second surface (200S) may be removed. That is, through the heat treatment process, only the second inhibitor layer (320) and the first portion (311) in contact with the second surface (200S) may be selectively removed due to the different physical properties of the first layer (100) and the second layer (200).

[0032] For example, when a heat treatment process is performed, hydrogen cations (H) in the second layer (200) + Hydrogen cations are emitted. The emitted hydrogen cations can react with the second inhibitor layer (320) on the second surface (200S). Since the second inhibitor layer (320) contains a substance that dissociates by acid, if the second inhibitor layer (320) reacts with hydrogen cations, the second inhibitor layer (320) may dissociate. On the other hand, even if a heat treatment process is performed, hydrogen cations are not generated within the first layer (100). Accordingly, the first inhibitor layer (310) is not removed. In the case of the first portion (311), one side is located in contact with the first surface (100S), while the other side is located in contact with the second surface (200S). Therefore, hydrogen cations (H) emitted within the second layer (200) + It can be dissociated by ).

[0033] Referring to FIG. 1a and FIG. 5, a layer of interest (400) can be formed on the second surface (200S) of the second layer (200) (S140).

[0034] In some embodiments, the layer of interest (400) may be deposited on a second surface (200S). For example, the layer of interest (400) may be deposited using Chemical Vapor Deposition (CVD). For example, the layer of interest (400) may be deposited using Atomic Layer Deposition (ALD). The layer of interest (400) may include a first layer of interest (401) in contact with the first surface (100S) and a second layer of interest (402) in contact only with the second surface (200S). That is, the layer of interest (400) may be deposited on the second surface (200S) and simultaneously deposited on a portion of the first surface (100S).

[0035] As described above, as the first portion (311) in contact with the first surface (100S) and the second surface (200S) is removed, a portion of the first surface (100S) may be exposed. For example, a second portion (100S2) of the first surface (100S) may be exposed. A second layer of interest (402) may be deposited on the exposed second portion (100S2) of the first surface (100S).

[0036] The layer of interest (400) may include organic and inorganic materials. Specifically, it may include various materials capable of a deposition process (e.g., CVD, ALD) at a temperature range in which a heat treatment process is performed on the inhibitor layer (300), i.e., about 200°C to about 250°C. For example, the layer of interest (400) may include tantalum nitride, aluminum oxide, hafnium oxide, niobium oxide, silicon oxide, etc. In some other embodiments, depending on the temperature and environment of the heat treatment process, the layer of interest (400) may include other materials not mentioned above.

[0037] Referring to FIG. 1b, prior to the step (S120) of forming an inhibitor layer (300) on the first surface (100S) of the first layer (100) and the second surface (200S) of the second layer (200), a pretreatment process may be performed on the first surface (100S) of the first layer (100) (S111). Specifically, the steps of treating the first surface (100S) of the first layer (100) with an aqueous HF solution, treating the first surface with an H2 plasma, and / or treating the first surface with an NH3 plasma may be performed.

[0038] The selectivity of the subsequent film formed on the first surface (100S) of the first layer (100) and the second surface (200S) of the second layer (200) can be increased by the above pretreatment process. A detailed explanation of the pretreatment process will be provided with reference to FIGS. 12 to 15.

[0039] In some embodiments, the steps of FIGS. 4 and FIGS. 5 may be performed through the same process. That is, the step of selectively removing the inhibitor layer (300) on the second surface (200S) (S130) and the step of forming the layer of interest (400) on the second surface (200S) (S140) may be performed through the same process. For example, the second inhibitor layer (320) and the first portion (311) on the second surface (200S) may be removed by performing a heat treatment process during the process of forming the layer of interest (400). That is, a separate heat treatment process for removing the second inhibitor layer (320) and the first portion (311) on the second surface (200S) may not be performed.

[0040] Referring further to FIG. 1c and FIG. 6, the step of removing the first inhibitor layer (310) to expose the first surface (100S) may be further performed (S150).

[0041] In some embodiments, acid treatment may be used to remove the first inhibitor layer (310). As described above, the first inhibitor layer (310) may contain a substance capable of dissociating by acid or hydrogen cations, so the first inhibitor layer (310) can be removed by acid treatment.

[0042] When the first inhibitor layer (310) is removed, the first surface (100S) of the first layer (100) on which the first inhibitor layer (310) was formed may be exposed. Specifically, a portion of the first surface (100S) may be exposed. For example, a portion of the first surface (100S) where the layer of interest (400) is not formed may be exposed. For example, a portion excluding the second portion (100S2) of the first surface (100S) may be exposed.

[0043] Referring further to FIG. 1c and FIG. 7, a step of etching the first layer (100) exposed through the first surface (100S) may be further performed (S160).

[0044] In some embodiments, the first layer (100) exposed through the first surface (100S) can be etched using a wet etching process. The first layer (100) can be etched to form a first trench (100T).

[0045] Referring further to FIG. 8, the layer of interest (400) can be removed so that the second surface (200S) of the second layer (200) is exposed. That is, the layer of interest (400) can be removed so that the second trench (200T) is exposed.

[0046] In some embodiments, the degree to which the first layer (100) is etched, i.e., the width (L1) of the first trench (100T), may be smaller than the degree to which the sublayers (210, 220) of the second layer (200) are spaced apart, i.e., the width (L2) of the second trench (200T). That is, the first trench (100T) may be formed in an area narrower than the second trench (200T).

[0047] In some embodiments, as shown in FIGS. 2 to 5, as the inhibitor layer (311) of a portion of the first surface (100S) of the first layer (100) (i.e., the second portion (100S2)) is removed, a first layer of interest (401) may be formed on the second portion (100S2). By doing so, when the first layer (100) is etched to form a first trench (100T) in the subsequent process of FIGS. 6 to 8, a first trench (100T) of narrow width may be formed. If the first layer of interest (401) is not formed on the second portion (100S2), the first surface (100S) in FIG. 6 may be completely exposed and a trench of the intended width may not be formed.

[0048] In some embodiments, the steps illustrated in FIGS. 6 through 8 may be performed through the same process. For example, as a wet etching process is performed to etch the first layer (100), the first inhibitor layer (310) that can be dissociated by acid is removed, the exposed first layer (100) is etched to form the first trench (100T), and the layer of interest (400) may be removed. That is, a separate acid treatment process for removing the first inhibitor layer (310) and the layer of interest (400) may not be performed separately. This will be described in detail later with reference to FIGS. 11, FIGS. 17 through 24.

[0049] FIGS. 9a, FIGS. 9b, FIGS. 10, and FIGS. 11 are graphs showing experimental data of one embodiment to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention.

[0050] FIGS. 9a and 9b are graphs for confirming the degree to which the inhibitor layer (300) is bonded to the second layer (200) when heat treatment is performed. Specifically, 4-TFBA is applied to the gap-fill insulating layer, and the graphs are for confirming the FC peak at temperatures of about 200°C, about 240°C, and about 250°C.

[0051] Referring to Figures 9a and 9b, the FC peak is observed to be largest at approximately 200°C, but it can be seen that the FC peak is reduced at temperatures of approximately 240°C and approximately 250°C. In other words, it can be confirmed that 4-TFBA was desorbed from the surface of the gap-fill insulating layer due to heat treatment. It can be expected that hydrogen cations were released from the gap-fill insulating layer due to heat treatment, causing the 4-TFBA on the gap-fill insulating layer to dissociate and be desorbed. In particular, at a temperature of approximately 250°C, it can be seen that the FC peak is almost similar to that of the gap-fill insulating layer without 4-TFBA applied, and therefore it can be expected that the 4-TFBA was completely desorbed.

[0052] FIG. 10 is a graph to confirm that the inhibitor layer (300) maintains a bonded state on the first layer (100) even after heat treatment. Specifically, 4-TFBA is applied to the TiN surface, and the graphs are to confirm the FC peak at temperatures of about 200°C and about 240°C.

[0053] Referring to Figure 10, it can be seen that the size of the FC peak hardly decreases regardless of temperature, and that the size of the FC peak increases compared to the case of TiN without 4-TFBA coating. This confirms that 4-TFBA is strongly bound to TiN even after heat treatment.

[0054] Figure 11 is a graph to confirm whether the inhibitor layer is dissociated and detached by acid, as predicted from the previous experimental results. Specifically, it is a graph to confirm the FC peak when the TiN surface to which 4-TFBA is bound is acid-treated.

[0055] Referring to Figure 11, a large FC peak size is observed for the TiN surface bound to 4-TFBA, whereas a decrease in the FC peak size is observed when the surface is acid-treated with a 0.6% acetic acid solution. In particular, when acid-treated for 5 minutes, the FC peak size is slightly reduced compared to when acid-treated, whereas when acid-treated for 30 minutes, the FC peak size is significantly reduced.

[0056] In other words, the experimental results in Figs. 9a, 9b, 10, and 11 confirm that 4-TFBA is strongly bound to the surface of TiN, whereas it is desorbed from the surface of the gap-fill insulating layer by heat treatment. That is to say, it can be confirmed that 4-TFBA has high selectivity for TiN. Furthermore, it can be confirmed that the high selectivity of 4-TFBA for TiN is due to 4-TFBA dissociating and desorbing when exposed to acid.

[0057] Additionally, since 4-TFBA bonded to the TiN surface is detached when further acid treatment is performed, when a wet etching process including acid treatment is performed in a subsequent process for manufacturing a semiconductor device according to the technical concept of the present specification, a separate acid treatment process to remove 4-TFBA may not be required.

[0058] FIGS. 12 and 13 are schematic diagrams relating to a pretreatment process to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. Specifically, FIGS. 12 and 13 are schematic diagrams illustrating whether an inhibitor layer (300) and a layer of interest (400) are formed and the degree of formation when the pretreatment process (P1, P2) is performed and when it is not performed.

[0059] Referring to FIG. 12, a pretreatment process (P1) can be performed on the first surface (100S) of the first layer (100). The pretreatment process (P1) may include, for example, a process of treating the first surface (100S) of the first layer (100) with H2 plasma.

[0060] As shown in FIG. 12 (a), (b) and (c), when an inhibitor layer (300) and a layer of interest (400) are applied after performing a pretreatment process (P1) on a first surface (100S), the coverage of the inhibitor layer (300) is high enough to completely cover the first surface (100S) and inhibit the formation of the layer of interest (400) by the inhibitor layer (300).

[0061] Referring to FIG. 13, a pretreatment process (P2) can be performed on the first surface (100S) of the first layer (100). The pretreatment process (P2) may include, for example, a process of treating the first surface (100S) of the first layer (100) with an aqueous HF solution or a process of treating it with NH3 plasma.

[0062] As illustrated in FIG. 13 (a), (b) and (c), when an inhibitor layer (300) and a layer of interest (400) are applied after performing a pretreatment process (P2) on a first surface (100S), the coverage of the inhibitor layer (300) is low, so it cannot completely cover the first surface (100S), and therefore the formation of the layer of interest (400) cannot be completely suppressed. Specifically, the inhibitor layer (300a) may be formed in a part of the first surface (100S), and the layer of interest (400a) may be formed in another part of the first surface (100S) that is not covered by the inhibitor layer (300a).

[0063] FIGS. 14, FIGS. 15a, FIGS. 15b, FIGS. 15c, and FIGS. 15d are graphs showing experimental data regarding a pretreatment process to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention.

[0064] Figure 14 is a graph to confirm the FC peak and F-Ti peak when an inhibitor layer is deposited after a pretreatment process. Specifically, it is a graph to confirm the FC peak and F-Ti peak when an inhibitor layer is deposited on TiN pretreated with an aqueous HF solution, NH3 plasma, and H2 plasma at a temperature of about 250°C.

[0065] Referring to Figure 14, it can be seen that the sizes of the FC peak and F-Ti peak differ depending on the pretreatment process.

[0066] Specifically, it can be observed that the size of the F-Ti peak when no inhibitor layer is deposited decreases in the order of pretreatment with an aqueous HF solution, pretreatment with NH3 plasma, no pretreatment process (blank), and pretreatment with H2 plasma. In other words, it can be predicted that F-Ti groups are formed on the TiN surface when pretreated with an aqueous HF solution and when pretreated with NH3 plasma. On the other hand, it can be predicted that F-Ti groups present before the pretreatment process are removed when pretreated with H2 plasma.

[0067] Next, looking at the size of the FC peak, it can be seen that it decreases in the order of pretreatment with H2 plasma, pretreatment with NH3 plasma, and pretreatment with an aqueous HF solution. In other words, it can be seen that the degree of inhibitor layer deposition on the TiN surface follows the reverse order of the F-Ti peak sizes observed earlier.

[0068] Through this, it can be seen that pre-treating the surface of TiN using H2 plasma is a more appropriate pre-treatment method, but the technical concept of the present invention is not limited thereto and may also include cases where pre-treated with NH3 plasma and cases where pre-treated with an aqueous HF solution.

[0069] The results of Figure 14 were quantified and shown in Table 1 below.

[0070]

[0071] FIGS. 15a to 15d are graphs for confirming FC peaks and F-Ti peaks depending on the presence of an inhibitor layer when a layer of interest is formed after a pretreatment process. Specifically, these are graphs for confirming FC peaks and F-Ti peaks depending on the presence of an inhibitor layer when PDMAT (Pentakis(dimethylamino)tantalum(V)) is applied to TiN pretreated with an aqueous HF solution, NH3 plasma, and H2 plasma at a temperature of about 250°C to form a layer of interest (e.g., TaN). The results after the PDMAT application process was carried out for 5, 10, 20, and 40 cycles, respectively, are shown in FIGS. 15a to 15d.

[0072] Referring to FIGS. 15a to 15d, the extent to which the inhibitor layer formed on the TiN surface inhibits the formation of the layer of interest can be confirmed by comparing the peak sizes when the inhibitor layer is present and when it is absent. It can be confirmed that the extent to which the inhibitor layer formed on the TiN surface inhibits the formation of the layer of interest decreases in the order of pretreatment with H2 plasma, pretreatment with NH3 plasma, and pretreatment with an aqueous HF solution. In other words, it can be confirmed that the inhibitor layer's performance in inhibiting the formation of the layer of interest is proportional to the size of the FC peak in FIG. 14, that is, the degree of deposition of the inhibitor layer.

[0073] The results of Figures 15a to 15d were quantified and are shown in Table 2 below.

[0074]

[0075] Referring to Table 1, it can be seen that the size of the Ti-F peak on the TiN surface after the pretreatment process is inversely proportional to the degree of adsorption of the inhibitor layer, i.e., the size of the FC peak. Additionally, referring to Table 2, it can be confirmed that the inhibition performance of the inhibitor layer has a selectivity of 25 or higher up to 20 cycles when pretreated with H2 plasma, a selectivity of approximately 1.9 or higher when pretreated with an aqueous HF solution, and a selectivity of approximately 3.8 or higher when pretreated with NH3 plasma. Even at 40 cycles, it can be confirmed that a high selectivity of approximately 7.7 or higher is maintained when pretreated with H2 plasma.

[0076] FIGS. 16a and 16b are graphs showing experimental data of one embodiment to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. Specifically, FIGS. 16a and 16b are graphs to confirm that when an inhibitor layer is deposited on a TiN surface and a gap-fill insulating film surface at a temperature of about 240°C and then a layer of interest is applied, results similar to those obtained at a temperature of about 250°C are obtained.

[0077] Referring to Fig. 16a, it can be seen that the peak size is significantly reduced when PDMAT is applied after depositing an inhibitor layer on the TiN surface, but referring to Fig. 16b, it can be seen that the peak size is not reduced even when PDMAT is applied after depositing an inhibitor layer on the surface of the gap-fill insulating layer. In other words, similar to the results of the previous experiment conducted at a temperature of about 250°C, it can be confirmed that the inhibitor layer is deposited on the TiN surface with high selectivity, thereby suppressing the formation of the subsequent layer of interest.

[0078] FIGS. 17 to 24 are schematic diagrams relating to a wet etching process and drawings relating to electron microscope observation results to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention.

[0079] Referring to Fig. 17, TiN is removed by a wet etching process. When referring to the electron microscope observation results in Fig. 18, it can be confirmed that TiN is removed. In particular, it can be confirmed that TiN is removed without any wet delay.

[0080] Referring to Fig. 19, TiN and TaN applied on TiN are removed by a wet etching process. When referring to the electron microscope observation results in Fig. 20, it can be confirmed that TiN and TaN are removed. In particular, it can be confirmed that TiN is removed without any etching delay phenomenon while leaving no TaN residue.

[0081] Referring to Fig. 21, the gap-fill insulating layer applied to TiN and TiN is removed by a wet etching process. When referring together with the electron microscope observation results of Fig. 22, it can be confirmed that the gap-fill insulating layer applied to TiN and TiN is removed.

[0082] Referring to FIG. 23, the gap-fill insulating layer applied on TiN and TaN on the gap-fill insulating layer are removed by the wet etching process, while TiN is not removed. When referring to the electron microscope observation results in FIG. 24, it can be confirmed that the gap-fill insulating layer and TaN on the gap-fill insulating layer are removed, while TiN remains on the substrate. That is, it can be confirmed that no TaN residue remains, and at the same time, TiN is not removed due to the etching delay phenomenon.

[0083] As can be seen from FIGS. 17 to 24, the TiN and TaN formed on the substrate do not require a separate removal process and are removed by a wet etching process for etching TiN.

[0084] FIGS. 25, 26a to 26c are graphs showing experimental data of one embodiment to explain a method for manufacturing a semiconductor device according to embodiments of the technical concept of the present invention. Specifically, FIGS. 25, 26a to 26c are graphs to confirm the performance of inhibiting the formation of a subsequent layer of interest when 3,5-Bis(trifluoromethyl)aniline (BTFMA) having a benzene ring is used as an inhibitor layer.

[0085] Referring to Fig. 25, it can be seen that the FC peak is observed even when BTFMA is used as the inhibitor layer. That is, it can be seen that BTFMA is deposited on the TiN surface.

[0086] Referring to FIGS. 26a to 26c, it can be seen that the binding of the subsequent layer of interest (PDMAT) is reduced when BTFMA is present.

[0087] That is, through the experimental results of FIGS. 25 and FIGS. 26a to 26c, it can be seen that BTFMA has the ability to strongly bind to the TiN surface and suppress the formation of a subsequent layer of interest.

[0088] In some embodiments, a subsequent layer of interest may be deposited on a wafer that has undergone a pretreatment process and a deposition process of an inhibitor layer. Specifically, the subsequent layer of interest may include tantalum nitride, aluminum oxide, hafnium oxide, niobium oxide, and silicon oxide. In the embodiments, experiments were performed to measure the performance of the inhibitor layer according to the type of layer of interest in Experimental Examples 1 through 4.

[0089] In the first experimental example, PDMAT was used as a precursor to deposit tantalum nitride (TaN) as a subsequent layer of interest. It was confirmed that it has a selectivity ratio of about 25 or more depending on the presence or absence of an inhibitor layer.

[0090] In Experimental Example 2-1, a first aluminum precursor of small size was used as a precursor to deposit aluminum oxide as a subsequent layer of interest. The first aluminum precursor is, for example, 5 in the case of a monomer. Below, in the case of a dimer, the shorter portion is 4.5 Below, the long part is 7.5 It can have a diameter of . It was confirmed that it has a selectivity ratio of about 1.5 or higher depending on the presence or absence of an inhibitor layer.

[0091] In Experimental Example 2-2, an intermediate-sized second aluminum precursor was used as a precursor to deposit aluminum oxide as a subsequent layer of interest. The second aluminum precursor is, for example, 7 in the case of a monomer. Below, in the case of a dimer, the short part is 7 Below, the long part is 9 It can have a diameter of . It was confirmed that it has a selectivity ratio of about 1.5 or higher depending on the presence or absence of an inhibitor layer.

[0092] In Experimental Example 2-3, a large-sized third aluminum precursor was used as a precursor to deposit aluminum oxide as a subsequent layer of interest. The third aluminum precursor is, for example, 7.5 in the case of the monomer. Below, in the case of a dimer, 10 It can have a diameter of less than or equal to the following. It was confirmed that it has a selectivity ratio of approximately 7.7 or higher depending on the presence or absence of an inhibitor layer.

[0093] In the third experimental example, TEMAH (Tetrakis(ethylmethylamino)hafnium(IV)) was used as a precursor to deposit hafnium oxide as a subsequent layer of interest. It was confirmed that there was a selectivity ratio of approximately 8.3 or higher depending on the presence or absence of an inhibitor layer.

[0094] In the fourth experimental example, to deposit niobium oxide as a subsequent layer of interest, the monomer size as a precursor is 10 Niobium precursors with a lower value were used. It was confirmed that they have a selectivity ratio of approximately 3.8 or higher depending on the presence or absence of an inhibitor layer.

[0095] Although embodiments of the technical concept of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0096] 100: 1st layer, 100S: 1st surface, 200: 2nd layer, 200S: 2nd surface, 300: Inhibitor layer, 400: Layer of interest

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: providing a first layer having a first surface and a second layer having a second surface perpendicular to the first surface; forming an inhibitor layer conformally on the first surface and the second surface; selectively removing the inhibitor layer on the second surface among the first surface and the second surface to expose the second surface; and forming a layer of interest on the exposed second surface, wherein the step of exposing the second surface includes selectively removing an edge portion of the inhibitor layer on the first surface that contacts the second surface. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the inhibitor layer comprises a benzene ring. Claim 3 With respect to claim 2, the inhibitor layer comprises 4-trifluoromethyl benzaldehyde (4-TFBA), 3,5-bis(trifluoromethyl)aniline, benzaldehyde, 4-trifluoromethyl aniline, aniline, benzene, 3-trifluoromethyl benzaldehyde, 4-trifluoromethyl acetophenone, 3,5-bis(trifluoromethyl)acetophenone, 3-trifluoromethyl acetophenone, and 3-trifluoromethyl benzonitrile. A method for manufacturing a semiconductor device comprising at least one selected from 4-fluorotoluene, 3-fluorophenylacetylene, 4-trifluoromethyl benzoyl chloride, and 4-methylthioaniline. Claim 4 A method for manufacturing a semiconductor device according to claim 1, wherein the step of exposing the second surface exposes the entire second surface. Claim 5 A method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the layer of interest on the exposed second surface comprises forming a second portion in contact with the first surface and the second surface. Claim 6 A method for manufacturing a semiconductor device according to claim 1, wherein the step of selectively removing an inhibitor layer on the second surface among the first surface and the second surface to expose the second surface is characterized in that the center of the inhibitor layer on the first surface is not removed and the center does not come into contact with the second surface. Claim 7 A method for manufacturing a semiconductor device according to claim 1, wherein the first layer comprises at least one of titanium nitride and titanium aluminum nitride. Claim 8 A method for manufacturing a semiconductor device according to claim 1, wherein the second layer emits a substance containing acid or hydrogen cations upon stimulation. Claim 9 A method for manufacturing a semiconductor device according to claim 1, wherein the inhibitor layer is dissociated by a chemical reaction with a substance containing an acid or a hydrogen cation. Claim 10 A method for manufacturing a semiconductor device according to claim 1, wherein the layer of interest comprises at least one selected from tantalum nitride, aluminum oxide, hafnium oxide, silicon oxide, and niobium oxide.

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