Display apparatus

Abstract

The present invention provides a display device comprising: a substrate having a non-display area having a display area, a first area, a second area, a bending area disposed between the first area and the second area, and a pad area; a display unit disposed on the display area; a driving circuit unit disposed on the non-display area; and a fan-out unit that transmits a data signal applied from the driving circuit unit disposed on the first area, the bending area, and the second area between the display unit and the driving circuit unit to the display unit; wherein the fan-out unit comprises a first data line including a first-1 data line disposed on the second area and a first-2 data line disposed on the pad area but disposed on a layer different from the first-1 data line.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] Among display devices, organic light-emitting diodes (OLEDs) are attracting attention as next-generation display devices due to their advantages, including a wide viewing angle, excellent contrast, and fast response speed.

[0003] Generally, organic light-emitting display devices form thin-film transistors and organic light-emitting diodes on a substrate, and operate by the organic light-emitting diodes emitting light themselves. Such organic light-emitting display devices are used as display units for small products such as mobile phones, as well as for large products such as televisions.

[0004] A display device such as an organic light-emitting display device has a display portion located on a substrate and a fan-out portion with wiring extending to one side of the display portion. In such a display device, by bending at least a portion, visibility from various angles can be improved or the area of ​​the non-display area can be reduced. The problem to be solved

[0005] The present invention aims to provide a display device in which the non-display area is minimized and the luminescence uniformity between adjacent pixels is improved. However, this objective is exemplary and does not limit the scope of the present invention. means of solving the problem

[0006] According to one aspect of the present invention, a display device is provided, comprising: a substrate having a non-display area having a display area, a first area, a second area, a bending area disposed between the first area and the second area, and a pad area; a display unit disposed on the display area; a driving circuit unit disposed on the non-display area; and a fan-out unit that transmits a data signal applied from the driving circuit unit disposed on the first area, the bending area, and the second area between the display unit and the driving circuit unit to the display unit; wherein the fan-out unit comprises a first data line including a first-1 data line disposed on the second area and a first-2 data line disposed on the pad area and disposed on a layer different from the first-1 data line.

[0007] In the present embodiment, the first data line further includes a first-third data line disposed on the bending area, and the first-third data line may be disposed on a different layer from the first-second data line.

[0008] In this embodiment, the first-1 data line and the first-2 data line may be provided with different materials.

[0009] In the present embodiment, the fan-out portion may include a second data line comprising a second-1 data line disposed on the second region and a second-2 data line disposed on the pad region but on a layer different from the second-1 data line.

[0010] In this embodiment, the first-1 data line and the second-1 data line may be placed on the same layer.

[0011] In this embodiment, the first-2 data line and the second-2 data line may be placed on different layers.

[0012] In the present embodiment, the fan-out portion may further include a first fan-out portion, a second fan-out portion, and a spaced portion between the first fan-out portion and the second fan-out portion.

[0013] In the present embodiment, the first-1 data line and the first-2 data line can be electrically connected through a first contact hole located in the second area.

[0014] In this embodiment, the position of the first contact hole within the first fan-out portion may gradually move closer to or further away from the display portion.

[0015] In the present embodiment, the 2-1 data line and the 2-2 data line can be electrically connected through a second contact hole located in the second area.

[0016] In the present embodiment, regarding the second data line and the first data line arranged closest to each other with the aforementioned separation portion in between, the second contact hole that electrically connects the second-1 data line and the second-2 data line of the second data line may be located closer to the display part than the first contact hole that electrically connects the first-1 data line and the first-2 data line of the first data line.

[0017] In this embodiment, the display device can be folded around a folding axis.

[0018] According to another aspect of the present invention, a display device is provided comprising: a substrate having a non-display area having a display area, a first area, a second area, a bending area disposed between the first area and the second area, and a pad area; a display unit disposed on the display area; a driving circuit unit disposed on the non-display area; and a fan-out unit that transmits a data signal applied from the driving circuit unit disposed on the first area, the bending area, and the second area between the display unit and the driving circuit unit to the display unit; wherein the fan-out unit comprises a first-1 data line disposed on the second area and including a first part and a second part disposed on different layers, and a first-2 data line disposed on the pad area and including a first-2 data line disposed on the same layer as the first part or the second part.

[0019] In this embodiment, the same signal may be applied to the first part and the second part.

[0020] In this embodiment, the first part and the second part may overlap at least partially.

[0021] In the present embodiment, the first-2 data lines have a first width, and the first portion may have a second width greater than the first width.

[0022] In the present embodiment, the fan-out portion may include a second data line comprising a second-1 data line disposed on the second region and a second-2 data line disposed on the pad region but on a layer different from the second-1 data line.

[0023] In this embodiment, the second-2 data line may be placed on the same layer as the first part or the second part.

[0024] In this embodiment, the second-1 data line may overlap at least partially with the first part.

[0025] In this embodiment, a shielding layer interposed between the first-1 data line and the second-1 data line may be further included.

[0026] According to another aspect of the present invention, a display device that folds with respect to a folding axis is provided, comprising: a substrate having a non-display area having a display area, a first area, a second area, a bending area disposed between the first area and the second area, and a pad area; a display unit disposed on the display area; a driving circuit unit disposed on the non-display area; and a fan-out unit that transmits a data signal applied from the driving circuit unit disposed on the first area, the bending area, and the second area between the display unit and the driving circuit unit to the display unit; wherein the fan-out unit comprises a first data line including a first-1 data line and a first-2 data line disposed on different layers.

[0027] In the present embodiment, the first-1 data line is placed on the second area, and the first-2 data line can be placed on the pad area.

[0028] Other aspects, features, and advantages other than those described above will become clear from the specific details, claims, and drawings for implementing the invention below. Effects of the invention

[0029] According to one embodiment of the present invention as described above, a display device can be implemented in which the non-display area is reduced and the luminescence uniformity between adjacent pixels is improved. Of course, the scope of the present invention is not limited by these effects. Brief explanation of the drawing

[0030] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment. FIGS. 2a and FIGS. 2b are plan views schematically illustrating a display device according to one embodiment. FIGS. 3 and FIGS. 4 are equivalent circuit diagrams of pixels that may be included in a display device according to one embodiment. FIG. 5 is a cross-sectional view schematically illustrating a display device according to one embodiment. FIG. 6 is a schematic plan view illustrating a display device according to one embodiment. FIG. 7 is a schematic plan view illustrating a display device according to one embodiment. FIGS. 8 and FIGS. 9 are cross-sectional views schematically illustrating a display device according to one embodiment. FIGS. 10a to 10d are plan views schematically illustrating a display device according to one embodiment. FIG. 11 is a schematic plan view illustrating a display device according to one embodiment. FIG. 12 is a cross-sectional view schematically illustrating a display device according to one embodiment. FIG. 13 is a plan view schematically illustrating a display device according to one embodiment. FIGS. 14 and FIGS. 15 are cross-sectional views schematically illustrating a display device according to one embodiment. FIG. 16 is a cross-sectional view schematically illustrating a display device according to one embodiment. Specific details for implementing the invention

[0031] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0032] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0033] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0034] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0035] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0036] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and therefore the present invention is not necessarily limited to what is illustrated.

[0037] In this specification, "A and / or B" indicates the case where it is A, B, or both A and B. Additionally, in this specification, "at least one of A and B" indicates the case where it is A, B, or both A and B.

[0038] In the following embodiments, the meaning of "the wiring extends in a first direction or a second direction" includes not only extending in a straight line shape, but also extending in a zigzag or curved shape along the first direction or the second direction.

[0039] In the following embodiments, "planar" refers to the view of the target part from above, and "cross-sectional" refers to the view of the cross-section obtained by vertically cutting the target part from the side. In the following embodiments, "superimposition" includes the superposition of the "planar" and "cross-sectional" views.

[0040] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings, and when describing with reference to the drawings, identical or corresponding components will be given the same reference numerals.

[0041] FIG. 1 is a perspective view schematically illustrating a display device according to one embodiment, and FIG. 2a and FIG. 2b are plan views schematically illustrating a display device according to one embodiment.

[0042] Referring to FIG. 1, a display device (1) according to one embodiment may include a display area (DA) and a non-display area (NDA) around the display area (DA). The non-display area (NDA) may include a bending area (BA) in which a portion of the non-display area (NDA) is bent. The remaining area excluding the bending area (BA) may be an area having a roughly flat surface. The bending area (BA) may be bent with respect to a bending axis (BAX) extended in a first direction (X direction) as shown in FIG. 1.

[0043] The substrate (100) may include various materials having flexible, bendable, or rollable properties. For example, the substrate (100) may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0044] Of course, the substrate (100) comprises two layers containing such a polymer resin and silicon oxide (SiO₂) interposed between the layers. X ), silicon nitride (SiN X ), silicon oxynitride (SiO₂ X N YVarious variations are possible, such as having a multilayer structure including a barrier layer containing inorganic materials such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). In one embodiment, for a display device in which the substrate (100) does not need to be bent, the substrate (100) may include glass.

[0045] In the substrate (100), the width in the first direction (X direction) of the non-display area (NDA) including the bending area (BA) may be smaller than the width in the first direction (X direction) of the portion where the display area (DA) is located. Additionally, the corner portion (100c) of the edge of the substrate (100) may have a rounded shape. Such a shape may also be applied to the display area (DA) as shown in FIG. 2a.

[0046] Referring to FIG. 2a, the display device (1) may include a display area (DA) where a plurality of pixels (P) are located, and a non-display area (NDA) located outside the display area (DA). This may be understood as the substrate (100) having a display area (DA) and a non-display area (NDA). The non-display area (NDA) may include a pad area (PDA) on one side of the display area (DA), which is an area where various electronic components such as an integrated circuit (IC) or a printed circuit board are electrically attached.

[0047] FIG. 2a may be understood as a plan view showing the appearance of a substrate (100), etc. during the manufacturing process. In the case of a final display device or an electronic device such as a smartphone including a display device, a part of the substrate (100), etc., may be bent as in FIG. 1 in order to minimize the area of ​​the non-display area (NDA) recognized by the user. For example, as shown in FIG. 1 and FIG. 2a, the substrate (100) may have a part with a different width in the first direction (X direction), and the substrate (100) may be bent around (based on) a bending axis (BAX) parallel to the first direction (X direction) in the narrow part.

[0048] In this case, at least a portion of the pad area (PDA) can be positioned to overlap with the display area (DA). Of course, the bending direction can be set so that the pad area (PDA) is positioned behind the display area (DA) rather than obscuring the display area (DA). Accordingly, the user may perceive that the display area (DA) occupies most of the display device (1).

[0049] The edges of the display area (DA) may have a shape similar to a rectangle or a square overall. Specifically, the display area (DA) may include a first edge (E1) and a second edge (E2) facing each other, and a third edge (E3) and a fourth edge (E4) facing each other and located between the first edge (E1) and the second edge (E2). The pad area (PDA) may be located adjacent to the fourth edge (E4) among the first edge (E1) to the fourth edge (E4). In this case, the first part (F1) connecting the first edge (E1) and the fourth edge (E4) may have a round shape. Of course, the display area (DA) may also have a round shape in the second part (F2) connecting the second edge (E2) and the fourth edge (E4). Additionally, the display area (DA) may have a round shape in other parts of the edges as well.

[0050] A display unit (10) including a plurality of pixels (P) may be disposed on the display area (DA). A fan-out unit (20) including a plurality of data lines may be disposed on the pad area (PDA). One side of the fan-out unit (20) may be connected to the display unit (10), and the other side of the fan-out unit (20) may be connected to a driving circuit unit (30). The driving circuit unit (30) may include various electronic components such as an integrated circuit (IC).

[0051] A scan driving circuit may be further disposed on the left and / or right side of the display area (DA). The scan driving circuit may provide a scan signal to each pixel (P) through a scan line and may provide a light emission control signal to each pixel (P) through a light emission control line.

[0052] Referring to FIG. 2b, a display device (1) according to one embodiment can be folded around (based on) a folding axis (FAX). Specifically, the display device (1) can be folded around (based on) a folding axis (FAX) parallel to a first direction (X direction). By folding the display device (1) around (based on) a folding axis (FAX) parallel to the first direction (X direction), a display area (DA) above the folding axis (FAX) and a display area (DA) below the folding axis (FAX) can face each other. In one embodiment, the folding axis (FAX) can cross at least a portion of the display area (DA).

[0053] FIG. 2b illustrates a display device (1) being folded around (based on) a folding axis (FAX) parallel to a first direction (X direction), but the present invention is not limited thereto. In one embodiment, the display device (1) may be folded around (based on) a folding axis (FAX) parallel to a second direction (Y direction) that intersects the first direction (X direction).

[0054] In one embodiment, the display device (1) may include a display unit (10) disposed on a display area (DA). In one embodiment, the display unit (10) may include a plurality of pixels (P).

[0055] In one embodiment, the pixel (P) may include a first pixel (P1), a second pixel (P2), and a third pixel (P3). In one embodiment, the first pixel (P1), the second pixel (P2), and the third pixel (P3) may each emit red, green, and blue light, respectively. However, the present invention is not limited thereto.

[0056] In one embodiment, the first pixel (P1), the second pixel (P2), and / or the third pixel (P3) may be provided in a landscape shape in which the length in the horizontal direction (e.g., the first direction (X direction)) is longer than the length in the vertical direction (e.g., the second direction (Y direction)). In one embodiment, the first pixel (P1), the second pixel (P2), and / or the third pixel (P3) may be provided in a portrait shape in which the length in the vertical direction (e.g., the second direction (Y direction)) is longer than the length in the horizontal direction (e.g., the first direction (X direction)).

[0057] Alternatively, in one embodiment, the first pixel (P1), the second pixel (P2), and / or the third pixel (P3) may be arranged in various shapes, such as a pentile structure, a stripe structure, a mosaic array structure, a delta array structure, etc.

[0058] FIGS. 3 and FIGS. 4 are equivalent circuit diagrams of pixels that may be included in a display device according to one embodiment.

[0059] Referring to FIG. 3, the pixel circuit (PC) can be connected to an organic light-emitting diode (OLED) to enable light emission of pixels (P). The pixel circuit (PC) may include a driving thin-film transistor (T1), a switching thin-film transistor (T2), and a storage capacitor (Cst). The switching thin-film transistor (T2) is connected to a scan line (SL) and a data line (DL), and can transmit a data signal (Dm) input through the data line (DL) to the driving thin-film transistor (T1) according to a scan signal (Sn) input through the scan line (SL).

[0060] The storage capacitor (Cst) is connected to the switching thin-film transistor (T2) and the driving voltage line (PL), and can store a voltage corresponding to the difference between the voltage received from the switching thin-film transistor (T2) and the driving voltage (ELVDD) supplied to the driving voltage line (PL).

[0061] The driving thin-film transistor (T1) is connected to the driving voltage line (PL) and the storage capacitor (Cst), and can control the driving current flowing from the driving voltage line (PL) to the organic light-emitting diode (OLED) in correspondence with the voltage value stored in the storage capacitor (Cst). The organic light-emitting diode (OLED) can emit light having a predetermined brightness by the driving current.

[0062] Figure 3 describes a case where the pixel circuit (PC) includes two thin-film transistors and one storage capacitor, but the present invention is not limited thereto.

[0063] Referring to FIG. 4, the pixel circuit (PC) may include a driving thin-film transistor (T1), a switching thin-film transistor (T2), a compensation thin-film transistor (T3), a first initialization thin-film transistor (T4), an operation control thin-film transistor (T5), a light emission control thin-film transistor (T6), a second initialization thin-film transistor (T7), and a storage capacitor (Cst).

[0064] FIG. 4 illustrates a case in which signal lines (SL, SL-1, SL+1, EL, DL), an initialization voltage line (VL), and a driving voltage line (PL) are provided for each pixel circuit (PC), but the present invention is not limited thereto. In one embodiment, at least one of the signal lines (SL, SL-1, SL+1, EL, DL), or / and the initialization voltage line (VL) may be shared among neighboring pixel circuits.

[0065] The drain electrode of the driving thin-film transistor (T1) can be electrically connected to the organic light-emitting diode (OLED) via the light-emitting control thin-film transistor (T6). The driving thin-film transistor (T1) can receive a data signal (Dm) according to the switching operation of the switching thin-film transistor (T2) and supply a driving current to the organic light-emitting diode (OLED).

[0066] The gate electrode of the switching thin-film transistor (T2) can be connected to the scan line (SL), and the source electrode can be connected to the data line (DL). The drain electrode of the switching thin-film transistor (T2) is connected to the source electrode of the driving thin-film transistor (T1) and can be connected to the driving voltage line (PL) via the operation control thin-film transistor (T5).

[0067] The switching thin-film transistor (T2) can perform a switching operation in which it is turned on according to the scan signal (Sn) received through the scan line (SL) and transmits the data signal (Dm) transmitted through the data line (DL) to the source electrode of the driving thin-film transistor (T1).

[0068] The gate electrode of the compensation thin-film transistor (T3) can be connected to the scan line (SL). The source electrode of the compensation thin-film transistor (T3) is connected to the drain electrode of the driving thin-film transistor (T1) and can be connected to the pixel electrode of the organic light-emitting diode (OLED) via the light-emitting control thin-film transistor (T6). The drain electrode of the compensation thin-film transistor (T3) can be connected together with one electrode of the storage capacitor (Cst), the source electrode of the first initialization thin-film transistor (T4), and the gate electrode of the driving thin-film transistor (T1). The compensation thin-film transistor (T3) is turned on according to the scan signal (Sn) received through the scan line (SL) to connect the gate electrode and the drain electrode of the driving thin-film transistor (T1) to each other, thereby making the driving thin-film transistor (T1) diode-connected.

[0069] The gate electrode of the first initialization thin film transistor (T4) can be connected to the previous scan line (SL-1). The drain electrode of the first initialization thin film transistor (T4) can be connected to the initialization voltage line (VL). The source electrode of the first initialization thin film transistor (T4) can be connected together with one electrode of the storage capacitor (Cst), the drain electrode of the compensation thin film transistor (T3), and the gate electrode of the driving thin film transistor (T1). The first initialization thin film transistor (T4) can be turned on according to the previous scan signal (Sn-1) received through the previous scan line (SL-1) to transmit an initialization voltage (Vint) to the gate electrode of the driving thin film transistor (T1) and perform an initialization operation to initialize the voltage of the gate electrode of the driving thin film transistor (T1).

[0070] The gate electrode of the operation control thin film transistor (T5) can be connected to the light emission control line (EL). The source electrode of the operation control thin film transistor (T5) can be connected to the driving voltage line (PL). The drain electrode of the operation control thin film transistor (T5) is connected to the source electrode of the driving thin film transistor (T1) and the drain electrode of the switching thin film transistor (T2).

[0071] The gate electrode of the light-emitting control thin film transistor (T6) can be connected to the light-emitting control line (EL). The source electrode of the light-emitting control thin film transistor (T6) can be connected to the drain electrode of the driving thin film transistor (T1) and the source electrode of the compensation thin film transistor (T3). The drain electrode of the light-emitting control thin film transistor (T6) can be electrically connected to the pixel electrode of the organic light-emitting diode (OLED). The operation control thin film transistor (T5) and the light-emitting control thin film transistor (T6) are simultaneously turned on according to the light-emitting control signal (En) received through the light-emitting control line (EL), so that the driving voltage (ELVDD) is transmitted to the organic light-emitting diode (OLED) and the driving current flows through the organic light-emitting diode (OLED).

[0072] The gate electrode of the second initialization thin-film transistor (T7) can be connected to the scan line (SL+1). The source electrode of the second initialization thin-film transistor (T7) can be connected to the pixel electrode of the organic light-emitting diode (OLED). The drain electrode of the second initialization thin-film transistor (T7) can be connected to the initialization voltage line (VL). The second initialization thin-film transistor (T7) can be turned on according to the scan signal (Sn+1) received through the scan line (SL+1) to initialize the pixel electrode of the organic light-emitting diode (OLED).

[0073] FIG. 4 illustrates a case where the first initialization thin film transistor (T4) and the second initialization thin film transistor (T7) are connected to the previous scan line (SL-1) and the subsequent scan line (SL+1), respectively, but the present invention is not limited thereto. In one embodiment, the first initialization thin film transistor (T4) and the second initialization thin film transistor (T7) are both connected to the previous scan line (SLn-1) and can be driven according to the previous scan signal (Sn-1).

[0074] Another electrode of the storage capacitor (Cst) can be connected to the driving voltage line (PL). Any one electrode of the storage capacitor (Cst) can be connected together to the gate electrode of the driving thin-film transistor (T1), the drain electrode of the compensation thin-film transistor (T3), and the source electrode of the first initialization thin-film transistor (T4).

[0075] The counter electrode (e.g., cathode) of the organic light-emitting diode (OLED) can be provided with a common voltage (ELVSS). The organic light-emitting diode (OLED) can emit light by receiving a driving current from a driving thin-film transistor (T1).

[0076] The pixel circuit (PC) is not limited to the number and circuit design of the thin-film transistor and storage capacitor described with reference to FIG. 4, and the number and circuit design can be varied.

[0077] FIG. 5 is a cross-sectional view schematically illustrating a display device according to one embodiment. FIG. 5 corresponds to a cross-sectional view taken along line II' of FIG. 2a.

[0078] Referring to FIG. 5, a thin-film transistor (TFT) and an organic light-emitting diode (OLED) may be placed on a substrate (100).

[0079] A buffer layer (101) may be disposed on a substrate (100). The buffer layer (101) may be positioned on the substrate (100) to reduce or block the penetration of foreign matter, moisture, or outside air from the bottom of the substrate (100), and may provide a flat surface on the substrate (100). The buffer layer (101) may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite, and may be composed of a single layer or a multilayer structure of inorganic and organic materials.

[0080] In one embodiment, the buffer layer (101) is silicon oxide (SiO₂). X ), silicon nitride (SiN X ), silicon oxynitride (SiO₂ X N Y It may include at least one inorganic insulating material selected from the group including aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). Alternatively, the buffer layer (101) may include an organic insulating material such as polyimide or siloxane.

[0081] In one embodiment, the buffer layer (101) may have a thickness of 50 nm or more and 10 μm or less.

[0082] A thin-film transistor (TFT) may be disposed on the buffer layer (101). The thin-film transistor (TFT) may include a semiconductor layer (134), a gate electrode (136) overlapping with the semiconductor layer (134), and a connection electrode electrically connected to the semiconductor layer (134). The thin-film transistor (TFT) may be connected to an organic light-emitting diode (OLED) to drive the organic light-emitting diode (OLED).

[0083] The semiconductor layer (134) is disposed on the buffer layer (101) and may include a channel region (131) that overlaps with the gate electrode (136), a source region (132) disposed on both sides of the channel region (131) and containing a higher concentration of impurities than the channel region (131), and a drain region (133). Here, the impurities may include N-type impurities or P-type impurities. The source region (132) and the drain region (133) may be electrically connected to a connecting electrode.

[0084] The semiconductor layer (134) may include an oxide semiconductor and / or a silicon semiconductor. When the semiconductor layer (134) is formed as an oxide semiconductor, the semiconductor layer (134) may include an oxide of at least one material selected from the group comprising indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). For example, the semiconductor layer (134) may be ITZO (InSnZnO), IGZO (InGaZnO), etc. When the semiconductor layer (134) is formed as a silicon semiconductor, it may include, for example, amorphous silicon (a-Si) or low temperature polysilicon (LTPS) crystallized from amorphous silicon (a-Si).

[0085] A first insulating layer (103) may be disposed on the semiconductor layer (134). The first insulating layer (103) is silicon oxide (SiO₂). X ), silicon nitride (SiN X), silicon oxynitride (SiO₂ X N Y It may include at least one inorganic insulating material selected from the group including aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The first insulating layer (103) may be provided as a single layer or a multilayer including the aforementioned inorganic insulating material.

[0086] A gate electrode (136) may be disposed on the first insulating layer (103). The gate electrode (136) may be formed as a single layer or a multilayer of one or more metals selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode (136) may be connected to a gate line that applies an electrical signal to the gate electrode (136).

[0087] In one embodiment, the thickness of the gate electrode (136) may be 50 nm or more.

[0088] A second insulating layer (105) may be disposed on the gate electrode (136). The second insulating layer (105) is silicon oxide (SiO₂). X ), silicon nitride (SiN X ), silicon oxynitride (SiO₂ X N Y It may include at least one inorganic insulating material selected from the group including aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The second insulating layer (105) may be provided as a single layer or a multilayer including the aforementioned inorganic insulating material.

[0089] A storage capacitor (Cst) may be disposed on the first insulating layer (103). The storage capacitor (Cst) may include a lower electrode (144) and an upper electrode (146) that overlaps with the lower electrode (144). The lower electrode (144) and the upper electrode (146) of the storage capacitor (Cst) may overlap with the second insulating layer (105) in between.

[0090] The lower electrode (144) of the storage capacitor (Cst) overlaps with the gate electrode (136) of the thin-film transistor (TFT), and the lower electrode (144) of the storage capacitor (Cst) may be arranged integrally with the gate electrode (136) of the thin-film transistor (TFT). In one embodiment, the storage capacitor (Cst) may not overlap with the thin-film transistor (TFT), and the lower electrode (144) of the storage capacitor (Cst) may be a separate and independent component from the gate electrode (136) of the thin-film transistor (TFT).

[0091] The upper electrode (146) of the storage capacitor (Cst) may comprise aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be a single layer or a multilayer of the aforementioned materials.

[0092] In one embodiment, the thickness of the upper electrode (146) may be 50 nm or more.

[0093] A third insulating layer (107) may be disposed on the upper electrode (146) of the storage capacitor (Cst). The third insulating layer (107) is silicon oxide (SiO₂). X ), silicon nitride (SiN X ), silicon oxynitride (SiO₂ X N YIt may include at least one inorganic insulating material selected from the group including aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO). The third insulating layer (107) may be provided as a single layer or a multilayer including the aforementioned inorganic insulating material.

[0094] A source electrode (137) and a drain electrode (138), which are connecting electrodes, may be disposed on the third insulating layer (107). The source electrode (137) and the drain electrode (138) may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer including the above materials. The source electrode (137) and the drain electrode (138) may be formed as a multilayer structure of Ti / Al / Ti.

[0095] A first flattening layer (111) may be disposed on the source electrode (137) and the drain electrode (138). The first flattening layer (111) may be formed as a single layer or a multilayer film made of an organic or inorganic material. In one embodiment, the first flattening layer (111) may include general-purpose polymers such as benzocyclobutene (BCB), polyimide (PI), hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, and blends thereof. Meanwhile, the first flattening layer (111) is silicon oxide (SiO₂ X ), silicon nitride (SiN X ), silicon oxynitride (SiO₂ X N YIt may include aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO), etc. After forming the first flattening layer (111), chemical mechanical polishing may be performed to provide a flat upper surface.

[0096] A contact metal layer (CM) may be disposed on the first flattening layer (111). The contact metal layer (CM) may include aluminum (Al), copper (Cu), titanium (Ti), etc., and may be formed as a multilayer or single layer. The contact metal layer (CM) may be composed of a multilayer structure of Ti / Al / Ti.

[0097] A second flattening layer (113) may be disposed on the contact metal layer (CM). In one embodiment, the second flattening layer (113) may include the same material as the first flattening layer (111). In one embodiment, the second flattening layer (113) may include a different material from the first flattening layer (111).

[0098] An organic light-emitting diode (OLED) including a pixel electrode (210), an intermediate layer (220), and a counter electrode (230) may be disposed on the second flattening layer (113). The pixel electrode (210) is electrically connected to a contact metal layer (CM) through a contact hole penetrating the second flattening layer (113), and the contact metal layer (CM) is electrically connected to a source electrode (137) or a drain electrode (138), which is a connecting electrode of a thin-film transistor (TFT), through a contact hole penetrating the first flattening layer (111), so that the organic light-emitting diode (OLED) may be electrically connected to the thin-film transistor (TFT).

[0099] A pixel electrode (210) may be disposed on the second planarization layer (113). The pixel electrode (210) may be a (semi)transparent electrode or a reflective electrode. The pixel electrode (210) may have a reflective film formed of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu), and compounds thereof, and a transparent or semitransparent electrode layer formed on the reflective film. The transparent or translucent electrode layer may comprise at least one selected from the group including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). The pixel electrode (210) may be provided with a structure laminated with ITO / Ag / ITO.

[0100] A pixel defining film (180) may be disposed on the second planarization layer (113), and the pixel defining film (180) may have an opening (OP) that exposes at least a portion of the pixel electrode (210). The area exposed by the opening (OP) of the pixel defining film (180) may be defined as a light-emitting region (EA). The periphery of the light-emitting regions (EA) is a non-light-emitting region (NEA), and the non-light-emitting region (NEA) may surround the light-emitting regions (EA). That is, the display area (DA) may include a plurality of light-emitting regions (EA) and a non-light-emitting region (NEA) surrounding them. The pixel defining film (180) can prevent arcs or the like from occurring at the edges of the pixel electrode (210) by increasing the distance between the pixel electrode (210) and the opposing electrode (230) above the pixel electrode (210). The pixel definition film (180) can be formed using an organic insulating material such as, for example, polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO (hexamethyldisiloxane), and phenolic resin, by a method such as spin coating.

[0101] An intermediate layer (220) may be disposed on a pixel electrode (210) that is exposed in at least a portion by a pixel defining film (180). The intermediate layer (220) may include a light-emitting layer (220b), and a first functional layer (220a) and / or a second functional layer (220c) may be optionally disposed below and above the light-emitting layer (220b).

[0102] In one embodiment, the intermediate layer (220) may be disposed on a pixel electrode (210) in which at least a portion is exposed by a pixel defining film (180). More specifically, the light-emitting layer (220b) of the intermediate layer (220) may be disposed on a pixel electrode (210) in which at least a portion is exposed by a pixel defining film (180).

[0103] The first functional layer (220a) may include a hole injection layer (HIL) and / or a hole transport layer (HTL), and the second functional layer (220c) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0104] The light-emitting layer (220b) may include an organic material comprising a fluorescent or phosphorescent material that emits red, green, blue, or white light. The light-emitting layer (220b) may include a low-molecular-weight organic material or a high-molecular-weight organic material.

[0105] When the light-emitting layer (220b) contains a low-molecular-weight organic material, the intermediate layer (220) may have a structure in which a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, an electron injection layer, etc. are stacked in a single or composite structure, and the low-molecular-weight organic material may include various organic materials such as copper phthalocyanine (CuPc), N,N'-Di(naphthalene-1-yl)-N,N'-diphenyl-benzidine (NPB), tris-8-hydroxyquinoline aluminum (Alq3), etc. These layers may be formed by a vacuum deposition method.

[0106] When the light-emitting layer (220b) contains a polymer organic material, the intermediate layer (220) may generally have a structure including a hole transport layer and a light-emitting layer (220b). In this case, the hole transport layer may contain PEDOT, and the light-emitting layer may contain polymer materials such as PPV (Poly-Phenylene Vinylene) and Polyfluorene. Such a light-emitting layer can be formed by screen printing, inkjet printing, or laser induced thermal imaging (LITI).

[0107] A counter electrode (230) may be disposed on the intermediate layer (220). The counter electrode (230) may be disposed on the intermediate layer (220) in a manner that covers the entire intermediate layer (220). The counter electrode (230) may be disposed on the upper part of the display area (DA) in a manner that covers the entire display area (DA). That is, the counter electrode (230) may be formed integrally over the entire display panel using an open mask to cover a plurality of pixels (P) disposed in the display area (DA).

[0108] The counter electrode (230) may include a conductive material with a low work function. For example, the counter electrode (230) may include a (semi)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer including the aforementioned materials.

[0109] FIG. 6 is a schematic plan view illustrating a display device according to one embodiment. Specifically, FIG. 6 is a plan view illustrating an enlarged view of portion A of FIG. 2a.

[0110] Referring to FIG. 6, in one embodiment, the non-display area (NDA) may include a first area (1A), a bending area (BA), a second area (2A), and a pad area (PDA). The first area (1A) may be the area closest to the display area (DA). For example, the first area (1A) may be the area between the fourth edge (E4) and the bending area (BA). The bending area (BA) may be the area between the first area (1A) and the second area (2A). The first area (1A) and the second area (2A) may be defined with the bending area (BA) as the center. The second area (2A) may be the area between the bending area (BA) and the pad area (PDA), which is not visible from the front when the bending area (BA) is bent. The pad area (PDA) may be an area where the driving circuit part (30) and other circuits are arranged.

[0111] As described above, the first area (1A) may be an area recognized by a user in an electronic device such as a smartphone including the final display device (1) or the display device (1), such as a non-display area (NDA) that contacts the first edge (E1) to the third edge (E3) of the display area (DA) as in FIG. 2a. Since the fan-out portion (20) is disposed on this first area (1A), it may not be easy to reduce the width of the area itself compared to other non-display areas (i.e., non-display areas that contact the first edge (E1) to the third edge (E3) of the display area (DA).

[0112] In a display device (1) according to one embodiment, the width (WA1) of a first region (1A) can be reduced by designing the fan-out section (20) by dividing it into "multiple sections." The "multiple sections" can be understood to correspond to the first fan-out portion (21) and the second fan-out portion (22) of the fan-out section (20), respectively. Accordingly, in one embodiment, the width (WA1) of the first region (1A) may be smaller than the width (WA2) of the second region (2A). However, the present invention is not limited thereto. The width (WA1) of the first region (1A) may be equal to or greater than the width (WA2) of the second region (2A).

[0113] In one embodiment, the fan-out section (20) may be provided with a first fan-out section (21) and a second fan-out section (22). In one embodiment, the first fan-out section (21) may be located on both sides with the second fan-out section (22) in between. In one embodiment, the fan-out section (20) may be provided with an overall symmetrical shape, and the first fan-out section (21) may be symmetrically arranged with the second fan-out section (22) in between. The second fan-out section (22) is provided with a symmetrical shape around the axis of symmetry (SAX), and the first fan-out section (21) may be placed on one side and the other side, respectively, with the second fan-out section (22) in between. For example, the first fan-out section (21) may be placed on the outside of the second fan-out section (22). In the present invention, the first fan-out section (21) and the second fan-out section (22) may be separated by a separation section (SA).

[0114] In FIG. 6, the fan-out section (20) is shown as being divided into three regions, but the present invention is not limited thereto. In one embodiment, the fan-out section (20) may be provided by being divided into various numbers of regions, such as four, five, or six. For example, the fan-out section (20) may be provided by being divided into five regions with a plurality of spaced-out sections (SA) in between.

[0115] In this specification, the description will be based on the first fan-out portion (21) positioned to the left of the second fan-out portion (22).

[0116] In one embodiment, a plurality of data lines (DL) may be arranged in each of the first fan-out portion (21) and the second fan-out portion (22). In one embodiment, the plurality of data lines (DL) may include a plurality of first data lines (DL1) and a plurality of second data lines (DL2).

[0117] In the present invention, the data line (DL) is referred to as the first data line (DL1) and the second data line (DL2) to explain the features of the invention; however, both the first data line (DL1) and the second data line (DL2) are data lines (DL) and can perform the same role. However, the present invention is not limited thereto.

[0118] In one embodiment, a plurality of first data lines (DL1) and a plurality of second data lines (DL2) may be arranged in the first fan-out portion (21) and the second fan-out portion (22), respectively. The plurality of first data lines (DL1) and the plurality of second data lines (DL2) can transmit data signals applied from the driving circuit portion (30) to the display portion (10). In one embodiment, the plurality of first data lines (DL1) and the plurality of second data lines (DL2) may be arranged alternately with each other. For example, the second data line (DL2) may be arranged between the first data line (DL1) and the first data line (DL1).

[0119] Specifically, a first data line (DL1) may be placed at the leftmost part of the first fan-out section (21) (the beginning part of the first fan-out section (21)), a second data line (DL2) may be placed spaced apart from the first data line (DL1) in the first direction (X direction), and the first data line (DL1) may be placed again spaced apart from the second data line (DL2) in the first direction (X direction). That is, the first data line (DL1), the second data line (DL2), the first data line (DL1), and the second data line (DL2) may be placed sequentially. While the first data line (DL1) and the second data line (DL2) are placed sequentially, the second data line (DL2) may be placed at the rightmost part of the first fan-out section (21) (the end part of the first fan-out section (21)). Additionally, a first data line (DL1) may be placed at the leftmost part of the second fan-out section (22) (the beginning part of the second fan-out section (22)), a second data line (DL2) may be placed spaced apart from the first data line (DL1) in the first direction (X direction), and the first data line (DL1) may be placed again spaced apart from the second data line (DL2) in the first direction (X direction). However, the present invention is not limited thereto. A first data line (DL1) may be placed at the rightmost part of the first fan-out section (21) (the end part of the first fan-out section (21)), and a second data line (DL2) may be placed at the leftmost part of the second fan-out section (22) (the beginning part of the second fan-out section (22)). In addition, various variations are possible, such as placing the first data line (DL1) at the far right of the first fan-out section (21) (at the end of the first fan-out section (21)) and placing the first data line (DL1) at the far left of the second fan-out section (22) (at the beginning of the second fan-out section (22)).

[0120] A plurality of first data lines (DL1) and a plurality of second data lines (DL2) of the first fan-out portion (21) may be formed with different lengths. In one embodiment, the length of each of the plurality of first data lines (DL1) and the plurality of second data lines (DL2) may decrease as one moves from the left to the right of the first fan-out portion (21). For example, the length of each of the plurality of first data lines (DL1) and the plurality of second data lines (DL2) may decrease as one moves toward the first direction (X direction) (e.g., the center of the display device (1)). However, the present invention is not limited thereto.

[0121] The difference in length between data lines can cause a difference in resistance between data lines, and the difference in resistance between data lines can cause an RC Delay difference between pixels connected to each data line, but as the magnitude of the resistance of the data line gradually decreases from the left to the right of the first fan-out portion (21), the difference in RC Delay between pixels may not be visible to the user.

[0122] A plurality of first data lines (DL1) and a plurality of second data lines (DL2) may be arranged to pass sequentially through a first region (1A), a bending region (BA), and a second region (2A). As shown in FIG. 6, a plurality of first data lines (DL1) and a plurality of second data lines (DL2) may be bent at least twice. The portion where the plurality of first data lines (DL1) and a plurality of second data lines (DL2) are bent may be located on the first region (1A) and / or the second region (2A). Since stress is concentrated in the bending region (BA), it can be understood that the portion where the plurality of first data lines (DL1) and a plurality of second data lines (DL2) are bent is formed by avoiding the bending region (BA), where there is a high risk of wire breakage.

[0123] A plurality of first data lines (DL1) and a plurality of second data lines (DL2) may be extended diagonally in a direction intersecting the first direction (X direction) and the second direction (Y direction) on the first area (1A) and the second area (2A), and may be extended in a direction approximately parallel to the second direction (Y direction) on the bending area (BA). A portion of the plurality of first data lines (DL1) and a plurality of second data lines (DL2) placed on the bending area (BA) may be extended at least partially into the first area (1A) and the second area (2A).

[0124] In one embodiment, a driving circuit unit (30) may be disposed in the pad area (PDA). The driving circuit unit (30) may include various electronic components such as an integrated circuit (IC). Additionally, an inspection circuit unit (35) may be further disposed in the pad area (PDA). The inspection circuit unit (35) may include a lighting inspection circuit, an electrostatic discharge protection circuit, etc. The inspection circuit unit (35) may overlap at least partially with a plurality of first data lines (DL1) and a plurality of second data lines (DL2).

[0125] FIG. 7 is a plan view schematically illustrating a display device according to one embodiment, and FIG. 8 and FIG. 9 are cross-sectional views schematically illustrating a display device according to one embodiment. FIG. 8 is a cross-sectional view taken along the line II-II' of FIG. 7, and FIG. 9 is a cross-sectional view taken along the line III-III' of FIG. 7.

[0126] FIG. 7 illustrates a first data line (DL1) and a second data line (DL2) positioned adjacent to each other on the first fan-out section (21), and a first data line (DL1) and a second data line (DL2) positioned adjacent to each other on the second fan-out section (22). The remaining data lines that are positioned consecutively on the first fan-out section (21) and the second fan-out section (22), respectively, have been omitted for convenience of explanation. At this time, the second data line (DL2) positioned at the far right of the first fan-out section (21) and the first data line (DL1) positioned at the far left of the second fan-out section (22) may be data lines (DL1, DL2) positioned closest to each other with a separation section (SA) in between.

[0127] A gap (SA) may be formed between the second data line (DL2) of the first fan-out section (21) and the first data line (DL1) of the second fan-out section (22). The gap (SA) overlaps with the bending area (BA), and at least a portion of the gap (SA) may extend to the first area (1A) and the second area (2A). Additionally, although not illustrated, at least a portion of the gap (SA) may extend to the pad area (PDA).

[0128] Referring to FIGS. 7 through 9, in one embodiment, a buffer layer (101), a first insulating layer (103), a second insulating layer (105), a third insulating layer, and a first flattening layer (111) may be disposed on a substrate (100). A second flattening layer (113, FIG. 5) and / or additional layers may be disposed on the first flattening layer (111), but have been omitted for convenience of explanation.

[0129] In one embodiment, the first data line (DL1) may include a first-1 data line (DL1-1), a first-2 data line (DL1-2), a first-3 data line (DL1-3), and a first-4 data line (DL1-4). Although not illustrated, the second data line (DL2) may include a second-1 data line, a second-2 data line, a second-3 data line, and a second-4 data line.

[0130] In one embodiment, the first-1 data line (DL1-1) and the first-2 data line (DL1-2) may be placed on different layers. Additionally, the first-1 data line (DL1-1) and the first-3 data line (DL1-3) may be placed on different layers.

[0131] Although not illustrated, the 2-1 data line and the 2-2 data line may be placed on different floors. Additionally, the 2-1 data line and the 2-3 data line may be placed on different floors.

[0132] Data line 1-1 (DL1-1) and data line 2-1 can be placed on the second area (2A), data line 1-2 (DL1-2) and data line 2-2 can be placed on the pad area (PDA), data line 1-3 (DL1-3) and data line 2-3 can be placed on the bending area (BA), and data line 1-4 (DL1-4) and data line 2-4 can be placed on the first area (1A).

[0133] The first-2 data line (DL1-2) is placed on the pad area (PDA), and at least a portion of the first-2 data line (DL1-2) may extend to the second area (2A). In one embodiment, the first-2 data line (DL1-2) may be placed on the first insulating layer (103). In one embodiment, the first-2 data line (DL1-2) may be placed on the same layer as the aforementioned gate electrode (136, FIG. 5) and may be made of the same material. In one embodiment, the first-2 data line (DL1-2) may be placed on the second insulating layer (105). When the first-2 data line (DL1-2) is placed on the second insulating layer (105), the first-2 data line (DL1-2) may be made of the same material as the aforementioned upper electrode (146, FIG. 5). In one embodiment, the first-2 data lines (DL1-2) may be alternately arranged on the first insulating layer (103) and the second insulating layer (105).

[0134] Additionally, although not illustrated, the second-2 data line may be placed on the pad area (PDA), and at least a portion of the second-2 data line may extend to the second area (2A). In one embodiment, the second-2 data line may be placed on the second insulating layer (105). In one embodiment, the second-2 data line may be placed on the same layer as the aforementioned upper electrode (146, FIG. 5) and may be made of the same material. In one embodiment, the second-2 data line may be placed on the first insulating layer (103). When the second-2 data line is placed on the first insulating layer (103), the second-2 data line may be made of the same material as the aforementioned gate electrode (136, FIG. 5). In one embodiment, the second-2 data line may be placed alternately on the first insulating layer (103) and the second insulating layer (105).

[0135] The first-1 data line (DL1-1) may be placed on the second region (2A). In one embodiment, the first-1 data line (DL1-1) may be placed on the third insulating layer (107). The first-1 data line (DL1-1) may be placed on the same layer as the source electrode (137, FIG. 5) or drain electrode (138, FIG. 5), which are the aforementioned connecting electrodes, and may be made of the same material. The first-1 data line (DL1-1) and the first-2 data line (DL1-2) may be electrically connected through a contact hole (e.g., first contact hole (CNT1)) defined in the second insulating layer (105) and the third insulating layer (107). FIG. 8 is illustrated as having a contact hole (e.g., a first contact hole (CNT1)) defined in the second insulating layer (105) and the third insulating layer (107), but when the first-second data line (DL1-2) is placed on the second insulating layer (105), the contact hole (e.g., a first contact hole (CNT1)) may be defined in the third insulating layer (107).

[0136] In one embodiment, a contact hole (e.g., a first contact hole (CNT1)) that electrically connects the first-1 data line (DL1-1) and the first-2 data line (DL1-2) may be located on the second area (2A). Alternatively, in one embodiment, a contact hole (e.g., a first contact hole (CNT1)) that electrically connects the first-1 data line (DL1-1) and the first-2 data line (DL1-2) may be located on the pad area (PDA).

[0137] Alternatively, although not illustrated, the 2-1 data line may be placed on the 2nd region (2A). In one embodiment, the 2-1 data line may be placed on the 3rd insulating layer (107). The 2-1 data line may be placed on the same layer as the source electrode (137, FIG. 5) or drain electrode (138, FIG. 5), which are the aforementioned connection electrodes, and may be made of the same material. The 2-1 data line and the 2-2 data line may be electrically connected through a contact hole defined in the 2nd insulating layer (105) and / or the 3rd insulating layer (107). In one embodiment, the contact hole electrically connecting the 2-1 data line and the 2-2 data line may be located on the 2nd region (2A). Alternatively, in one embodiment, the contact hole electrically connecting the 2-1 data line (DL1-1) and the 2-2 data line may be located on the pad region (PDA).

[0138] The first-third data line (DL1-3) may be placed on the bending region (BA). In one embodiment, the buffer layer (101), the first insulating layer (103), the second insulating layer (105), and the third insulating layer (107) placed on the substrate (100) may have an opening that exposes at least a portion of the upper surface of the substrate (100). For example, the opening may overlap (correspond) with at least a portion of the bending region (BA). In one embodiment, various variations are possible, such as the opening being defined in the first insulating layer (103), the second insulating layer (105), and the third insulating layer (107), or the opening being defined in the buffer layer (101), the first insulating layer (103), and the second insulating layer (105).

[0139] Alternatively, although not illustrated, at least a portion of a buffer layer (101), a first insulating layer (103), a second insulating layer (105), and / or a third insulating layer (107) may be disposed on the bending region (BA).

[0140] An organic insulating layer (115) may be disposed within the opening. In one embodiment, the organic insulating layer (115) may contain an organic material. Since inorganic films are more susceptible to stress than organic films, stress in the bending region (BA) during bending can be relieved by removing a portion of the inorganic film (i.e., buffer layer (101), first insulating layer (103), second insulating layer (105), and third insulating layer (107)) disposed on the bending region (BA) and then filling the opening with an organic insulating layer (115) containing an organic material. In one embodiment, the organic insulating layer (115) may contain the same material as the first flattening layer (111).

[0141] A first-third data line (DL1-3) may be disposed on the organic insulating layer (115). The first-third data line (DL1-3) may be disposed on the same layer as the aforementioned contact metal layer (CM, FIG. 5) and may be made of the same material. At least a portion of the first-third data line (DL1-3) may extend to a first region (1A) and / or a second region (2A). The first-third data line (DL1-3) may be electrically connected to the first-first data line (DL1-1) through a contact hole (e.g., a second contact hole (CNT2)) defined in the first flattening layer (111). In one embodiment, the contact hole (e.g., a second contact hole (CNT2)) electrically connecting the first-third data line (DL1-3) and the first-first data line (DL1-1) may be located on the second region (2A). Alternatively, although not illustrated, a contact hole (e.g., a second contact hole (CNT2)) that electrically connects the first-3 data line (DL1-3) and the first-1 data line (DL1-1) may be located on the bending area (BA).

[0142] Additionally, although not illustrated, a second-third data line may be disposed on the organic insulating layer (115). The second-third data line may be disposed on the same layer as the aforementioned contact metal layer (CM, FIG. 5) and may be made of the same material. At least a portion of the second-third data line may extend to the first region (1A) and / or the second region (2A). The second-third data line may be electrically connected to the second-first data line through a contact hole defined in the first flattening layer (111). In one embodiment, the contact hole electrically connecting the second-third data line and the second-first data line may be located on the second region (2A). Alternatively, although not illustrated, the contact hole electrically connecting the second-third data line and the second-first data line may be located on the bending region (BA).

[0143] The first-fourth data line (DL1-4) may be placed on the first region (1A). In one embodiment, the first-fourth data line (DL1-4) may be placed on the first insulating layer (103). The first-fourth data line (DL1-4) may be placed on the same layer as the aforementioned gate electrode (136, FIG. 5) and may be made of the same material. In one embodiment, the first-fourth data line (DL1-4) may be placed on the second insulating layer (105). In this case, the first-fourth data line (DL1-4) may be made of the same material as the aforementioned upper electrode (146, FIG. 5). In one embodiment, the first-fourth data line (DL1-4) may be placed alternately on the first insulating layer (103) and the second insulating layer (105).

[0144] Additionally, although not illustrated, the second-fourth data line may be placed on the first region (1A). In one embodiment, the second-fourth data line may be placed on the second insulating layer (105). The second-fourth data line may be placed on the same layer as the aforementioned upper electrode (146, FIG. 5) and may be made of the same material. In one embodiment, the second-fourth data line may be placed on the first insulating layer (103). In this case, the second-fourth data line may be made of the same material as the aforementioned upper electrode (136, FIG. 5). In one embodiment, the second-fourth data line may be placed alternately on the first insulating layer (103) and the second insulating layer (105).

[0145] In one embodiment, a test circuit section (35) may be disposed on the pad area (PDA). The test circuit section (35) may be disposed on the third insulating layer (107). In one embodiment, the test circuit section (35) may overlap at least partially with the first-2 data line (DL1-2). Additionally, although not illustrated, in one embodiment, the test circuit section (35) may overlap at least partially with the second-2 data line.

[0146] In one embodiment, the first-1 data line (DL1-1) may be provided with a first material, and the first-2 data line (DL1-2) may be provided with a second material having a higher resistivity than the first material. In this case, the first material may be aluminum (Al) and / or titanium (Ti), and the second material may be molybdenum (Mo).

[0147] In one embodiment, the 2-1 data line may be provided with a first material, and the 2-2 data line may be provided with a second material having a higher resistivity than the first material.

[0148] In one embodiment, the first-1 data line (DL1-1) placed on the second region (2A) is provided with a material having low resistivity, so that the total resistance of the first data line (DL1) can be reduced, thereby preventing or minimizing the occurrence of black luminance abnormalities, increased crosstalk, and stain defects.

[0149] Specifically, if the first-1 data line (DL1-1) placed on the second region (2A) is provided with molybdenum (Mo), the total resistance of the first data line (DL1) including the first-1 data line (DL1-1) may increase. Therefore, by providing the first-1 data line (DL1-1) placed on the second region (2A) with a material having a lower resistivity than molybdenum (Mo), the total resistance of the first data line (DL1) including the first-1 data line (DL1-1) is reduced, thereby preventing or minimizing the occurrence of black luminance abnormalities, increased crosstalk, and stain defects. This can be applied equally to the second data line.

[0150] Referring to FIG. 9, in one embodiment, the first-2 data line (DL1-2) of the first data line (DL1) may be placed on a different layer from the second-2 data line (DL2-2) of the adjacent second data line (DL2). For example, the first-2 data line (DL1-2) may be placed on the first insulating layer (103), and the second-2 data line (DL2-2) closest to the first-2 data line (DL1-2) may be placed on the second insulating layer (105). Alternatively, although not illustrated, the first-2 data line (DL1-2) may be placed on the second insulating layer (105), and the second-2 data line (DL2-2) closest to the first-2 data line (DL1-2) may be placed on the first insulating layer (103). Alternatively, the first-2 data line (DL1-2) of the first data line (DL1) may be placed on the same layer as the second-2 data line (DL2-2) of the second data line (DL2).

[0151] FIGS. 10a to 10d are plan views schematically illustrating a display device according to one embodiment. Specifically, FIG. 10a is a plan view schematically illustrating a display device according to one embodiment, FIG. 10b is an enlarged view of part B of FIG. 10a, and FIG. 10c and FIG. 10d are enlarged views of part C of FIG. 10b.

[0152] FIG. 10a illustrates data lines (DL) arranged in the first fan-out section (21) and data lines (DL) arranged in the second fan-out section (22). FIG. 10a illustrates that four data lines (DL) are arranged in each of the first fan-out section (21) and the second fan-out section (22) for convenience of explanation, but the present invention is not limited thereto.

[0153] Referring to FIG. 10a, the fan-out section (20) may include a first fan-out section (21) and a second fan-out section (22), and data lines (DL) may be arranged in the first fan-out section (21) and the second fan-out section (22). The data lines (DL) arranged in the first fan-out section (21) and the second fan-out section (22) may be at least one of the first data lines (DL1) and the second data lines (DL2).

[0154] In one embodiment, a gap (SA) may be located between the first fan-out portion (21) and the second fan-out portion (22).

[0155] In one embodiment, a plurality of data lines (DL) may be placed on a first area (1A), a bending area (BA), a second area (2A), and a pad area (PDA). As described above in FIG. 8, each data line (DL) placed on the first area (1A), the bending area (BA), the second area (2A), and the pad area (PDA) may be placed on different layers rather than being integrally provided on the same layer, and may be electrically connected through contact holes.

[0156] In one embodiment, the first data line (DL1) may include a first-1 data line (DL1-1), a first-2 data line (DL1-2), a first-3 data line (DL1-3), and a first-4 data line (DL1-4). In one embodiment, the first-1 data line (DL1-1) may be placed on the second area (2A), the first-2 data line (DL1-2) may be placed on the pad area (PDA), the first-3 data line (DL1-3) may be placed on the bending area (BA), and the first-4 data line (DL1-4) may be placed on the first area (1A).

[0157] Additionally, the second data line (DL2) may include a second-1 data line (DL2-1), a second-2 data line (DL2-2), a second-3 data line (DL2-3), and a second-4 data line (DL2-4). The second-1 data line (DL2-1) may be placed on the second area (2A), the second-2 data line (DL2-2) may be placed on the pad area (PDA), the second-3 data line (DL2-3) may be placed on the bending area (BA), and the second-4 data line (DL2-4) may be placed on the first area (1A).

[0158] In one embodiment, the first-1 data line (DL1-1) and the second-1 data line (DL2-1) may be provided with a first material, and the first-2 data line (DL1-2) and the second-2 data line (DL2-2) may be provided with a second material different from the first material. Additionally, the first-3 data line (DL1-3) and the second-3 data line (DL2-3) may be provided with a first material, and the first-4 data line (DL1-4) and the second-4 data line (DL2-4) may be provided with a second material. That is, the first-1 data line (DL1-1), the second-1 data line (DL2-1), the first-3 data line (DL1-3), and the second-3 data line (DL2-3) may be provided with a first material, and the first-2 data line (DL1-2), the second-2 data line (DL2-2), the first-4 data line (DL1-4), and the second-4 data line (DL2-4) may be provided with a second material different from the first material. In this case, the resistivity of the first material may be lower than the resistivity of the second material. In one embodiment, the first material may be aluminum (Al) or titanium (Ti), and the second material may be molybdenum (Mo). However, the present invention is not limited thereto.

[0159] In one embodiment, assuming that the total length of the first data line (DL1) is constant, if the lengths of the first-1 data line (DL1-1) and the first-3 data line (DL1-3) made of the first material increase, and the lengths of the first-2 data line (DL1-2) and the first-4 data line (DL1-4) made of the second material decrease, the total resistance of the first data line (DL1) may decrease. Conversely, assuming that the total length of the first data line (DL1) is constant, if the lengths of the first-1 data line (DL1-1) and the first-3 data line (DL1-3) made of the first material decrease, and the lengths of the first-2 data line (DL1-2) and the first-4 data line (DL1-4) made of the second material increase, the total resistance of the first data line (DL1) may increase. This may be applied equally to the second data line (DL2).

[0160] Referring to FIG. 10b, data lines (DL) may be arranged in the second area (2A) and the pad area (PDA). The data lines (DL) may include first data lines (DL1) and second data lines (DL2). Accordingly, first data lines (DL1) and second data lines (DL2) may be arranged in the second area (2A) and the pad area (PDA). In one embodiment, the first data lines (DL1) and the second data lines (DL2) may be arranged alternately in a first direction (X direction). For example, the first data line (DL1), the second data line (DL2), the first data line (DL1), and the second data line (DL2) may be arranged sequentially along the first direction (X direction). However, the present invention is not limited thereto.

[0161] In one embodiment, the first data lines (DL1) and the second data lines (DL2) may be placed in the first fan-out section (21) and the second fan-out section (22). In one embodiment, the first data line (DL1) may be placed at the leftmost part of the first fan-out section (21) (the beginning part of the first fan-out section (21)), and the second data line (DL2) may be placed at the rightmost part of the first fan-out section (21) (the end part of the first fan-out section (21)). Additionally, in one embodiment, the first data line (DL1) may be placed at the leftmost part of the second fan-out section (22) (the beginning part of the second fan-out section (22)). However, the present invention is not limited thereto.

[0162] Each first data line (DL1) may include a first-1 data line (DL1-1) and a first-2 data line (DL1-2). Additionally, each second data line (DL2) may include a second-1 data line (DL2-1) and a second-2 data line (DL2-2). The first-1 data line (DL1-1) and the second-1 data line (DL2-1) may be placed on the second area (2A), and the first-2 data line (DL1-2) and the second-2 data line (DL2-2) may be placed on the pad area (PDA). The first-2 data line (DL1-2) and the second-2 data line (DL2-2) placed on the pad area (PDA) may be extended at least partially into the second area (2A).

[0163] In one embodiment, the first-1 data line (DL1-1) and the first-2 data line (DL1-2) of the first data line (DL1) may be electrically connected through a contact hole (CNT) located on the second region (2A). At this time, the contact hole (CNT) may be the first contact hole (CNT1) described above in FIG. 8.

[0164] Additionally, in one embodiment, the second-1 data line (DL2-1) and the second-2 data line (DL2-2) of the second data line (DL2) can be electrically connected through a contact hole (CNT) located on the second region (2A).

[0165] In one embodiment, among the contact holes (CNTs) located on the second region (2A), the contact hole (CNT) located closest to the pad region (PDA) in the second direction (Y direction) may be spaced at least 10 μm apart in the second direction (Y direction) from the inspection circuit portion (35) placed on the pad region (PDA).

[0166] In one embodiment, since a plurality of first data lines (DL1) and a plurality of second data lines (DL2) may be arranged in the first fan-out portion (21), a plurality of contact holes (CNT) may be located in the first fan-out portion (21). The positions of the plurality of contact holes (CNT) in the first fan-out portion (21) may gradually become closer to the display portion (10, FIG. 10a) as they move from the left to the right of the first fan-out portion (21). That is, the contact holes (CNT) located on the right side of the first fan-out portion (21) (the end of the first fan-out portion (21)) may be located closer to the display portion (10, FIG. 10a) than the contact holes (CNT) located on the left side of the first fan-out portion (21) (the beginning of the first fan-out portion (21)). However, the present invention is not limited thereto. The contact holes (CNTs) located in the first fan-out section (21) to the right of the second fan-out section (22) can gradually move away from the display section (10, FIG. 10a) as they go from the left to the right of the first fan-out section (21).

[0167] Referring to FIG. 10c, the contact holes (CNTs) located in the first fan-out section (21) may repeatedly rise and fall, and may gradually become closer to the display section (10, FIG. 2a) as they move from the left to the right of the first fan-out section (21). For example, three contact holes (CNTs) may form a unit and repeatedly rise and fall in the second direction (Y direction), and may gradually become closer to the display section (10, FIG. 2a) as they move from the left to the right of the first fan-out section (21). However, the present invention is not limited thereto. Various variations are possible for the unit of contact holes (CNTs) that repeatedly rise and fall in the second direction (Y direction), such as two or four.

[0168] In addition, the contact holes (CNTs) located in the second fan-out section (22) can also likewise form a unit of three contact holes (CNTs) and repeatedly rise and fall in the second direction (Y direction).

[0169] Referring to FIG. 10d, the contact holes (CNTs) located in the first fan-out portion (21) can gradually get closer to the display portion (10, FIG. 2a) as they move from the left to the right of the first fan-out portion (21).

[0170] In one embodiment, since a plurality of first data lines (DL1) and a plurality of second data lines (DL2) may be arranged in the second fan-out portion (22), a plurality of contact holes (CNT) may be located in the second fan-out portion (22). The positions of the plurality of contact holes (CNT) in the second fan-out portion (22) may gradually become closer to the display portion (10, FIG. 10a) as one moves from the left to the right of the second fan-out portion (22). However, when viewed as a whole, the positions of the plurality of contact holes (CNT) in the second fan-out portion (22) may gradually become closer to the display portion (10, FIG. 10a) as one moves from the left to the right of the second fan-out portion (22), and then become further away again.

[0171] A plurality of data lines (DL) arranged in the first fan-out portion (21) may be formed with different lengths. Accordingly, the resistance of each of the plurality of data lines (DL) arranged in the first fan-out portion (21) may be different. For example, if the length of the data line (DL) is long, the total resistance of the data line (DL) may increase, and if the length of the data line (DL) is short, the total resistance of the data line (DL) may decrease.

[0172] Specifically, a plurality of first data lines (DL1) and a plurality of second data lines (DL2) arranged in the first fan-out portion (21) may be formed with different lengths. Accordingly, the respective resistances of the plurality of first data lines (DL1) and a plurality of second data lines (DL2) arranged in the first fan-out portion (21) may be different. For example, if the length of the data lines (DL1, DL2) is long, the total resistance of the data lines (DL1, DL2) may increase, and if the length of the data lines (DL1, DL2) is short, the total resistance of the data lines (DL1, DL2) may decrease.

[0173] Additionally, when a plurality of data lines (DL) arranged in the first fan-out portion (21) have different lengths, the plurality of data lines (DL) may each have different resistances, and due to the difference in resistance of each of the plurality of data lines (DL), an abnormality in black luminance may occur, crosstalk may increase, or stain defects may occur.

[0174] Assuming that the total length of one data line (DL1, DL2) is constant, if the length of the part equipped with a low resistivity material increases and the length of the part equipped with a high resistivity material decreases, the total resistance of the data line (DL1, DL2) can be reduced.

[0175] In one embodiment, the total resistance of the data lines (DL1, DL2) can be controlled by adjusting the position of the contact hole (CNT) in the second region (2A). For example, the total resistance of the data lines (DL1, DL2) can be reduced by increasing the length of the first-1 data line (DL1-1) and the second-1 data line (DL2-1) provided with the first material, and decreasing the length of the first-2 data line (DL1-2) and the second-2 data line (DL2-2) provided with the second material having a higher resistivity than the first material, and conversely, the total resistance of the data lines (DL1, DL2) can be increased.

[0176] Accordingly, by adjusting the position of the contact holes (CNTs) located in the first fan-out portion (21), the resistance difference (deviation) between the data lines (DL1, DL2) can be reduced, and the visibility of the display device can be improved.

[0177] As described above, since the first-4 data line (DL1-4) and the second-4 data line (DL2-4) are provided with a material having high resistivity, if the length of the first-4 data line (DL1-4) and the second-4 data line (DL2-4) increases, the resistance of the data lines (DL1, DL2) may increase.

[0178] Alternatively, if there is a difference in length between the first-fourth data line (DL1-4) and the second-fourth data line (DL2-4), there may be a difference in resistance (deviation) between the first-fourth data line (DL1-4) and the second-fourth data line (DL2-4).

[0179] Referring to FIG. 10a and FIG. 10b, there may be a difference in resistance between the data lines (DL1, DL2) placed in the first fan-out section (21) and the second fan-out section (22). When comparing the data line placed at the far right of the first fan-out section (21) (e.g., the second data line (DL2)) and the data line placed at the far left of the second fan-out section (22) (e.g., the first data line (DL1)), there may be a difference in resistance (deviation) between the data line placed at the far right of the first fan-out section (21) (e.g., the second data line (DL2)) and the data line placed at the far left of the second fan-out section (22) (e.g., the first data line (DL1)) due to the difference in length between the first-fourth data line (DL1-4) and the second-fourth data line (DL2-4). For example, the length of the first-fourth data line (DL1-4) positioned at the far left of the second fan-out section (22) may be longer than the length of the second-fourth data line (DL2-4) positioned at the far right of the first fan-out section (21), so that the resistance of the data line positioned at the far left of the second fan-out section (22) (e.g., the first data line (DL1)) may be greater than the resistance of the data line positioned at the far right of the first fan-out section (21) (e.g., the second data line (DL2)). Due to the difference in resistance between the closest data lines (DL1, DL2) with the separation section (SA) in between, an abnormality in black luminance may occur, crosstalk may increase, or stain defects may occur.

[0180] In one embodiment, when the position of the contact hole (CNT) electrically connecting the first-1 data line (DL1-1) and the first-2 data line (DL1-2) moves closer to the display unit (10) in the second direction (Y direction), the length of the first-1 data line (DL1-1) may be reduced and the length of the first-2 data line (DL1-2) may be increased. Conversely, when the position of the contact hole (CNT) moves away from the display unit (10) in the second direction (Y direction), the length of the first-1 data line (DL1-1) may be increased and the length of the first-2 data line (DL1-2) may be reduced.

[0181] In one embodiment, when the length of the first-1 data line (DL1-1) increases and the length of the first-2 data line (DL1-2) decreases, the total resistance of the data line (e.g., the first data line (DL1)) may decrease, and when the length of the first-1 data line (DL1-1) decreases and the length of the first-2 data line (DL1-2) increases, the total resistance of the data line (e.g., the second data line (DL2)) may increase.

[0182] Accordingly, when the position of the contact hole (CNT) electrically connecting the first-1 data line (DL1-1) and the first-2 data line (DL1-2) moves closer to the display unit (10) in the second direction (Y direction), the length of the first-1 data line (DL1-1) decreases and the length of the first-2 data line (DL1-2) increases, so that the total resistance of the data line (e.g., the first data line (DL1)) may increase. Additionally, when the position of the contact hole (CNT) moves away from the display unit (10) in the second direction (Y direction), the length of the first-1 data line (DL1-1) increases and the length of the first-2 data line (DL1-2) decreases, so that the total resistance of the data line (e.g., the first data line (DL1)) may decrease. This can be applied equally to the second data line (DL2).

[0183] In one embodiment, by positioning the contact hole (CNT) located at the far right of the first fan-out portion (21) closer to the display portion (10) than the contact hole (CNT) located at the far left of the second fan-out portion (22), the total resistance of the data line (e.g., second data line (DL2)) located at the far right of the first fan-out portion (21) can be increased, and the total resistance of the data line (e.g., first data line (DL1)) located at the far left of the second fan-out portion (22) can be decreased. Accordingly, the resistance difference (deviation) between the data line (e.g., second data line (DL2)) located at the far right of the first fan-out portion (21) and the data line (e.g., first data line (DL1)) located at the far left of the second fan-out portion (22) can be reduced. In addition, by reducing the resistance difference (deviation) between the data line positioned at the far right of the first fan-out section (21) (e.g., second data line (DL2)) and the data line positioned at the far left of the second fan-out section (22) (e.g., first data line (DL1)), it is possible to prevent or minimize the occurrence of black luminance abnormalities, increased crosstalk, and stain defects.

[0184] FIG. 11 is a plan view schematically illustrating a display device according to one embodiment, and FIG. 12 is a cross-sectional view schematically illustrating a display device according to one embodiment. The embodiments of FIG. 11 and FIG. 12 differ from the embodiments of FIG. 6 and FIG. 8 in that a driving power supply line (40) and a common power supply line (45) are further disposed on the first flattening layer (111). In FIG. 11 and FIG. 12, the same reference numerals as in FIG. 6 and FIG. 8 refer to the same components, so their redundant description is omitted.

[0185] Referring to FIGS. 11 and FIGS. 12, a driving power supply line (40) and a common power supply line (45) may be arranged on the non-display area (NDA).

[0186] At least a portion of the drive power supply line (40) may be positioned on the separation portion (SA). That is, at least a portion of the drive power supply line (40) may be positioned on the separation portion (SA), i.e., between the first fan-out portion (21) and the second fan-out portion (22).

[0187] At least a portion of the common power supply line (45) may be positioned outside the fan-out section (20). Although not illustrated, the common power supply line (45) may have a loop shape with one side open to partially surround the display area (DA).

[0188] The driving power supply line (40) and the common power supply line (45) may be arranged across the first area (1A), the bending area (BA), the second area (2A), and the pad area (PDA). For example, the driving power supply line (40) and the common power supply line (45) may overlap at least partially with the first area (1A), the bending area (BA), the second area (2A), and the pad area (PDA).

[0189] In one embodiment, the driving power supply line (40) and the common power supply line (45) may overlap at least partially with the data lines (e.g., the first data line (DL1), and / or the second data line (DL2)). In one embodiment, the driving power supply line (40) and the common power supply line (45) may be placed on the first flattening layer (111). The driving power supply line (40) and the common power supply line (45) may be placed on the same layer as the first-third data lines (DL1-3) and may be made of the same material.

[0190] FIG. 13 is a plan view schematically illustrating a display device according to one embodiment, and FIG. 14 and FIG. 15 are cross-sectional views schematically illustrating a display device according to one embodiment. FIG. 14 is a cross-sectional view taken along line IV-IV' of FIG. 13, and FIG. 15 is a cross-sectional view taken along line VV' of FIG. 13. The embodiment of FIG. 13 to FIG. 15 differs from the embodiment of FIG. 7 to FIG. 9 in that the first-1 data line (DL1-1) includes a first part (DL1-1a) and a second part (DL1-1b), and the first-1 data line (DL1-1) and the second-1 data line (DL2-1) overlap at least partially. In FIG. 13 to FIG. 15, the same reference numerals as in FIG. 7 to FIG. 9 refer to the same components, so their redundant description is omitted.

[0191] In FIG. 13, a first data line (DL1) and a second data line (DL2) are shown adjacent to each other in the first fan-out section (21), and a first data line (DL1) and a second data line (DL2) are shown adjacent to each other in the second fan-out section (22). The remaining data lines that are arranged consecutively in the first fan-out section (21) and the second fan-out section (22), respectively, have been omitted for convenience of explanation. A gap (SA) may be formed between the second data line (DL2) of the first fan-out section (21) and the first data line (DL1) of the second fan-out section (22) that are adjacent to each other.

[0192] Referring to FIGS. 13 and 14, the first data line (DL1) may include a first-1 data line (DL1-1) and a first-2 data line (DL1-2), and the second data line (DL2) may include a second-1 data line (DL2-1) and a second-2 data line (DL2-2).

[0193] In one embodiment, the first-1 data line (DL1-1) and the first-2 data line (DL1-2) of the first data line (DL1) may be electrically connected through a contact hole (e.g., the first contact hole (CNT1)) located on the second area (2A). Also, in one embodiment, the second-1 data line (DL2-1) and the second-2 data line (DL2-2) of the second data line (DL2) may be electrically connected through a contact hole (e.g., the fourth contact hole (CNT4)) located on the second area (2A). The fourth contact hole (CNT4) illustrated in FIG. 13 may refer to the same contact hole as the contact hole (CNT) described in FIG. 10a through 10d.

[0194] In one embodiment, the first-2 data line (DL1-2) may be placed on the first insulating layer (103), and the second-2 data line (DL2-2) may be placed on the second insulating layer (105). Although not illustrated, the first-2 data line (DL1-2) may be placed on the second insulating layer (105), and the second-2 data line (DL2-2) may be placed on the first insulating layer (103). Additionally, the first-2 data line (DL1-2) and the second-2 data line (DL2-2) may be placed on the same layer.

[0195] In one embodiment, the first-second data line (DL1-2) disposed on the first insulating layer (103) may have a first width (W1).

[0196] Referring to FIG. 15, in one embodiment, a first-1 data line (DL1-1) may include a first portion (DL1-1a) and a second portion (DL1-1b) disposed on different layers. Specifically, the first-1 data line (DL1-1) may include a first portion (DL1-1a) disposed on a first insulating layer (103) and a second portion (DL1-1b) disposed on a second insulating layer (105). The first portion (DL1-1a) and the second portion (DL1-1b) of the first-1 data line (DL1-1) may overlap at least partially.

[0197] In one embodiment, the first part (DL1-1a) and the second part (DL1-1b) of the first-1 data line (DL1-1) may be parts into which a single first-2 data line (DL1-2) is divided into two. For example, the first part (DL1-1a) of the first-1 data line (DL1-1) may be a part where the first-2 data line (DL1-2) is extended as is, and the second part (DL1-1b) of the first-1 data line (DL1-1) may be a layer electrically connected to the first-2 data line (DL1-2) through a contact hole (e.g., a first contact hole (CNT1)). Accordingly, the same signal may be applied to the first part (DL1-1a) and the second part (DL1-1b) of the first-1 data line (DL1-1).

[0198] In one embodiment, the second-1 data line (DL2-1) may be placed on the first planarization layer (111). The second-1 data line (DL2-1) may be placed on the same layer as the contact metal layer (CM, FIG. 5) and may be made of the same material. In one embodiment, the second-1 data line (DL2-1) may overlap at least partially with the first portion (DL1-1a) and / or the second portion (DL1-1b) of the first-1 data line (DL1-1).

[0199] Since different signals are applied to the overlapping 2-1 data line (DL2-1) and 1-1 data line (DL1-1), coupling may occur, resulting in a luminance deviation.

[0200] In one embodiment, a shielding layer (40, 45) may be disposed between the second-1 data line (DL2-1) and the first-1 data line (DL1-1). The shielding layer (40, 45) may be disposed on the third insulating layer (107). The shielding layer (40, 45) may be disposed on the same layer as the source electrode (137, FIG. 5), which is the connecting electrode, and may be made of the same material. In one embodiment, the shielding layer (40, 45) may be at least one of the driving power supply line (40) and the common power supply line (45).

[0201] By placing a shielding layer (40, 45) between the overlapping 2-1 data line (DL2-1) and 1-1 data line (DL1-1), the occurrence of brightness deviation due to coupling can be prevented or minimized.

[0202] The first-2 data line (DL1-2) and the second-2 data line (DL2-2) may be placed on different layers. For example, the first-2 data line (DL1-2) may be placed on the first insulating layer (103), and the second-2 data line (DL2-2) may be placed on the second insulating layer (105).

[0203] A second-2 data line (DL2-2) disposed on the second insulating layer (105) can be electrically connected to a second-1 data line (DL2-1) disposed on the first flattening layer (111) through a contact hole (e.g., a fourth contact hole (CNT4)). Since the second-2 data line (DL2-2) is electrically connected to the second-1 data line (DL2-1) disposed on the first flattening layer (111) through a contact hole (e.g., a fourth contact hole (CNT4)), a second portion (DL1-1b) of the first-1 data line (DL1-1) can be disposed on the second insulating layer (105) disposed below the second-1 data line (DL2-1).

[0204] At least a portion of the first-2 data line (DL1-2) disposed on the first insulating layer (103) may extend toward the second region (2A) to form the first portion (DL1-1a) of the first-1 data line (DL1-1). Additionally, at least a portion of the first-2 data line (DL1-2) disposed on the first insulating layer (103) may be electrically connected to the second portion (DL1-1b) of the first-1 data line (DL1-1) disposed on the second insulating layer (105) through a contact hole (e.g., the first contact hole (CNT1)).

[0205] Therefore, since the first part (DL1-1a) and the second part (DL1-1b) of the first-1 data line (DL1-1) are formed through a single first-2 data line (DL1-2), the same signal can be applied to the first part (DL1-1a) and the second part (DL1-1b) of the first-1 data line (DL1-1). Since the same signal is applied to the first part (DL1-1a) and the second part (DL1-1b) of the first-1 data line (DL1-1), even if the first part (DL1-1a) and the second part (DL1-1b) are arranged to overlap each other, a luminance deviation (difference) due to coupling may not occur.

[0206] In one embodiment, the first part (DL1-1a) and the second part (DL1-1b) of the first-1 data line (DL1-1) may have a second width (W2) that is different from the first width (W1) of the first-2 data line (DL1-2). In one embodiment, the second width (W2) may be provided to be larger than the first width (W1). Accordingly, the first part (DL1-1a) and the second part (DL1-1b) of the first-1 data line (DL1-1) may have a wider width than the first-2 data line (DL1-2). By increasing the width of the first part (DL1-1a) and the second part (DL1-1b) of the first-1 data line (DL1-1), the total resistance of the data line may be reduced.

[0207] In FIGS. 13 to 15, the first-1 data line (DL1-1) of the first data line (DL1) is shown divided into two parts, and the width of the divided parts is shown to be increased compared to the existing width, but the present invention is not limited thereto. Although not shown, the second-1 data line (DL2-1) of the second data line (DL2) may be divided into two parts, and the width of the divided parts may be shown to be wider than the existing width.

[0208] FIG. 16 is a cross-sectional view schematically illustrating a display device according to one embodiment. The embodiment of FIG. 16 differs from the embodiment of FIG. 15 in that a third part (DL1-1c) is further provided in the fourth insulating layer (109) and the first-1 data line (DL1-1). In FIG. 16, the same reference numerals as in FIG. 15 refer to the same components, so a redundant description thereof is omitted.

[0209] Referring to FIG. 16, a fourth insulating layer (109) may be disposed on the third insulating layer (107). The first-1 data line (DL1-1) may include a first part (DL1-1a), a second part (DL1-1b), and a third part (DL1-1c). The first part (DL1-1a), the second part (DL1-1b), and the third part (DL1-1c) may overlap at least partially with each other. Additionally, the same signal may be applied to the first part (DL1-1a), the second part (DL1-1b), and the third part (DL1-1c).

[0210] The second-1 data line (DL2-1) may be placed on the first flattening layer (111). The first portion (DL1-1a), second portion (DL1-1b), and third portion (DL1-1c) of the second-1 data line (DL2-1) and the first-1 data line (DL1-1) may overlap at least partially.

[0211] A shielding layer (40, 45) may be disposed between the second-1 data line (DL2-1) and the first-1 data line (DL1-1). The shielding layer (40, 45) may be disposed on the fourth insulating layer (109). In one embodiment, the shielding layer (40, 45) may be at least one of a driving power supply line (40) and a common power supply line (45).

[0212] By including a first part (DL1-1a), a second part (DL1-1b), and a third part (DL1-1c) that overlap each other, the resistance of the data line (e.g., the first data line (DL1)) can be reduced more effectively.

[0213] In one embodiment, a data line (e.g., a first data line (DL1)) may be provided as a first-1 data line (DL1-1) placed on a second area (2A), a first-2 data line (DL1-2) placed on a pad area (PDA), a first-3 data line (DL1-3) placed on a bending area (BA), and a first-4 data line (DL1-4) on a first area (1A).

[0214] In one embodiment, the first-1 data line (DL1-1) disposed on the second region (2A) is provided with a material having low resistivity, thereby reducing the total resistance of the data line (e.g., the first data line (DL1)), so that a display device (1) capable of high-speed driving of 120 Hz or higher can be provided, and by enabling high-speed driving of 120 Hz or higher, the resolution of the display device (1) can be increased and the quality of the display device (1) can be improved at the same time. In addition, by reducing the total resistance of the data line (e.g., the first data line (DL1)), the on-time of the scan signal can be secured, so that the occurrence of black luminance abnormality, increased crosstalk, and stain defects can be prevented or minimized.

[0215] In one embodiment, by adjusting the position of the contact hole (CNT) that electrically connects the first-1 data line (DL1-1) placed on the second region (2A) and the first-2 data line (DL1-2) placed on the pad region (PDA), it is possible to prevent or minimize the occurrence of a resistance difference caused by a length difference between different blocks (e.g., the first fan-out portion (21) and the second fan-out portion (22)).

[0216] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0217] DL1: 1st data line DL1-1 to DL1-4: Data lines 1-1 to 1-4 DL2-1 to DL2-4: Data lines 2-1 to 2-4 DL1-1a to DL1-1c: Part 1 to Part 3 1: Display device 100: Substrate 10: Display section 30: Driving circuit section

Claims

Claim 1 A display device comprises: a substrate having a non-display area including a display area, a first area, a second area, a bending area disposed between the first area and the second area, and a pad area; a display unit disposed on the display area; a driving circuit unit disposed on the non-display area; a fan-out unit disposed on the first area, the bending area, and the second area between the display unit and the driving circuit unit, and transmitting a data signal applied from the driving circuit unit to the display unit; a first insulating layer disposed on the substrate and comprising an inorganic insulating material; a second insulating layer disposed on the first insulating layer and comprising an inorganic insulating material; and a first planarization layer disposed on the second insulating layer and comprising an organic material. A display device comprising: an organic insulating layer comprising an organic material disposed within an opening defined in the bending region; wherein the fan-out portion comprises a first data line, the first data line comprises a first-1 data line disposed on the second region, a first-2 data line disposed on the pad region, and a first-3 data line disposed on the bending region, wherein the first-1 data line is located between the second insulating layer and the first flattening layer, the first-2 data line is located between the first insulating layer and the second insulating layer, and the first-3 data line is disposed on the organic insulating layer. Claim 2 delete Claim 3 A display device according to claim 1, wherein the first-1 data line and the first-2 data line are provided with different materials. Claim 4 A display device according to claim 1, wherein the fan-out portion comprises a second data line including a second-1 data line disposed on the second region and a second-2 data line disposed on the pad region but on a layer different from the second-1 data line. Claim 5 A display device according to claim 4, wherein the first-1 data line and the second-1 data line are placed on the same layer. Claim 6 A display device according to claim 4, wherein the first-2 data line and the second-2 data line are disposed on different layers. Claim 7 A display device according to claim 4, wherein the fan-out portion further comprises a first fan-out portion, a second fan-out portion, and a spaced portion between the first fan-out portion and the second fan-out portion. Claim 8 A display device according to claim 7, wherein the first-1 data line and the first-2 data line are electrically connected through a first contact hole located in the second area. Claim 9 In claim 8, the position of the first contact hole within the first fan-out portion gradually moves closer to or further away from the display portion, a display device. Claim 10 A display device according to claim 9, wherein the 2-1 data line and the 2-2 data line are electrically connected through a second contact hole located in the second area. Claim 11 A display device according to claim 10, wherein, in the second data line and the first data line arranged closest to each other with the above-mentioned separation portion in between, the second contact hole that electrically connects the second-1 data line and the second-2 data line of the second data line is located closer to the display portion than the first contact hole that electrically connects the first-1 data line and the first-2 data line of the first data line. Claim 12 In paragraph 1, the display device is a display device that folds around a folding axis. Claim 13 A display device comprising: a substrate having a non-display area including a display area, a first area, a second area, a bending area disposed between the first area and the second area, and a pad area; a display portion disposed on the display area; a driving circuit portion disposed on the non-display area; and a fan-out portion disposed on the first area, the bending area, and the second area between the display portion and the driving circuit portion, and transmitting a data signal applied from the driving circuit portion to the display portion; wherein the fan-out portion includes a first data line, and the first data line includes a first-1 data line disposed on the second area and comprising a first portion and a second portion disposed on different layers; and a first-2 data line disposed on the pad area and disposed on the same layer as the first portion or the second portion. Claim 14 A display device according to claim 13, wherein the same signal is applied to the first part and the second part. Claim 15 In paragraph 13, a display device wherein the first part and the second part overlap at least partially. Claim 16 A display device according to claim 13, wherein the first-2 data lines have a first width, and the first portion has a second width greater than the first width. Claim 17 A display device according to claim 13, wherein the fan-out portion comprises a second data line including a second-1 data line disposed on the second region and a second-2 data line disposed on the pad region but on a layer different from the second-1 data line. Claim 18 In claim 17, the above 2-2 data line is a display device disposed on the same layer as the above 1 part or the above 2 part. Claim 19 In paragraph 17, the above-mentioned 2-1 data line is a display device that overlaps at least partially with the above-mentioned 1 part. Claim 20 A display device according to claim 19, further comprising a shielding layer interposed between the first-1 data line and the second-1 data line. Claim 21 A display device that folds based on a folding axis, comprising: a substrate having a non-display area having a display area, a first area, a second area, a bending area disposed between the first area and the second area, and a pad area; a display unit disposed on the display area; a driving circuit unit disposed on the non-display area; and a fan-out unit disposed on the first area, the bending area, and the second area between the display unit and the driving circuit unit, and transmitting a data signal applied from the driving circuit unit to the display unit; wherein the fan-out unit includes a first data line, the first data line includes a first-1 data line and a first-2 data line disposed on different layers, and the first-1 data line includes a first part and a second part disposed on different layers. Claim 22 A display device according to claim 21, wherein the first-1 data line is placed on the second area and the first-2 data line is placed on the pad area.

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