Semiconductor device and capacitor including hydrogen-incorporated oxide layer

Abstract

A semiconductor device and a capacitor having low leakage current are disclosed. The disclosed semiconductor device comprises a semiconductor layer; an oxide layer disposed on the semiconductor layer; and a metal layer disposed on the oxide layer; wherein the hydrogen concentration in the oxide layer may be 0.7 at% or higher.

Description

Technology Field

[0001] The disclosed embodiments relate to semiconductor devices and capacitors, and more specifically, to semiconductor devices and capacitors comprising an oxide layer containing hydrogen at a concentration greater than a predetermined concentration. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) operate by utilizing a gate oxide layer to transmit the electric field from the gate to the channel. However, as semiconductor devices become more integrated and ultra-thin, the thickness of the gate oxide layer becomes very thin, leading to an increase in leakage current and causing various problems. Leakage current is closely related to the concentration of traps within the oxide layer, and oxygen vacancies present within the oxide layer are a typical example of a trap.

[0003] To reduce leakage current, heat treatment can be performed in an oxygen-containing atmosphere. Leakage current characteristics can be improved by eliminating oxygen vacancies through oxygen heat treatment. However, the thickness of the interface layer, which is intended to suppress the formation of interface traps between the oxide layer and the silicon substrate, may increase due to the oxygen heat treatment. Since the interface layer, which is silicon oxide, has a relatively low dielectric constant, the total capacitance of the metal oxide semiconductor field-effect transistor may degrade if the thickness of the interface layer is excessive. The problem to be solved

[0004] A semiconductor device and a capacitor with low leakage current are provided.

[0005] In addition, by maintaining a thin thickness of the interface layer, a semiconductor device and a capacitor are provided that do not experience capacitance degradation.

[0006] In particular, a semiconductor device and a capacitor are provided that include an oxide layer containing hydrogen at a concentration greater than a predetermined concentration. means of solving the problem

[0007] According to one embodiment, a semiconductor device may be provided comprising: a semiconductor layer; an oxide layer disposed on the semiconductor layer; and a metal layer disposed on the oxide layer, wherein the hydrogen concentration in the oxide layer may be, for example, about 0.7 at% or more.

[0008] The oxide layer may include, for example, a ferroelectric material.

[0009] The above oxide layer may have a crystalline structure.

[0010] For example, the oxide layer is HfO2, ZrO2, and Hf x Zr 1-x It may include at least one material selected from O2 (0 < x < 1).

[0011] In addition, the oxide layer may further include at least one dopant selected from, for example, Al, La, Y, Si, Sr, Gd, and Ge.

[0012] The hydrogen concentration in the oxide layer may be, for example, 10 at% or less.

[0013] The hydrogen concentration in the oxide layer may be, for example, about 1 at% to about 5 at%.

[0014] The semiconductor layer may include a semiconductor substrate doped with a first conductivity type; and a source region and a drain region formed in an upper region of the semiconductor substrate, each doped with a second conductivity type electrically opposite to the first conductivity type.

[0015] The oxide layer can be disposed on the upper surface of the semiconductor substrate between the source region and the drain region.

[0016] It may further include an interface layer disposed between the semiconductor substrate and the oxide layer.

[0017] The above interface layer may include an oxide of the semiconductor material of the semiconductor substrate.

[0018] The semiconductor device may further include a source electrode disposed over the source region and a drain electrode disposed over the drain region.

[0019] Additionally, according to another embodiment, a capacitor may be provided comprising: a first metal layer; an oxide layer disposed on the first metal layer; and a second metal layer disposed on the oxide layer, wherein the hydrogen concentration in the oxide layer may be, for example, about 0.7 at% or more.

[0020] The first metal layer and the second metal layer may comprise at least one metal material selected from, for example, Ti, TiN, TiAlN, TiAl, Ta, TaN W, WN, Mo, Ru, RuO, Pt, and Ni.

[0021] In addition, according to another embodiment, a memory device comprising a semiconductor device having the above-described configuration and a capacitor having the above-described configuration may be provided. Effects of the invention

[0022] According to the disclosed embodiment, by intentionally injecting hydrogen into an oxide layer within a semiconductor device or capacitor, the oxide layer within the semiconductor device or capacitor may contain hydrogen at a concentration greater than a predetermined level. Monatomic hydrogen within the oxide layer formed by hydrogen treatment can passivate oxygen vacancies, thereby hindering the movement of electrons through the oxide layer. Consequently, leakage current in the oxide layer within the semiconductor device or capacitor can be reduced or prevented. Furthermore, since oxygen heat treatment is not performed, the increase in the thickness of the interface layer is prevented, thereby preventing the deterioration of the capacitance of the semiconductor device or capacitor. Brief explanation of the drawing

[0023] FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor device according to one embodiment. Figure 2 schematically shows the process of hydrogenating the oxide layer after forming the oxide layer. Figure 3 schematically shows the process of hydrogenating the oxide layer after first depositing a metal material. Figure 4 is a graph showing the change in hydrogen concentration in the oxide layer, interface layer, and semiconductor layer after hydrogen treatment. Figure 5 is a schematic diagram showing the cause of leakage current in the comparative example. Figure 6 is a schematic diagram showing the cause of the reduction in leakage current in the embodiment. Figure 7 is a graph showing a comparison of leakage currents in the comparative example and the example. Figure 8 is a graph showing a comparison of capacitance in comparative examples and embodiments. FIG. 9 is a cross-sectional view schematically showing the configuration of a capacitor according to another embodiment. Figure 10 shows the circuit configuration of a memory cell of a memory device including a semiconductor element and a capacitor. Specific details for implementing the invention

[0024] Hereinafter, a semiconductor device and a capacitor comprising a hydrogen-containing oxide layer will be described in detail with reference to the attached drawings. In the drawings below, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of explanation. Furthermore, the embodiments described below are merely illustrative, and various modifications are possible from these embodiments.

[0025] In the following, terms designated as "upper" or "upper" may include not only those directly above in contact but also those above non-contact. Singular expressions include multiple expressions unless the context clearly indicates otherwise. Furthermore, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0026] The use of the term "for example" and similar descriptive terms may apply to both the singular and the plural. Unless there is an explicit description of the order of the steps constituting the method, these steps may be performed in a suitable order and are not necessarily limited to the described order.

[0027] Additionally, terms such as "...part," "module," etc., as described in the specification refer to a unit that processes at least one function or operation, and this may be implemented in hardware or software, or as a combination of hardware and software.

[0028] The connections of lines or connecting members between the components shown in the drawings are exemplary representations of functional connections and / or physical or circuit connections, and may be replaced or additionally represented as various functional connections, physical connections, or circuit connections in the actual device.

[0029] All examples or the use of exemplary terms are merely for the purpose of describing technical ideas in detail, and unless limited by the claims, the scope is not limited by such examples or exemplary terms.

[0030] FIG. 1 is a cross-sectional view schematically showing the configuration of a semiconductor device according to one embodiment. Referring to FIG. 1, a semiconductor device (100) according to one embodiment may include a semiconductor layer (101, 102, 103), an oxide layer (106) disposed on the semiconductor layer (101, 102, 103), and a metal layer (104, 105, 107) disposed on the semiconductor layer (101, 102, 103) and the oxide layer (106) and electrically connected to the semiconductor layer (101, 102, 103) and the oxide layer (106).

[0031] The semiconductor layer (101, 102, 103) may include, for example, a semiconductor substrate (101) made of a semiconductor doped with a first conductivity type, and a source region (102) and a drain region (103) made of a semiconductor doped with a second conductivity type that is electrically opposite to the first conductivity type. FIG. 1 is illustrated such that the semiconductor substrate (101) is doped with a p-type and the source region (102) and drain region (103) are doped with an n+ type, but this is merely an example and is not necessarily limited thereto. For example, the semiconductor substrate (101) may be doped with an n-type and the source region (102) and drain region (103) may be doped with a p+ type.

[0032] The semiconductor substrate (101), source region (102), and drain region (103) may be made of the same semiconductor material. For example, if the semiconductor substrate (101) is p-type and the source region (102) and drain region (103) are n+ type, the source region (102) and drain region (103) can be formed by doping the semiconductor substrate (101) to p-type, then patterning a mask on the upper surface of the semiconductor substrate (101), and doping the upper region of the semiconductor substrate (101) to n+ type.

[0033] The semiconductor material of the semiconductor substrate (101), source region (102), and drain region (103) may include, for example, silicon (Si) or germanium (Ge), but is not necessarily limited thereto. Various semiconductor materials other than silicon or germanium may be used. For example, the semiconductor material of the semiconductor substrate (101), source region (102), and drain region (103) may include a group III-V compound semiconductor, a group II-VI compound semiconductor, an oxide semiconductor, an organic semiconductor, a quantum dot, a two-dimensional crystal semiconductor, etc. A group III-V compound semiconductor may include, for example, GaN, GaP, GaAs, GaSb, InP, InAs, InSb, InGaAs, InGaN, etc. A group II-VI compound semiconductor may include, for example, ZnS, CdS, ZnSe, CdSe, ZnTe, CdTe, etc. In addition, oxide semiconductors may include, for example, SIZO (silicon indium zinc oxide), SZTO (silicon zinc tin oxide), IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), ZTO (zinc tin oxide), CuAlO2, CuG2O2, SrCu2O2, SnO2, etc. Two-dimensional crystal semiconductors may include, for example, transition metal dichalcogenides, which are compounds of transition metals and chalcogen elements.

[0034] An oxide layer (106) may be disposed on the upper surface of a semiconductor substrate (101) between a source region (102) and a drain region (103). The oxide layer (106) may comprise a ferroelectric material having a high dielectric constant. In particular, the oxide layer (106) may have a crystalline structure. For example, the oxide layer (106) may be composed of crystals of a ferroelectric material having a dielectric constant of 10 or more. Because the oxide layer (106) has a high dielectric constant of 10 or more, the semiconductor device (100) may have a large capacitance. The material of such an oxide layer (106) is, for example, HfO2, ZrO2, and Hf x Zr 1-x It may include O2 (0 < x < 1), etc. In addition, to further increase the dielectric constant of the oxide layer (106), the oxide layer (106) may be further doped with at least one dopant selected from Al, La, Y, Si, Sr, Gd, and Ge.

[0035] The metal layers (104, 105, 107) may include a source electrode (104) disposed over a source region (102), a drain electrode (105) disposed over a drain region (103), and a gate electrode (107) disposed over an oxide layer (106). The conductive material or metal material forming the source electrode (104), the drain electrode (105), and the gate electrode (107) may include, for example, at least one of Ti, TiN, TiAlN, TiAl, Ta, TaN, W, WN, Mo, Ru, RuO, Pt, and Ni.

[0036] In a semiconductor device (100) of this structure, the oxide layer (106) serves to prevent current leakage from the gate electrode (107) to the semiconductor substrate (101). The gate electrode (107) serves to apply an electric field to the semiconductor substrate (101) between the source region (102) and the drain region (103). When an electric field is applied to the semiconductor substrate (101) by the gate electrode (107), current can flow between the source region (102) and the drain region (103) through the semiconductor substrate (101). Thus, the semiconductor substrate (101) can serve as a channel between the source region (102) and the drain region (103). For example, the semiconductor device (100) may be a metal oxide semiconductor field-effect transistor (MOSFET).

[0037] Additionally, the semiconductor device (100) may further include an interfacial layer (108) disposed between the semiconductor substrate (101) and the oxide layer (106). The interfacial layer (108) serves to reduce leakage current by suppressing the formation of interfacial traps between the semiconductor substrate (101) and the oxide layer (106). The interfacial layer (108) may, for example, include an oxide of the semiconductor material of the semiconductor substrate (101). For example, if the semiconductor substrate (101) is silicon, the interfacial layer (108) may be made of silicon oxide (SiO2). Typically, since the material of the interfacial layer (108) has a low dielectric constant of 4 or less, the interfacial layer (108) can be formed with a thin thickness so that the capacitance of the semiconductor device (100) does not deteriorate. For example, the thickness of the interfacial layer (108) may be less than 1 nm.

[0038] According to the present embodiment, hydrogen can be intentionally injected into the oxide layer (106) through hydrogen treatment so that the leakage current does not increase even if the thickness of the oxide layer (106) is reduced due to the ultrathinning of the semiconductor device (100) having the structure described above. Accordingly, the oxide layer (106) in the semiconductor device (100) according to the present embodiment may contain hydrogen at a concentration greater than a predetermined concentration.

[0039] For example, FIG. 2 schematically illustrates the process of hydrogenating the oxide layer (106) after forming the oxide layer (106). After depositing the oxide layer (106) on the upper surface of the semiconductor substrate (101) or the upper surface of the interface layer (108), the oxide layer (106) can be crystallized through heat treatment. Then, monatomic hydrogens can be distributed within the oxide layer (106) by performing hydrogen plasma treatment (H2 plasma) or high-temperature heat treatment (e.g., forming gas annealing) in a hydrogen atmosphere on the structure containing the oxide layer (106). After completing the hydrogen treatment of the oxide layer (106), a source electrode (104), a drain electrode (105), and a gate electrode (107) can be formed through the deposition, heat treatment, and patterning of a metal material.

[0040] FIG. 2 illustrates the hydrogen treatment of the oxide layer (106) before the deposition of the metal material, but is not necessarily limited thereto. For example, FIG. 3 schematically shows the process of hydrogen treating the oxide layer (106) after depositing the metal material first. Referring to FIG. 3, the oxide layer (106) is deposited on the upper surface of the semiconductor substrate (101) or the upper surface of the interface layer (108), and then the oxide layer (106) is crystallized through heat treatment. Then, the metal material (110) can be deposited on the oxide layer (106) and heat treated. FIG. 3 illustrates only the metal material (110) deposited on the oxide layer (106) for convenience, but the metal material (110) can also be formed on the source region (102) and the drain region (105).

[0041] Then, by performing hydrogen plasma treatment or high-temperature heat treatment in a hydrogen atmosphere on a structure including a metal material (110), single-atom hydrogens can be distributed within the oxide layer (106). During the hydrogen treatment process, hydrogen atoms can pass through the metal material (110) and be distributed within the oxide layer (106). Since the hydrogen atoms are very small and the thickness of the metal material (110) is very thin, the hydrogen atoms can pass through the metal material (110) and reach the oxide layer (106). After completing the hydrogen treatment, the metal material (110) can be patterned to form a source electrode (104), a drain electrode (105), and a gate electrode (107).

[0042] FIG. 4 is a graph showing the change in hydrogen concentration in the oxide layer (106), interface layer (108), and semiconductor substrate (101) after hydrogen treatment. In FIG. 4, the graph indicated by the thick solid line shows the change in hydrogen concentration for a sample treated with hydrogen plasma at a temperature of 350°C for 1 minute with the output of the RF plasma generator set to 100W in a PECVD (plasma-enhanced chemical vapor deposition) chamber, the graph indicated by the thin solid line shows the change in hydrogen concentration for a sample treated with hydrogen plasma at a temperature of 350°C for 1 minute with the output of the RF plasma generator set to 200W in a PECVD chamber, and the graph indicated by the dotted line shows the change in hydrogen concentration for a sample that was not treated with hydrogen.

[0043] The graph shown in FIG. 4 is the result of measuring the amount of elements in the chamber using SIMS (secondary ion mass spectroscopy) while sequentially etching the interface layer (108) and the semiconductor substrate (101) from the upper surface of the oxide layer (106) through sputtering. At the beginning of sputtering, the elements constituting the oxide layer (106) are measured, and thereafter, the elements constituting the interface layer (108) and the semiconductor substrate (101) are measured in sequence. As shown in FIG. 4, with the output of the RF plasma generator set to 100W, the amount of hydrogen elements in the oxide layer (106) of the hydrogen plasma-treated sample was the highest, and the amount of hydrogen elements in the oxide layer of the sample that was not hydrogen-treated was the lowest. In addition, the amount of hydrogen elements within the oxide layer (106) did not change significantly with depth and remained relatively uniform. The amount of hydrogen elements increased in the interface layer (108) and then decreased significantly in the semiconductor substrate (101). In particular, as the depth of the semiconductor substrate (101) increases, the amount of hydrogen in the hydrogen-treated sample and the hydrogen-untreated sample becomes nearly the same.

[0044] FIG. 5 is a schematic diagram showing the cause of leakage current generation in a comparative example, and FIG. 6 is a schematic diagram showing the cause of leakage current reduction in an embodiment. Referring to FIG. 5, a plurality of oxygen vacancies (117) exist within the oxide layer (116) that is not hydrogen-treated. Electrons within the gate electrode (107) can move from the gate electrode (107) through the oxide layer (116) to the semiconductor substrate (101) by being trapped by these plurality of oxygen vacancies (117). On the other hand, referring to FIG. 6, in the hydrogen-treated oxide layer (106), monatomic hydrogen formed by hydrogen treatment passesivates the plurality of oxygen vacancies. Since the oxygen vacancies (109) that are passivated by hydrogen do not function as charge traps, electrons within the gate electrode (107) cannot move through the oxide layer (106) to the semiconductor substrate (101).

[0045] FIG. 7 is a graph comparing the leakage current in the comparative example and the embodiment, and FIG. 8 is a graph comparing the capacitance in the comparative example and the embodiment. The comparative example and the embodiment consist of a p-type silicon substrate, a 0.7 nm thick SiO2 interface layer, and a 1.5 nm thick Hf 0.5 Zr 0.5 It includes an O2 oxide layer and a Mo gate electrode with a thickness of 120 nm. Hydrogen treatment was not performed on the sample according to the comparative example, while hydrogen treatment was performed on the sample according to the example. In FIGS. 7 and 8, the graph indicated by the thick solid line relates to an example in which hydrogen plasma treatment was performed at a temperature of 350°C for 1 minute with the output of the RF plasma generator set to 100 W in a PECVD chamber, the graph indicated by the thin solid line relates to an example in which hydrogen plasma treatment was performed at a temperature of 350°C for 1 minute with the output of the RF plasma generator set to 200 W in a PECVD chamber, and the graph indicated by the dotted line relates to a comparative example in which hydrogen treatment was not performed.

[0046] Referring to FIG. 7, the leakage current was largest in the comparative example, the leakage current in the example treated with hydrogen plasma at 200W output was smaller than the leakage current of the comparative example, and the leakage current was smallest in the example treated with hydrogen plasma at 100W output. Also, referring to FIG. 8, the capacitance was smallest in the comparative example, the capacitance in the example treated with hydrogen plasma at 200W output was larger than the capacitance of the comparative example, and the capacitance in the example treated with hydrogen plasma at 100W output was largest.

[0047] As described above, by intentionally injecting hydrogen into the oxide layer (106) within the semiconductor device (100), the oxide layer (106) within the semiconductor device (100) can contain hydrogen at a concentration greater than a predetermined level. The monatomic hydrogen within the oxide layer (106) formed by the hydrogen treatment can passivate oxygen vacancies and hinder the movement of electrons through the oxide layer (106). Therefore, leakage current in the oxide layer (106) within the semiconductor device (100) can be reduced or prevented. Furthermore, since oxygen heat treatment is not performed, the increase in the thickness of the interface layer (108) is prevented, so the capacitance of the semiconductor device (100) does not deteriorate.

[0048] For example, according to the quantitative analysis of the hydrogen concentration in the oxide layer (106) confirmed through HR-ERDA (high-resolution elastic recoil detection analysis), the hydrogen concentration in the oxide layer (106) may be about 0.7 at% or higher. Meanwhile, referring to the graphs in FIGS. 3, FIGS. 7, and FIGS. 8, the leakage current does not necessarily decrease further as the hydrogen concentration in the oxide layer (106) increases; rather, if the hydrogen concentration in the oxide layer (106) increases above a critical value, the leakage current actually increases. For example, the hydrogen concentration in the oxide layer (106) may be approximately 10 at% or lower. In particular, the hydrogen concentration in the oxide layer (106) may have a range of about 1 at% to about 5 at%.

[0049] Although the oxide layer (106) of the semiconductor device (100) has been described so far in terms of hydrogen concentration, the above-described principle can be applied to other devices including an oxide layer in addition to the semiconductor device (100). For example, FIG. 9 is a cross-sectional view schematically showing the configuration of a capacitor according to another embodiment. Referring to FIG. 9, the capacitor (200) may include a first metal layer (202), an oxide layer (201) disposed on the first metal layer (202), and a second metal layer (203) disposed on the oxide layer (201).

[0050] The first metal layer (202) and the second metal layer (203) may be made of a conductive material or a metal material including, for example, at least one of Ti, TiN, TiAlN, TiAl, Ta, TaN, W, WN, Mo, Ru, RuO, Pt, and Ni. The first metal layer (202) and the second metal layer (203) may be made of the same material or different materials.

[0051] The oxide layer (201) may be made of the same material as the oxide layer (106) of the semiconductor device (100). For example, the oxide layer (201) of the capacitor (200) may also be made of a ferroelectric material having a high dielectric constant and may have a crystalline structure. The material of the oxide layer (201) is, for example, HfO2, ZrO2, and Hf x Zr 1-x It may include O2 (0 < x < 1), etc. Additionally, the oxide layer (201) may be further doped with at least one dopant selected from Al, La, Y, Si, Sr, Gd, and Ge.

[0052] Additionally, the oxide layer (201) of the capacitor (200) may also contain hydrogen at a concentration greater than a predetermined level through hydrogen treatment to reduce leakage current. Through this hydrogen treatment, the capacitance of the capacitor (200) including the oxide layer (201) may also be increased. For example, the hydrogen concentration within the oxide layer (201) may be about 0.7 at% or higher. Also, the hydrogen concentration within the oxide layer (201) may be about 10 at% or lower. In particular, the hydrogen concentration within the oxide layer (201) may have a range of about 1 at% to about 5 at%.

[0053] The semiconductor device (100) and the capacitor (200) described above can together form a memory cell. For example, FIG. 10 shows the circuit configuration of a memory cell of a memory device including a semiconductor device (100) and a capacitor (200). Referring to FIG. 10, a memory cell (300) may include a semiconductor device (100) and a capacitor (200) electrically connected to the source electrode (104) of the semiconductor device (100). The memory device may include a plurality of bit lines and a plurality of word lines, and may include a plurality of memory cells as shown in FIG. 10. Each word line may be electrically connected to the gate electrode (107) of the semiconductor device (100), and each bit line may be electrically connected to the drain electrode (105) of the semiconductor device (100). The first metal layer (202) of the capacitor (200) is electrically connected to the source electrode (104) of the semiconductor device (100), and the second metal layer (203) can be grounded. A memory device including such a memory cell (300) can have low power consumption because there is little leakage of current in the memory cell (300).

[0054] The semiconductor device and capacitor comprising the hydrogen-containing oxide layer described above have been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of rights is defined in the claims, not in the foregoing description, and all variations within the scope of equivalence should be interpreted as being included in the scope of rights. Explanation of the symbols

[0055] 100.....Semiconductor device 101.....Semiconductor substrate 102.....Source area 103.....Drain area 104.....Source electrode 105.....Drain electrode 106.....Oxide layer 107.....Gate electrode 108.....Interfacial layer 201.....Oxide layer 202, 203.....metal layer 300.....memory cell

Claims

Claim 1 A semiconductor device comprising: a semiconductor layer; an oxide layer disposed on the semiconductor layer; and a metal layer disposed on the oxide layer; wherein the oxide layer comprises a ferroelectric material having a crystalline structure, and monatomic hydrogens are distributed within the oxide layer to passivate a plurality of oxygen vacancies within the oxide layer, and the hydrogen concentration within the oxide layer is 0.7 at% or more; wherein the semiconductor layer comprises: a semiconductor substrate doped with a first conductivity type; and a source region and a drain region formed in an upper region of the semiconductor substrate, each doped with a second conductivity type electrically opposite to the first conductivity type; wherein the oxide layer is disposed on the upper surface of the semiconductor substrate between the source region and the drain region, and further comprises an interface layer disposed between the semiconductor substrate and the oxide layer, wherein the amount of hydrogen element increases from the oxide layer to the interface layer and decreases in the semiconductor substrate. Claim 2 delete Claim 3 delete Claim 4 In claim 1, the oxide layer is HfO2, ZrO2, and Hf x Zr 1-x A semiconductor device comprising at least one material selected from O2 (0 < x < 1). Claim 5 In claim 4, the oxide layer further comprises at least one dopant selected from Al, La, Y, Si, Sr, Gd, and Ge. Claim 6 A semiconductor device according to claim 1, wherein the hydrogen concentration in the oxide layer is 10 at% or less. Claim 7 A semiconductor device according to claim 6, wherein the hydrogen concentration in the oxide layer is 1 at% to 5 at%. Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 In claim 1, the interface layer comprises an oxide of the semiconductor material of the semiconductor substrate. Claim 12 A semiconductor device according to claim 1, further comprising a source electrode disposed over the source region and a drain electrode disposed over the drain region. Claim 13 A first metal layer; an oxide layer disposed on the first metal layer; and a second metal layer disposed on the oxide layer; wherein the oxide layer comprises a ferroelectric material having a crystalline structure, and monatomic hydrogens are distributed within the oxide layer to passivate a plurality of oxygen vacancies within the oxide layer, and the hydrogen concentration within the oxide layer is 0.7 at% or more, and the oxide layer comprises HfO2, ZrO2, and Hf x Zr 1-x A capacitor comprising at least one material selected from O2 (0 < x < 1), wherein the oxide layer further comprises at least one dopant selected from Si, Sr, and Ge. Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 In claim 13, the capacitor comprises at least one metal material selected from Ti, TiN, TiAlN, TiAl, Ta, TaN, W, WN, Mo, Ru, RuO, Pt, and Ni, wherein the first metal layer and the second metal layer comprise the same. Claim 19 A capacitor according to claim 13, wherein the hydrogen concentration in the oxide layer is 10 at% or less. Claim 20 A capacitor according to claim 19, wherein the hydrogen concentration in the oxide layer is 1 at% to 5 at%. Claim 21 A memory device comprising: a semiconductor device according to at least one of claims 1, 4 to 7, 11, and 12; and a capacitor according to at least one of claims 13 and 18 to 20.

Images