Package

Abstract

The present invention discloses a package and a method for manufacturing the same. The package of the present invention comprises a lower substrate, a lower chip provided on the lower substrate, posts on the edge of the lower substrate outside the lower chip, an upper substrate provided on the posts and the lower chip and having a cavity on the lower chip, and a crack reinforcing material provided within the edge of the cavity to minimize cracking of the upper substrate.

Description

Technology Field

[0001] The present invention relates to a package and a method for manufacturing the same, and more specifically, to an interposer package-on-package and a method for manufacturing the same. Background Technology

[0002] As semiconductor chips become more highly integrated, their size is gradually decreasing. On the other hand, the spacing between bumps on semiconductor chips is determined by international standards set by the International Semiconductor Standards Association. Consequently, it is difficult to control the number of bumps on a semiconductor chip. Furthermore, as semiconductor chips become smaller, their handling and testing become more challenging. In addition, there is a problem requiring diversification of the mounting boards depending on the size of the semiconductor chip. To address this, fan-out panel-level packaging, interposer package-on-package, and package-on-package have been proposed. The problem to be solved

[0003] The objective of the present invention is to provide a package capable of suppressing cracking in an upper substrate having a cavity. means of solving the problem

[0004] The present invention discloses a package. The package comprises: a lower substrate; a lower chip provided on the lower substrate; posts on the edge of the lower substrate outside the lower chip; an upper substrate provided on the posts and the lower chip and having a cavity on the lower chip; and a crack reinforcement provided within the edge of the cavity to minimize cracking of the upper substrate.

[0005] A package according to one example of the present invention comprises: a lower substrate; a lower chip provided on the lower substrate; posts on the lower substrate outside the lower chip; an upper substrate provided on the posts and the lower chip and having a cavity on the lower chip; an upper chip provided on the upper substrate of the cavity; and a crack reinforcing material provided within the edge of the cavity below the upper chip to minimize cracking of the upper substrate.

[0006] A method for manufacturing a package according to an example of the present invention comprises the steps of: forming posts on the edges of a lower substrate; mounting a lower chip on the center of the lower substrate between the posts; preparing an upper substrate; and providing the upper substrate on the lower chip and the lower substrate. Herein, the step of preparing the upper substrate may include: forming a cavity on the lower surface of the upper substrate; and forming a crack reinforcement within the edge of the cavity. Effects of the invention

[0007] As described above, the package according to an embodiment of the present invention can suppress cracks in the upper substrate by using a crack reinforcing material within the cavity edge. Brief explanation of the drawing

[0008] Fig. 1 This is a plan view showing an example of a package according to an embodiment of the present invention. Fig. 2 Is Fig. 1 This is a cross-sectional view taken by cutting along the II' line. Fig. 3a inside Fig. 3c Is Fig. 2 This is a cross-sectional view showing an example of a crack reinforcement. Fig. 4 Is Fig. 1 This is a flowchart showing the manufacturing method of the package. Fig. 5 inside Fig. 9 Is Fig. 1 These are process cross-sections of the package. Fig. 10This is a cross-sectional view showing an example of a package according to the concept of the present invention. Specific details for implementing the invention

[0009] Fig. 1 This shows an example of a package (100) according to an embodiment of the present invention. Fig. 2 Is Fig. 1 Cut and show the II' line.

[0010] Fig. 1 and Fig. 2 Referring to the above, the package (100) of the present invention may include an interposer package on package. According to one example, the package (100) of the present invention may include a lower substrate (10), posts (20), a lower chip (30), spacers (40), an upper substrate (50), a crack stiffener (60), and an upper chip (70).

[0011] A lower substrate (10) may be provided below the posts (20) and the lower chip (30). Although not illustrated, the lower substrate (10) may have lower wiring connecting the lower chip (30) and the posts (20). For example, the lower substrate (10) may have a thickness of about 80 μm to about 100 μm. The lower substrate (10) may include a redistribution layer or a redistribution board. Alternatively, the lower substrate (10) may include a printed circuit board, and the invention is not limited thereto. According to one example, the lower substrate (10) may have first lower bumps (12). The first lower bumps (12) may be provided below the lower surface of the lower substrate (10). The first lower bumps (12) may include gold (Au), solder, copper (Cu), or silver (Ag), and the invention is not limited thereto.

[0012] Posts (20) may be provided on the edges of the lower substrate (10). Posts (20) may be placed on the outer edge of the lower chip (30). Posts (20) may be connected to the lower chip (30) through the lower substrate (10). Posts (20) may be thicker than the lower chip (30). Posts (20) may be taller than the lower chip (30).

[0013] A lower chip (30) may be provided on the center of a lower substrate (10). A lower chip (30) may be provided between posts (20). A lower chip (30) may be connected to a lower substrate (10) through first upper bumps (32). The lower chip (30) may have a rectangular shape in a planar view. The first upper bumps (32) may be provided within a first underfill layer (34). The lower chip (30) may include an application processor chip. For example, the lower chip (30) may have a thickness of about 200 μm.

[0014] Spacers (40) may be provided between the lower chip (30) and the upper substrate (50). The spacers (40) may maintain a certain distance between the lower chip (30) and the upper substrate (50). That is, the spacers (40) may support the upper substrate (50). For example, the spacers (40) may include polymer blocks or polymer balls, but the present invention is not limited thereto.

[0015] An upper substrate (50) may be provided on a lower substrate (10), posts (20), a lower chip (30), and spacers (40). The upper substrate (50) may include an interposer substrate. Alternatively, the upper substrate (50) may include a redistribution layer or a redistribution substrate, but the invention is not limited thereto. The upper substrate (50) may have a thickness equal to the thickness of the lower substrate (10). For example, the upper substrate (50) may have a thickness of about 80 μm to about 100 μm. The height between the upper surface of the upper substrate (50) and the first lower bumps (12) may be about 0.45 mm to about 0.5 mm. According to one example, the upper substrate (50) may have a cavity (52).

[0016] A cavity (52) may be provided on the lower surface at the center of the upper substrate (50). The cavity (52) may accommodate the upper surface of the lower chip (30). The cavity (52) may have the same shape as the lower chip (30) in a planar view. The cavity (52) may have a square shape. For example, the cavity (52) may have a first width (W1) of about 5 mm to about 10 mm. The cavity (52) may have a depth of about 10 μm to 30 μm. The cavity (52) may have a rectangular shape. The cavity (52) may have an area larger than the area of ​​the lower chip (30).

[0017] Crack reinforcement (60) may be provided within the edge of the cavity (52). Crack reinforcement (60) may surround the outer edge of the spacers (40). Crack reinforcement (60) may be provided on the lower surface of the upper substrate (50). Crack reinforcement (60) may be provided on the inner sidewall of the upper substrate (50) within the cavity (52).

[0018] FIGS. 3a to 3c show an example of the crack reinforcement of FIG. 2.

[0019] Referring to FIGS. 3a through 3c, the crack reinforcement (60) may have a triangular cross-section from a vertical perspective. The crack reinforcement (60) may have a triangular shape with one side rounded. According to one example, the crack reinforcement (60) may have an arc-shaped cross-section. The crack reinforcement (60) may have a thickness (T) equal to the depth of the cavity (52). For example, the crack reinforcement (60) may have a thickness (T) of about 10 μm to about 30 μm.

[0020] The crack reinforcement (60) may have a rectangular shape in a planar view. According to one example, the crack reinforcement (60) may include straight reinforcements (62) and corner reinforcements (64). The straight reinforcements (62) may correspond to the sides of the rectangle. The straight reinforcements (62) may have a second width (W2) greater than the thickness (T) of the crack reinforcement (60). That is, the second width (W2) of the straight reinforcements (62) may be greater than the depth of the cavity (52). The second width (W2) of the straight reinforcements (62) may be smaller than half the first width (W1) of the cavity (52). For example, the second width (W2) of the straight reinforcements (62) may be about 10 μm to about 5 mm. The corner reinforcements (64) may correspond to the vertices of the rectangle. The straight reinforcing members (62) and corner reinforcing members (64) can prevent damage or cracking of the upper substrate (50) around the cavity (52). Accordingly, the package (100) of the present invention can minimize cracking of the upper substrate (50) around the cavity (52) by using crack reinforcing members (60).

[0021] An upper chip (70) may be provided on a cavity (52) and an upper substrate (50). The upper chip (70) may be connected to a lower chip (30) through a lower substrate (10), posts (20), and an upper substrate (50). For example, the upper chip (70) may include a memory chip. The upper chip (70) may be connected to the upper substrate (50) through second upper bumps (72). The second upper bumps (72) may be provided within a second underfill layer (74).

[0022] The method for manufacturing the package (100) of the present invention configured as described above is as follows.

[0023] Fig. 4 Is Fig. 1 Shows a method for manufacturing a package (100). Fig. 5 inside do 9 is Fig. 1 These are process cross-sectional views of the package (100).

[0024] Fig. 4 and do Referring to 5, posts (20) are formed on a lower substrate (10) (S10). The posts (20) may be formed on the edges of the lower substrate (10). The posts (20) may be formed through a photolithography process and an electroplating process, but the present invention is not limited thereto.

[0025] Fig. 4 and do Referring to 6, a lower chip (30) is mounted on the center of the lower substrate (10) between the posts (20) (S20). The lower chip (30) can be mounted on the center of the lower substrate (10). The lower chip (30) can be connected to wirings (not shown) within the lower substrate (10) by first upper bumps (32).

[0026] Fig. 4 and Fig. 7Referring to the, spacers (40) are formed on the lower chip (30) (S30). The spacers (40) may include polymer blocks or polymer balls. The spacers (40) may be formed through a coating process, a thin film deposition process, or an etching process, but the present invention is not limited thereto.

[0027] Fig. 4 and Fig. 8 Referring to the, an upper substrate (50) on a lower substrate (10) is prepared (S40). The upper substrate (50) may include an interposer substrate. The upper substrate (50) may include a polymer substrate and wiring (not shown) within the polymer substrate. The upper substrate (50) may be prepared through the following processes.

[0028] First, a cavity (52) is formed on the lower surface of the upper substrate (50) (S42). For example, the cavity (52) may be formed by an etching process of the upper substrate (50). Alternatively, the cavity (52) may be formed by a molding process of the upper substrate (50), and the present invention is not limited thereto.

[0029] Next, a crack reinforcement (60) can be formed within the edge of the cavity (52) (S44). According to one example, the crack reinforcement (60) can be formed by a printing method. For example, the crack reinforcement (60) can be formed through an inkjet printing or screen printing method. Alternatively, the crack reinforcement (60) can be formed by an underfill process, a sol-gel method, a spin coating, or a thermal melting method, but the invention is not limited thereto. The crack reinforcement (60) can minimize cracks in the upper substrate (50).

[0030] Next, an upper substrate (50) is provided on the lower substrate (10), posts (20), lower chip (30), and spacers (40) (S50). The upper surface of the lower chip (30) may be provided within the cavity (52). A crack reinforcement (60) can prevent cracks or damage to the upper substrate (50).

[0031] Then, a mold layer (22) is formed between the lower substrate (10) and the upper substrate (50) (S60). The mold layer (22) can fix the upper substrate (50) onto the lower substrate (10). The mold layer (22) can be formed through an underfill process. Subsequently, the lower substrate (10), the mold layer (22), and the upper substrate (50) can be divided, cut, or sawed into units of the lower chip (30). Additionally, the crack reinforcement (60) can prevent cracks or damage to the upper substrate (50).

[0032] Fig. 4 and Fig. 9 Referring to the above, an upper chip (70) is mounted on an upper substrate (50) (S70). The upper chip (70) may include a memory chip. The upper chip (70) may be connected to the wiring of the upper substrate (50) through second upper bumps (72). The upper bumps (72) may be provided within a second underfill layer (74). The second underfill layer (74) may secure the upper chip (70) on the upper substrate (50).

[0033] Fig. 2 and Fig. 4 Referring to the, first lower bumps (12) are formed on the lower surface of the lower substrate (10) (S80). The first lower bumps (12) can be electrically connected to the lower chip (30) and the upper chip (70). The first lower bumps (12) can connect the lower chip (30) and the upper chip (70) to an external substrate or an external component.

[0034] Fig. 10This shows an example of a package (100) according to the concept of the present invention.

[0035] Fig. 10 Referring to the above, the package (100) of the present invention may include a package on package. According to one example, the package (100) of the present invention may include an upper package (90) on an upper substrate (50). The lower substrate (10), posts (20), lower chip (30), spacers (40), upper substrate (50), and crack reinforcement (60) are Fig. 2 It can be configured in the same way as.

[0036] The upper package (90) may include an upper chip (70) and an upper package substrate (80). The upper package substrate (80) may be provided on the upper substrate (50). The upper package substrate (80) may have second lower bumps (82). The second lower bumps (82) may electrically connect the upper substrate (50) and the upper package substrate (80).

[0037] An upper chip (70) may be provided on an upper package substrate (80). The upper chip (70) may have second upper bumps (72). The second upper bumps (72) may be provided within a second underfill layer (74). The second upper bumps (72) may connect the upper chip (70) to package wiring (not shown) within the upper package substrate (80). The second underfill layer (74) may be provided between the upper chip (70) and the upper package substrate (80). The second underfill layer (74) may secure the upper chip (70) to the upper package substrate (80).

[0038] The description above describes specific examples for implementing the present invention. The present invention will include not only the embodiments described above, but also embodiments that can be easily modified or simply changed. Furthermore, the present invention will include technologies that can be easily modified and implemented in the future using the embodiments described above.

Claims

Claim 1 A package comprising: a lower substrate; a lower chip provided on the lower substrate; posts on the edge of the lower substrate outside the lower chip; an upper substrate provided on the posts and the lower chip and having a cavity on the lower chip; and a crack reinforcement provided within the edge of the cavity and having a square shape, wherein the crack reinforcement comprises: straight reinforcements corresponding to the sides of the square; and corner reinforcements connecting the straight reinforcements and corresponding to the vertices of the square. Claim 2 In claim 1, the crack reinforcement is a package having a thickness equal to the depth of the cavity. Claim 3 delete Claim 4 delete Claim 5 In claim 1, the straight reinforcing members are a package having a width greater than the depth of the cavity. Claim 6 In claim 1, the straight reinforcing members are a package having a width smaller than half the width of the cavity. Claim 7 In claim 1, the straight reinforcing members are a package having a width of 10 μm to 5 mm. Claim 8 delete Claim 9 delete Claim 10 In claim 1, the crack reinforcement is a package having a triangular cross-section.

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