Display panel and display device including the same

Abstract

A display panel may include a substrate comprising a display area and a pad area spaced apart from the display area in a first direction, a plurality of pixels disposed in the display area on the substrate, a plurality of pads disposed in the pad area on the substrate, and a plurality of transmission lines each connected to the plurality of pads. Each of the plurality of pads may include a lower electrode and an upper electrode disposed on the lower electrode and extending in a second direction intersecting the first direction. Each upper electrode may have a relatively large area. Accordingly, the reliability of the display panel and the display device including it may be improved.

Description

Technology Field

[0001] The present invention relates to a display panel and a display device including the same. More specifically, the present invention relates to a high-resolution display panel and a display device including the same. Background Technology

[0002] Flat panel displays are being used as replacements for cathode ray tube displays due to their characteristics, such as lightweight and thin profiles. Representative examples of such flat panel displays include liquid crystal displays and organic light-emitting diode displays.

[0003] The above display device may include a display panel comprising a plurality of pixels and a plurality of pads, and a driving circuit chip connected to the display panel. The pixels may receive driving signals from the driving circuit chip through the pads and transmission lines (e.g., fan-out lines) each connected to the pads. Meanwhile, a plurality of pads and a plurality of transmission lines may be required to achieve high resolution of the display device. The problem to be solved

[0004] One objective of the present invention is to provide a display panel with improved reliability.

[0005] Another objective of the present invention is to provide a display device with improved reliability.

[0006] However, the present invention is not limited by the purposes described above and may be extended in various ways without departing from the spirit and scope of the invention. means of solving the problem

[0007] To achieve one objective of the present invention as described above, a display panel according to exemplary embodiments of the present invention may include a substrate comprising a display area and a pad area spaced apart from the display area in a first direction, a plurality of pixels disposed in the display area on the substrate, a plurality of pads disposed in the pad area on the substrate, and a plurality of transmission lines each connected to the plurality of pads. Each of the plurality of pads may include a lower electrode and an upper electrode disposed on the lower electrode and extending in a second direction intersecting the first direction.

[0008] In one embodiment, each of the lower electrodes may extend in the first direction.

[0009] In one embodiment, the width of each lower electrode in the second direction may be smaller than the length of each upper electrode in the second direction.

[0010] In one embodiment, each of the lower electrodes may overlap with either of the two ends in the longitudinal direction of the corresponding upper electrode.

[0011] In one embodiment, each of the lower electrodes may overlap with the longitudinal central portion of the corresponding upper electrode.

[0012] In one embodiment, at least one of the upper electrodes may overlap with two or more of the transmission lines on a plane.

[0013] In one embodiment, the transfer lines may be disposed on the same layer as the lower electrodes.

[0014] In one embodiment, the upper electrodes may be arranged in a matrix form along the first direction and the second direction on a plane.

[0015] In one embodiment, the lower electrodes may be arranged in a zigzag shape on a plane.

[0016] In one embodiment, the pads may include a first pad comprising a first upper electrode and a first lower electrode disposed below the first upper electrode and connected to a first transmission line among the transmission lines, and a second pad comprising a second upper electrode adjacent to the first direction of the first upper electrode and a second lower electrode disposed below the second upper electrode and connected to a second transmission line among the transmission lines.

[0017] In one embodiment, the first lower electrode may overlap with the end of the first upper electrode in the second direction on a plane. The second lower electrode may overlap with the end of the second upper electrode in the third direction opposite to the second direction on a plane.

[0018] In one embodiment, the first upper electrode may overlap with the first transmission line and the second transmission line, respectively, on a plane.

[0019] In one embodiment, the second upper electrode may overlap with the second transmission line on a plane and be spaced apart from the first transmission line.

[0020] In one embodiment, the first upper electrode may overlap with the first transmission line on a plane and be spaced apart from the second transmission line.

[0021] In one embodiment, the second transmission line may be spaced apart from the first transmission line in the third direction on a plane.

[0022] In one embodiment, the first transmission line and the second transmission line may each be located on a plane between the first lower electrode and the second lower electrode.

[0023] In one embodiment, the pads may further include a third pad comprising a third upper electrode adjacent to the first direction of the second upper electrode and a third lower electrode disposed below the third upper electrode and connected to the third transmission line among the transmission lines. The third lower electrode may overlap with the end of the third upper electrode in the second direction.

[0024] In one embodiment, the first upper electrode may overlap with each of the first transmission line, the second transmission line, and the third transmission line on a plane. The second upper electrode may overlap with each of the second transmission line and the third transmission line on a plane and be spaced apart from the first transmission line. The third upper electrode may overlap with the third transmission line on a plane and be spaced apart from each of the first transmission line and the second transmission line.

[0025] In one embodiment, the first lower electrode may overlap with the second direction end of the first upper electrode on a plane. The second lower electrode may overlap with the second direction end of the second upper electrode on a plane.

[0026] In one embodiment, the first upper electrode may overlap with the first transmission line and the second transmission line, respectively, on a plane. The second upper electrode may overlap with the second transmission line on a plane and be spaced apart from the first transmission line.

[0027] In one embodiment, the upper electrodes may be arranged in a zigzag shape on a plane.

[0028] In one embodiment, each of the lower electrodes may overlap with the longitudinal central portion of the corresponding upper electrode.

[0029] In one embodiment, the display panel may further include an organic insulating layer disposed between the lower electrodes and the upper electrodes. Each of the upper electrodes may contact the corresponding lower electrode through a contact hole formed in the organic insulating layer.

[0030] In one embodiment, each of the pixels may include a transistor comprising an active layer, a gate electrode disposed on the active layer, a source electrode and a drain electrode disposed on the gate electrode, and a light-emitting element comprising an anode electrode disposed on the source electrode and the drain electrode, a light-emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light-emitting layer. Each of the lower electrodes may be disposed on the same layer as the gate electrode, and each of the upper electrodes may be disposed on the same layer as the anode electrode.

[0031] To achieve another objective of the present invention described above, a display device according to exemplary embodiments of the present invention may include a substrate comprising a display area and a pad area spaced apart from the display area in a first direction, a plurality of pixels disposed in the display area on the substrate, a plurality of pads disposed in the pad area on the substrate and comprising a lower electrode and an upper electrode disposed on the lower electrode and extending in a second direction intersecting the first direction, and a plurality of transmission lines each connected to the plurality of pads, a driving circuit chip disposed in the pad area on the display panel and comprising a plurality of bumps, and an anisotropic conductive film disposed between the display panel and the driving circuit chip and connecting the bumps corresponding to the pads respectively. Effects of the invention

[0032] A display device according to embodiments of the present invention may include a display panel and a driving circuit chip connected to the display panel. Pads connected to bumps of the driving circuit chip may be disposed in the pad area of ​​the display panel. Each of the pads may include a lower electrode and an upper electrode extending in the longitudinal direction of the pad area. Each of the upper electrodes may have a relatively large area. Accordingly, the display device can prevent or reduce connection failures between the pads and the bumps. Additionally, each of the lower electrodes disposed on the same layer as the transmission lines connected to each of the pads may have a relatively small area. Accordingly, the display device can prevent or reduce short circuit failures between the transmission lines. Thus, the reliability of the display device can be improved. Furthermore, a plurality of the pads and a plurality of the transmission lines may be disposed to realize a high resolution of the display device.

[0033] However, the effects of the present invention are not limited to the effects described above, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0034] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. Figure 2 is a cross-sectional view taken along line II' of Figure 1. FIG. 3 is an enlarged plan view showing an example of the pad area of ​​the display device of FIG. 1. Figures 4 and 5 are cross-sectional views taken along the line II-II' of Figure 3. Figure 6 is a cross-sectional view taken along the line III-III' of Figure 3. Figure 7 is a cross-sectional view taken along the line IV-IV' of Figure 3. Figure 8 is a cross-sectional view taken along the VV' line of Figure 3. Figure 9 is a cross-sectional view taken along the line VI-VI' of Figure 3. FIG. 10 is an enlarged plan view illustrating another example of the pad area of ​​the display device of FIG. 1. FIG. 11 is an enlarged plan view illustrating another example of the pad area of ​​the display device of FIG. 1. FIG. 12 is an enlarged plan view illustrating another example of the pad area of ​​the display device of FIG. 1. FIG. 13 is an enlarged plan view showing another example of the pad area of ​​the display device of FIG. 1. Figure 14 is a cross-sectional view taken along the line VII-VII' of Figure 13. Fig. 15 is a cross-sectional view taken along the line VIII-VIII' of Fig. 13. Figure 16 is a cross-sectional view taken along the IX-IX' line of Figure 13. Figure 17 is a cross-sectional view taken along the XX' line of Figure 13. FIG. 18 is a cross-sectional view taken along the line XI-XI' of FIG. 13. FIG. 19 is a plan view showing a display device according to another embodiment of the present invention. FIG. 20 is a block diagram showing an electronic device including a display device according to embodiments of the present invention. Specific details for implementing the invention

[0035] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical or similar reference numerals are used for identical components in the attached drawings.

[0036] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention.

[0037] Referring to FIG. 1, a display device (10) according to one embodiment of the present invention may include a display panel (100) and a driving circuit chip (200).

[0038] A display panel (100) (or a substrate included in the display panel (100)) may include a display area (DA) and a non-display area (NDA). A plurality of pixels for generating an image may be arranged in the display area (DA). The light emitted by each of the pixels may be combined to generate the image. For example, the pixels may be arranged in a matrix form along a first direction (D1) and a second direction (D2) that intersects the first direction (D1). The second direction (D2) may be perpendicular to the first direction (D1).

[0039] The non-display area (NDA) may be located around the display area (DA). For example, the non-display area (NDA) may surround the display area (DA) on a plane.

[0040] The non-display area (NDA) may include a pad area (PA). The pad area (PA) may be located on one side of the display area (DA). For example, the pad area (PA) may be located spaced apart from the display area (DA) in a first direction (D1). The pad area (PA) may extend in a second direction (D2). A plurality of pads may be arranged in the pad area (PA).

[0041] In one embodiment, the non-display area (NDA) may include a bending area (BA) located between the display area (DA) and the pad area (PA). The bending area (BA) may be bent around a bending axis extending in a second direction (D2). The bending area (BA) may be bent so that the pad area (PA) is located below the display area (DA).

[0042] A display panel (100) may include a plurality of transmission lines (TL) connecting a display area (DA) and a pad area (PA). The transmission lines (TL) may be located between the display area (DA) and the pad area (PA). Each transmission line (TL) may include a first end adjacent to the pad area (PA) and a second end adjacent to the display area (DA). The first end of each transmission line (TL) may be connected to a corresponding pad among the pads. The second end of each transmission line (TL) may be connected to a corresponding line among a plurality of lines (e.g., gate lines, data lines, driving voltage lines, etc.) placed in the display area (DA). The pads and the pixels may be electrically connected through the transmission lines (TL).

[0043] The driving circuit chip (200) may be placed in a pad area (PA) on the display panel (100). For example, the driving circuit chip (200) may be directly mounted on the display panel (100) using a chip on plastic (COP) method. The driving circuit chip (200) may include a plurality of bumps connected to the pads.

[0044] In one embodiment, although not shown in the drawing, a flexible printed circuit board (FPCB) may be attached to the end of the first direction (D1) of the display panel (100). A printed circuit board (PCB) may be attached to the end of the flexible printed circuit board.

[0045] The driving circuit chip (200), the flexible printed circuit board, and the printed circuit board can provide a driving signal to the display panel (100). The driving signal may refer to various signals that drive the display panel (100), such as a driving voltage, a gate signal, and a data signal. The driving signal can be transmitted to the pixels placed in the display area (DA) through the pads and transmission lines (TL).

[0046] Figure 2 is a cross-sectional view taken along line II' of Figure 1.

[0047] Hereinafter, the display area (DA) of the display panel (100) will be described in detail with reference to FIG. 1 and FIG. 2.

[0048] Referring to FIGS. 1 and 2, in one embodiment, a display panel (100) may include a substrate (110), a buffer layer (120), a pixel (PX), and an encapsulation layer (140). The pixel (PX) may include a first transistor (TR1), a second transistor (TR2), a capacitor (CAP), and a light-emitting element (LED).

[0049] The substrate (110) may be an insulating substrate formed from a transparent or opaque material. In one embodiment, the substrate (110) may include glass. In this case, the display panel (100) may be a rigid display panel. In another embodiment, the substrate (110) may include plastic. In this case, the display panel (100) may be a flexible display panel.

[0050] A buffer layer (120) may be disposed on a substrate (110). The buffer layer (120) can prevent impurities, such as oxygen and moisture, from diffusing to the upper surface of the substrate (110) through the substrate (110). The buffer layer (120) may include inorganic insulating materials such as silicon compounds and metal oxides. Examples of inorganic insulating materials that can be used in the buffer layer (120) include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), aluminum oxide (AlO), aluminum nitride (AlN), tantalum oxide (TaO), hafnium oxide (HfO), zirconium oxide (ZrO), and titanium oxide (TiO). These may be used alone or in combination with each other. The buffer layer (120) may have a single-layer structure or a multi-layer structure including a plurality of insulating layers.

[0051] A first transistor (TR1), a second transistor (TR2), and a capacitor (CAP) may be disposed on the buffer layer (120). The first transistor (TR1) may include an active layer (AL1), a gate electrode (GE1), a source electrode (SE1), and a drain electrode (DE1). The first transistor (TR1) may be a driving transistor connected to a light-emitting element (LED). The second transistor (TR2) may include an active layer (AL2), a gate electrode (GE2), a source electrode (SE2), and a drain electrode (DE2). The second transistor (TR2) may be a switching transistor connected to a data line.

[0052] Active layers (AL1, AL2) may be disposed on a buffer layer (120). Each of the active layers (AL1, AL2) may include an oxide semiconductor, a silicon semiconductor, an organic semiconductor, etc. For example, the oxide semiconductor may include at least one oxide selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. Each of the active layers (AL1, AL2) may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0053] A first insulating layer (131) may be disposed on the active layers (AL1, AL2). The first insulating layer (131) may cover the active layers (AL1, AL2) on the buffer layer (120). The first insulating layer (131) may include an inorganic insulating material.

[0054] Gate electrodes (GE1, GE2) may be disposed on the first insulating layer (131). The gate electrode (GE1) may overlap with the channel region of the active layer (AL1), and the gate electrode (GE2) may overlap with the channel region of the active layer (AL2). Each of the gate electrodes (GE1, GE2) may include a conductive material such as a metal, an alloy, a conductive metal nitride, a conductive metal oxide, or a transparent conductive material. Examples of the conductive materials that can be used for each of the gate electrodes (GE1, GE2) include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum, alloys containing silver, alloys containing copper, alloys containing molybdenum, aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), strontium ruthenium oxide (SrRuO), zinc oxide (ZnO), indium tin oxide (ITO), tin oxide (SnO), indium oxide (InO), gallium oxide (GaO), and indium zinc. There are oxides (IZO), etc. These can be used alone or in combination with each other. Each of the gate electrodes (GE1, GE2) may have a single-layer structure or a multilayer structure including multiple conductive layers.

[0055] A second insulating layer (132) may be disposed on the gate electrodes (GE1, GE2). The second insulating layer (132) may cover the gate electrodes (GE1, GE2) on the first insulating layer (131). The second insulating layer (132) may include an inorganic insulating material.

[0056] A capacitor electrode (CE) may be disposed on the second insulating layer (132). The capacitor electrode (CE) may overlap with the gate electrode (GE1). The gate electrode (GE1), the second insulating layer (132), and the capacitor electrode (CE) may form a capacitor (CAP).

[0057] A third insulating layer (133) may be disposed on the capacitor electrode (CE). The third insulating layer (133) may cover the capacitor electrode (CE) on the second insulating layer (132). The third insulating layer (133) may include an inorganic insulating material.

[0058] Source electrodes (SE1, SE2) and drain electrodes (DE1, DE2) may be disposed on the third insulating layer (133). The source electrode (SE1) and the drain electrode (DE1) may be connected to the source region and the drain region of the active layer (AL1), respectively. The source electrode (SE2) and the drain electrode (DE2) may be connected to the source region and the drain region of the active layer (AL2), respectively. Each of the source electrodes (SE1, SE2) and the drain electrodes (DE1, DE2) may include a conductive material.

[0059] A fourth insulating layer (134) may be disposed on the source electrodes (SE1, SE2) and drain electrodes (DE1, DE2). The fourth insulating layer (134) may comprise an organic insulating material. Examples of organic insulating materials that may be used for the fourth insulating layer (134) include photoresist, polyacryl-based resin, polyimide-based resin, polyamide-based resin, siloxane-based resin, acrylic-based resin, epoxy-based resin, etc. These may be used alone or in combination with each other.

[0060] An anode electrode (AE) may be disposed on the fourth insulating layer (134). The anode electrode (AE) may include a conductive material. The anode electrode (AE) may be connected to a drain electrode (DE1) through a contact hole formed in the fourth insulating layer (134). Accordingly, the anode electrode (AE) may be electrically connected to the first transistor (TR1).

[0061] A fifth insulating layer (135) may be disposed on the anode electrode (AE). The fifth insulating layer (135) may cover the periphery of the anode electrode (AE) and define a pixel opening that exposes the center of the anode electrode (AE). The fifth insulating layer (135) may include an organic insulating material.

[0062] A light-emitting layer (EL) may be disposed on the anode electrode (AE). The light-emitting layer (EL) may be disposed within the pixel opening of the fifth insulating layer (135). The light-emitting layer (EL) may include at least one of an organic light-emitting material and quantum dots.

[0063] In one embodiment, the organic light-emitting material may include a low-molecular-weight organic compound or a high-molecular-weight organic compound. Examples of the low-molecular-weight organic compound include copper phthalocyanine, N,N'-diphenylbenzidine, and tris-(8-hydroxyquinoline)aluminum. Examples of the high-molecular-weight organic compound include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, and polyfluorene, but the present invention is not limited thereto. These may be used alone or in combination with each other.

[0064] In one embodiment, the quantum dot may include a core comprising a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and combinations thereof. In one embodiment, the quantum dot may have a core-shell structure comprising the core and a shell surrounding the core. The shell may serve as a protective layer to maintain semiconductor properties by preventing chemical degradation of the core and as a charging layer to impart electrophoretic properties to the quantum dot.

[0065] A cathode electrode (CE) may be disposed on the light-emitting layer (EL). The cathode electrode (CE) may also be disposed on the fifth insulating layer (135). The cathode electrode (CE) may include a conductive material. The anode electrode (AE), the light-emitting layer (EL), and the cathode electrode (CE) may form a light-emitting device (LED).

[0066] The encapsulation layer (140) may be disposed on the cathode electrode (CE). The encapsulation layer (140) may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In one embodiment, the encapsulation layer (140) may include a first inorganic encapsulation layer (141) disposed on the cathode electrode (CE), an organic encapsulation layer (142) disposed on the first inorganic encapsulation layer (141), and a second inorganic encapsulation layer (143) disposed on the organic encapsulation layer (142).

[0067] FIG. 3 is an enlarged plan view showing an example of a pad area of ​​the display device of FIG. 1. FIG. 4 and FIG. 5 are cross-sectional views cut along the line II-II' of FIG. 3. FIG. 6 is a cross-sectional view cut along the line III-III' of FIG. 3. FIG. 7 is a cross-sectional view cut along the line IV-IV' of FIG. 3. FIG. 8 is a cross-sectional view cut along the line VV' of FIG. 3. FIG. 9 is a cross-sectional view cut along the line VI-VI' of FIG. 3. For example, FIG. 4, FIG. 6, FIG. 7, FIG. 8 and FIG. 9 are cross-sectional views showing a display panel (100), and FIG. 5 may be a cross-sectional view showing a display device (10) in which an anisotropic conductive film (300) and a driving circuit chip (200) are disposed on the display panel (100) of FIG. 4.

[0068] Hereinafter, the pad area (PA) of the display panel (100) will be described in detail with reference to FIGS. 1 to 9.

[0069] Referring to FIGS. 1 through 9, the display panel (100) may include a plurality of pads (PDs) disposed in a pad area (PA). Additionally, the first ends of a plurality of transmission lines (TLs), each connected to a plurality of pads (PDs), may be located in the pad area (PA). In the following description, the transmission line (TL) may refer to the first end of the transmission line (TL) located in the pad area (PA).

[0070] In one embodiment, as shown in FIG. 3, a plurality of pads (PDs) may be arranged in a matrix form along a first direction (D1) and a second direction (D2). That is, the pads (PDs) may be arranged in a plurality of rows and a plurality of columns.

[0071] Each pad (PD) may include a lower electrode (PDa) and an upper electrode (PDb) placed on top of the lower electrode (PDa). Each upper electrode (PDb) may extend in a second direction (D2). That is, each upper electrode (PDb) may extend in the longitudinal direction of the pad area (PA). Each upper electrode (PDb) may have a larger area than each lower electrode (PDa). Each lower electrode (PDa) may overlap with either end of the longitudinal direction of the corresponding upper electrode (PDb) (i.e., end in the second direction (D2) or end in the third direction (D3). In one embodiment, as shown in FIG. 3, the upper electrodes (PDb) may be arranged in a matrix form along the first direction (D1) and the second direction (D2) in a plane, and the lower electrodes (PDa) may be arranged in a zigzag form in a plane.

[0072] In one embodiment, the lower electrodes (PDa) may be disposed on the same layer as the transfer lines (TL). That is, the lower electrodes (PDa) may be formed substantially simultaneously with the transfer lines (TL). At least one of the upper electrodes (PDb) may overlap with two or more transfer lines (TL) in a planar direction (i.e., in the thickness direction). This will be described in detail later.

[0073] An insulating layer may be disposed between the lower electrodes (PDa) and the upper electrodes (PDb). The insulating layer may include at least one organic insulating layer. In one embodiment, the insulating layer may further include at least one inorganic insulating layer. The insulating layer may cover the entire pad area (PA). Contact holes may be formed in the insulating layer that overlap with each of the lower electrodes (PDa). For example, the contact holes may be arranged in a zigzag shape on a plane.

[0074] The lower electrodes (PDa) and transfer lines (TL) disposed in the pad region (PA) are disposed on the same layer as any one of the conductive layers disposed in the display region (DA) and can be formed substantially simultaneously. The upper electrodes (PDb) are disposed on the same layer as another of the conductive layers disposed in the display region (DA) and can be formed substantially simultaneously. That is, the lower electrodes (PDa) and the upper electrodes (PDb) can be formed substantially simultaneously with each of the two conductive layers spaced vertically apart by at least one organic insulating layer among the various conductive layers disposed in the display region (DA). For example, the lower electrodes (PDa) and transfer lines (TL) are disposed on the same layer as the gate electrodes (GE1, GE2) and can be formed substantially simultaneously. The upper electrodes (PDb) are disposed on the same layer as the anode electrode (AE) and can be formed substantially simultaneously. In this case, as illustrated in FIGS. 4 through 9, the insulating layer between the lower electrodes (PDa) and the upper electrodes (PDb) may include second and third insulating layers (132, 133) which are inorganic insulating layers and a fourth insulating layer (134) which is an organic insulating layer. However, this is exemplary and the invention is not limited thereto. In another example, the lower electrodes (PDa) and the transfer lines (TL) may be placed on the same layer as the capacitor electrode (CE) or the drain electrodes (DE1, DE2) and may be formed substantially simultaneously. Additionally, if the third insulating layer (133) is an organic insulating layer, the upper electrodes (PDb) may be placed on the same layer as the drain electrodes (DE1, DE2) and may be formed substantially simultaneously.

[0075] Hereinafter, the pad area (PA) of the display panel (100) is described in more detail, focusing on an embodiment in which the pads (PDs) are arranged in eight rows as shown in FIG. 3. However, this is exemplary and the present invention is not limited thereto. For example, the pads (PDs) may be arranged in two to seven or nine or more rows.

[0076] The first to eighth pads (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) can form a single column. Multiple columns may be arranged in the second direction (D2) and the third direction (D3) opposite to the second direction (D2) from the column formed by the first to eighth pads (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8). The details regarding the column formed by the first to eighth pads (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) described below may be applied equally to other columns.

[0077] The first to eighth pads (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) may be arranged sequentially along the first direction (D1). The first to eighth pads (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) may each be connected to the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8).

[0078] The first pad (PD1) may include a first lower electrode (PD1a) and a first upper electrode (PD1b) disposed on the first lower electrode (PD1a). The first upper electrode (PD1b) may overlap with the first lower electrode (PD1a) in a planar manner. The first upper electrode (PD1b) may contact the first lower electrode (PD1a) through a first contact hole (CNT1) formed in the insulating layer.

[0079] In one embodiment, the first lower electrode (PD1a) may be extended in a first direction (D1). That is, the length of the first lower electrode (PD1a) in the first direction (D1) may be greater than the width in the second direction (D2).

[0080] In one embodiment, the first lower electrode (PD1a) may be electrically and physically connected to the first transmission line (TL1). The first transmission line (TL1) may be adjacent to the third direction (D3) of the first lower electrode (PD1a). For example, the first lower electrode (PD1a) may be formed integrally with the first transmission line (TL1).

[0081] The first upper electrode (PD1b) can be extended in a second direction (D2). That is, the length of the first upper electrode (PD1b) in the second direction (D2) can be greater than the width in the first direction (D1).

[0082] The first upper electrode (PD1b) extending in the second direction (D2) may have a relatively large area. The first upper electrode (PD1b) may have a larger area than the first lower electrode (PD1a). In one embodiment, as shown in FIG. 3, the length of the first upper electrode (PD1b) in the second direction (D2) may be larger than the width of the first lower electrode (PD1a) in the second direction (D2).

[0083] The first lower electrode (PD1a) may overlap with a part of the first upper electrode (PD1b). In one embodiment, the first lower electrode (PD1a) may overlap with the end of the first upper electrode (PD1b) in the second direction (D2).

[0084] The second pad (PD2) may be adjacent to the first pad (PD1) in a first direction (D1). The second pad (PD2) may include a second lower electrode (PD2a) and a second upper electrode (PD2b) disposed on the second lower electrode (PD2a). The second pad (PD2) may be substantially identical or similar to the first pad (PD1) described above, except that the second lower electrode (PD2a) overlaps with the end of the second upper electrode (PD2b) in a third direction (D3).

[0085] The second upper electrode (PD2b) may be adjacent to the first upper electrode (PD1b) in the first direction (D1). The second lower electrode (PD2a) may overlap with the end of the second upper electrode (PD2b) in the third direction (D3). The second upper electrode (PD2b) may contact the second lower electrode (PD2a) through a second contact hole (CNT2) formed in the insulating layer. The second lower electrode (PD2a) may be electrically and physically connected to the second transmission line (TL2). The second transmission line (TL2) may be adjacent to the second direction (D2) of the second lower electrode (PD2a). For example, the second lower electrode (PD2a) may be formed integrally with the second transmission line (TL2).

[0086] Each of the third pad (PD3), the fifth pad (PD5), and the seventh pad (PD7) may be substantially identical or similar to the first pad (PD1). For example, the third lower electrode (PD3a) of the third pad (PD3) may overlap with the end of the third upper electrode (PD3b) in the second direction (D2). The third upper electrode (PD3b) may contact the third lower electrode (PD3a) through a third contact hole (CNT3) formed in the insulating layer. The fifth lower electrode (PD5a) of the fifth pad (PD5) may overlap with the end of the fifth upper electrode (PD5b) in the second direction (D2). The seventh lower electrode (PD7a) of the seventh pad (PD7) may overlap with the end of the seventh upper electrode (PD7b) in the second direction (D2). Each of the fourth pad (PD4), the sixth pad (PD6), and the eighth pad (PD8) may be substantially identical or similar to the second pad (PD2). For example, the fourth lower electrode (PD4a) of the fourth pad (PD4) may overlap with the third direction (D3) end of the fourth upper electrode (PD4b). For example, the sixth lower electrode (PD6a) of the sixth pad (PD6) may overlap with the third direction (D3) end of the sixth upper electrode (PD6b). For example, the eighth lower electrode (PD8a) of the eighth pad (PD8) may overlap with the third direction (D3) end of the eighth upper electrode (PD8b). That is, in one embodiment, as shown in FIG. 3, the first to eighth upper electrodes (PD1b, PD2b, PD3b, PD4b, PD5b, PD6b, PD7b, PD8b) are arranged in a line along the first direction (D1), and the first to eighth lower electrodes (PD1a, PD2a, PD3a, PD4a, PD5a, PD6a, PD7a, PD8a) can be arranged in a zigzag shape along the first direction (D1).

[0087] In one embodiment, within the pad area (PA), the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be arranged adjacent to each other. The first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be spaced apart from each other in a second direction (D2) and a third direction (D3). For example, the second, fourth, sixth, and eighth transmission lines (TL2, TL4, TL6, TL8) may be spaced apart from the first, third, fifth, and seventh transmission lines (TL1, TL3, TL5, TL7) in the third direction (D3).

[0088] In one embodiment, the pad area (PA) may include an overlapping area (OA) and a non-overlapping area (NOA). The overlapping area (OA) may be an area that overlaps with the first to eighth upper electrodes (PD1b, PD2b, PD3b, PD4b, PD5b, PD6b, PD7b, PD8b). The overlapping area (OA) may extend in a first direction (D1). The non-overlapping area (NOA) may be an area that does not overlap with the first to eighth upper electrodes (PD1b, PD2b, PD3b, PD4b, PD5b, PD6b, PD7b, PD8b) and upper electrodes (PDb) of an adjacent other row. The non-overlapping area (NOA) may be located in a second direction (D2) and a third direction (D3), respectively, from the overlapping area (OA) and may extend in a first direction (D1).

[0089] The first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be placed in an overlapping area (OA). That is, within the pad area (PA), the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be placed between the first lower electrode (PD1a) and the second lower electrode (PD2a).

[0090] In one embodiment, the first upper electrode (PD1b) may overlap with each of the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) on a plane. The second upper electrode (PD2b) may overlap with each of the second to eighth transmission lines (TL2, TL3, TL4, TL5, TL6, TL7, TL8) on a plane and may be spaced apart from the first transmission line (TL1). The third upper electrode (PD3b) may overlap with each of the third to eighth transmission lines (TL3, TL4, TL5, TL6, TL7, TL8) on a plane and may be spaced apart from each of the first and second transmission lines (TL1, TL2). The fourth upper electrode (PD4b) may overlap with each of the fourth to eighth transmission lines (TL4, TL5, TL6, TL7, TL8) on a plane and be spaced apart from each of the first to third transmission lines (TL1, TL2, TL3). The fifth upper electrode (PD5b) may overlap with each of the fifth to eighth transmission lines (TL5, TL6, TL7, TL8) on a plane and be spaced apart from each of the first to fourth transmission lines (TL1, TL2, TL3, TL4). The sixth upper electrode (PD6b) may overlap with each of the sixth to eighth transmission lines (TL6, TL7, TL8) on a plane and be spaced apart from each of the first to fifth transmission lines (TL1, TL2, TL3, TL4, TL5). The seventh upper electrode (PD7b) may overlap with each of the seventh and eighth transmission lines (TL7, TL8) in a plane and be spaced apart from each of the first to sixth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6). The eighth upper electrode (PD8b) may overlap with the eighth transmission line (TL8) in a plane and be spaced apart from each of the first to seventh transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7). However, this is exemplary and the invention is not limited thereto.

[0091] Although FIG. 3 shows the spacing in the second direction (D2) between the seventh transmission line (TL7) and the eighth transmission line (TL8) as relatively large, in one embodiment, the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be arranged at substantially uniform spacing in the second direction (D2).

[0092] In another embodiment, additional transmission lines may be arranged between the seventh transmission line (TL7) and the eighth transmission line (TL8). For example, ninth and tenth pads may be additionally arranged in the first direction (D1) of the eighth pad (PD8), and ninth and tenth transmission lines connected to each of the ninth and tenth pads may be arranged between the seventh transmission line (TL7) and the eighth transmission line (TL8). That is, the number of pads (PDs) constituting a column may be increased. Accordingly, the display device (10) can achieve high resolution.

[0093] Referring to FIGS. 1, 3 and 5, an anisotropic conductive film (300) and a driving circuit chip (200) may be disposed on pads (PDs). The anisotropic conductive film (300) may include a resin layer (310) and a plurality of conductive balls (320) dispersed within the resin layer (310). The driving circuit chip (200) may include a base substrate (210) and a plurality of bumps (220) disposed below the base substrate (210) and spaced apart from each other. Each upper electrode (PDb) may be connected to a corresponding bump (220) through at least one conductive ball (320). For example, a first upper electrode (PD1b) may be connected to a first bump, and a second upper electrode (PD2b) may be connected to a second bump spaced apart from the first bump. As each upper electrode (PDb) extends in the second direction (D2), each upper electrode (PDb) can have a relatively large area. Accordingly, the display device (10) can prevent or reduce poor connection between the pads (PD) of the display panel (100) and the bumps (220) of the driving circuit chip (200). Thus, the reliability of the display device (10) can be improved.

[0094] Additionally, the lower electrodes (PDa) and the transfer lines (TL) may be placed on a different layer from the upper electrodes (PDb) that are in contact with the anisotropic conductive film (300). Thus, even if the area of ​​each lower electrode (PDa) is reduced, the pads (PD) can be sufficiently connected to the corresponding bumps (220) through each upper electrode (PDb) having a relatively large area. Thus, the area of ​​each lower electrode (PDa) can be reduced (e.g., the width of each lower electrode (PDa) in the second direction (D2) can be reduced), and the area of ​​the region where the transfer lines (TL) can be placed within the pad region (PA) (e.g., the region excluding the lower electrodes (PDa)) can be increased. Thus, the display device (10) can prevent or reduce short circuit defects between the transfer lines (TL). Also, as described above, the number of pads (PD) constituting a row may be increased. Therefore, the display device (10) can achieve high resolution.

[0095] FIG. 10 is an enlarged plan view illustrating another example of the pad area of ​​the display device of FIG. 1. FIG. 11 is an enlarged plan view illustrating yet another example of the pad area of ​​the display device of FIG. 1. Hereinafter, the differences from the embodiment described with reference to FIG. 3 to 9 will be explained.

[0096] Referring to FIGS. 1, 10 and 11, in one embodiment, some of the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be placed in a non-overlapping area (NOA). That is, within the pad area (PA), some of the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be located outside the first upper electrode (PD1b) (i.e., in the second direction (D2) or the third direction (D3)).

[0097] For example, as illustrated in FIG. 10, the second transmission line (TL2) may be placed in a non-overlapping area (NOA), and the first transmission line (TL1) and the third to eighth transmission lines (TL3, TL4, TL5, TL6, TL7, TL8) may be placed in an overlapping area (OA). The second transmission line (TL2) may be located in a third direction (D3) from the first upper electrode (PD1b). In this case, the first upper electrode (PD1b) may overlap with each of the first transmission line (TL1) and the third to eighth transmission lines (TL3, TL4, TL5, TL6, TL7, TL8) in a plane and be spaced apart from the second transmission line (TL2).

[0098] As another example, as illustrated in FIG. 11, the first and second transmission lines (TL1, TL2) may be placed in a non-overlapping area (NOA), and the third to eighth transmission lines (TL3, TL4, TL5, TL6, TL7, TL8) may be placed in an overlapping area (OA). The first transmission line (TL1) may be located in the second direction (D2) from the first upper electrode (PD1b). The second transmission line (TL2) may be located in the third direction (D3) from the first upper electrode (PD1b). However, this is exemplary and the invention is not limited thereto, and other transmission lines among the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be placed in the non-overlapping area (NOA).

[0099] If some of the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) are placed in a non-overlapping area (NOA) and others are placed in an overlapping area (OA), the spacing between the transmission lines (TL) can be relatively large. Accordingly, the display device (10) can prevent or reduce short circuit defects occurring between the transmission lines (TL). In addition, the display device (10) can achieve high resolution.

[0100] FIG. 12 is an enlarged plan view illustrating another example of the pad area of ​​the display device of FIG. 1. Hereinafter, the differences from the embodiment described with reference to FIG. 3 to 9 will be explained.

[0101] Referring to FIGS. 1 and FIGS. 12, in one embodiment, the first lower electrode (PD1a) may overlap with the end of the second direction (D2) of the first upper electrode (PD1b). The second lower electrode (PD2a) may overlap with the end of the second direction (D2) of the second upper electrode (PD2b). The third lower electrode (PD3a) may overlap with the end of the second direction (D2) of the third upper electrode (PD3b). The fourth lower electrode (PD4a) may overlap with the end of the second direction (D2) of the fourth upper electrode (PD4b).

[0102] The fifth lower electrode (PD5a) may overlap with the third direction (D3) end of the fifth upper electrode (PD5b). The sixth lower electrode (PD6a) may overlap with the third direction (D3) end of the sixth upper electrode (PD6b). The seventh lower electrode (PD7a) may overlap with the third direction (D3) end of the seventh upper electrode (PD7b). The eighth lower electrode (PD8a) may overlap with the third direction (D3) end of the eighth upper electrode (PD8b).

[0103] Although FIG. 12 shows that the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) are all placed in an overlapping area (OA), in one embodiment, some of the first to eighth transmission lines (TL1, TL2, TL3, TL4, TL5, TL6, TL7, TL8) may be placed in a non-overlapping area (NOA).

[0104] FIG. 13 is an enlarged plan view illustrating another example of the pad area of ​​the display device of FIG. 1. FIG. 14 is a cross-sectional view taken along the line VII-VII' of FIG. 13. FIG. 15 is a cross-sectional view taken along the line VIII-VIII' of FIG. 13. FIG. 16 is a cross-sectional view taken along the line IX-IX' of FIG. 13. FIG. 17 is a cross-sectional view taken along the line XX' of FIG. 13. FIG. 18 is a cross-sectional view taken along the line XI-XI' of FIG. 13. The following description focuses on the differences from the embodiment described with reference to FIG. 3 to 9.

[0105] Referring to FIGS. 1, 13 to 18, in one embodiment, a plurality of pads (PDs) may be arranged in a zigzag shape on a plane. Upper electrodes (PDb) may be arranged in a zigzag shape on a plane. Each lower electrode (PDa) may overlap with the central portion of the length direction (i.e., the second direction (D2)) of the corresponding upper electrode (PDb). Accordingly, the lower electrodes (PDb) may be arranged in a zigzag shape on a plane.

[0106] For example, the first to eighth pads (PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8) constituting a column can be arranged in a zigzag shape along the first direction (D1).

[0107] The first to eighth upper electrodes (PD1b, PD2b, PD3b, PD4b, PD5b, PD6b, PD7b, PD8b) can be arranged in a zigzag shape along the first direction (D1). The first to eighth lower electrodes (PD1a, PD2a, PD3a, PD4a, PD5a, PD6a, PD7a, PD8a) can overlap with the central portion in the longitudinal direction of each of the first to eighth upper electrodes (PD1b, PD2b, PD3b, PD4b, PD5b, PD6b, PD7b, PD8b). Accordingly, the first to eighth lower electrodes (PD1a, PD2a, PD3a, PD4a, PD5a, PD6a, PD7a, PD8a) can be arranged in a zigzag shape along the first direction (D1). Additionally, the contact holes formed in the insulating layer can be arranged in a zigzag shape on a plane.

[0108] Within the pad area (PA), the first, third, fifth, and seventh transfer lines (TL1, TL3, TL5, TL7) may be located in the third direction (D3) from the first lower electrode (PD1a). The first, third, fifth, and seventh transfer lines (TL1, TL3, TL5, TL7) may be located in the second direction (D2) from the second lower electrode (PD2a). The second, fourth, sixth, and eighth transfer lines (TL2, TL4, TL6, TL8) may be located in the third direction (D3) from the second lower electrode (PD2a).

[0109] According to embodiments of the present invention, each pad (PD) disposed within a pad area (PA) may include a lower electrode (PDa) and an upper electrode (PDb). Each upper electrode (PDb) extends in a second direction (D2) and may be connected to a corresponding bump (220) through an anisotropic conductive film (300). As each upper electrode (PDb) extends in the second direction (D2), each upper electrode (PDb) may have a relatively large area. Accordingly, the display device (10) can prevent or reduce poor connection between the pads (PD) of the display panel (100) and the bumps (220) of the driving circuit chip (200). Accordingly, the reliability of the display device (10) can be improved.

[0110] Additionally, the lower electrodes (PDa) and the transfer lines (TL) may be placed on a different layer from the upper electrodes (PDb) that are in contact with the anisotropic conductive film (300). Thus, even if the area of ​​each lower electrode (PDa) is reduced, the pads (PD) can be sufficiently connected to the corresponding bumps (220) through each upper electrode (PDb) having a relatively large area. Thus, the area of ​​each lower electrode (PDa) can be reduced (e.g., the width of each lower electrode (PDa) in the second direction (D2) can be reduced), and the area of ​​the region where the transfer lines (TL) can be placed within the pad region (PA) (e.g., the region excluding the lower electrodes (PDa)) can be increased. Thus, the display device (10) can prevent or reduce short circuit defects between the transfer lines (TL). Also, as described above, the number of pads (PD) constituting a row may be increased. Therefore, the display device (10) can achieve high resolution.

[0111] FIG. 19 is a plan view showing a display device according to another embodiment of the present invention.

[0112] Referring to FIG. 19, a display device (11) according to another embodiment of the present invention may include a display panel (101) and a plurality of driving circuit chips (200). The display panel (101) of FIG. 19 may have a relatively large area compared to the display panel (100) of FIG. 1. The display panel (101) may include a display area (DA) and a non-display area (NDA). A plurality of pixels for generating an image may be arranged in the display area (DA). The non-display area (NDA) may be located around the display area (DA). The non-display area (NDA) may include a plurality of pad areas (PA). A plurality of driving circuit chips (200) may be mounted on each of the plurality of pad areas (PA) of the display panel (101). A plurality of pads may be arranged in each pad area (PA). A plurality of transmission lines (TL) may be arranged between the display area (DA) and each pad area (PA). The various embodiments described with reference to FIGS. 3 to 18 can also be applied to a large-area display panel (101) shown in FIG. 19.

[0113] FIG. 20 is a block diagram showing an electronic device including a display device according to embodiments of the present invention.

[0114] Referring to FIG. 20, in one embodiment, the electronic device (900) may include a processor (910), a memory device (920), a storage device (930), an input / output device (940), a power supply (950), and a display device (960). In this case, the display device (960) may correspond to either the display device (10) of FIG. 1 or the display device (11) of FIG. 19. The electronic device (900) may further include several ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. In one embodiment, the electronic device (900) may be implemented as a television. In another embodiment, the electronic device (900) may be implemented as a smartphone. However, the electronic device (900) is not limited to this, and, for example, the electronic device (900) may be implemented as a mobile phone, video phone, smart pad, smart watch, tablet PC, vehicle navigation, computer monitor, laptop, head mounted display (HMD), etc.

[0115] The processor (910) can perform specific calculations or tasks. In one embodiment, the processor (910) may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor (910) may be connected to other components via an address bus, a control bus, a data bus, etc. In one embodiment, the processor (910) may also be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0116] The memory device (920) can store data necessary for the operation of the electronic device (900). For example, the memory device (920) may include non-volatile memory devices such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and / or volatile memory devices such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.

[0117] The storage device (930) may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input / output device (940) may include input means such as a keyboard, a keypad, a touchpad, a touchscreen, a mouse, etc., and output means such as a speaker, a printer, etc.

[0118] The power supply (950) can supply power necessary for the operation of the electronic device (900). The display device (960) can be connected to other components via buses or other communication links. In one embodiment, the display device (960) may be included in the input / output device (940). Industrial applicability

[0119] The present invention can be applied to various display devices. For example, the present invention can be applied to various display devices such as display devices for vehicles, ships, and aircraft, portable communication devices, display devices for exhibition or information transmission, medical display devices, etc.

[0120] Although the present invention has been described above with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Explanation of the symbols

[0121] 10, 11: Display device 100: Display panel 200: Driving circuit chip 300: Anisotropic conductive film DA: Display area NDA: Non-display area TL: Delivery Line PDA: Pad Area PD: Pad PDa: Lower electrode PDb: Upper electrode

Claims

Claim 1 A display panel comprising: a substrate including a display area and a pad area spaced apart from the display area in a first direction; a plurality of pixels disposed in the display area on the substrate; a plurality of pads disposed in the pad area on the substrate, each pad including a lower electrode and an upper electrode disposed above the lower electrode and extending in a second direction perpendicular to the first direction; and a plurality of transmission lines each connected to the plurality of pads, wherein the length of the pad area in the second direction is greater than the width of the pad area in the first direction, and the length of the upper electrode in the second direction is greater than the width of the upper electrode in the first direction. Claim 2 A display panel according to claim 1, characterized in that the length of each lower electrode in the first direction is greater than the width of each lower electrode in the second direction. Claim 3 A display panel according to claim 2, characterized in that the width of each lower electrode in the second direction is smaller than the length of each upper electrode in the second direction. Claim 4 A display panel according to claim 3, characterized in that each of the lower electrodes overlaps with either of the two ends of the second direction of the corresponding upper electrode. Claim 5 A display panel characterized in that, in claim 3, each of the above-mentioned lower electrodes overlaps with the central portion of the second direction of the corresponding above-mentioned upper electrode. Claim 6 A display panel according to claim 1, characterized in that at least one of the upper electrodes overlaps with two or more of the transmission lines on a plane. Claim 7 A display panel according to claim 6, characterized in that the transmission lines are disposed on the same layer as the lower electrodes. Claim 8 A display panel according to claim 1, characterized in that the upper electrodes are arranged in a matrix form along the first direction and the second direction on a plane. Claim 9 A display panel according to claim 8, characterized in that the lower electrodes are arranged in a zigzag shape on a flat surface. Claim 10 A display panel according to claim 8, wherein the pads comprise: a first pad including a first upper electrode and a first lower electrode disposed below the first upper electrode and connected to a first transmission line among the transmission lines; and a second pad including a second upper electrode adjacent to the first direction of the first upper electrode and a second lower electrode disposed below the second upper electrode and connected to a second transmission line among the transmission lines. Claim 11 A display panel according to claim 10, characterized in that the first lower electrode overlaps with the end of the first upper electrode in the second direction on a flat plane, and the second lower electrode overlaps with the end of the second upper electrode in the third direction opposite to the second direction on a flat plane. Claim 12 A display panel according to claim 11, characterized in that the first upper electrode overlaps with the first transmission line and the second transmission line, respectively, on a plane. Claim 13 A display panel according to claim 12, characterized in that the second upper electrode overlaps with the second transmission line on a plane and is spaced apart from the first transmission line. Claim 14 A display panel according to claim 11, characterized in that the first upper electrode overlaps with the first transmission line on a plane and is spaced apart from the second transmission line. Claim 15 A display panel according to claim 11, characterized in that the second transmission line is spaced apart from the first transmission line in the third direction on a plane. Claim 16 A display panel according to claim 11, characterized in that each of the first transmission line and the second transmission line is located on a plane between the first lower electrode and the second lower electrode. Claim 17 A display panel according to claim 11, wherein the pads further comprise a third pad including a third upper electrode adjacent to the first direction of the second upper electrode and a third lower electrode disposed below the third upper electrode and connected to the third transmission line among the transmission lines, wherein the third lower electrode overlaps with the end of the second direction of the third upper electrode. Claim 18 A display panel according to claim 17, wherein the first upper electrode overlaps with the first transmission line, the second transmission line, and the third transmission line, respectively, on a plane, the second upper electrode overlaps with the second transmission line and the third transmission line, respectively, and is spaced apart from the first transmission line, and the third upper electrode overlaps with the third transmission line, respectively, on a plane, and is spaced apart from the first transmission line and the second transmission line, respectively. Claim 19 A display panel according to claim 10, characterized in that the first lower electrode overlaps with the second direction end of the first upper electrode on a flat plane, and the second lower electrode overlaps with the second direction end of the second upper electrode on a flat plane. Claim 20 A display panel according to claim 19, wherein the first upper electrode overlaps with the first transmission line and the second transmission line, respectively, on a plane, and the second upper electrode overlaps with the second transmission line on a plane and is spaced apart from the first transmission line. Claim 21 A display panel according to claim 1, characterized in that the upper electrodes are arranged in a zigzag shape on a flat surface. Claim 22 A display panel according to claim 21, characterized in that each of the lower electrodes overlaps with the longitudinal central portion of the corresponding upper electrode. Claim 23 A display panel according to claim 1, further comprising an organic insulating layer disposed between the lower electrodes and the upper electrodes, wherein each of the upper electrodes contacts the corresponding lower electrode through a contact hole formed in the organic insulating layer. Claim 24 A display panel according to claim 1, wherein each of the pixels comprises: a transistor including an active layer, a gate electrode disposed on the active layer, a source electrode and a drain electrode disposed on the gate electrode; and a light-emitting element including an anode electrode disposed on the source electrode and the drain electrode, a light-emitting layer disposed on the anode electrode, and a cathode electrode disposed on the light-emitting layer, wherein each of the lower electrodes is disposed on the same layer as the gate electrode, and each of the upper electrodes is disposed on the same layer as the anode electrode. Claim 25 A display device comprising: a substrate including a display area and a pad area spaced apart from the display area in a first direction; a plurality of pixels disposed in the display area on the substrate; a plurality of pads disposed in the pad area on the substrate, each pad including a lower electrode and an upper electrode disposed on the lower electrode and extending in a second direction perpendicular to the first direction; and a plurality of transmission lines each connected to the plurality of pads; a driving circuit chip disposed in the pad area on the display panel and including a plurality of bumps; and an anisotropic conductive film disposed between the display panel and the driving circuit chip and connecting the bumps corresponding to the pads, wherein the length of the pad area in the second direction is greater than the width of the pad area in the first direction, and the length of the upper electrode in the second direction is greater than the width of the upper electrode in the first direction.

Images