Thin film transistor manufactured using deep ultraviolet pre-annealing process

Abstract

The present invention relates to a thin-film transistor comprising a substrate having the function of a lower gate electrode, an insulating layer formed on the substrate, an active layer formed as a solution-process-based amorphous oxide thin film on the insulating layer, and an upper electrode formed on the active layer including a source electrode and a drain electrode, wherein the active layer is formed by performing a deep UV pretreatment process by irradiating deep UV, and the entire structure is manufactured by performing a heat treatment process before the pretreatment process is performed and the upper electrode is formed. According to the present invention, there is an effect of maintaining the chemical stability of graphene oxide while reducing oxygen defects within the indium oxide / graphene oxide (In2O3 / GO) composite layer.

Description

Technology Field

[0001] The present invention relates to a thin-film transistor, and more specifically, to a thin-film transistor applicable to digital circuits. Background Technology

[0003] Over the past few decades, amorphous metal oxide semiconductors have emerged as attractive candidates for replacing silicon-based logic in specific fields due to their inherent n-type operating characteristics, high electron density, charge carrier mobility, and excellent transparency in the visible light region. Binary and ternary mixed oxides, such as indium oxide (In2O3), indium zinc oxide (IZO), and indium zinc gallium oxide (IGZO), are widely used in the fabrication of high-performance thin film transistors (TFTs).

[0004] One of the characteristics of In2O3 is that high-performance amorphous thin films can be easily deposited using solution process technology, which is a key method for reducing semiconductor production costs. Conventional methods such as sputtering or atomic layer deposition require long processing times accompanied by expensive equipment and strict size limitations. In particular, spin coating using indium nitrate dissolved in water can be used to form high-quality thin films at appropriate baking temperatures.

[0005] A wide range of methods have been proposed to improve the performance of conventional metal oxide thin films, such as pulsed laser treatment, deep UV treatment in an inert environment, and deep UV and ozone treatment under ambient conditions. In the case of solution processes, various dopants can be introduced at arbitrary concentrations by preparing mixed precursor solutions. Over the past decade, the use of oxides of various metals has been the primary approach used to control the performance of In2O3 semiconductor thin films.

[0006] Graphene or its derivatives, such as graphene oxide (GO), reduced graphene oxide (rGO), and alkylated graphene, are electrically active materials that have previously been used in conjunction with oxide semiconductors. However, due to differences in atomic structure, doping inventions have rarely occurred. Graphene itself acts as a conductor because it has no band gap between the conduction band and the valence band, and it is frequently used as an electrode material. However, in the case of derivatives such as GO, additional covalent bonds bind free electrons, causing sp² 2 It disrupts the network and reduces conductivity. On the other hand, the covalent oxygen functional groups of GO possess greater mechanical strength and chemical sensing capabilities at the molecular level, improving the quality of thin film formation and controlling the electrical properties of metal oxide thin films. However, challenges remain regarding the homogeneity and stability of these hybrid layers.

[0007] Thermal annealing is the most common method in TFT manufacturing processes and can effectively improve the crystallinity of thin films and the electronic structure of oxides. However, since thermal annealing generally requires high temperatures of 300°C or higher, its application to flexible or low-temperature substrates is limited. Currently, there are few inventions regarding devices having a mixed active layer of metal oxide and graphene derivative combined with processing processes other than thermal annealing. Prior art literature

[0008] Republic of Korea Published Patent 10-2021-0043553 The problem to be solved

[0009] The present invention has been devised to solve the above-mentioned problems, and aims to provide a thin-film transistor manufactured using a deep UV pretreatment process to improve the electrical characteristics of the transistor.

[0010] The objectives of the present invention are not limited to those mentioned above, and other unmentioned objectives will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0012] The present invention, for achieving the above purpose, relates to a thin-film transistor comprising a substrate having the function of a lower gate electrode, an insulating layer formed on the substrate, an active layer formed as a solution-process-based amorphous oxide thin film on the insulating layer, and an upper electrode formed on the active layer including a source electrode and a drain electrode, wherein the active layer is formed by performing a deep UV pretreatment process by irradiating deep UV, and the entire structure is manufactured by performing a heat treatment process before the pretreatment process is performed and the upper electrode is formed.

[0013] The above active layer may be formed as a thin film of graphene oxide doped into indium oxide (In2O3).

[0014] The insulating layer may be formed by growing SiO2 as a gate dielectric on the substrate.

[0015] The upper electrode may be formed by depositing aluminum.

[0016] The above active layer may be formed by performing the deep ultraviolet pretreatment process by irradiating deep ultraviolet rays having two wavelengths of 185 nm and 254 nm. Effects of the invention

[0018] According to the present invention, by introducing a deep UV pretreatment process in a thin-film transistor manufacturing process, it is possible to reduce oxygen defects within an indium oxide / graphene oxide (In2O3 / GO) composite layer while maintaining the chemical stability of graphene oxide.

[0019] In addition, according to the present invention, there is an effect of improving overall electrical characteristics, such as improving the mobility of the transistor, stabilizing the threshold voltage, reducing the subthreshold swing, reducing the trap density, and improving the On / Off current ratio.

[0020] In addition, the thin-film transistor manufactured according to the present invention has the effect of being applicable to digital circuits, including inverter circuits. Brief explanation of the drawing

[0021] FIG. 1 is a diagram showing a stacked structure of a thin-film transistor according to one embodiment of the present invention. FIG. 2 illustrates a schematic diagram of a TFT device structure according to one embodiment of the present invention and a deep ultraviolet pre-annealing process including heat treatment. Figure 3 shows the XPS spectrum with Gaussian and relative peak areas applied to the TFT device in the experiment of the present invention. Figure 4 shows the FTIR spectra of the original state and deep ultraviolet pre-heat-treated In2O3 / GO TFT in the experiment of the present invention. FIG. 5 is a schematic diagram of the formation of an In2O3 / GO active layer in the experiment of the present invention, in the case of (a) heat treatment only on a pristine thin film and (b) heat treatment after deep ultraviolet pre-annealing treatment. Figure 6 illustrates the output curve and transfer curve of a TFT device in an experiment of the present invention. Figure 7 illustrates (a) saturation charge carrier mobility, (b) on / off current ratio, (c) threshold voltage, and (d) subthreshold swing (SS) distribution of a pristine TFT device and a TFT device having a deep UV-treated In2O3 / GO active layer in an experiment of the present invention. Figure 8 illustrates the transfer characteristics of a TFT device before and after PBS and NBS in an experiment of the present invention. Figure 9 shows the change in threshold voltage of an In2O3 / GO TFT as a function of bias stress time under (i) PBS and (ii) NBS in an experiment of the present invention. Figure 10 is a graph showing the results of various electrical performance tests of a TFT device and a load-type inverter in an experiment of the present invention. Specific details for implementing the invention

[0022] The present invention is capable of various modifications and may have various embodiments, and specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0023] The terms used in this application are used merely to describe specific embodiments and are not intended to limit the invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, terms such as "comprising" or "having" are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0024] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this application.

[0025] Furthermore, in the description referring to the attached drawings, identical components are assigned the same reference numeral regardless of drawing symbols, and redundant descriptions thereof are omitted. In describing the present invention, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of the present invention, such detailed description is omitted.

[0026] The present invention relates to a thin-film transistor.

[0027] FIG. 1 is a diagram showing a stacked structure of a thin-film transistor according to one embodiment of the present invention.

[0028] Referring to FIG. 1, the present invention relates to a thin-film transistor comprising a substrate (110) having the function of a lower gate electrode, an insulating layer (120) formed on the substrate (110), an active layer (130) formed as a solution-process-based amorphous oxide thin film on the insulating layer (120), and upper electrodes (142, 144) formed on the active layer (130) including a source electrode (142) and a drain electrode (144). Here, the active layer (130) is formed by performing a deep UV pretreatment process by irradiating deep UV, and is manufactured by performing a heat treatment process overall before the pretreatment process is performed and the upper electrodes (142, 144) are formed.

[0029] In the present invention, the active layer (130) may be formed as a thin film of graphene oxide doped into indium oxide (In2O3).

[0030] In the present invention, the insulating layer (120) may be formed by growing SiO2 as a gate dielectric on a substrate (110).

[0031] In the present invention, the upper electrode (142, 144) may be formed by depositing aluminum.

[0032] In the present invention, the active layer (130) may be formed by performing the deep ultraviolet pretreatment process by irradiating deep ultraviolet rays having two wavelengths of 185 nm and 254 nm. That is, the deep ultraviolet pretreatment process may be performed by irradiating the active layer (130) with deep ultraviolet rays having two wavelengths of 185 nm and 254 nm. In one embodiment of the present invention, deep ultraviolet rays may be irradiated onto the active layer (130) for 20 seconds. Furthermore, the deep ultraviolet pretreatment process may be performed by irradiating the active layer (130) for 20 seconds at a ratio of 10% of the 185 nm wavelength and 90% of the 254 nm wavelength.

[0033] In carrying out the heat treatment process in the present invention, the heat treatment process can be carried out by soft-bake at 80°C for 5 minutes and hard-bake at 250°C for 2 hours.

[0034] FIG. 2 illustrates a schematic diagram of a TFT device structure according to one embodiment of the present invention and a deep ultraviolet pre-annealing process including heat treatment.

[0035] Referring to FIG. 2, a thin film transistor according to one embodiment of the present invention includes a substrate (110), an insulator layer (120), an active layer (130), and top electrodes (142, 144).

[0036] A thin-film transistor according to one embodiment of the present invention can be fabricated with a top-contact bottom-gate structure.

[0037] The substrate (110) includes the function of a lower gate electrode. In one embodiment of the present invention, the substrate (110) may be implemented as an N-type heavily doped silicon (Si) wafer substrate and used as a gate lower electrode. For example, the substrate (110) may be implemented as a silicon (Si) wafer substrate with a thickness of 600 μm.

[0038] An insulating layer (120) is formed on a substrate (110). In one embodiment of the present invention, the insulating layer (110) may be formed by growing SiO2 on the substrate (110). For example, it may be formed by growing 100 nm of SiO2 through a thermal oxidation process in a furnace.

[0039] The active layer (130) is formed on the insulating layer (120). In one embodiment of the present invention, the active layer (130) may be formed as a thin film of graphene oxide doped indium oxide (In2O3).

[0040] The upper electrode is formed on the active layer (130) including a source electrode (142) and a drain electrode (144). In one embodiment of the present invention, the upper electrode may be formed by depositing aluminum.

[0041] In the present invention, a deep UV pre-annealing process is performed by irradiating the active layer (130) with deep UV. Then, after the pre-annealing process, a thermal annealing process is performed overall. After the thermal annealing process, an upper electrode including a source electrode (142) and a drain electrode (144) is formed on the active layer (130).

[0042] In the present invention, the deep UV irradiator (200) irradiates deep UV light onto the active layer (130).

[0043] In one embodiment of the present invention, the deep ultraviolet irradiator (200) can irradiate the active layer (130) with deep ultraviolet rays having two wavelengths of 185 nm and 254 nm. In one embodiment of the present invention, the deep ultraviolet irradiator (200) can irradiate the active layer (1130) with deep ultraviolet rays for 20 seconds. Furthermore, the deep ultraviolet irradiator (200) can irradiate the active layer (130) for 20 seconds at a ratio of 10% of the 185 nm wavelength and 90% of the 254 nm wavelength.

[0044] The heat treatment process can be carried out by soft-bake at 80°C for 5 minutes and hard-bake at 250°C for 2 hours.

[0046] In the present invention, the performance of the In2O3 / GO composite active layer is improved under room temperature deep UV pre-annealing conditions.

[0047] In the present invention, the active layer thin film is deposited by a single-step spin coating process in which an aqueous solution of In(NO3)3 is mixed with a GO (graphene oxide) suspension. Subsequent deep ultraviolet irradiation acts as a low-temperature photochemical activation method that induces effective condensation and densification of the oxide semiconductor thin film. High-energy deep ultraviolet irradiation promotes the photochemical cleavage of alkoxy groups and activates metal and oxygen atoms to promote the formation of a MOM network. Continuous irradiation gradually removes oxygen and carbon species, thereby enabling nearly complete condensation and densification of the thin film.

[0048] When deep ultraviolet rays are irradiated at room temperature, ozone is expected to be generated from oxygen in the atmosphere, and deep ultraviolet rays are expected to help decompose nitrate anions. However, since the two wavelengths of 254 nm (90%) and 185 nm (10%) emitted by currently used low-pressure mercury lamps are still not satisfactory for device optimization, the present invention aims to achieve an optimal balance between device performance and stability by combining a GO-doped active layer with the synergistic effect of deep ultraviolet pretreatment.

[0049] Chemical changes in thin films caused by exposure were investigated using X-ray photoelectron spectroscopy (XPS), and experiments were conducted to compare and evaluate the effect of UV treatment on electronic performance characteristics for transistor devices having an untreated (original) active layer and a UV-treated active layer in a dark room environment. In addition, the gate bias stability of the two types of active layers was compared under negative (-) and positive (+) stress. Furthermore, the applicability of UV-treated devices in digital logic was evaluated by testing current stability during use, and a simple load-type inverter was fabricated for evaluation.

[0050] The experiment of the present invention is described in detail as follows.

[0051] The active layer thin film was deposited in an aqueous precursor solution containing indium nitrate [In(NO3)3] and GO. Indium nitrate hydrate [In(NO3) 3· [xH2O] was dissolved in 0.1 M deionized water, and the solution was stirred on a hot plate at 45°C for 2 hours. Oxide devices with a GO concentration of 1 wt% achieved a balance between performance (e.g., mobility and subthreshold swing) and stability. Therefore, in this invention, a GO concentration of 1 wt% was selected as the experimental condition to further investigate the effect on device performance. The precursor solution was prepared by mixing 10 mg of a 1.0 wt% GO aqueous dispersion with 990 mg of an indium nitrate solution. Before use, the mixture was stirred for an additional 1 hour at room temperature (20–25°C).

[0052] In the present invention, a TFT device was fabricated on an n++-doped Si substrate having a thermally grown 100 nm thick SiO2 layer. This SiO2 / Si layer serves as a gate electrode and a dielectric. First, the substrate was washed in an ultrasonic cleaner with a detergent solution, deionized water, acetone, and propane-2-ol, and then dried in a drying oven. Next, the substrate surface was treated with a UV / ozone generator for 20 minutes to improve hydrophilicity.

[0053] Then, an active layer thin film was deposited on the substrate by spin coating at 3000 rpm for 30 seconds. As measured with a Bruker DektakXT stylus profiler, the thin film thickness was approximately 8 nm.

[0054] For the deep UV-treated thin film, the dried precursor thin film was irradiated with 184 nm and 254 nm UV rays for 20 seconds. Afterward, it was soft-baked at 80 °C for 5 minutes and hard-baked on a hot plate at 250 °C for 2 hours. At these temperatures, the nitrate decomposes, and indium oxide containing GO flakes is formed.

[0055] For TFT device fabrication, 100 nm thick aluminum source and drain electrodes were deposited via thermal vacuum deposition using a shadow mask to control the channel size to a length of 200 μm and a width of 2000 μm. Electrical characteristics, such as IV curves, transistor gate bias stability, and voltage transfer curves of a load-type inverter, were measured using a semiconductor parameter analyzer (Keithley 4200, Keithley Instruments LLC, Cleveland, Ohio) under dark and room temperature conditions. XPS characterization of the In2O3 thin film was performed using PHI Quantera-II. Fourier transform infrared spectroscopy (FTIR) spectra of the In2O3 / GO thin film were obtained using a Cary670 (Main Bench) / Cary620 (Microscope) spectrometer.

[0056] Figure 2 shows a schematic diagram of the device structure and process for deep UV treatment of a GO-doped In2O3 (In2O3 / GO) layer.

[0057] Generally, two wavelengths, 254 nm and 185 nm, are used for deep ultraviolet treatment. 185 nm UV irradiation separates oxygen molecules to generate reactive oxygen species, which compensates for oxygen vacancies (V) in thin films. O While it effectively fills ) and promotes metal-oxygen bond (MOM) formation, the 254 nm wavelength is V O It provides high-energy photons that promote generation. XPS of the C 1s and O 1s peaks was performed to gain insight into the chemical composition of the active layer thin film. While the carbon peak was expected to appear only in GO, the oxygen peak resulted from both GO and In2O3.

[0059] Figure 3 shows the XPS spectrum with Gaussian and relative peak areas applied to the TFT device in the experiment of the present invention.

[0060] In FIG. 3, (a) the XPS spectra with Gaussian and relative peak areas applied to the C 1s peak of the pristine and (b) UV-treated In2O3 / GO thin films are shown, and (c) the XPS spectra with Gaussian and relative peak areas applied to the O 1s peak of the pristine and (d) UV-treated In2O3 / GO thin films are shown.

[0061] Referring to Figures 3 (a) and (b), the C 1s peak was split into two separate peaks, with the smaller peak at 288.2 eV belonging to the C=O group. The larger peak can be approximated as the sum of two Gaussian distributions: one originating from a carbon bonded to a hydroxyl group (C-OH) at 285.7 eV, and the other centered at 284.3 eV, corresponding to a carbon atom with only CC bonds. Comparing the peak area ratios based on the fitting of the three peaks, no significant change was observed. This suggests that deep UV treatment did not have a significant effect on the chemical composition of GO within the thin film.

[0062] Referring to Figures 3 (c) and (d), for the O 1s peak, four Gaussian peaks were used for optimal fit. This includes a peak at 532.6 eV, which is not typically found in metal oxide spectra and is assigned to the C-OH groups of GO. On the other hand, the peak at 531.7 eV can be assigned to both the C=O groups and metal ion-bonded OH groups (M-OH) of GO. The peaks at 530.8 and 529.4 eV are not typically found in GO and, respectively, V OIt is assigned to and MOM. By comparing the spectra of the original state and deep UV-treated thin films, it was found that the relative C-OH peak remained almost unchanged, which is consistent with the results for the C 1s peak. The peaks of M-OH and C=O were similar in the original state and UV-treated thin films. However, in the case of the VO peak, a significant decrease was observed in the treated device, which is related to a significant increase in the relative area of ​​the MOM peak.

[0064] In the experiment of the present invention, FTIR measurements were performed as shown in Fig. 4 to investigate in more detail the chemical structural changes of the In2O3 / GO thin film due to deep ultraviolet exposure.

[0065] Figure 4 shows the FTIR spectra of the original state and deep ultraviolet pre-heat-treated In2O3 / GO TFT in the experiment of the present invention.

[0066] Referring to Fig. 4, the hydroxyl group (~3400 cm⁻¹) -1 ), carbonyl group (~1720 cm⁻¹) -1 ), C=C bond (~1620 cm -1 ), and C-OH stretching vibration (~1050 cm⁻¹) -1 The characteristic absorption band of ) was clearly observed in both spectra. In particular, the intensity and position of these peaks hardly changed even after deep UV irradiation, indicating that the chemical structure of GO was largely preserved. This result is consistent with the XPS analysis results, confirming that deep UV treatment did not significantly alter the oxygen-containing functional groups of GO.

[0067] V in amorphous metal oxide semiconductors O Although it is generally considered a major electron donor, it can act as a trap site at high concentrations. Therefore, V is necessary for the fabrication of high-performance metal oxide devices. OControl is important. Another significant factor in charge traps is M-OH groups, which are known to cause performance degradation in metal oxide semiconductors, but are not significantly affected by deep UV treatment.

[0069] FIG. 5 is a schematic diagram of the formation of an In2O3 / GO active layer in the experiment of the present invention, in the case of (a) heat treatment only on a pristine thin film and (b) heat treatment after deep ultraviolet pre-annealing treatment.

[0070] Referring to Fig. 5 (a), according to the XPS results, the GO dopant in the active layer is not affected by deep UV pretreatment, but promotes MOM bond formation while V O It reduces. In the original thin film, the formation of In2O3 by spin coating and the conversion of dried In(NO3)3 is induced during the hard baking step at high temperature, causing V O A thin film rich in [something] is formed.

[0071] Referring to Fig. 5 (b), using deep UV pretreatment allows high-energy UV irradiation to break the bonds of nitrate anions, thereby promoting the conversion process. Ozone generated from atmospheric oxygen during UV irradiation also influences the formation of metal oxides, V O It can reduce.

[0073] Figure 6 illustrates the output curve and transfer curve of a TFT device in an experiment of the present invention.

[0074] In FIG. 6, output curves of a TFT device having (a) a pristine state and (b) a UV-treated In2O3 / GO thin film are shown, and optical microscope images (inset) and transfer curves of a TFT device having (c) a pristine state and (d) a UV-treated In2O3 / GO thin film are shown.

[0075] In FIG. 6 (a) and (b), the drain-source voltage (V) at various fixed gate voltages (VDS) is shown. DSDrain-source current (I) according to ) DS By recording ), the output curves of the device with a pristine In2O3 / GO active layer and the device with a UV-treated active layer were obtained. Both devices had low amounts of V DS It shows a linear increase in IDS, and after reaching the pinch-off point, a higher V DS It exhibited typical n-type behavior saturating at. The saturation current levels of the two devices were similar. However, the device with the pristine In2O3 / GO layer showed a significant increase in back gate current, resulting in low V DS Negative leakage current was exhibited under bias. Here, deep UV treatment of the active layer was proven to be an efficient method for reducing back gate current.

[0076] I in Figs. 6 (c) and (d) DS is V DS V when fixed at 20V GS The device's transfer curve was generated by recording it as a function of . This curve shows a low current level at negative gate bias, a steep turn-on curve near 0V bias, and a threshold voltage of approximately 5V (V TH It exhibited typical n-type characteristics having ). In addition, the UV-treated device showed V compared to the original device. TH It was slightly lower. Both devices showed excellent performance, but dark spots appeared on the active layer due to strong UV treatment.

[0077] In the experiments of the present invention, to quantitatively understand the effect of deep ultraviolet treatment on the electronic performance of In2O3 / GO-based devices, the IV curves of all operating TFT channels were evaluated. Performance characteristics were calculated based on the transfer curves. Using the gradual channel assumption in the saturation region, the saturation mobility (μ) of charge carriers SAT ) and V TH It can be calculated as follows.

[0078] (1)

[0079] Here, L is the channel length of the SiO2 gate dielectric, W is the channel width of the SiO2 gate dielectric, and C i is the capacitance per unit area of ​​the SiO2 gate dielectric.

[0080] In the experiment of the present invention, to characterize the switching performance of the device between the on / off states, I in the on / off state DS The on-off current ratio of I On / I Off It was calculated as. To quantify the device switching characteristics near the off state, I from the transfer curve DS The subthreshold swing (SS) was calculated at the point where it begins to increase rapidly, and the calculation formula is as follows (2).

[0081] (2)

[0083] Figure 7 illustrates (a) saturation charge carrier mobility, (b) on / off current ratio, (c) threshold voltage, and (d) subthreshold swing (SS) distribution of a pristine TFT device and a TFT device having a deep UV-treated In2O3 / GO active layer in an experiment of the present invention.

[0084] In Fig. 7, summarized performance parameters for the TFT device measured in the experiment of the present invention can be seen.

[0085] Referring to Fig. 7, each substrate has nine channels arranged in a 3 × 3 array to generate reported values ​​and corresponding error bars. Average μ SAT is 0.3 cm 2 V -1 s -1 from 0.6 cm 2 V -1 s -1 It was found to have improved to (a). Average I On / I Off The value improved by about 2 times (b).

[0086] V of pristine In2O3 / GO-based devices TH was measured to be approximately 6.25 ± 0.75V, but for devices with a deep UV-treated active layer, V TH The value decreased to approximately 4.3 ± 0.31V, which indicates a significant improvement in average and inter-channel reproducibility (c).

[0087] Likewise, SS is approximately 1.7 to 1.1 Vdec -1 It decreased to and the variance around the mean improved (d). The SS value is mainly influenced by the trap site density of the semiconductor and semiconductor-dielectric interface, and V TH It generally moves in the positive direction due to electron capture. This suggests that deep UV pretreatment improves device performance by effectively removing trap sites in the active layer. Furthermore, it can be confirmed that there is a very close interdependence between changes in SS values ​​during the process flow and oxygen-related trap states. To quantify this relationship, the interfacial trap density (N it ) can be calculated using the following equation (3).

[0088] (3)

[0089] Here, T is temperature, K is the Boltzmann constant, and C i is the unit effective capacitance, and q represents the electronic charge.

[0090] Calculation results of N of Pristine In2O3 / GO TFT and UV-treated In2O3 / GO TFT it are 1.23 × 10⁻⁶ respectively 13 and 6.58 × 10 12 cm -2This indicates that the number of trap states is significantly reduced and the performance of the UV-treated In2O3 / GO TFT is improved compared to the pristine device. This improvement is likely the combined result of GO doping and deep UV pre-annealing treatment. Furthermore, SS is directly related to the trap site density in the channel layer. This suggests that GO particles embedded in the In2O3 thin film may act as additional trap sites within the film. Overall, despite a moderate balance in terms of mobility, the combined effect of GO doping and deep UV treatment contributes noticeably to the improved electrical stability of the TFT device.

[0092] Figure 8 illustrates the transfer characteristics of a TFT device before and after PBS and NBS in an experiment of the present invention.

[0093] In Fig. 8, the transfer curves of a TFT device having (a) a pristine state and (b) a deep UV-treated In2O3 / GO thin film before and during PBS (positive gate bias stability) are shown. Also, the transfer curves of a TFT device having (c) a pristine state and (d) a deep UV-treated In2O3 / GO thin film before and during NBS (negative gate bias stability) are shown.

[0094] To evaluate the practical applicability of TFTs in circuits, it is important to test performance stability under gate bias stress (GBS). Generally, under a constant gate bias, instability arises from the movement of mobile ions within the gate dielectric, charge carrier capture near the semiconductor-dielectric interface, or electron capture by adsorbed water and oxygen within the In2O3 channels, and all these factors V THThis results in a change. For devices with pristine and deep UV-treated In2O3 / GO active layers, positive Gate Bias Stability (PBS) measurements were performed by applying a 20V bias stress for a total of 1000 seconds after measuring the transfer curves. This process was interrupted intermittently to repeatedly measure the transfer characteristics. Changes in the transfer curves during the measurement are shown in Figures 8 (a) and 8 (b) for devices with pristine and deep UV-treated active layers, respectively. Here, both TFT devices showed positive changes during the PBS test.

[0095] The negative gate bias stability (NBS) test was performed using the same method, but the bias voltage was set to -20V.

[0096] Figures 8 (c) and 8 (d) show the changes in the transfer curves of the pristine and deep UV-treated devices during the experiment. The pristine In2O3 / GO TFT shifted significantly in the negative direction in the transfer curve, whereas the TFT with the deep UV-treated active layer showed almost no change under stress. Positive V during the PBS test TH Movement is V O This may be because electrons are captured, but in NBS, hole traps occur at the interface, improving channel conductivity and negative V TH It can lead to movement.

[0097] In Fig. 8, it can be seen that the offset of the UV-treated In2O3 / GO TFT in PBS / NBS is improved compared to the two pure devices. Additionally, M-OH groups at the dielectric / channel layer interface can act as charge trapping centers, which can lead to a decrease in the stability of PBS / NBS. As can be seen in Fig. 3, the number of M-OH groups decreases in the deep UV-treated device. This demonstrates that the trapping density of the device has decreased, which is consistent with the conclusion derived from Equation (3). For a more detailed comparison, the threshold voltage change (ΔV) of the two devices TH= V TH - V TH,initial ) was calculated and shown in Fig. 9.

[0098] Figure 9 shows the change in threshold voltage of an In2O3 / GO TFT as a function of bias stress time under (i) PBS and (ii) NBS in an experiment of the present invention.

[0099] Referring to Fig. 9, device characteristics related to trapping were improved through deep UV treatment, but positive bias stability was only slightly improved. This suggests that the movement of mobile ions under a constant positive bias in the In2O3 / GO TFT can also play an important role.

[0100] In the experiments of the present invention, the advantage obtained by introducing GO doping and deep UV pre-annealing pretreatment to the TFT device is that the stability of the device is improved under electrically biased stress and environmental exposure conditions. This suggests that these dual treatments alleviate electron trapping and contribute to a reduction in threshold voltage drift under bias stress.

[0102] Figure 10 is a graph showing the results of various electrical performance tests of a TFT device and a load-type inverter in an experiment of the present invention.

[0103] In Fig. 10, the voltage V between the drain and source DS This is a graph showing (a) switching and (b) on-and-off current stability of the In2O3 / GO active layer at =20 V, and V DD (c) Voltage transfer characteristics and gain, and (d) Dynamic response of a load-type inverter with a 1MΩ resistive load at =20 V are graphs.

[0104] Referring to FIG. 9, in the experiment of the present invention, switching, current, and off-current stability were measured to confirm the applicability of a TFT device having an In2O3 / GO active layer treated with deep UV in a digital circuit. V DS= V at 20V GS It switched between 0 and 20V in a square wave pattern with a cycle time of 0.2 seconds, and I DS It was recorded as a function of time. On and off state I DS was separated by more than 200 times over 400 seconds (a). The on-current stability is V DS = 20V and V GS = was measured consistently at 20V, and in the case of off-current stability, V GS = was set to 0V. The TFT device exhibited excellent current stability and on / off I DS It was separated into three sizes in order for 400 seconds (b).

[0105] Next, in the experiment of the present invention, a load-type inverter was fabricated by connecting a TFT device to a 1MΩ resistor as a model of In2O3 / GO active layer-based digital logic. The voltage transfer characteristic (VTC) curve is the input voltage (V In Output voltage (V) as a function of ) Out ) was measured and recorded. The VTC of the TFT device is the power supply voltage (V DD It varies depending on ), and V DD As increases, the gain increases (c). V DD = Vi at 20V n = V out The switching voltage is V M = 14.2V, and the high-noise margin and low-noise margin were NMH = 2.2V and NML = 4.5V, respectively.

[0106] Connect the input terminal to the square wave generator and V In The dynamic voltage response of the TFT device was tested by switching between -20V and 20V at 1Hz. When switching between the on and off states, V In and V OutThe time it takes to reach 50% of the voltage range between them is called propagation delay, and the time from low voltage to high voltage is t PLH = 12.7ms, from high voltage to low voltage is t PHL = It was 211ms. V Out The rise time, which is the delay time taken to rise from 10% to 90% of this voltage range, is τ r = was 23.0ms, and V Out The fall time, which is the delay time taken to drop from 90% to 10% of this voltage range, is τ. f = 225.2ms.

[0108] In the experiments of the present invention, the electrical performance of a TFT having a solution-processed In2O3 / GO active layer can be controlled through a simple deep UV pre-annealing treatment at room temperature, which does not cause chemical changes to the embedded GO flakes while affecting the V of the In2O3 thin film. O It can be confirmed that the number is significantly reduced. Changes in the chemical composition of the active layer reduced charge trapping and improved device performance characteristics and stability under negative bias stress. Furthermore, by measuring current stability under switching and on / off bias for deep UV-pretreated In2O3 / GO and fabricating a model logic circuit with a resistive load, it was demonstrated that it can be used as an feasible active layer in digital circuits. In fabricating high-performance digital circuit devices through the present invention, to optimize the GO-containing metal oxide layer, deep UV treatment does not affect the graphene oxide, while the V of the oxide thin film O It shows that it can be used as a method to control numbers.

[0109] Although the present invention has been described above using several preferred embodiments, these embodiments are illustrative and not limiting. Those skilled in the art will understand that various changes and modifications can be made without departing from the spirit of the invention and the scope of rights set forth in the appended claims. Explanation of the symbols

[0111] 110 Substrate 120 Insulating layer 130 Active layer 142 Source electrode 144 Drain Electrode 200 Deep UV Irradiator

Claims

Claim 1 A substrate including the function of a lower gate electrode; an insulating layer formed on the substrate; an active layer formed on the insulating layer as a solution-process-based amorphous oxide thin film; and a top electrode formed on the active layer including a source electrode and a drain electrode, wherein the active layer is formed by performing a deep UV pretreatment process by irradiating with deep UV, and the active layer is formed as a thin film doped with graphene oxide on indium oxide (In2O3), and when the C 1s X-ray photoelectron spectroscopy (XPS) spectrum of the active layer is peak-separated using a Gaussian function, the C 1s XPS spectrum includes a C=O peak centered at a binding energy of 288.2 eV, a C-OH peak centered at a binding energy of 285.7 eV, and a CC peak centered at a binding energy of 284.3 eV, and the relative peak areas of the C=O peak, the C-OH peak, and the CC peak are respectively The values ​​are 10.8%, 7.9%, and 81.3%, and when the O 1s XPS spectrum of the active layer is peak-separated using a Gaussian function, the O 1s XPS spectrum includes a peak centered at a binding energy of 532.6 eV corresponding to the C-OH group of the graphene oxide, a peak centered at a binding energy of 531.7 eV corresponding to the C=O group and metal ion-bonded OH group of the graphene oxide, a peak centered at a binding energy of 530.8 eV corresponding to oxygen vacancies, and a peak centered at a binding energy of 529.4 eV corresponding to metal-oxygen-metal bonds (MOM), and the relative peak areas of the peaks centered at binding energies of 532.6 eV, 531.7 eV, 530.8 eV, and 529.4 eV are 7.5%, 29.0%, 22.7%, and 40%, respectively.A thin-film transistor characterized by being manufactured by performing a heat treatment process in which, before the pretreatment process is performed and the upper electrode is formed, the above M is indium (In), the insulating layer is formed by growing SiO2 as a gate dielectric on the substrate, the upper electrode is formed by depositing aluminum, the active layer is formed by performing a deep ultraviolet pretreatment process in which deep ultraviolet rays having a ratio of 10% of a 185nm wavelength and 90% of a 254nm wavelength are irradiated for 20 seconds, and before the upper electrode is formed, the entire structure is soft-baked at 80°C for 5 minutes and hard-baked at 250°C for 2 hours. Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete

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