Semiconductor device

Abstract

The purpose is to provide a semiconductor device capable of improving device performance and reliability. A semiconductor device comprises a first active pattern including a first lower pattern extended in a first direction and a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction, a plurality of first gate structures spaced apart in a first direction on the first lower pattern and including a first gate electrode and a first gate insulating film, wherein the first gate electrode adjacent in the first direction is spaced apart by a first distance, a second active pattern including a second lower pattern extended in a first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in a second direction, a plurality of second gate structures spaced apart in a first direction on the second lower pattern and including a second gate electrode and a second gate insulating film, wherein the second gate electrode adjacent in the first direction is spaced apart by a second distance greater than a first distance, a first source / drain recess defined between adjacent first gate structures, a second source / drain recess defined between adjacent second gate structures, a first source / drain pattern disposed within the first source / drain recess, and a second It includes a second source / drain pattern disposed within a source / drain recess, wherein the depth from the upper surface of the first lower pattern to the lowest part of the first source / drain pattern is smaller than the depth from the upper surface of the second lower pattern to the lowest part of the second source / drain pattern, and the first source / drain pattern and the second source / drain pattern contain impurities of the same conductivity type.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to an MBCFET TM This relates to a semiconductor device including a Multi-Bridge Channel Field Effect Transistor. Background Technology

[0002] As one of the scaling techniques to increase the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or silicon body) in the shape of a fin or nanowire is formed on a substrate and a gate is formed on the surface of the multi-channel active pattern.

[0003] Since these multi-gate transistors utilize a three-dimensional channel, they are easy to scale. In addition, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, the short channel effect (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a semiconductor device capable of improving device performance and reliability.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] One aspect of a semiconductor device of the present invention for solving the above problem comprises: a first active pattern including a first lower pattern extended in a first direction and a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction; a plurality of first gate structures spaced apart in a first direction on the first lower pattern and including a first gate electrode and a first gate insulating film, wherein the first gate electrode adjacent in the first direction is spaced apart by a first distance; a second active pattern including a second lower pattern extended in a first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in a second direction; a plurality of second gate structures spaced apart in a first direction on the second lower pattern and including a second gate electrode and a second gate insulating film, wherein the second gate electrode adjacent in the first direction is spaced apart by a second distance greater than the first distance; a first source / drain recess defined between adjacent first gate structures; a second source / drain recess defined between adjacent second gate structures; and within the first source / drain recess It includes a first source / drain pattern disposed therein and a second source / drain pattern disposed within a second source / drain recess, wherein the depth from the upper surface of the first lower pattern to the lowest part of the first source / drain pattern is smaller than the depth from the upper surface of the second lower pattern to the lowest part of the second source / drain pattern, and the first source / drain pattern and the second source / drain pattern contain impurities of the same conductivity type.

[0007] Another aspect of the semiconductor device of the present invention for solving the above problem comprises: a first active pattern including a first lower pattern extended in a first direction and a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction; a plurality of first gate structures spaced apart in a first direction on the first lower pattern and including a first gate electrode and a first gate insulating film, wherein the first gate electrode adjacent in the first direction is spaced apart by a first distance; a second active pattern including a second lower pattern extended in a first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in a second direction; a plurality of second gate structures spaced apart in a first direction on the second lower pattern and including a second gate electrode and a second gate insulating film, wherein the second gate electrode adjacent in the first direction is spaced apart by a second distance greater than the first distance; a first source / drain recess defined between adjacent first gate structures; a second source / drain recess defined between adjacent second gate structures; and a first disposed within the first source / drain recess. It includes a source / drain pattern and a second source / drain pattern disposed within a second source / drain recess, wherein the height from the upper surface of the first lower pattern to the lowest part of the upper surface of the first source / drain pattern is greater than the height from the upper surface of the second lower pattern to the lowest part of the upper surface of the second source / drain pattern, and the first source / drain pattern and the second source / drain pattern each include n-type impurities.

[0008] Another aspect of the semiconductor device of the present invention for solving the above problem comprises: a first active pattern including a first lower pattern extended in a first direction and a plurality of first sheet patterns spaced apart from the first lower pattern in a second direction; a plurality of first gate structures spaced apart in a first direction on the first lower pattern and including a first gate electrode and a first gate insulating film, wherein the first gate electrode adjacent in the first direction is spaced apart by a first distance; a second active pattern including a second lower pattern extended in a first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in a second direction; a plurality of second gate structures spaced apart in a first direction on the second lower pattern and including a second gate electrode and a second gate insulating film, wherein the second gate electrode adjacent in the first direction is spaced apart by a second distance greater than the first distance; a first source / drain recess defined between adjacent first gate structures; a second source / drain recess defined between adjacent second gate structures; and a first disposed within the first source / drain recess. It includes a source / drain pattern and a second source / drain pattern disposed within a second source / drain recess, wherein the height from the lowest part of the upper surface of the first source / drain pattern to the highest part of the upper surface of the first source / drain pattern is a first height, and the height from the lowest part of the upper surface of the second source / drain pattern to the highest part of the upper surface of the second source / drain pattern is a second height greater than the first height.

[0009] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0010] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. Figure 2 is a cross-sectional view taken along A-A of Figure 1. Figure 3 is a cross-sectional view taken along B-B of Figure 1. Figure 4 is a cross-sectional view taken along C-C of Figure 1. FIGS. 5 and 6 are drawings for illustrating a semiconductor device according to some embodiments. FIG. 7 is a drawing for explaining a semiconductor device according to some embodiments. FIG. 8 is a drawing for illustrating a semiconductor device according to some embodiments. FIGS. 9 to 12 are drawings for illustrating semiconductor devices according to several embodiments. FIG. 13 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. Figure 14 is a cross-sectional view taken along D-D of Figure 13. Figure 15 is a cross-sectional view taken along E-E of Figure 13. FIG. 16 is a drawing for illustrating a semiconductor device according to some embodiments. Specific details for implementing the invention

[0011] A semiconductor device according to some embodiments may include a tunneling FET, a three-dimensional (3D) transistor, or a transistor based on a two-dimensional material (2D material based FETs) and a heterostructure thereof. Additionally, a semiconductor device according to some embodiments may include a bipolar junction transistor, a horizontal dual diffusion transistor (LDMOS), etc.

[0012] With reference to FIGS. 1 to 4, a semiconductor device according to some embodiments will be described.

[0013] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 2 is a cross-sectional view taken along A-A of FIG. 1. FIG. 3 is a cross-sectional view taken along B-B of FIG. 1. FIG. 4 is a cross-sectional view taken along C-C of FIG. 1.

[0014] For reference, although not illustrated, a cross-sectional view cut along the second gate electrode (220) in FIG. 1 in the second direction (D2) may be similar to FIG. 4.

[0015] Referring to FIGS. 1 to 4, a semiconductor device according to some embodiments may include a first active pattern (AP1), a plurality of first gate electrodes (120), a first source / drain pattern (150), a second active pattern (AP2), a plurality of second gate electrodes (220), and a second source / drain pattern (250).

[0016] The substrate (100) may include a first region (I) and a second region (II). In one example, the first region (I) and the second region (II) may be adjacent regions to each other. For example, one of the second gate electrodes (220) of the second region (II) may be the first gate electrode (120) of the first region (I). In another example, the first region (I) and the second region (II) may be separated regions from each other.

[0017] The substrate (100) may include a first region (I) and a second region (II). The first region (I) and the second region (II) may each be one of a logic region, an SRAM region, and an I / O region. For example, the first region (I) and the second region (II) may be regions that perform the same function. For another example, the first region (I) and the second region (II) may be regions that perform different functions.

[0018] The first region (I) and the second region (II) may be regions where transistors of the same conductivity type are formed. For example, the first region (I) and the second region (II) may be regions where NMOS are formed.

[0019] The substrate (100) may be bulk silicon or SOI (silicon-on-insulator). Alternatively, the substrate (100) may be a silicon substrate or may include other materials, such as silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but is not limited thereto.

[0020] A first active pattern (AP1), a plurality of first gate electrodes (120), and a first source / drain pattern (150) are disposed in a first region (I) of the substrate (100). A second active pattern (AP2), a plurality of second gate electrodes (220), and a second source / drain pattern (250) are disposed in a second region (II) of the substrate (100).

[0021] The first active pattern (AP1) and the second active pattern (AP2) can each be disposed on the substrate (100). The first active pattern (AP1) and the second active pattern (AP2) can each be extended in a first direction (D1).

[0022] Unlike what is depicted, one of the first active pattern (AP1) and the second active pattern (AP2) may extend in the first direction (D1), and the other may extend in the second direction (D2). In the following description, the first active pattern (AP1) and the second active pattern (AP2) are described as extending in the first direction (D1).

[0023] The first active pattern (AP1) and the second active pattern (AP2) may each be a multichannel active pattern. The first active pattern (AP1) may include a first sub-pattern (BP1) and a plurality of first sheet patterns (NS1). The second active pattern (AP2) may include a second sub-pattern (BP2) and a plurality of second sheet patterns (NS2).

[0024] The first lower pattern (BP1) may protrude from the substrate (100). The first lower pattern (BP1) may be extended in a first direction (D1). The second lower pattern (BP2) may protrude from the substrate (100). The second lower pattern (BP2) may be extended in a first direction (D1).

[0025] A plurality of first sheet patterns (NS1) may be placed on the upper surface (BP1_US) of the first lower pattern. A plurality of first sheet patterns (NS1) may be spaced apart from the first lower pattern (BP1) in a third direction (D3). Each first sheet pattern (NS1) may be spaced apart in the third direction (D3).

[0026] A plurality of second sheet patterns (NS2) may be placed on the upper surface (BP2_US) of the second lower pattern. A plurality of second sheet patterns (NS2) may be spaced apart from the second lower pattern (BP2) in a third direction (D3). Each second sheet pattern (NS2) may be spaced apart in the third direction (D3).

[0027] Each first sheet pattern (NS1) may include an upper surface (NS1_US) and a lower surface (NS1_BS). The upper surface (NS1_US) of the first sheet pattern is a surface opposite to the lower surface (NS1_BS) of the first sheet pattern in the third direction (D3).

[0028] Each second sheet pattern (NS2) may include an upper surface (NS2_US) and a lower surface (NS2_BS). The upper surface (NS2_US) of the second sheet pattern is a surface opposite to the lower surface (NS2_BS) of the second sheet pattern in a third direction (D3). The third direction (D3) may be a direction that intersects the first direction (D1) and the second direction (D2). For example, the third direction (D3) may be the thickness direction of the substrate (100). The first direction (D1) may be a direction that intersects the second direction (D2).

[0029] Although the first sheet pattern (NS1) and the second sheet pattern (NS2) are each depicted as being arranged in three places in the third direction (D3), this is for convenience of explanation only and is not limited thereto.

[0030] The first lower pattern (BP1) and the second lower pattern (BP2) may each be formed by etching a portion of the substrate (100) and may include an epitaxial layer grown from the substrate (100). The first lower pattern (BP1) and the second lower pattern (BP2) may each include silicon or germanium, which are elemental semiconductor materials. Additionally, the first lower pattern (BP1) and the second lower pattern (BP2) may each include a compound semiconductor, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0031] Group IV-IV compound semiconductors may be, for example, binary compounds, ternary compounds containing at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds doped with a Group IV element.

[0032] A III-V compound semiconductor may be, for example, one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of the group III elements aluminum (Al), gallium (Ga), and indium (In) with one of the group V elements phosphorus (P), arsenic (As), and antimonium (Sb).

[0033] The first sheet pattern (NS1) and the second sheet pattern (NS2) may each include one of an elemental semiconductor material such as silicon or germanium, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. Each first sheet pattern (NS1) may include the same material as the first sub-pattern (BP1) or may include a different material from the first sub-pattern (BP1). Each second sheet pattern (NS2) may include the same material as the second sub-pattern (BP2) or may include a different material from the second sub-pattern (BP2).

[0034] In a semiconductor device according to some embodiments, the first lower pattern (BP1) and the second lower pattern (BP2) may each be a silicon lower pattern containing silicon, and the first sheet pattern (NS1) and the second sheet pattern (NS2) may each be a silicon sheet pattern containing silicon.

[0035] The width of the first sheet pattern (NS1) in the second direction (D2) may increase or decrease in proportion to the width of the upper surface (BP1_US) of the first lower pattern in the second direction (D2). The width of the second sheet pattern (NS2) in the second direction (D2) may increase or decrease in proportion to the width of the upper surface (BP2_US) of the second lower pattern in the second direction (D2).

[0036] Although it has been illustrated that the width of the first sheet pattern (NS1) stacked in the third direction (D3) in the second direction (D2) is the same, this is merely for convenience of explanation and is not limited thereto. Unlike what is illustrated, the width of the first sheet pattern (NS1) stacked in the third direction (D3) in the second direction (D2) may decrease as it moves away from the first lower pattern (BP1). Of course, the above description can also be applied to the second active pattern (AP2).

[0037] In FIG. 1, the width of the first active pattern (AP1) in the second direction (D2) is shown as being the same as the width of the second active pattern (AP2) in the second direction (D2), but is not limited thereto. For reference, the width of the first active pattern (AP1) in the second direction (D2) may be the width of the upper surface (BP1_US) of the first lower pattern in the second direction (D2).

[0038] A field insulating film (105) may be formed on a substrate (100). The field insulating film (105) may be disposed on the sidewall of a first lower pattern (BP1). The field insulating film (105) is not disposed on the upper surface (BP1_US) of the first lower pattern.

[0039] For example, the field insulating film (105) may cover the entire sidewall of the first lower pattern (BP1). Unlike what is illustrated, the field insulating film (105) may cover only a portion of the sidewall of the first lower pattern (BP1). In this case, a portion of the first lower pattern (BP1) may protrude in a third direction (D3) above the upper surface of the field insulating film (105).

[0040] Each first sheet pattern (NS1) is positioned higher than the upper surface of the field insulating film (105). The above description may also be applied to the relationship between the field insulating film (105) and the second lower pattern (BP2).

[0041] The field insulating film (105) may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. Although the field insulating film (105) is depicted as a single film, this is for convenience of explanation only and is not limited thereto.

[0042] A plurality of first gate structures (GS1) may be disposed on a substrate (100). Each first gate structure (GS1) may extend in a second direction (D2). The first gate structures (GS1) may be disposed spaced apart in a first direction (D1). The first gate structures (GS1) may be adjacent to each other in a first direction (D1). For example, the first gate structures (GS1) may be disposed on both sides of the first source / drain pattern (150) in a first direction (D1).

[0043] A first gate structure (GS1) can be placed on a first active pattern (AP1). The first gate structure (GS1) can intersect with the first active pattern (AP1). The first gate structure (GS1) can intersect with a first lower pattern (BP1). The first gate structure (GS1) can wrap around each first sheet pattern (NS1).

[0044] The first gate structure (GS1) may include, for example, a first gate electrode (120), a first gate insulating film (130), a first gate spacer (140), and a first gate capping pattern (145).

[0045] The first gate structure (GS1) may include a plurality of inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1) disposed between the first sheet pattern (NS1) adjacent in the third direction (D3) and between the first lower pattern (BP1) and the first sheet pattern (NS1). The inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1) may be disposed between the upper surface (BP1_US) of the first lower pattern and the lower surface (NS1_BS) of the first lowest sheet pattern, and between the upper surface (NS1_US) of the first sheet pattern facing in the third direction (D3) and the lower surface (NS1_BS) of the first sheet pattern.

[0046] The number of inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1) may be proportional to the number of first sheet patterns (NS1) included in the active pattern (AP1). For example, the number of inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1) may be equal to the number of first sheet patterns (NS1). Since the first active pattern (AP1) includes a plurality of first sheet patterns (NS1), the first gate structure (GS1) may include a plurality of inner gate structures.

[0047] The inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) contacts the upper surface (BP1_US) of the first lower pattern, the upper surface (NS1_US) of the first sheet pattern, and the lower surface (NS1_BS) of the first sheet pattern.

[0048] The inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1) can come into contact with the first source / drain pattern (150) to be described later. For example, the inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1) can come into direct contact with the first source / drain pattern (150).

[0049] The following explanation is based on the case where the number of inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1) is 3.

[0050] The first gate structure (GS1) may include a first inner gate structure (INT1_GS1), a second inner gate structure (INT2_GS1), and a third inner gate structure (INT3_GS1). The first inner gate structure (INT1_GS1), the second inner gate structure (INT2_GS1), and the third inner gate structure (INT3_GS1) may be sequentially arranged on the first lower pattern (BP1).

[0051] The third inner gate structure (INT3_GS1) may be placed between the first lower pattern (BP1) and the first sheet pattern (NS1). The third inner gate structure (INT3_GS1) may be placed at the bottom of the inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1). The third inner gate structure (INT3_GS1) may be the bottom inner gate structure. The third inner gate structure (INT3_GS1) may be in contact with the upper surface (BP1_US) of the first lower pattern.

[0052] The first inner gate structure (INT1_GS1) and the second inner gate structure (INT2_GS1) may be placed between the first sheet pattern (NS1) adjacent in the third direction (D3). The first inner gate structure (INT1_GS1) may be placed at the top of the inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1). The first inner gate structure (INT1_GS1) may be the top inner gate structure. The first inner gate structure (INT1_GS1) may be in contact with the lower surface (NS1_BS) of the first sheet pattern placed at the top. The second inner gate structure (INT2_GS1) is placed between the first inner gate structure (INT1_GS1) and the third inner gate structure (INT3_GS1).

[0053] The inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) includes a first gate electrode (120) and a first gate insulating film (130) disposed between adjacent first sheet patterns (NS1) and between the first lower pattern (BP1) and the first sheet pattern (NS1).

[0054] For example, the width (W11) of the first inner gate structure (INT1_GS1) in the first direction (D1) may be the same as the width (W12) of the second inner gate structure (INT2_GS1) in the first direction (D1). In a semiconductor device according to some embodiments, the width (W13) of the third inner gate structure (INT3_GS1) in the first direction (D1) may be the same as the width (W12) of the second inner gate structure (INT2_GS1) in the first direction (D1).

[0055] For example, in the case of the second inner gate structure (INT2_GS1), the width (W12) of the second inner gate structure (INT2_GS1) can be measured at the midpoint between the upper surface (NS1_US) and the lower surface (NS1_BS) of the first sheet pattern facing in the third direction (D3).

[0056] A plurality of second gate structures (GS2) may be disposed on the substrate (100). Each second gate structure (GS2) may extend in a second direction (D2). The second gate structures (GS2) may be disposed spaced apart in a first direction (D1). The second gate structures (GS2) may be adjacent to each other in the first direction (D1). For example, the second gate structures (GS2) may be disposed on both sides of the second source / drain pattern (250) in the first direction (D1).

[0057] The second gate structure (GS2) may be placed on the second active pattern (AP2). The second gate structure (GS2) may intersect with the second active pattern (AP2). The second gate structure (GS2) may intersect with the second lower pattern (BP2). Although not illustrated, the second gate structure (GS2) may wrap around each second sheet pattern (NS2).

[0058] The second gate structure (GS2) may include, for example, a second gate electrode (220), a second gate insulating film (230), a second gate spacer (240), and a second gate capping pattern (245).

[0059] The second gate structure (GS2) may include a plurality of inner gate structures (INT1_GS2, INT2_GS2, INT3_GS2) disposed between the second sheet pattern (NS2) adjacent in the third direction (D3) and between the second lower pattern (BP2) and the second sheet pattern (NS2). The inner gate structures (INT1_GS2, INT2_GS2, INT3_GS2) are in contact with the upper surface (BP2_US) of the second lower pattern, the upper surface (NS2_US) of the second sheet pattern, and the lower surface (NS2_BS) of the second sheet pattern. The inner gate structures (INT1_GS2, INT2_GS2, INT3_GS2) may be in contact with the second source / drain pattern (250) to be described later.

[0060] The second gate structure (GS2) may include a fourth inner gate structure (INT1_GS2), a fifth inner gate structure (INT2_GS2), and a sixth inner gate structure (INT3_GS2). The sixth inner gate structure (INT3_GS2) may be placed between the second lower pattern (BP2) and the second sheet pattern (NS2). The sixth inner gate structure (INT3_GS2) may be the lowest inner gate structure. The fourth inner gate structure (INT1_GS2) may be placed at the top of the inner gate structures (INT1_GS2, INT2_GS2, INT3_GS2). The fourth inner gate structure (INT1_GS2) may be the top inner gate structure. The fifth inner gate structure (INT2_GS2) is placed between the fourth inner gate structure (INT1_GS2) and the sixth inner gate structure (INT3_GS2).

[0061] The inner gate structure (INT1_GS2, INT2_GS2, INT3_GS2) includes a second gate electrode (220) and a second gate insulating film (230) disposed between adjacent second sheet patterns (NS2) and between the second lower pattern (BP2) and the second sheet pattern (NS2).

[0062] For example, the width (W21) of the fourth inner gate structure (INT1_GS2) in the first direction (D1) may be the same as the width (W22) of the fifth inner gate structure (INT2_GS2) in the first direction (D1). The width (W23) of the sixth inner gate structure (INT3_GS2) in the first direction (D1) may be the same as the width (W22) of the fifth inner gate structure (INT2_GS2) in the first direction (D1).

[0063] When the first active pattern (AP1) and the second active pattern (AP2) are extended in different directions, the direction in which the second gate structure (GS2) is extended is different from the direction in which the first gate structure (GS1) is extended.

[0064] The first gate electrode (120) may be placed on the first lower pattern (BP1). The first gate electrode (120) may intersect with the first lower pattern (BP1). The first gate electrode (120) may wrap around the first sheet pattern (NS1). A portion of the first gate electrode (120) may be placed between adjacent first sheet patterns (NS1) and between the first lower pattern (BP1) and the first sheet pattern (NS1).

[0065] The second gate electrode (220) may be placed on the second lower pattern (BP2). The second gate electrode (220) may intersect with the second lower pattern (BP2). A portion of the second gate electrode (220) may be placed between adjacent second sheet patterns (NS2) and between the second lower pattern (BP2) and the second sheet pattern (NS2). Although not illustrated, the second gate electrode (220) may wrap around the second sheet pattern (NS2).

[0066] A first gate electrode (120) adjacent in a first direction (D1) may be spaced apart by a first distance (L1). A second gate electrode (220) adjacent in a first direction (D1) may be spaced apart by a second distance (L2). The distance (L2) at which the second gate electrode (220) is spaced apart is greater than the distance (L1) at which the first gate electrode (120) is spaced apart.

[0067] For example, in two first gate electrodes (120) positioned with the first source / drain pattern (150) in between, the distance (L1) between the first gate electrodes (120) in the first direction (D1) may be the distance between the side walls of the first gate electrodes (120) facing each other in the first direction (D1) with the first source / drain pattern (150) in between.

[0068] The first gate electrode (120) and the second gate electrode (220) may each include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrode (120) is, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum It may include at least one of nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but is not limited thereto. Conductive metal oxides and conductive metal oxynitrides may include oxidized forms of the materials described above, but are not limited thereto.

[0069] The first gate electrode (120) may be placed on both sides of the first source / drain pattern (150), which will be described later. The first gate structure (GS1) may be placed on both sides in the first direction (D1) of the first source / drain pattern (150).

[0070] For example, the first gate electrode (120) placed on both sides of the first source / drain pattern (150) may both be normal gate electrodes used as gates of the transistor. For another example, the first gate electrode (120) placed on one side of the first source / drain pattern (150) may be used as a gate of the transistor, while the first gate electrode (120) placed on the other side of the first source / drain pattern (150) may be a dummy gate electrode.

[0071] The second gate electrode (220) may be placed on both sides of the second source / drain pattern (250), which will be described later. The second gate structure (GS2) may be placed on both sides in the first direction (D1) of the second source / drain pattern (250).

[0072] For example, the second gate electrode (220) placed on both sides of the second source / drain pattern (250) may both be normal gate electrodes used as gates of the transistor. For another example, the second gate electrode (220) placed on one side of the second source / drain pattern (250) may be used as a gate of the transistor, while the second gate electrode (220) placed on the other side of the second source / drain pattern (250) may be a dummy gate electrode.

[0073] The first gate insulating film (130) may extend along the upper surface of the field insulating film (105) and the upper surface (BP1_US) of the first lower pattern. The first gate insulating film (130) may wrap around a plurality of first sheet patterns (NS1). The first gate insulating film (130) may be arranged along the perimeter of the first sheet pattern (NS1). The first gate electrode (120) is placed on the first gate insulating film (130). The first gate insulating film (130) is placed between the first gate electrode (120) and the first sheet pattern (NS1).

[0074] A portion of the first gate insulating film (130) may be positioned between the first sheet pattern (NS1) adjacent in the third direction (D3) and between the first lower pattern (BP1) and the first sheet pattern (NS1). When the first sheet pattern (NS1) includes the lower sheet pattern and the upper sheet pattern adjacent in the third direction (D3), a portion of the first gate insulating film (130) may extend along the upper surface (NS1_US) of the lower sheet pattern and the lower surface (NS1_BS) of the upper sheet pattern facing each other.

[0075] The first gate insulating film (130) may include a first gate interface insulating film (131) and a first gate high dielectric constant insulating film (132). The first gate high dielectric constant insulating film (132) may be disposed between the first gate interface insulating film (131) and the first gate electrode (120).

[0076] The first gate interface insulating film (131) may extend along the upper surface (BP1_US) of the first lower pattern. The first gate interface insulating film (131) may extend along the first source / drain pattern (150). The first gate interface insulating film (131) may be placed along the perimeter of the first sheet pattern (NS1). The first gate interface insulating film (131) may be in direct contact with the first lower pattern (BP1), the first source / drain pattern (150), and the first sheet pattern (NS1).

[0077] The first gate interface insulating film (131) may not extend along the upper surface of the field insulating film (105). The first gate interface insulating film (131) may not extend along the sidewall of the first gate spacer (140), which will be described later. However, depending on the method of forming the first gate interface insulating film (131), the first gate interface insulating film (131) may extend along the upper surface of the field insulating film (105) and the sidewall of the first gate spacer (140).

[0078] The first gate high dielectric constant insulating film (132) may extend along the upper surface of the field insulating film (105) and the upper surface (BP1_US) of the first lower pattern. The first gate high dielectric constant insulating film (132) may extend along the first source / drain pattern (150). The first gate high dielectric constant insulating film (132) may be placed along the perimeter of the first sheet pattern (NS1). The first gate high dielectric constant insulating film (132) may extend along the sidewall of the first gate spacer (140), which will be described later.

[0079] Since the description of the second gate insulating film (230) is similar to the description of the first gate insulating film (130), the second gate insulating film (230) is described briefly.

[0080] The second gate electrode (220) is placed on the second gate insulating film (230). The second gate insulating film (230) is placed between the second gate electrode (220) and the second sheet pattern (NS2).

[0081] The second gate insulating film (230) may include a second gate interface insulating film (231) and a second gate high dielectric constant insulating film (232). The second gate high dielectric constant insulating film (232) may be disposed between the second gate interface insulating film (231) and the second gate electrode (220).

[0082] The first gate interface insulating film (131) and the second gate interface insulating film (231) may comprise at least one of silicon oxide, silicon-germanium oxide, and germanium oxide. The first gate interface insulating film (131) and the second gate interface insulating film (231) may further comprise at least one of boron (B), phosphorus (P), carbon (C), arsenic (As), antimony (Sb), and bismuth (Bi), but are not limited thereto.

[0083] The first gate high dielectric constant insulating film (132) and the second gate high dielectric constant insulating film (232) may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0084] A semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor. In one example, the first gate high dielectric constant insulating film (132) and / or the second gate high dielectric constant insulating film (232) may include a ferroelectric material film having ferroelectric properties. In another example, the first gate high dielectric constant insulating film (132) and / or the second gate high dielectric constant insulating film (232) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0085] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0086] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0087] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0088] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0089] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0090] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0091] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0092] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0093] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0094] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0095] For example, the first gate high dielectric constant insulating film (132) and / or the second gate high dielectric constant insulating film (232) may include a single ferroelectric material film. For another example, the first gate high dielectric constant insulating film (132) and / or the second gate high dielectric constant insulating film (232) may include a plurality of ferroelectric material films spaced apart from each other. The first gate high dielectric constant insulating film (132) and / or the second gate high dielectric constant insulating film (232) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0096] The first gate spacer (140) may be disposed on the side wall of the first gate electrode (120). The first gate spacer (140) may not be disposed between the first lower pattern (BP1) and the first sheet pattern (NS1), and between the first sheet patterns (NS1) adjacent in the third direction (D3).

[0097] The second gate spacer (240) may be disposed on the sidewall of the second gate electrode (220). The second gate spacer (240) may not be disposed between the second lower pattern (BP2) and the second sheet pattern (NS2), and between the second sheet pattern (NS1) adjacent in the third direction (D3). In a semiconductor device according to some embodiments, the first gate spacer (140) and the second gate spacer (240) may include only the outer spacer.

[0098] The first gate spacer (140) and the second gate spacer (240) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonate (SiOC), and combinations thereof. Although the first gate spacer (140) and the second gate spacer (240) are each depicted as single films, this is for convenience of explanation only and is not limited thereto.

[0099] A first gate capping pattern (145) may be disposed on a first gate electrode (120) and a first gate spacer (140). A second gate capping pattern (245) may be disposed on a second gate electrode (220) and a second gate spacer (240). The upper surface of the first gate capping pattern (145) and the upper surface of the second gate capping pattern (245) may be placed in the same plane as the upper surface of the interlayer insulating film (190).

[0100] Unlike what is illustrated, the first gate capping pattern (145) may be placed between the first gate spacers (140), and the second gate capping pattern (245) may be placed between the second gate spacers (240).

[0101] The first gate capping pattern (145) and the second gate capping pattern (245) may each include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The first gate capping pattern (145) and the second gate capping pattern (245) may include a material having an etching selectivity ratio for the interlayer insulating film (190).

[0102] The first source / drain pattern (150) may be placed on the first active pattern (AP1). The first source / drain pattern (150) may be placed on the first lower pattern (BP1). The first source / drain pattern (150) is connected to the first sheet pattern (NS1). The first source / drain pattern (150) contacts the first sheet pattern (NS1).

[0103] The first source / drain pattern (150) may be placed on the side of the first gate structure (GS1). The first source / drain pattern (150) may be placed between the first gate structures (GS1) adjacent in the first direction (D1). For example, the first source / drain pattern (150) may be placed on both sides of the first gate structure (GS1). Unlike what is illustrated, the first source / drain pattern (150) may be placed on one side of the first gate structure (GS1) and not on the other side of the first gate structure (GS1).

[0104] The second source / drain pattern (250) may be placed on the second active pattern (AP2). The second source / drain pattern (250) may be placed on the second lower pattern (BP2). The second source / drain pattern (250) is connected to the second sheet pattern (NS2). The second source / drain pattern (250) is in contact with the second sheet pattern (NS2).

[0105] The second source / drain pattern (250) may be placed on the side of the second gate structure (GS2). The second source / drain pattern (250) may be placed between adjacent second gate structures (GS2) in the first direction (D1). For example, the second source / drain pattern (250) may be placed on both sides of the second gate structure (GS2). Unlike what is illustrated, the second source / drain pattern (250) may be placed on one side of the second gate structure (GS2) and not on the other side of the second gate structure (GS2).

[0106] The first source / drain pattern (150) and the second source / drain pattern (250) may be included in the source / drain of a transistor using the first sheet pattern (NS1) and the second sheet pattern (NS2) as channel regions.

[0107] A first source / drain pattern (150) may be placed within a first source / drain recess (150R). A second source / drain pattern (250) may be placed within a second source / drain recess (250R). The first source / drain recess (150R) and the second source / drain recess (250R) each extend in a third direction (D3). The first source / drain recess (150R) may be defined between adjacent first gate structures (GS1) in a first direction (D1). The second source / drain recess (250R) may be defined between adjacent second gate structures (GS2) in a second direction (D2). For example, the first source / drain recess (150R) and the second source / drain recess (250R) may be formed by the same manufacturing process, but are not limited thereto.

[0108] The bottom surface of the first source / drain recess (150R) can be defined by the first bottom pattern (BP1). The bottom surface of the second source / drain recess (250R) can be defined by the second bottom pattern (BP2).

[0109] In a semiconductor device according to some embodiments, the sidewall of the first source / drain recess (150R) may be defined by the first sheet pattern (NS1) and the inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1). The sidewall of the second source / drain recess (250R) may be defined by the second sheet pattern (NS2) and the inner gate structure (INT1_GS2, INT2_GS2, INT3_GS2). For example, the first gate structure (GS1) may include an upper surface facing the lower surface (NS1_BS) of the first sheet pattern. The inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) includes a lower surface facing the upper surface (NS1_US) of the first sheet pattern or the upper surface (BP1_US) of the first lower pattern. The inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) includes a side wall connecting the upper surface of the inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) and the lower surface of the inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1). The side wall of the inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) may define a part of the side wall of the first source / drain recess (150R).

[0110] The upper surface (BP1_US) of the first lower pattern may be the boundary between the third inter-gate structure (INT3_GS1) positioned at the bottom and the first lower pattern (BP1). The bottom surface of the first source / drain recess (150R) is lower than the upper surface (BP1_US) of the first lower pattern. Likewise, the bottom surface of the second source / drain recess (250R) is lower than the upper surface (BP2_US) of the second lower pattern.

[0111] The sidewalls of the first source / drain recess (150R) and the second source / drain recess (250R) may each have a wavy shape. The first source / drain recess (150R) may include a plurality of first width extension areas (150R_ER). Each first width extension area (150R_ER) may be defined above the upper surface (BP1_US) of the first lower pattern. The second source / drain recess (250R) may include a plurality of second width extension areas (250R_ER). Each second width extension area (250R_ER) may be defined above the upper surface (BP2_US) of the second lower pattern.

[0112] The first width extension region (150R_ER) may be defined between the first sheet pattern (NS1) adjacent in the third direction (D3). The first width extension region (150R_ER) may be defined between the first lower pattern (BP1) and the first sheet pattern (NS1). The first width extension region (150R_ER) may extend between the first sheet pattern (NS1) adjacent in the third direction (D3). The first width extension region (150R_ER) may be defined between the inner gate structures (INT_GS1, INT_GS2, INT_GS3) adjacent in the first direction (D1).

[0113] As one moves away from the upper surface (BP1_US) of the first lower pattern, each first width expansion area (150R_ER) may include a portion in which the width increases in the first direction (D1) and a portion in which the width decreases in the first direction (D1). For example, as one moves away from the upper surface (BP1_US) of the first lower pattern, the width of the first width expansion area (150R_ER) may increase and then decrease.

[0114] In each first width expansion area (150R_ER), the point where the width of the first width expansion area (150R_ER) is maximum is located between the first sheet pattern (NS1) and the first lower pattern (BP1) adjacent in the third direction (D3), and between the first sheet pattern (NS1) adjacent in the third direction (D3).

[0115] Since the description of the first width expansion area (150R_ER) described above can be applied to the second width expansion area (250R_ER), the description of the second width expansion area (250R_ER) is omitted.

[0116] The first source / drain pattern (150) contacts the first sheet pattern (NS1) and the first lower pattern (BP1). Since the first gate spacer (140) is not placed between adjacent first sheet patterns (NS1) and between the first sheet pattern (NS1) and the first lower pattern (BP1), the inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) can contact the first source / drain pattern (150). The first gate insulating film (130) of the inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) can contact the first source / drain pattern (150).

[0117] The second source / drain pattern (250) is in contact with the second sheet pattern (NS2) and the second lower pattern (BP2). The inner gate structure (INT1_GS2, INT2_GS2, INT3_GS2) may be in contact with the second source / drain pattern (250). The second gate insulating film (230) of the inner gate structure (INT1_GS2, INT2_GS2, INT3_GS2) may be in contact with the second source / drain pattern (250).

[0118] The first source / drain pattern (150) and the second source / drain pattern (250) may include an epitaxial pattern. The first source / drain pattern (150) and the second source / drain pattern (250) include a semiconductor material.

[0119] The first source / drain pattern (150) and the second source / drain pattern (250) may include, for example, silicon or germanium, which are elemental semiconductor materials. Additionally, the first source / drain pattern (150) and the second source / drain pattern (250) may include, for example, a binary compound, a ternary compound, or a compound doped with a group IV element, comprising at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn). For example, the first source / drain pattern (150) and the second source / drain pattern (250) may include silicon, silicon-germanium, silicon carbide, etc., but are not limited thereto.

[0120] The first source / drain pattern (150) and the second source / drain pattern (250) may include impurities doped into the semiconductor material. For example, the first source / drain pattern (150) and the second source / drain pattern (250) may include impurities of the same conductivity type, for example, n-type impurities. The doped impurities may include at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0121] The first source / drain pattern (150) and the second source / drain pattern (250) are depicted as a single film, but this is for convenience of explanation only and is not limited thereto. Since the first source / drain pattern (150) and the second source / drain pattern (250) are formed in the same manufacturing process, the first source / drain pattern (150) and the second source / drain pattern (250) may have the same semiconductor material film structure.

[0122] The following description is based on a cross-sectional view in which the first lower pattern (BP1) and the second lower pattern (BP2) are cut in the first direction (D1) in which they are extended.

[0123] For example, the upper surface (250US) of the second source / drain pattern may have a concave shape. In a semiconductor device according to some embodiments, the upper surface (150US) of the first source / drain pattern may have a convex shape.

[0124] When the first source / drain contact (180) is formed, the upper surface (150US) of the first source / drain pattern having a convex shape can be seen between the side wall of the first source / drain contact (180) and the side wall of the first gate structure (GS1). When the second source / drain contact (280) is formed, the upper surface (250US) of the second source / drain pattern having a concave shape can be seen between the side wall of the second source / drain contact (280) and the side wall of the second gate structure (GS2).

[0125] The depth (H11) from the upper surface (BP1_US) of the first lower pattern to the lowest part of the first source / drain pattern (150) is smaller than the depth (H21) from the upper surface (BP2_US) of the second lower pattern to the lowest part of the second source / drain pattern (250).

[0126] The height (H12) from the upper surface (BP1_US) of the first lower pattern to the lowest part of the upper surface (150US) of the first source / drain pattern is greater than the height (H22) from the upper surface (BP2_US) of the second lower pattern to the lowest part of the upper surface (250US) of the second source / drain pattern.

[0127] When the first source / drain contact (180) is formed, the lowest part of the upper surface (150US) of the first source / drain pattern may be the lowest position on the upper surface (150US) of the first source / drain pattern where the first source / drain contact (180) is not formed. When the second source / drain contact (280) is formed, the lowest part of the upper surface (250US) of the second source / drain pattern may be the lowest position on the upper surface (250US) of the second source / drain pattern where the second source / drain contact (280) is not formed.

[0128] The height from the lowest part of the upper surface (150US) of the first source / drain pattern to the highest part of the upper surface (150US) of the first source / drain pattern may be a first height (H13). The height from the lowest part of the upper surface (250US) of the second source / drain pattern to the highest part of the upper surface (250US) of the second source / drain pattern may be a second height (H23). For example, the second height (H23) on the upper surface (250US) of the second source / drain pattern is greater than the first height (H13) on the upper surface (150US) of the first source / drain pattern.

[0129] For example, the first source / drain pattern (150) may have a height (H11 + H12 + H13) of the first source / drain pattern (150) from the lowest part of the first source / drain pattern (150) to the highest part of the upper surface (150US) of the first source / drain pattern. The height (H11 + H12 + H13) of the first source / drain pattern (150) is smaller than the height (H21 + H22 + H23) of the second source / drain pattern (250).

[0130] The fourth inner gate structure (INT1_GS2) is the uppermost inner gate structure among the second gate structures (GS2). In a semiconductor device according to some embodiments, the height (H22) from the upper surface (BP2_US) of the second lower pattern to the lowest part of the upper surface (250US) of the second source / drain pattern may be smaller than the height (H24) from the upper surface (BP2_US) of the second lower pattern to the lower surface of the fourth inner gate structure (INT1_GS2).

[0131] Unlike what is described, the height (H22) from the upper surface (BP2_US) of the second lower pattern to the lowest part of the upper surface (250US) of the second source / drain pattern may be equal to or greater than the height (H24) from the upper surface (BP2_US) of the second lower pattern to the lower surface of the fourth inner gate structure (INT1_GS2).

[0132] The first inner gate structure (INT1_GS1) is the uppermost inner gate structure among the first gate structures (GS1). For example, the height (H12) from the upper surface (BP1_US) of the first lower pattern to the lowest part of the upper surface (150US) of the first source / drain pattern may be greater than the height from the upper surface (BP1_US) of the first lower pattern to the upper surface of the first inner gate structure (INT1_GS1).

[0133] The source / drain etch stop layer (185) may be disposed on the sidewall of the first gate structure (GS1) and on the upper surface (150US) of the first source / drain pattern. The source / drain etch stop layer (185) may be disposed on the sidewall of the second gate structure (GS2) and on the upper surface (250US) of the second source / drain pattern. Although not illustrated, the source / drain etch stop layer (185) may be disposed on the upper surface of the field insulating layer (105).

[0134] The source / drain etching stop layer (185) may comprise a material having an etching selectivity ratio with respect to the interlayer insulating layer (190) to be described later. The source / drain etching stop layer (185) may comprise, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0135] The interlayer insulating film (190) may be placed on the source / drain etch stop film (185). The interlayer insulating film (190) may be placed on the first source / drain pattern (150) and the second source / drain pattern (250). The interlayer insulating film (190) may not cover the upper surface of the first gate capping pattern (145) and the upper surface of the second gate capping pattern (245).

[0136] The interlayer insulating film (190) may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Low-k materials include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate) Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, It may include mesoporous silica or a combination thereof, but is not limited thereto.

[0137] A first source / drain contact (180) is disposed on a first source / drain pattern (150). The first source / drain contact (180) is connected to the first source / drain pattern (150). The first source / drain contact (180) can be connected to the first source / drain pattern (150) by passing through an interlayer insulating film (190) and a source / drain etch stop film (185).

[0138] The second source / drain contact (280) is placed on the second source / drain pattern (250). The second source / drain contact (280) is connected to the second source / drain pattern (250).

[0139] A first metal silicide film (155) may be further disposed between the first source / drain contact (180) and the first source / drain pattern (150). A second metal silicide film (255) may be further disposed between the second source / drain contact (280) and the second source / drain pattern (250).

[0140] Although the first source / drain contact (180) and the second source / drain contact (280) are each depicted as a single film, this is for convenience of explanation only and is not limited thereto. The first source / drain contact (180) and the second source / drain contact (280) may each include at least one of, for example, a metal, a metal alloy, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material.

[0141] The first metal silicide film (155) and the second metal silicide film (255) may include metal silicide.

[0142] FIGS. 5 and 6 are drawings for illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIGS. 1 to 4.

[0143] Referring to FIGS. 5 and 6, in a semiconductor device according to some embodiments, a first gate structure (GS1) further includes a plurality of first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1). A second gate structure (GS2) further includes a plurality of second inner spacers (ISP1_GS2, ISP2_GS2, ISP3_GS2).

[0144] A plurality of first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1) may be disposed between first sheet patterns (NS1) adjacent in the third direction (D3) and between the first lower pattern (BP1) and the first sheet pattern (NS1). The first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1) may be disposed between the upper surface (BP1_US) of the first lower pattern and the lower surface (NS1_BS) of the first lowest sheet pattern, and between the upper surface (NS1_US) of the first sheet pattern and the lower surface (NS1_BS) of the first sheet pattern facing in the third direction (D3).

[0145] A plurality of first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1) are in contact with the upper surface (BP1_US) of the first lower pattern, the upper surface (NS1_US) of the first sheet pattern, and the lower surface (NS1_BS) of the first sheet pattern. A plurality of first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1) are arranged between the inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) and the first source / drain pattern (150). The number of a plurality of first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1) arranged in the third direction (D3) is equal to the number of inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1).

[0146] The first gate spacer (140) may include a first sub-inner spacer (ISP1_GS1), a second sub-inner spacer (ISP2_GS1), and a third sub-inner spacer (ISP3_GS1). The first sub-inner spacer (ISP1_GS1), the second sub-inner spacer (ISP2_GS1), and the third sub-inner spacer (ISP3_GS1) may be sequentially arranged on the first lower pattern (BP1).

[0147] The third sub-inner spacer (ISP3_GS1) can be positioned between the first lower pattern (BP1) and the first sheet pattern (NS1). The third sub-inner spacer (ISP3_GS1) can be positioned at the lowest of the first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1). The third sub-inner spacer (ISP3_GS1) can contact the upper surface (BP1_US) of the first lower pattern.

[0148] The first sub-inner spacer (ISP1_GS1) and the second sub-inner spacer (ISP2_GS1) may be placed between the first sheet pattern (NS1) adjacent in the third direction (D3). The second sub-inner spacer (ISP2_GS1) is placed between the first sub-inner spacer (ISP1_GS1) and the third sub-inner spacer (ISP3_GS1).

[0149] The first gate interface insulating film (131) may not extend along the sidewalls of the first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1). The first gate high dielectric constant insulating film (132) extends along the sidewalls of the first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1). However, depending on the method of forming the first gate interface insulating film (131), the first gate interface insulating film (131) may extend along the sidewalls of the first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1).

[0150] Since the first inner spacer (ISP1_GS1, ISP2_GS1, ISP3_GS1) is placed, the inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) does not come into contact with the first source / drain pattern (150).

[0151] The sidewalls of the first source / drain recess (150R) may be defined by the first sheet pattern (NS1) and the first inner spacers (ISP1_GS1, ISP2_GS1, ISP3_GS1). The first source / drain recess (150R) may not include a width extension area (150R_ER in FIG. 2).

[0152] A plurality of second inner spacers (ISP1_GS2, ISP2_GS2, ISP3_GS2) may be disposed between adjacent second sheet patterns (NS2) in the third direction (D3) and between the second lower pattern (BP2) and the second sheet pattern (NS2). The plurality of second inner spacers (ISP1_GS2, ISP2_GS2, ISP3_GS2) contact the upper surface (BP2_US) of the second lower pattern, the upper surface (NS2_US) of the second sheet pattern, and the lower surface (NS2_BS) of the second sheet pattern.

[0153] A plurality of second inner spacers (ISP1_GS2, ISP2_GS2, ISP3_GS2) are disposed between the inner gate structure (INT1_GS2, INT2_GS2, INT3_GS2) and the first source / drain pattern (250). The second gate spacer (240) may include a fourth sub-inner spacer (ISP1_GS2), a fifth sub-inner spacer (ISP2_GS2), and a sixth sub-inner spacer (ISP3_GS2).

[0154] The sixth sub-inner spacer (ISP3_GS2) may be positioned between the second lower pattern (BP2) and the second sheet pattern (NS2). The sixth sub-inner spacer (ISP3_GS2) may be positioned at the lowest of the second inner spacers (ISP1_GS2, ISP2_GS2, ISP3_GS2). The fifth sub-inner spacer (ISP2_GS2) is positioned between the fourth sub-inner spacer (ISP1_GS2) and the sixth sub-inner spacer (ISP3_GS2).

[0155] The second gate interface insulating film (231) may not extend along the sidewall of the second inner spacer (ISP1_GS2, ISP2_GS2, ISP3_GS2). The second gate high dielectric constant insulating film (232) extends along the sidewall of the second inner spacer (ISP1_GS2, ISP2_GS2, ISP3_GS2). The inner gate structure (INT1_GS2, INT2_GS2, INT3_GS2) does not come into contact with the second source / drain pattern (250). The sidewall of the second source / drain recess (250R) may be defined by the second sheet pattern (NS2) and the second inner spacer (ISP1_GS2, ISP2_GS2, ISP3_GS2).

[0156] The first inner spacer (ISP1_GS1, ISP2_GS1, ISP3_GS1) and the second inner spacer (ISP1_GS2, ISP2_GS2, ISP3_GS2) may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron nitride (SiOBN), silicon carbonitride (SiOC), and combinations thereof.

[0157] In FIG. 5, the thickness (t11) of the first sub-inner spacer (ISP1_GS1) in the first direction (D1) may be the same as the thickness (t12) of the second sub-inner spacer (ISP2_GS1) in the first direction (D1). The thickness (t13) of the third sub-inner spacer (ISP3_GS1) in the first direction (D1) may be the same as the thickness (t12) of the second sub-inner spacer (ISP2_GS1) in the first direction (D1).

[0158] For example, the second sub-inner spacer (ISP2_GS1) can be measured in the middle between the upper surface (NS1_US) and the lower surface (NS1_BS) of the first sheet pattern facing in the third direction (D3), with the thickness (t12) of the second sub-inner spacer (ISP2_GS1) in the first direction (D1) being measured.

[0159] In FIG. 6, the thickness (t21) of the fourth sub-inner spacer (ISP1_GS2) in the first direction (D1) may be the same as the thickness (t22) of the fifth sub-inner spacer (ISP2_GS2) in the first direction (D1). The thickness (t23) of the sixth sub-inner spacer (ISP3_GS2) in the first direction (D1) may be the same as the thickness (t22) of the fifth sub-inner spacer (ISP2_GS2) in the first direction (D1).

[0160] FIG. 7 is a drawing illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 5 and 6.

[0161] Referring to FIG. 7, in a semiconductor device according to some embodiments, the thickness (t13) of the third sub-inner spacer (ISP3_GS1) in the first direction (D1) is greater than the thickness (t12) of the second sub-inner spacer (ISP2_GS1) in the first direction (D1).

[0162] The thickness (t11) of the first sub-inner spacer (ISP1_GS1) in the first direction (D1) may be smaller than the thickness (t12) of the second sub-inner spacer (ISP2_GS1) in the first direction (D1).

[0163] Unlike what is described, the thickness (t11) of the first sub-inner spacer (ISP1_GS1) in the first direction (D1) may be the same as the thickness (t12) of the second sub-inner spacer (ISP2_GS1) in the first direction (D1).

[0164] Even if the thickness of the first inner spacer (ISP1_GS1, ISP2_GS1, ISP3_GS1) varies depending on the distance from the first lower pattern (BP1), the thickness of the second inner spacer (ISP1_GS2, ISP2_GS2, ISP3_GS2) may be the same as described in FIG. 6.

[0165] FIG. 8 is a drawing illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 1 to 4.

[0166] Referring to FIG. 8, in a semiconductor device according to some embodiments, the width (W13) of the third inner gate structure (INT3_GS1) in the first direction (D1) may be larger than the width (W12) of the second inner gate structure (INT2_GS1) in the first direction (D1).

[0167] Among the inner gate structures (INT1_GS1, INT2_GS1, INT3_GS1) included in the first gate structure (GS1), the width (W13) of the third inner gate structure (INT3_GS1) may be the largest.

[0168] On the other hand, the width of the inner gate structure (INT1_GS2, INT2_GS2, INT3_GS2) included in the second gate structure (GS2) may be the same as described using FIG. 3.

[0169] FIGS. 9 to 12 are drawings illustrating semiconductor devices according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIGS. 1 to 4.

[0170] Referring to FIG. 9, in a semiconductor device according to some embodiments, the upper surface (150US) of the first source / drain pattern may be flat.

[0171] Meanwhile, the upper surface (250US) of the second source / drain pattern may have a concave shape.

[0172] Referring to FIG. 10, in a semiconductor device according to some embodiments, the upper surface (150US) of the first source / drain pattern and the upper surface (250US) of the second source / drain pattern may each have a concave shape.

[0173] Referring to FIG. 11, in a semiconductor device according to some embodiments, the first source / drain recess (150R) does not include a plurality of first width extension regions (150R_ER in FIG. 2).

[0174] The sidewall of the first source / drain recess (150R) does not have a wavy shape. The upper sidewall of the first source / drain recess (150R) may have a width in the first direction (D1) that decreases as it moves away from the first lower pattern (BP1).

[0175] Although not shown, the second source / drain recess (250R) does not include a plurality of second width extension regions (250R_ER in FIG. 3).

[0176] Referring to FIG. 12, in a semiconductor device according to some embodiments, an inner gate structure (INT1_GS1, INT2_GS1, INT3_GS1) may protrude in a first direction (D1) toward a first source / drain pattern (150) from at least one first sheet pattern (NS1).

[0177] For example, a portion of the first inner gate structure (INT1_GS1) and a portion of the second inner gate structure (INT_GS2) may protrude toward the first source / drain pattern (150) beyond the first sheet pattern (NS1) between the first inner gate structure (INT1_GS1) and the second inner gate structure (INT2_GS1).

[0178] A portion of the second inner gate structure (INT2_GS1) and a portion of the third inner gate structure (INT3_GS1) may protrude toward the first source / drain pattern (150) beyond the first sheet pattern (NS1) between the second inner gate structure (INT2_GS1) and the third inner gate structure (INT3_GS1).

[0179] Although not illustrated, the inner gate structure (INT1_GS2, INT2_GS2, INT3_GS2) may protrude in a first direction (D1) toward the second source / drain pattern (250) beyond at least one second sheet pattern (NS2).

[0180] FIG. 13 is an exemplary layout diagram for illustrating a semiconductor device according to some embodiments. FIG. 14 is a cross-sectional view taken along D-D of FIG. 13. FIG. 15 is a cross-sectional view taken along E-E of FIG. 13.

[0181] For reference, the cross-sectional view taken along A-A and B-B in FIG. 13 may be identical to one of FIG. 2, FIG. 3, FIG. 5 through FIG. 12. Additionally, the description of the first region (I) and the second region (II) in FIG. 13 may be substantially the same as the description using FIG. 1 through FIG. 12. Accordingly, the following description focuses on the content regarding the third region (III) and the fourth region (IV) in FIG. 13.

[0182] Referring to FIGS. 13 to 15, a semiconductor device according to some embodiments may include a first active pattern (AP1), a plurality of first gate electrodes (120), a first source / drain pattern (150), a second active pattern (AP2), a plurality of second gate electrodes (220), a second source / drain pattern (250), a third active pattern (AP3), a plurality of third gate electrodes (320), a third source / drain pattern (350), a fourth active pattern (AP4), a plurality of fourth gate electrodes (420), and a fourth source / drain pattern (450).

[0183] The substrate (100) may include a first region (I), a second region (II), a third region (III), and a fourth region (IV). The first region (I) and the second region (II) may be regions where NMOS is formed, and the third region (III) and the fourth region (IV) may be regions where PMOS is formed. For example, the third region (III) and the fourth region (IV) may be regions that perform the same function. For another example, the third region (III) and the fourth region (IV) may be regions that perform different functions.

[0184] The third active pattern (AP3) may include a third lower pattern (BP3) and a plurality of third sheet patterns (NS3). The fourth active pattern (AP4) may include a fourth lower pattern (BP4) and a plurality of fourth sheet patterns (NS4). The third lower pattern (BP3) may be extended in a first direction (D1). A plurality of third sheet patterns (NS3) may be placed on the third lower pattern (BP3). The fourth lower pattern (BP4) may be extended in a first direction (D1). A plurality of fourth sheet patterns (NS4) may be placed on the fourth lower pattern (BP4).

[0185] Each third sheet pattern (NS3) may include an upper surface (NS3_US) and a lower surface (NS3_BS). Each fourth sheet pattern (NS4) may include an upper surface (NS4_US) and a lower surface (NS4_BS).

[0186] The third sub-pattern (BP3) and the fourth sub-pattern (BP4) may each include one of an elemental semiconductor material, such as silicon or germanium, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. The third sheet pattern (NS3) and the fourth sheet pattern (NS4) may each include one of an elemental semiconductor material, such as silicon or germanium, a group IV-IV compound semiconductor, or a group III-V compound semiconductor.

[0187] A plurality of third gate structures (GS3) may be disposed on the substrate (100). Each third gate structure (GS3) may extend in a second direction (D2). The third gate structures (GS3) may be disposed spaced apart in a first direction (D1). A plurality of fourth gate structures (GS4) may be disposed on the substrate (100). Each fourth gate structure (GS4) may extend in a second direction (D2). The fourth gate structures (GS4) may be disposed spaced apart in a first direction (D1).

[0188] The third gate structure (GS3) may include a plurality of inner gate structures (INT1_GS3, INT2_GS3, INT3_GS3) disposed between the third sheet pattern (NS3) adjacent in the third direction (D3) and between the third lower pattern (BP3) and the third sheet pattern (NS3). The third gate structure (GS3) may include a seventh inner gate structure (INT1_GS3), an eighth inner gate structure (INT2_GS3), and a ninth inner gate structure (INT3_GS3). The inner gate structures (INT1_GS3, INT2_GS3, INT3_GS3) may come into contact with the third source / drain pattern (350), which will be described later.

[0189] The fourth gate structure (GS4) may include a plurality of inner gate structures (INT1_GS4, INT2_GS4, INT3_GS4) disposed between the fourth sheet pattern (NS4) adjacent in the third direction (D3) and between the fourth lower pattern (BP4) and the fourth sheet pattern (NS4). The fourth gate structure (GS4) may include a tenth inner gate structure (INT1_GS4), a eleventh inner gate structure (INT2_GS4), and a twelfth inner gate structure (INT3_GS4). The inner gate structures (INT1_GS4, INT2_GS4, INT3_GS4) may come into contact with the fourth source / drain pattern (450), which will be described later.

[0190] The third gate structure (GS3) may include, for example, a third gate electrode (320), a third gate insulating film (330), a third gate spacer (340), and a third gate capping pattern (345). The fourth gate structure (GS4) may include, for example, a fourth gate electrode (420), a fourth gate insulating film (430), a fourth gate spacer (440), and a fourth gate capping pattern (445).

[0191] A third gate electrode (320) may be placed on a third lower pattern (BP3). A fourth gate electrode (420) may be placed on a fourth lower pattern (BP4). A third gate electrode (320) adjacent in a first direction (D1) may be spaced apart by a third distance (L3). A fourth gate electrode (420) adjacent in a first direction (D1) may be spaced apart by a fourth distance (L4). The distance (L4) at which the fourth gate electrode (420) is spaced apart is greater than the distance (L3) at which the third gate electrode (320) is spaced apart.

[0192] The third gate insulating film (330) may include a third gate interface insulating film (331) and a third gate high dielectric constant insulating film (332). The fourth gate insulating film (430) may include a fourth gate interface insulating film (431) and a fourth gate high dielectric constant insulating film (432).

[0193] Other descriptions regarding the third gate electrode (320), the fourth gate electrode (420), the third gate insulating film (330), the fourth gate insulating film (430), the third gate spacer (340), the fourth gate spacer (440), the third gate capping pattern (345), and the fourth gate capping pattern (445) are substantially the same as the descriptions regarding the first gate electrode (120), the first gate insulating film (130), the first gate spacer (140), and the first gate capping pattern (145), so they are omitted below.

[0194] The third source / drain pattern (350) may be placed on the third active pattern (AP3). The third source / drain pattern (350) may be placed on the third lower pattern (BP3). The third source / drain pattern (350) is connected to the third sheet pattern (NS3).

[0195] The fourth source / drain pattern (450) may be placed on the fourth active pattern (AP4). The fourth source / drain pattern (450) may be placed on the fourth lower pattern (BP4). The fourth source / drain pattern (450) is connected to the fourth sheet pattern (NS3).

[0196] A third source / drain pattern (350) may be placed within a third source / drain recess (350R). A fourth source / drain pattern (450) may be placed within a fourth source / drain recess (450R). In semiconductor devices according to some embodiments, the third source / drain recess (350R) and the fourth source / drain recess (450R) may be formed by different manufacturing processes.

[0197] The bottom surface of the third source / drain recess (350R) can be defined by the third lower pattern (BP3). The bottom surface of the fourth source / drain recess (450R) can be defined by the fourth lower pattern (BP4). The sidewalls of the third source / drain recess (350R) are defined by the third sheet pattern (NS3) and the inner gate structure (INT1_GS3, INT2_GS3, INT3_GS3). The sidewalls of the fourth source / drain recess (450R) can be defined by the fourth sheet pattern (NS4) and the inner gate structure (INT1_GS4, INT2_GS4, INT3_GS4).

[0198] The third source / drain recess (350R) may include a plurality of third width extension regions (350R_ER). The fourth source / drain recess (450R) may include a plurality of fourth width extension regions (450R_ER). The description of the shape of the third source / drain recess (350R) and the fourth source / drain recess (450R) may be similar to that of the first source / drain recess (150R) and the second source / drain recess (250R).

[0199] Unlike what is shown, the sidewalls of the third source / drain recess (350R) and the fourth source / drain recess (450R) may have a shape similar to the first source / drain recess (150R) shown in FIGS. 11 and 12.

[0200] The third source / drain pattern (350) can be in contact with the third sheet pattern (NS3), the third lower pattern (BP3), and the inner gate structure (INT1_GS3, INT2_GS3, INT3_GS3). The fourth source / drain pattern (450) can be in contact with the fourth sheet pattern (NS4), the fourth lower pattern (BP4), and the inner gate structure (INT1_GS4, INT2_GS4, INT3_GS4).

[0201] The third source / drain pattern (350) may include a first semiconductor liner (351) and a first semiconductor filling film (352). The first semiconductor liner (351) may extend along the bottom surface and side wall of the third source / drain recess (350R). The first semiconductor filling film (352) is disposed on the first semiconductor liner (351).

[0202] The fourth source / drain pattern (450) may include a second semiconductor liner (451) and a second semiconductor filling film (452). The second semiconductor liner (451) may extend along the bottom surface and side wall of the fourth source / drain recess (450R). The second semiconductor filling film (452) is disposed on the second semiconductor liner (451).

[0203] For example, the thickness (t31) of the first semiconductor liner (351) at the bottom surface of the third source / drain recess (350R) may be equal to or greater than the thickness (t32) of the second semiconductor liner (451) at the bottom surface of the fourth source / drain recess (450R).

[0204] The first semiconductor liner (351), the first semiconductor filling film (352), the second semiconductor liner (451), and the second semiconductor filling film (452) may each contain silicon germanium. The fraction of germanium in the first semiconductor liner (351) is smaller than the fraction of germanium in the first semiconductor filling film (352). The fraction of germanium in the second semiconductor liner (451) is smaller than the fraction of germanium in the second semiconductor filling film (452).

[0205] The third source / drain pattern (350) and the fourth source / drain pattern (450) may include impurities doped into the semiconductor material. For example, the third source / drain pattern (350) and the fourth source / drain pattern (450) may include p-type impurities. The doped impurities may include boron (B), but are not limited thereto.

[0206] The upper surface (350US) of the third source / drain pattern and the upper surface (450US) of the fourth source / drain pattern are each depicted as having a convex shape, but are not limited thereto.

[0207] The depth (H31) from the upper surface (BP3_US) of the third lower pattern to the lowest part of the third source / drain pattern (350) may be the same as the depth (H41) from the upper surface (BP4_US) of the fourth lower pattern to the lowest part of the fourth source / drain pattern (450), but is not limited thereto. That is, the depth (H31) from the upper surface (BP3_US) of the third lower pattern to the lowest part of the third source / drain pattern (350) may be smaller or larger than the depth (H41) from the upper surface (BP4_US) of the fourth lower pattern to the lowest part of the fourth source / drain pattern (450).

[0208] The height (H32) from the upper surface (BP3_US) of the third lower pattern to the lowest part of the upper surface (350US) of the third source / drain pattern may be the same as the height (H42) from the upper surface (BP4_US) of the fourth lower pattern to the lowest part of the upper surface (450US) of the fourth source / drain pattern, but is not limited thereto.

[0209] The height (H33) from the lowest part of the upper surface (350US) of the third source / drain pattern to the highest part of the upper surface (350US) of the third source / drain pattern may be the same as the height (H43) from the lowest part of the upper surface (450US) of the fourth source / drain pattern to the highest part of the upper surface (450US) of the fourth source / drain pattern, but is not limited thereto.

[0210] The 10th inner gate structure (INT1_GS4) is the uppermost inner gate structure among the 4th gate structures (GS4). In a semiconductor device according to some embodiments, the height (H42) from the upper surface (BP4_US) of the 4th lower pattern to the lowest part of the upper surface (450US) of the 4th source / drain pattern may be greater than the height (H44) from the upper surface (BP4_US) of the 4th lower pattern to the lower surface of the 10th inner gate structure (INT1_GS4). For example, the height (H42) from the upper surface (BP4_US) of the 4th lower pattern to the lowest part of the upper surface (450US) of the 4th source / drain pattern may be greater than the height from the upper surface (BP4_US) of the 4th lower pattern to the upper surface of the 10th inner gate structure (INT1_GS4).

[0211] The seventh inner gate structure (INT1_GS3) is the uppermost inner gate structure among the third gate structures (GS3). For example, the height (H32) from the upper surface (BP3_US) of the third lower pattern to the lowest part of the upper surface (350US) of the third source / drain pattern may be greater than the height from the upper surface (BP3_US) of the third lower pattern to the upper surface of the seventh inner gate structure (INT1_GS3).

[0212] A third source / drain contact (380) is placed on a third source / drain pattern (350). The third source / drain contact (380) is connected to the third source / drain pattern (150).

[0213] The fourth source / drain contact (480) is placed on the fourth source / drain pattern (450). The fourth source / drain contact (480) is connected to the fourth source / drain pattern (450).

[0214] A third metal silicide film (355) may be further disposed between the third source / drain contact (380) and the third source / drain pattern (350). A fourth metal silicide film (455) may be further disposed between the fourth source / drain contact (480) and the fourth source / drain pattern (450).

[0215] FIG. 16 is a drawing illustrating a semiconductor device according to several embodiments. For convenience of explanation, the explanation will focus on the differences from the description using FIG. 13 to 15.

[0216] Referring to FIG. 16, in a semiconductor device according to some embodiments, the depth (H31) from the upper surface (BP3_US) of the third lower pattern to the lowest part of the third source / drain pattern (350) is smaller than the depth (H41) from the upper surface (BP4_US) of the fourth lower pattern to the lowest part of the fourth source / drain pattern (450).

[0217] The height (H32) from the upper surface (BP3_US) of the third lower pattern to the lowest part of the upper surface (350US) of the third source / drain pattern is greater than the height (H42) from the upper surface (BP4_US) of the fourth lower pattern to the lowest part of the upper surface (450US) of the fourth source / drain pattern.

[0218] The height (H33) from the lowest part of the upper surface (350US) of the third source / drain pattern to the highest part of the upper surface (350US) of the third source / drain pattern is smaller than the height (H43) from the lowest part of the upper surface (450US) of the fourth source / drain pattern to the highest part of the upper surface (450US) of the fourth source / drain pattern.

[0219] The height (H31 + H32 + H33) of the third source / drain pattern (350) is smaller than the height (H41 + H42 + H43) of the fourth source / drain pattern (450).

[0220] The height (H42) from the upper surface (BP4_US) of the fourth lower pattern to the lowest part of the upper surface (450US) of the fourth source / drain pattern may be smaller than the height (H44) from the upper surface (BP4_US) of the fourth lower pattern to the lower surface of the tenth inner gate structure (INT1_GS4).

[0221] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0222] 100: Substrate 105: Field insulating film 150, 250, 350, 450: Source / Drain Pattern AP1, AP2, AP3, AP4: Activation pattern BP1, BP2, BP3, BP4: Sub-pattern NS1, NS2, NS3, NS4: Sheet Pattern GS1, GS2, GS3, GS4: Gate structures

Claims

Claim 1 A first active pattern comprising a first lower pattern extending in a first direction and a plurality of first sheet patterns including a width in a second direction and spaced apart from the first lower pattern in a third direction; a plurality of first gate structures spaced apart in the first direction on the first lower pattern and comprising a first gate electrode and a first gate insulating film, wherein the first gate electrodes of the first gate structures adjacent to each other in the first direction among the plurality of first gate structures are spaced apart by a first distance; a second active pattern comprising a second lower pattern extending in the first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in the third direction; a plurality of second gate structures spaced apart in the first direction on the second lower pattern and comprising a second gate electrode and a second gate insulating film, wherein the second gate electrodes of the second gate structures adjacent to each other in the first direction among the plurality of second gate structures are spaced apart by a second distance greater than the first distance; a first source / drain recess defined between the adjacent first gate structures; and the adjacent second gate A semiconductor device comprising: a second source / drain recess defined between structures; a first source / drain pattern disposed within the first source / drain recess; and a second source / drain pattern disposed within the second source / drain recess, wherein the depth from the upper surface of the first lower pattern to the lowest part of the first source / drain pattern is smaller than the depth from the upper surface of the second lower pattern to the lowest part of the second source / drain pattern, and the height from the lowest part of the upper surface of the first source / drain pattern to the highest part of the upper surface of the first source / drain pattern is smaller than the height from the lowest part of the upper surface of the second source / drain pattern to the highest part of the upper surface of the second source / drain pattern, and the first source / drain pattern and the second source / drain pattern contain impurities of the same conductivity type. Claim 2 A semiconductor device according to claim 1, wherein the first gate structure comprises an inner gate structure disposed between the first lower pattern and the first sheet pattern and between adjacent first sheet patterns, and including the first gate electrode and the first gate insulating film, and the first source / drain pattern is in contact with the first gate insulating film of the inner gate structure. Claim 3 A semiconductor device according to claim 1, wherein the first gate structure comprises a plurality of inner spacers disposed between the first lower pattern and the first sheet pattern and between adjacent first sheet patterns. Claim 4 A semiconductor device according to claim 1, wherein the second gate structure comprises a first inner gate structure disposed between the second lower pattern and the second sheet pattern, and a second inner gate structure disposed between adjacent second sheet patterns, wherein the width of the first inner gate structure in the first direction is the same as the width of the second inner gate structure in the first direction. Claim 5 A semiconductor device according to claim 4, wherein the first gate structure comprises a third inner gate structure disposed between the first lower pattern and the first sheet pattern, and a fourth inner gate structure disposed between adjacent first sheet patterns, and the width of the third inner gate structure in the first direction is the same as the width of the fourth inner gate structure in the first direction. Claim 6 A semiconductor device according to claim 4, wherein the first gate structure comprises a third inner gate structure disposed between the first lower pattern and the first sheet pattern, and a fourth inner gate structure disposed between adjacent first sheet patterns, wherein the width of the third inner gate structure in the first direction is greater than the width of the fourth inner gate structure in the first direction. Claim 7 A semiconductor device according to claim 1, wherein the upper surface of the first source / drain pattern has a convex shape and the upper surface of the second source / drain pattern has a concave shape. Claim 8 A semiconductor device according to claim 1, wherein the upper surface of the first source / drain pattern is flat and the upper surface of the second source / drain pattern has a concave shape. Claim 9 A semiconductor device according to claim 1, wherein the upper surface of the first source / drain pattern and the upper surface of the second source / drain pattern each have a concave shape. Claim 10 delete Claim 11 A first active pattern comprising a first lower pattern extending in a first direction and a plurality of first sheet patterns including a width in a second direction and spaced apart from the first lower pattern in a third direction; a plurality of first gate structures spaced apart in the first direction on the first lower pattern and comprising a first gate electrode and a first gate insulating film, wherein the first gate electrodes of the first gate structures adjacent to each other in the first direction among the plurality of first gate structures are spaced apart by a first distance; a second active pattern comprising a second lower pattern extending in the first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in the third direction; a plurality of second gate structures spaced apart in the first direction on the second lower pattern and comprising a second gate electrode and a second gate insulating film, wherein the second gate electrodes of the second gate structures adjacent to each other in the first direction among the plurality of second gate structures are spaced apart by a second distance greater than the first distance; a first source / drain recess defined between the adjacent first gate structures; and the adjacent second gate A semiconductor device comprising: a second source / drain recess defined between structures; a first source / drain pattern disposed within the first source / drain recess; and a second source / drain pattern disposed within the second source / drain recess, wherein the height from the upper surface of the first lower pattern to the lowest part of the upper surface of the first source / drain pattern is greater than the height from the upper surface of the second lower pattern to the lowest part of the upper surface of the second source / drain pattern, and the height from the lowest part of the upper surface of the first source / drain pattern to the highest part of the upper surface of the first source / drain pattern is less than the height from the lowest part of the upper surface of the second source / drain pattern to the highest part of the upper surface of the second source / drain pattern, and wherein the first source / drain pattern and the second source / drain pattern each comprise an n-type impurity. Claim 12 A semiconductor device according to claim 11, wherein the height of the first source / drain pattern is smaller than the height of the second source / drain pattern. Claim 13 A semiconductor device according to claim 11, wherein the depth from the upper surface of the first lower pattern to the lowest part of the first source / drain pattern is smaller than the depth from the upper surface of the second lower pattern to the lowest part of the second source / drain pattern. Claim 14 A semiconductor device according to claim 11, wherein the first gate structure comprises an inner gate structure disposed between the first lower pattern and the first sheet pattern and between adjacent first sheet patterns, and including the first gate electrode and the first gate insulating film, and the first source / drain pattern is in contact with the first gate insulating film of the inner gate structure. Claim 15 A semiconductor device according to claim 11, wherein the first gate structure comprises a plurality of inner spacers disposed between the first lower pattern and the first sheet pattern and between adjacent first sheet patterns. Claim 16 A semiconductor device according to claim 11, wherein the second gate structure comprises a plurality of inner gate structures disposed between the second lower pattern and the second sheet pattern and between adjacent second sheet patterns, and the plurality of inner gate structures comprises an uppermost inner gate structure furthest from the second lower pattern, and the height from the upper surface of the second lower pattern to the lowest part of the upper surface of the second source / drain pattern is smaller than the height from the upper surface of the second lower pattern to the lower surface of the uppermost inner gate structure. Claim 17 A first active pattern comprising a first lower pattern extending in a first direction and a plurality of first sheet patterns including a width in a second direction and spaced apart from the first lower pattern in a third direction; a plurality of first gate structures spaced apart in the first direction on the first lower pattern and comprising a first gate electrode and a first gate insulating film, wherein the first gate electrodes of the first gate structures adjacent to each other in the first direction among the plurality of first gate structures are spaced apart by a first distance; a second active pattern comprising a second lower pattern extending in the first direction and a plurality of second sheet patterns spaced apart from the second lower pattern in the third direction; a plurality of second gate structures spaced apart in the first direction on the second lower pattern and comprising a second gate electrode and a second gate insulating film, wherein the second gate electrodes of the second gate structures adjacent to each other in the first direction among the plurality of second gate structures are spaced apart by a second distance greater than the first distance; a first source / drain recess defined between the adjacent first gate structures; and the adjacent second gate A semiconductor device comprising: a second source / drain recess defined between structures; a first source / drain pattern disposed within the first source / drain recess; and a second source / drain pattern disposed within the second source / drain recess, wherein the height from the lowest part of the upper surface of the first source / drain pattern to the highest part of the upper surface of the first source / drain pattern is a first height, and the height from the lowest part of the upper surface of the second source / drain pattern to the highest part of the upper surface of the second source / drain pattern is a second height greater than the first height. Claim 18 A semiconductor device according to claim 17, wherein the depth from the upper surface of the first lower pattern to the lowest part of the first source / drain pattern is smaller than the depth from the upper surface of the second lower pattern to the lowest part of the second source / drain pattern. Claim 19 A semiconductor device according to claim 17, wherein the height of the first source / drain pattern is smaller than the height of the second source / drain pattern. Claim 20 In claim 17, the first source / drain pattern and the second source / drain pattern are each semiconductor devices containing n-type impurities.

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