Semiconductor package and fabricating method of the same

Abstract

A semiconductor package is provided. The semiconductor package includes a substrate extending in first and second directions intersecting each other, a first semiconductor chip having first and second surfaces facing each other on the substrate, wherein first and second trenches are respectively formed along the first and second directions on the first surface, and a second semiconductor chip disposed on the first semiconductor chip in an area between the first and second trenches.

Description

Technology Field

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same. Background Technology

[0002] To achieve high integration and high-performance operation of semiconductor devices, methods for stacking semiconductor chips are being proposed. For example, multi-chip packages, in which multiple chips are mounted within a single semiconductor package, or system-in-packages, in which stacked heterogeneous chips operate as a single system, are being presented.

[0003] Wire bonding or flip-chip bonding methods can be used to electrically connect stacked semiconductor chips. Flip-chip bonding refers to a packaging method that electrically connects a die to electrode terminals, while wire bonding refers to a packaging method that uses wires as wiring.

[0004] Meanwhile, when stacking semiconductor chips using this method, characteristic defects may occur due to misalignment between the semiconductor chips. The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide a semiconductor package with improved product reliability by preventing misalignment between semiconductor chips.

[0006] The technical problem that the present invention aims to solve is to provide a method for manufacturing a semiconductor package with improved product reliability by preventing misalignment between semiconductor chips.

[0007] The technical problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises a substrate extending in first and second directions intersecting each other, a first semiconductor chip having first and second surfaces facing each other on the substrate, wherein first and second trenches are respectively formed along the first and second directions on the first surface, and a second semiconductor chip disposed on the first semiconductor chip in an area between the first and second trenches.

[0009] A semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises a substrate extending in first and second directions intersecting each other, a first semiconductor chip having first and second trenches formed along the first and second directions respectively on the substrate, and a second semiconductor chip disposed on the first semiconductor chip, wherein each of the first and second trenches includes a sidewall extending in a third direction intersecting the first and second directions and a bottom surface connecting the sidewalls, and the sidewall of the first trench is aligned with the second semiconductor chip in the third direction.

[0010] A method for manufacturing a semiconductor package according to some embodiments of the present invention for achieving the above technical problem comprises a substrate extending in first and second directions intersecting each other, a first semiconductor chip having first and second trenches formed along the first and second directions respectively on the substrate, and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is formed in an area between the first and second trenches on the first semiconductor chip to align the sidewalls of the first and second trenches with the second semiconductor chip.

[0011] A semiconductor package manufacturing method according to some embodiments of the present invention for achieving the above technical problem comprises forming a plurality of dies on a silicon wafer, forming a trench on each of the upper surfaces of the plurality of dies, cutting the silicon wafer along a cutting line to form a plurality of first semiconductor chips with trenches formed thereon, attaching a substrate to the lower part of the first semiconductor chips, and forming a second semiconductor chip on the upper part of the first semiconductor chips.

[0012] Specific details of other embodiments are included in the detailed description and drawings. Brief explanation of the drawing

[0013] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor package according to some embodiments of the present invention. Figure 2 is a cross-sectional view taken along the line I-I' of Figure 1. Figure 3 is an enlarged view of area R of Figure 1. Figure 4 is a cross-sectional view taken along the line II-II' of Figure 1. FIG. 5 is an exemplary layout diagram according to some embodiments of the present invention. Figure 6 is a cross-sectional view taken along the line III-III' of Figure 5. FIG. 7 is an exemplary layout diagram according to some embodiments of the present invention. Figure 8 is a cross-sectional view taken along the line IV-IV' of Figure 7. FIGS. 9 and FIGS. 10 are exemplary layout drawings according to some embodiments of the present invention. FIGS. 11 to 14 are drawings for explaining a method of manufacturing a semiconductor package according to some embodiments of the present invention. Specific details for implementing the invention

[0014] Embodiments of the present invention will be described in detail below with reference to the attached drawings. Identical components in the drawings are denoted by the same reference numerals, and redundant descriptions thereof are omitted.

[0015] FIG. 1 is an exemplary layout diagram for illustrating a semiconductor package according to some embodiments of the present invention. FIG. 2 is a cross-sectional view taken along the line I-I' of FIG. 1. FIG. 3 is an enlarged view of area R of FIG. 1. FIG. 4 is a cross-sectional view taken along the line II-II' of FIG. 1.

[0016] Referring to FIG. 1, a semiconductor package according to some embodiments of the present invention includes a substrate (100), a first semiconductor chip (200), and a second semiconductor chip (300), and may further include a mold layer (400).

[0017] The substrate (100) may include an insulating layer (110) comprising a first protective film (111), a second protective film (112), and an insulating film (113), and a wiring layer (120) comprising a plurality of wirings (121, 122, 123).

[0018] One side (i.e., the upper surface) of the substrate (100) may be extended in a first direction (Y) and a second direction (X) that intersect each other. A first and second semiconductor chip (200, 300), which will be described later, may be stacked on the upper surface of the substrate (100).

[0019] A plurality of external connection terminals (900) may be disposed on the other side (i.e., the lower side) of the substrate (100). The substrate (100) may include a plurality of wires (121, 122, 123) for electrically connecting the first and second semiconductor chips (200, 300) and the external connection terminals (900).

[0020] The external connection terminal (900) may be, for example, spherical or elliptical, but is not limited thereto. The external connection terminal (900) may include, for example, at least one of tin (Sn), indium (In), lead (Pb), zinc (Zn), nickel (Ni), gold (Au), silver (Ag), copper (Cu), antimony (Sb), bismuth (Bi), and combinations thereof, but the technical concept of the present invention is not limited thereto.

[0021] The external connection terminal (900) can electrically connect the substrate (100) to an external device. Accordingly, the external connection terminal (900) can provide an electrical signal to the substrate (100) or provide an electrical signal provided from the substrate (100) to the external device.

[0022] The substrate (100) may include, for example, a printed circuit board (PCB) or a ceramic substrate. However, the technical concept of the present invention is not limited thereto.

[0023] When the substrate (100) includes a printed circuit board, the insulating film (113) may be made of at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the insulating film (113) may include at least one material selected from ABF (Ajinomoto Build-up Film), FR-4, tetrafunctional epoxy, polyphenylene ether, epoxy / polyphenylene oxide, BT (bismaleimide triazine), thermount, cyanate ester, polyimide, and liquid crystal polymer.

[0024] The first protective layer (111) and the second protective layer (112) may include, for example, a photoimageable dielectric (PID), but are not limited thereto.

[0025] One side of the insulating film (113) is covered with the first protective film (111), and a portion of the wiring (121) may be exposed without being covered by the first protective film (111). The exposed wiring (121) acts as a pad, so that the exposed wiring (121) and the pad (310) of the second semiconductor chip (300) can be connected through a bonding wire (350).

[0026] The other side of the insulating film (113) is covered with a second protective film (112), and a portion of the wiring (123) may be exposed without being covered by the second protective film (112). The exposed wiring (123) may be directly connected to an external connection terminal (900).

[0027] The wiring (121) may include a first alignment pattern (121a) arranged to correspond to a corner area of ​​the first semiconductor chip (200). The first alignment pattern (121a) may refer to wiring (121) exposed by etching a portion of the first protective film (111). The first alignment pattern (121a) may be used to align the position of the second semiconductor chip (300).

[0028] The wiring layer (120) may be arranged in multiple layers. The multiple wirings (121, 122, 123) may be formed in, for example, three layers, but are not limited thereto. For example, the wiring layer (120) may be formed in two layers or four or more layers.

[0029] Although not specifically illustrated, the wiring layer (120) may further include a plurality of vias for electrically connecting a plurality of wirings (121, 122, 123).

[0030] The wiring layer (120) may include, for example, a conductive material. For example, the wiring layer (120) may include at least one metal or metal alloy selected from the group consisting of copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), zinc (Zn), and carbon (C).

[0031] A first semiconductor chip (200) is placed on a first protective film (111). The first semiconductor chip (200) may include a first surface (200_1) and a second surface (200_2) facing each other. The first semiconductor chip (200) may be mounted on a substrate (100) by a flip chip bonding method. The first surface (200_1) of the first semiconductor chip (200) may refer to an active surface that is electrically connected to the substrate (100).

[0032] The substrate (100) may further include a second alignment pattern (114) protruding in a third direction (Z) from the upper surface of the first protective film (111). The second alignment pattern (114) may include, for example, a portion of the solder resist layer of the substrate (100). Referring to FIG. 1, in a planar view, the second alignment pattern (114) may be arranged to surround the first semiconductor chip (200).

[0033] The second alignment pattern (114) may include first and second extension portions (114a, 114b) that are further extended in the first direction (Y) in a planar view and spaced apart from each other in the second direction (X). The first and second extension portions (114a, 114b) may be formed to correspond to the corners of the second semiconductor chip (300), respectively.

[0034] The distance along the second direction (X) between the first and second extension portions (114a, 114b) may correspond to the length of one side (302) of the second semiconductor chip (300). The first and second extension portions (114a, 114b) may serve to prevent misalignment of the second semiconductor chip (300) on the substrate (100) and the first semiconductor chip (200).

[0035] Meanwhile, although not specifically illustrated, the first and second extensions (114a, 114b) may be further extended in the second direction (X) from a planar perspective and spaced apart from each other in the first direction (Y).

[0036] In some embodiments, the position where the second alignment pattern (114) protrudes, the length of the protrusion, and the number of second alignment patterns (114) are not limited to those shown in FIG. 1, provided that they are intended to more accurately implement the alignment of the second semiconductor chip (300). Additionally, the shape of the second alignment pattern (114) may be a shape that is indented into the substrate (100) in a third direction (Z), unlike that shown in FIG. 2. In this case, the second alignment pattern (114) may be formed concavely in the third direction (Z) from the upper surface of the first protective film (111).

[0037] Referring to FIGS. 1 and 2, first and second trenches (T1, T2) extending along first and second directions (Y, X) may be formed on the second surface (200_2) of the first semiconductor chip (200). A second semiconductor chip (300) may be disposed in the area between the first and second trenches (T1, T2).

[0038] For example, the first semiconductor chip (200) may be a silicon (Si) chip, and the second semiconductor chip (300) may be a memory chip.

[0039] The second semiconductor chip (300) may be, for example, a volatile memory chip such as DRAM (Dynamic Random Access Memory) or SRAM (Static RAM), a non-volatile memory chip such as PRAM (Phase-change RAM), MRAM (Magneto resistive RAM), FeRAM (Ferroelectric RAM), or RRAM (Resistive RAM), or an HBM (High Bandwidth Memory) memory chip in which multiple DRAM memory chips are stacked. However, the scope of the present invention is not limited thereto.

[0040] Referring to FIGS. 1 and 2, the first semiconductor chip (200) may include first and second sides (201, 202) facing each other in a first direction (Y), and third and fourth sides (203, 204) facing each other in a second direction (X) and connected to the first and second sides (201, 202). The first to fourth sides (201 to 204) may connect the first and second sides (200_1, 200_2) facing each other.

[0041] Referring to FIG. 3, the first trench (T1) may include a side wall (T1_S) extending in a third direction (Z, vertical direction) intersecting the first and second directions (Y, X) and a bottom surface (T1_B) connecting the side wall (T1_S). The side wall (T1_S) of the first trench may be aligned with the second semiconductor chip (300) in the third direction (Z).

[0042] For example, the length (W1) along the second direction (X) of the bottom surface (T1_B) of the first trench, i.e., the width of the first trench (T1), may be longer than the length (Z1) along the third direction (Z) of the side wall (T1_S) of the first trench. However, the technical concept of the present invention is not limited thereto.

[0043] Referring to FIG. 4, the second trench (T2) may include a side wall (T2_S) extending in a third direction (Z, vertical direction) and a bottom surface (T2_B) connecting the side wall (T2_S). The side wall (T2_S) of the second trench may be aligned with the second semiconductor chip (300) in the third direction (Z).

[0044] Although not specifically illustrated, the length along the first direction (Y) of the bottom surface (T2_B) of the second trench may be longer than the length along the third direction (Z) of the side wall (T2_S) of the second trench. However, the technical concept of the present invention is not limited thereto.

[0045] The first semiconductor chip (200) can be electrically connected to the substrate (100) through a bump (600) between the first semiconductor chip (200) and the substrate (100).

[0046] The bump (600) can connect the pad (210) and the substrate (100). For example, the bump (600) can be connected to some of the wiring (121) of the substrate (100). The bump (600) may be, for example, spherical or elliptical, but is not limited thereto. The bump (600) may include, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and combinations thereof, but is not limited thereto.

[0047] A pad (210) of the first semiconductor chip (200) may be placed on a first surface (200_1) of the first semiconductor chip (200). The pad (210) may include, for example, copper (Cu), copper alloy, nickel (Ni), palladium (Pd), platinum (Pt), gold (Au), cobalt (Co), and combinations thereof, but is not limited thereto.

[0048] A second semiconductor chip (300) may be placed on a first semiconductor chip (200). The second semiconductor chip (300) may include a first surface (300_1) and a second surface (300_2) facing each other. Through a pad (310) formed on the second surface (300_2) of the second semiconductor chip (300), the second semiconductor chip (300) may be electrically connected to a substrate (100).

[0049] The pad (310) may include, for example, copper (Cu), copper alloy, nickel (Ni), palladium (Pd), platinum (Pt), gold (Au), cobalt (Co) and combinations thereof, but is not limited thereto.

[0050] Referring to FIGS. 1 and 2, the second semiconductor chip (300) includes first and second sides (301, 302) facing each other in a first direction (Y), and third and fourth sides (303, 304) facing each other in a second direction (X) and connected to the first and second sides (301, 302). The first to fourth sides (301 to 304) can connect the first and second sides (300_1, 300_2).

[0051] Referring to FIG. 1, for example, the length (X1) along the second direction (X) from the third side (203) of the first semiconductor chip to the third side (303) of the second semiconductor chip may be the same as the length (X2) along the second direction (X) from the fourth side (204) of the first semiconductor chip to the fourth side (304) of the second semiconductor chip.

[0052] Meanwhile, conversely, the length (X1) along the second direction (X) from the third side (203) of the first semiconductor chip to the third side (303) of the second semiconductor chip may be different from the length (X2) along the second direction (X) from the fourth side (204) of the first semiconductor chip to the fourth side (304) of the second semiconductor chip. That is, the position of the second semiconductor chip (300) can be formed in various ways depending on the size of the second semiconductor chip (300), and is not limited to the position on the first semiconductor chip (200) shown in FIG. 1.

[0053] The length (Y1) along the first direction (Y) from the first side (201) of the first semiconductor chip to the first side (301) of the second semiconductor chip may be different from the length along the first direction (Y) from the second side (202) of the first semiconductor chip to the second side (302) of the second semiconductor chip.

[0054] For example, since the side (202) of the first semiconductor chip (200) shown in FIG. 1 is in contact with the side (302) of the second semiconductor chip (300), the length (Y1) along the first direction (Y) from the first side (201) of the first semiconductor chip to the first side (301) of the second semiconductor chip may be longer than the length along the first direction (Y) from the second side (202) of the first semiconductor chip to the second side (302) of the second semiconductor chip.

[0055] Referring to FIGS. 1 and FIGS. 4, the second side (302) of the second semiconductor chip can be aligned with the second side (202) of the first semiconductor chip in a third direction (Z).

[0056] The sidewall (T1_S) of the first trench can be aligned with the third side (303) of the second semiconductor chip in the third direction (Z). The sidewall (T2_S) of the second trench can be aligned with the first side (301) of the second semiconductor chip in the third direction (Z).

[0057] The mold layer (400) can cover the first and second semiconductor chips (200, 300) and fill the interior of the first and second trenches (T1, T2). The mold layer (400) can cover at least a portion of the first protective film (111) on the substrate (100).

[0058] The mold layer (400) may include, for example, an insulating polymer material such as EMC (epoxy molding compound). The mold layer (400) may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin containing reinforcing materials such as fillers, for example, ABF, FR-4, BT resin, etc.

[0059] The filler may use at least one selected from the group consisting of silica (SiO2), alumina (Al2O3), silicon carbide (SiC), barium sulfate (BaSO4), talc, clay, mica powder, aluminum hydroxide (Al(OH)3), magnesium hydroxide (Mg(OH)2), calcium carbonate (CaCO3), magnesium carbonate (MgCO3), magnesium oxide (MgO), boron nitride (BN), aluminum borate (AlBO3), barium titanate (BaTiO3), and calcium zirconate (CaZrO3). However, the material of the filler is not limited thereto.

[0060] The adhesive layer (500) may be attached to the first surface (300_1) of the second semiconductor chip (300). The second semiconductor chip (300) may be mounted on the first semiconductor chip (200) by the adhesive layer (500). The adhesive layer (500) may include, for example, at least one of liquid epoxy, adhesive tape, a conductive medium, and combinations thereof, but is not limited thereto.

[0061] An underfill material (700) can be formed on a substrate (100). The underfill material (700) can fill the area between the substrate (100) and the first semiconductor chip (200). The underfill material (700) can prevent the first semiconductor chip (200) from breaking by fixing the first semiconductor chip (200) on the substrate (100). The underfill material (700) can cover a bump (600). The bump (600) can penetrate the underfill material (700) to electrically connect the substrate (100) and the first semiconductor chip (200).

[0062] The underfill material (700) may include, for example, an insulating polymer material such as EMC (epoxy molding compound), but is not limited thereto. In some embodiments, the underfill material (700) may include a material different from the mold layer (400) described below. For example, the underfill material (700) may include an insulating material having better fluidity than the mold layer (400). Accordingly, the underfill material (700) can efficiently fill the narrow space between the substrate (100) and the first semiconductor chip (200).

[0063] FIG. 5 is an exemplary layout diagram according to some embodiments of the present invention. FIG. 6 is a cross-sectional view taken along the line III-III' of FIG. 5. For convenience of explanation, the explanation will focus on the differences from the semiconductor package described using FIG. 1 to 4.

[0064] Referring to FIG. 5, on the first semiconductor chip (200), a first trench (T1) extending along the first direction (Y) may be formed in multiple numbers. Specifically, the first trench (T1) may include a first_1 trench (T1_1) and a first_2 trench (T1_2) spaced apart from each other in the second direction (X).

[0065] Referring to FIG. 6, both sides of the second semiconductor chip (300) and the side walls of the first_1 trench (T1_1) and the first_2 trench (T1_2) can be aligned with each other.

[0066] The first_1 trench (T1_1) includes a side wall extending in the third direction (Z) and a bottom surface connecting the side walls, and the side wall of the first_1 trench (T1_1) can be aligned with the second semiconductor chip (300) in the third direction (Z). The first_2 trench (T1_2) includes a side wall extending in the third direction (Z) and a bottom surface connecting the side walls, and the side wall of the first_2 trench (T1_2) can be aligned with the second semiconductor chip (300) in the third direction (Z).

[0067] FIG. 7 is an exemplary layout diagram according to some embodiments of the present invention. FIG. 8 is a cross-sectional view taken along the line IV-IV' of FIG. 7. For convenience of explanation, the explanation will focus on the differences from the semiconductor package described using FIG. 1 to 4.

[0068] Referring to FIGS. 7 and 8, the second semiconductor chip (300) may be placed at the center of the first semiconductor chip (200). In this case, the side of the second semiconductor chip (300) and the side of the first semiconductor chip (200) may not come into contact with each other.

[0069] In this case, the length along the first direction (Y) from the first side (201) of the first semiconductor chip to the first side (301) of the second semiconductor chip may be the same as the length along the first direction (Y) from the second side (202) of the first semiconductor chip to the second side (302) of the second semiconductor chip.

[0070] Meanwhile, the position of the second semiconductor chip (300) on the first semiconductor chip (200) is not limited to that shown in FIGS. 1 to 8. That is, depending on the size of the second semiconductor chip (300), the position of the second semiconductor chip (300) can be arranged in various ways. In addition, the position and number of the first and second trenches (T1, T2) can also be arranged in various ways depending on the size of the second semiconductor chip (300) and the desired position.

[0071] However, even in this case, the position of the second semiconductor chip (300) can be accurately aligned on the first semiconductor chip (200) by means of the first and second trenches (T1, T2).

[0072] FIGS. 9 and 10 are exemplary layout diagrams according to several embodiments of the present invention. For convenience of explanation, the description will focus on the differences from the semiconductor package described using FIGS. 1 to 4.

[0073] Referring to FIG. 9, the first and second trenches (T1, T2) may be partially extended in the first and second directions (Y, X). For example, the starting point of the first and second trenches (T1, T2) may be in contact with the side of the first semiconductor chip (200), and the ending point of the extended first and second trenches (T1, T2) may not be in contact with the side of the first semiconductor chip (200).

[0074] Referring to FIG. 10, the length of the first and second trenches (T1, T2) extended in the first and second directions (Y, X) may be smaller than the length of the second semiconductor chip (300) along the first and second directions (Y, X). For example, the starting point of the first and second trenches (T1, T2) and the ending point of the first and second trenches (T1, T2) may not be in contact with the side of the first semiconductor chip (200).

[0075] FIGS. 11 to 14 are drawings for explaining a method of manufacturing a semiconductor package according to some embodiments of the present invention. For convenience of explanation, details identical to those described using FIGS. 1 to 4 may be omitted. Additionally, in FIGS. 11 to 14, details regarding the second alignment pattern (114) and the external connection terminal (900) may be omitted.

[0076] Referring to FIG. 11, a plurality of dies (d) may be formed on a silicon wafer (W), and trenches (T1, T2) may be formed on the upper surface of each of the plurality of dies (d). In this case, trenches (T1, T2) may be formed on the upper surface of the plurality of dies (d) using a laser. The trenches (T1, T2) may be formed to intersect each other. Although FIG. 11 shows two trenches (T1, T2), the number and location of the trenches (T1, T2) are not limited to those shown in FIG. 11.

[0077] Referring to FIG. 12, a silicon wafer (W) can be cut along a cutting line (L) to form a first semiconductor chip (200) in which trenches (T1, T2) are formed. The first semiconductor chip (200) may be formed in multiple numbers.

[0078] Referring to FIG. 13, a substrate (100) can be attached to the lower part of the first semiconductor chip (200). The substrate (100) may include an insulating layer and a wiring layer as described using FIG. 2 above.

[0079] By forming an underfill material (700) that fills the area between the substrate (100) and the first semiconductor chip (200), the first semiconductor chip (200) can be fixed on the substrate (100).

[0080] Referring to FIG. 14, a second semiconductor chip (300) can be formed on top of a first semiconductor chip (200). The second semiconductor chip (300) can be stacked on top of the first semiconductor chip (200) through an adhesive layer (500) attached to the second semiconductor chip (300).

[0081] In this case, a second semiconductor chip (300) can be formed in the region between the trenches (T1, T2) on the first semiconductor chip (200). The sidewalls of the trenches (T1, T2) and the second semiconductor chip (300) can be aligned in a vertical direction. That is, in some embodiments of semiconductor packages, by forming trenches on a silicon wafer, the alignment characteristics of the semiconductor chips can be improved when the semiconductor chips are stacked.

[0082] Afterwards, a mold layer (400) can be formed to cover the first and second semiconductor chips (200, 300) and fill the inside of the trench (T1).

[0083] The first semiconductor chip (200) and the substrate (100) can be electrically connected through a bump (600) between the substrate (100) and the first semiconductor chip (200), and the second semiconductor chip (300) and the substrate (100) can be electrically connected through a bonding wire (350). By doing so, a semiconductor package according to some embodiments can be formed.

[0084] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0085] 100: Substrate 110: Insulating layer 120: Wiring layer 114: Second alignment pattern 200: The first semiconductor chip 300: The Second Semiconductor Chip 400: Mold layer 500: Adhesive layer 600: Bump 700: Underfill material

Claims

Claim 1 A semiconductor package comprising: a substrate extending in first and second directions intersecting each other; a first semiconductor chip having first and second faces facing each other on the substrate, wherein first and second trenches are respectively formed along the first and second directions on the first face; and a second semiconductor chip disposed on the first semiconductor chip in an area between the first and second trenches, wherein each of the first and second trenches includes a sidewall extending in a third direction intersecting the first and second directions and a bottom surface connecting the sidewalls, and the sidewall of the first trench is aligned with the second semiconductor chip in the third direction. Claim 2 delete Claim 3 A semiconductor package according to claim 1, wherein the first semiconductor chip further comprises a second surface facing the first surface, and the second semiconductor chip comprises a third surface on the first semiconductor chip and a fourth surface facing the third surface, wherein the second surface of the first semiconductor chip is electrically connected to the substrate through a bump between the first semiconductor chip and the substrate, and the fourth surface of the second semiconductor chip is electrically connected to the substrate through a bonding wire. Claim 4 A semiconductor package according to claim 1, further comprising a mold layer that covers the first and second semiconductor chips and fills the interiors of the first and second trenches. Claim 5 In claim 1, the substrate comprises a first alignment pattern protruding from the upper surface of the substrate, and, from a planar perspective, the first alignment pattern is arranged to surround the first semiconductor chip. Claim 6 A semiconductor package according to claim 1, wherein the first semiconductor chip is a silicon (Si) chip and the second semiconductor chip is a memory chip. Claim 7 A semiconductor package comprising: a substrate extending in first and second directions intersecting each other; a first semiconductor chip having first and second trenches formed respectively along the first and second directions on the substrate; and a second semiconductor chip disposed on the first semiconductor chip, wherein each of the first and second trenches includes a sidewall extending in a third direction intersecting the first and second directions and a bottom surface connecting the sidewalls, and the sidewall of the first trench is aligned with the second semiconductor chip in the third direction. Claim 8 A semiconductor package according to claim 7, wherein the second semiconductor chip is disposed in an area between the first and second trenches, and the side of the second semiconductor chip is aligned with the side of the first semiconductor chip in the third direction. Claim 9 In claim 7, the semiconductor package further comprises a mold layer covering the first and second semiconductor chips, wherein the mold layer fills the interior of the first and second trenches. Claim 10 A method for manufacturing a semiconductor package comprising a substrate extending in first and second directions intersecting each other, a first semiconductor chip having first and second trenches formed along the first and second directions respectively on the substrate, and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is formed in an area between the first and second trenches on the first semiconductor chip to align the sidewalls of the first and second trenches with the second semiconductor chip.

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