Logic operation method and logic operation circuit using SOM elements

Abstract

A logical operation method is disclosed that implements a logical operation using a SOM element. A logic operation method according to one embodiment of the disclosed invention comprises the steps of: setting a first memory element sharing an external resistor and a reference node to either a P state or an N state; setting a read memory element sharing the external resistor and the reference node to either the P state or the N state; applying a first operation pulse to the first memory element by a first voltage application unit; and applying a read operation pulse to the read memory element by a read voltage application unit, wherein the external resistor determines the first memory element and the read memory element to have either a PN characteristic or an NP characteristic, the P state is a state in which a positive pulse is applied to at least one of the first memory element and the read memory element, and the N state is a state in which a negative pulse is applied to at least one of the first memory element and the read memory element, the PN characteristic is a characteristic in which the threshold voltage of the element when the element is in the P state is smaller than the threshold voltage of the element when the element is in the N state, and the NP characteristic is a characteristic in which the threshold voltage of the element when the element is in the N state is of the The characteristic is smaller than the threshold voltage of the above device, and the device is either the first memory device or the read memory device.

Description

Technology Field

[0001] The present invention relates to a method and circuit for implementing a logic operation of a memory device in which the threshold voltage can be changed. More specifically, it relates to a method and circuit for implementing a stateful logic operation using a SOM device made of a chalcogenide material. Background Technology

[0002] With the recent proliferation of artificial intelligence, the efficiency of large-scale data computation is becoming increasingly important. Traditionally, bottlenecks caused by data transfer between the central processing unit (CPU) and memory have resulted in problems such as reduced computation speed or decreased reliability.

[0003] To solve these problems, there is a need for a device with integrated computation and storage functions that can minimize data movement by performing computations within the memory device itself.

[0004] Therefore, technology for developing devices with integrated computation and storage functions is required. The problem to be solved

[0005] The problem that the present invention aims to solve is to implement logical operations using SOM elements.

[0006] Another problem that the present invention aims to solve is to integrate semiconductor products by performing logical operations and storing information using only a single element, without separate selectors or transistors.

[0007] Meanwhile, the technical problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present invention belongs from the description below. means of solving the problem

[0008] A logic operation method according to one aspect of the present invention for achieving the above objective comprises the steps of: setting a first memory element sharing an external resistor and a reference node to either a P state or an N state; setting a read memory element sharing the external resistor and the reference node to either the P state or the N state; applying a first operation pulse to the first memory element by a first voltage application unit; and applying a read operation pulse to the read memory element by a read voltage application unit, wherein the external resistor determines the first memory element and the read memory element to have either a PN characteristic or an NP characteristic, the P state is a state in which a positive pulse is applied to at least one of the first memory element and the read memory element, and the N state is a state in which a negative pulse is applied to at least one of the first memory element and the read memory element, the PN characteristic is a characteristic in which the threshold voltage of the element when the element is in the P state is smaller than the threshold voltage of the element when the element is in the N state, and the NP characteristic is the of the element when the element is in the N state The threshold voltage is a characteristic that is smaller than the threshold voltage of the device when the P state is the above, and the device is either the first memory device or the read memory device.

[0009] In addition, the step of applying the read operation pulse is performed after the step of applying the first operation pulse.

[0010] In addition, the first memory element and the read memory element are determined to have the PN characteristics by the external resistance, and prior to the step of applying the read operation pulse, the read memory element is set to the N state and configured to perform an IMPLY operation.

[0011] In addition, at least one of the first memory element and the read memory element is a SOM element, and the SOM element has either the PN characteristic or the NP characteristic based on the resistance value to be compared.

[0012] A logic operation method according to another aspect of the present invention for achieving the above objective comprises the steps of: setting a first memory element sharing an external resistor and a reference node to either a P state or an N state; setting a second memory element sharing the external resistor and the reference node to either the P state or the N state; setting a read memory element sharing the external resistor and the reference node to the P state or the N state; applying a first operation pulse to the first memory element by a first voltage application unit; applying a second operation pulse to the second memory element by a second voltage application unit; and applying a read operation pulse to the read memory element by a read voltage application unit, wherein the external resistor determines the first memory element, the second memory element, and the read memory element to be either a PN characteristic or an NP characteristic, the P state is a state in which a positive pulse is applied to at least one of the first memory element, the second memory element, and the read memory element, and the N state is to at least one of the first memory element, the second memory element, and the read memory element A negative pulse is applied, and the PN characteristic is a characteristic in which the threshold voltage of the device when the device is in the P state is smaller than the threshold voltage of the device when the device is in the N state, and the NP characteristic is a characteristic in which the threshold voltage of the device when the device is in the N state is smaller than the threshold voltage of the device when the device is in the P state, and the device is any one of the first memory device, the second memory device, and the read memory device.

[0013] In addition, the step of applying the read operation pulse is performed after the step of applying the first operation pulse or the step of applying the second operation pulse.

[0014] In addition, the first memory element, the second memory element, and the read memory element are determined to have the PN characteristics by the external resistance, and prior to the step of applying the read operation pulse, the read memory element is set to the N state and configured to perform a NAND operation or a NOR operation.

[0015] In addition, the first memory element, the second memory element, and the read memory element are determined to have the NP characteristics by the external resistance, and prior to the step of applying the read operation pulse, the read memory element is set to the N state and configured to perform an AND operation or an OR operation.

[0016] In addition, at least one of the first memory element, the second memory element, and the read memory element is a SOM element, and the SOM element has either the PN characteristic or the NP characteristic based on the resistance value to be compared.

[0017] A logic operation circuit according to another aspect of the present invention for achieving the above objective comprises a first voltage application unit capable of applying a first operation pulse, a read voltage application unit capable of applying a read operation pulse, an external resistor having one end connected to a reference node and the other end grounded, a first memory element having one end connected to the reference node and the other end connected to the first voltage application unit, and a read memory element having one end connected to the reference node and the other end connected to the read voltage application unit, wherein the first memory element and the read memory element are set to either a P state or an N state, and the external resistor determines the first memory element and the read memory element to have either a PN characteristic or an NP characteristic, wherein the P state is a state in which a positive pulse is applied to at least one of the first memory element and the read memory element, and the N state is a state in which a negative pulse is applied to at least one of the first memory element and the read memory element, and the PN characteristic is such that the threshold voltage of the element when the element is in the P state is the same as the threshold voltage when the element is in the N state The device has a characteristic that is smaller than the threshold voltage, and the NP characteristic is a characteristic in which the threshold voltage of the device when the device is in the N state is smaller than the threshold voltage of the device when the device is in the P state, and the device is either the first memory device or the read memory device.

[0018] In addition, applying the above-mentioned read operation pulse is performed after applying the above-mentioned first operation pulse.

[0019] In addition, the first memory element and the read memory element are determined to have the PN characteristics by the external resistance, and the read memory element is set to the N state before applying the read operation pulse, and is configured to perform an IMPLY operation.

[0020] In addition, at least one of the first memory element and the read memory element is a SOM element, and the SOM element has either the PN characteristic or the NP characteristic based on the resistance value to be compared.

[0021] In addition, it further includes an output measuring unit that detects the current of the reference node and reads the result of a logical operation.

[0022] A logic operation circuit according to another aspect of the present invention for achieving the above objective comprises a first voltage application unit capable of applying a first operation pulse, a second voltage application unit capable of applying a second operation pulse, a read voltage application unit capable of applying a read operation pulse, an external resistor having one end connected to a reference node and the other end grounded, a first memory element having one end connected to the reference node and the other end connected to the first voltage application unit, a second memory element having one end connected to the reference node and the other end connected to the second voltage application unit, and a read memory element having one end connected to the reference node and the other end connected to the read voltage application unit, wherein the first memory element, the second memory element, and the read memory element are set to either a P state or an N state, and the external resistor determines the first memory element, the second memory element, and the read memory element to have either a PN characteristic or an NP characteristic, and the P state is such that a positive pulse is applied to at least one of the first memory element, the second memory element, and the read memory element. It is an authorized state, and the N state is a state in which a negative pulse is applied to at least one of the first memory element, the second memory element, and the read memory element, and the PN characteristic is a characteristic in which the threshold voltage of the element when the element is in the P state is smaller than the threshold voltage of the element when the element is in the N state, and the NP characteristic is a characteristic in which the threshold voltage of the element when the element is in the N state is smaller than the threshold voltage of the element when the element is in the P state, and the element is any one of the first memory element, the second memory element, and the read memory element.

[0023] In addition, applying the above-mentioned read operation pulse is performed after applying the above-mentioned first operation pulse or applying the above-mentioned second operation pulse.

[0024] In addition, the first memory element, the second memory element, and the read memory element are determined to have the PN characteristics by the external resistance, and prior to the step of applying the read operation pulse, the read memory element is set to the N state and configured to perform a NAND operation or a NOR operation.

[0025] In addition, the first memory element, the second memory element, and the read memory element are determined to have the NP characteristics by the external resistance, and prior to the step of applying the read operation pulse, the read memory element is set to the N state and configured to perform an AND operation or an OR operation.

[0026] In addition, at least one of the first memory element, the second memory element, and the read memory element is a SOM element, and the SOM element has either the PN characteristic or the NP characteristic based on the resistance value to be compared.

[0027] In addition, it further includes an output measuring unit that detects the current of the reference node and reads the result of a logical operation. Effects of the invention

[0028] The present invention can implement logical operations using SOM elements.

[0029] In addition, the present invention can integrate semiconductor products by performing logic operations and storing information using only a single element without separate selection elements or transistors.

[0030] Meanwhile, the effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present invention belongs from the description below. Brief explanation of the drawing

[0031] Figure 1a is a circuit diagram for verifying the voltage characteristics of a variable element. Figure 1b is a graph showing the voltage characteristics of a variable element. Figure 1c is a diagram showing the voltage characteristics of a variable element according to the size of the resistor connected to the variable element. FIG. 2 is a graph showing a logic operation circuit according to some embodiments of the present invention. FIG. 3a is a diagram illustrating a logical operation method according to some embodiments of the present invention. Figure 3b is the truth table of the IMPLY operation. FIG. 4 is a graph showing a logic operation circuit according to some embodiments of the present invention. FIG. 5a is a diagram illustrating a logical operation method according to some embodiments of the present invention. Figure 5b is a truth table of the NAND operation. FIG. 6a is a diagram illustrating a logical operation method according to some embodiments of the present invention. Figure 6b is the truth table of the NOR operation. FIG. 7a is a diagram illustrating a logical operation method according to some embodiments of the present invention. Figure 7b is a truth table for the AND operation. FIG. 8a is a diagram illustrating a logical operation method according to some embodiments of the present invention. Figure 8b is a truth table for the OR operation. Specific details for implementing the invention

[0032] Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the contents described in the attached drawings. However, the present invention is not limited or restricted by the exemplary embodiments. Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall be used in a meaning that is commonly understood by those skilled in the art to which this disclosure belongs, but this may vary depending on the intent of those skilled in the art, case law, the emergence of new technology, etc.

[0033] Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise. In certain cases, terms have been selected at the applicant's discretion, and in such cases, their meanings will be described in detail in the relevant explanatory sections. Accordingly, terms used in this disclosure should be defined not merely by their names, but based on their meanings and the content throughout this disclosure.

[0034] Throughout this specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Furthermore, the singular form used in this specification includes the plural form unless specifically stated otherwise. Additionally, the expression "at least one of a, b, and / or c" as used throughout this specification may encompass 'a alone', 'b alone', 'c alone', 'a and b', 'a and c', 'b and c', or 'a, b, and c all'.

[0035] Meanwhile, terms such as "first and / or second" used in this specification may be used to describe various components, but they are used solely for the purpose of distinguishing one component from another and are not intended to limit the scope to the components referred to by such terms. For example, without departing from the scope of the present invention, the first component may be named the second component, and the second component may also be named the first component.

[0036] Additionally, terms such as “…part,” “…module,” etc., as described in this specification refer to a unit that processes at least one function or operation, which may be implemented in hardware or software, or a combination of hardware and software. Furthermore, embodiments of this disclosure may be represented in this specification by functional block configurations and various processing steps. These functional blocks may be implemented by various numbers of hardware and / or software configurations that execute specific functions. For example, embodiments of this disclosure may employ direct circuit configurations such as memory, processing, logic, look-up tables, etc., which can execute various functions under the control of one or more microprocessors or other control devices.

[0037] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In describing the embodiments, technical details that are well known in the art to which the present invention pertains and are not directly related to the present invention will be omitted. This is to ensure that the essence of the present invention is conveyed more clearly without obscuring it by omitting unnecessary descriptions. For the same reason, some components in the accompanying drawings may be exaggerated, omitted, or schematically depicted. Furthermore, the size of each component does not entirely reflect its actual size. Throughout this specification, the same reference numerals may refer to the same or corresponding components.

[0038] Figure 1a is a circuit diagram for verifying the voltage characteristics of a variable element. Figure 1b is a graph showing the voltage characteristics of a variable element. Figure 1c is a diagram showing the voltage characteristics of a variable element according to the size of the resistor connected to the variable element.

[0039] Referring to FIGS. 1a to 1c, the circuit diagram of an experiment to verify the voltage characteristics of a variable element may include a voltage application unit (10), an oscilloscope (20), a variable element (30), and a resistor unit (R).

[0040] The voltage application unit (10) can apply voltage to the variable element (30).

[0041] For example, the voltage application unit (10) may be an arbitrary function generator (AFG). The arbitrary function generator can apply a voltage of a waveform desired by the experimenter to the variable element (30). In particular, the arbitrary function generator can apply a pulse-shaped voltage to the variable element (30) and can adjust the width of the pulse.

[0042] The oscilloscope (20) (OSC) may be a device that measures and records the change in voltage across the variable element (30) in real time in response to the voltage applied by the voltage application unit (10). The recorded change in voltage across the variable element (30) can be verified by the experimenter.

[0043] For example, the oscilloscope (20) can measure and record the change in voltage of the first node (N1) and the second node (N2) located at both ends of the variable element (30) in real time.

[0044] The variable element (30) may be a device having a characteristic in which the threshold voltage changes. The electrical characteristics of the variable element (30) may change at the threshold voltage. When a voltage smaller than the threshold voltage is applied to the variable element (30), the current flowing may be small. When the voltage applied to the variable element (30) is gradually increased until the threshold voltage is reached, the resistance of the variable element (30) decreases rapidly, and the current flowing at the threshold voltage may increase rapidly.

[0045] For example, the variable element (30) may be a Symmetric Ovonic Memory (SOM) element. The SOM element may be an amorphous state-based memory element using a chalcogenide material. The threshold voltage of the SOM element may change depending on the polarity of the pulse applied to the SOM element and the resistance value of the resistor (R).

[0046] A positive pulse can be applied to the SOM element. The state in which a positive pulse is applied to the SOM element can be said to be the P state of the SOM element.

[0047] A negative pulse can be applied to the SOM element. The state in which a negative pulse is applied to the SOM element can be said to be the N state of the SOM element.

[0048] The threshold voltage may differ when the SOM element is in the N state and when the SOM element is in the P state.

[0049] If the threshold voltage when the SOM device is in the P state is smaller than the voltage when the SOM device is in the N state, the SOM device may have PN characteristics. In other words, if the threshold voltage when the SOM device is in the N state is larger than the voltage when the SOM device is in the P state, the SOM device may have PN characteristics.

[0050] If the threshold voltage when the SOM device is in the N state is smaller than the voltage when the SOM device is in the P state, the SOM device may have NP characteristics. In other words, if the threshold voltage when the SOM device is in the P state is larger than the threshold voltage when the SOM device is in the N state, the SOM device may have NP characteristics.

[0051] The SOM device may include a chalcogenide material. For example, the SOM device may be composed of an active layer containing a Ge-Sb-Te (GST)-based chalcogenide material and electrodes containing metals such as TiN or Pt at both ends of the active layer.

[0052] In chalcogenide materials, a high resistance state can be maintained in the low-voltage region because electrons are trapped and the conduction path is blocked. When the chalcogenide material reaches a critical voltage, the traps become full, and an avalanche phenomenon may occur in which electrons accelerated by the electric field collide with other atoms to generate new electrons. When a voltage higher than the critical voltage is applied to the chalcogenide material, the amorphous structure rearranges, and the resistance may drop sharply.

[0053] The resistor (R) is a component that hinders the flow of current, and Ohm's law may be applied. One end of the resistor (R) may be grounded, and the other end of the resistor (R) may be a second node (N2). The resistor (R) may have a resistance value. The resistor (R) may be connected in series with a variable element (30).

[0054] The graph of FIG. 1b can show the voltage change when the voltage application unit (10) of FIG. 1a applies a pulse voltage. The horizontal axis of the graph of FIG. 1b can represent time, and the unit can be microseconds (us). The vertical axis of the graph of FIG. 1b can represent voltage, and the unit can be volts (V).

[0055] The voltage of the first node (N1) can be measured to determine the magnitude of the voltage applied by the voltage application unit (10). The voltage of the first node (N1) may be V1. The voltage application unit (10) may apply a pulse voltage at 0 seconds.

[0056] The magnitude of the voltage applied across the resistor (R) can be determined by measuring the voltage of the second node (N2). The voltage of the second node (N2) may be V2. The voltage of the second node (N2) may gradually increase due to the RC delay, and then gradually decrease from the moment the pulse voltage is not applied.

[0057] The magnitude of the voltage applied to both ends of the variable element (30) can be determined by measuring the difference between the voltage of the first node (N1) and the voltage of the second node (N2). The voltage applied to the variable element (30) may be V1-V2. When a pulse voltage is applied to the variable element (30), a positive voltage is applied, but from the moment the pulse voltage is not applied, a negative voltage may be applied.

[0058] When the same pulse voltage is applied, the larger the resistance value of the resistor (R), the longer the negative voltage is maintained in the variable element (30) and the larger the magnitude of the negative voltage applied to the variable element (30). Therefore, when the same pulse voltage is applied, the larger the resistance value of the resistor (R), the greater the effect of a negative pulse being applied.

[0059] FIG. 1c can illustrate that as the resistance value of the resistor (R) increases, an effect similar to that of a negative pulse being applied occurs.

[0060] When the resistance value of the resistor (R) connected to the variable element (30) (e.g., SOM element) is small, the variable element (30) has PN characteristics, but when the resistance value of the resistor (R) connected to the variable element (30) (e.g., SOM element) is large, the variable element (30) may have NP characteristics. In other words, when the resistance value of the resistor (R) connected to the variable element (30) (e.g., SOM element) is small, the threshold voltage in the P state is smaller than the threshold voltage in the N state, but when the resistance value of the resistor (R) connected to the variable element (30) (e.g., SOM element) is large, the threshold voltage in the N state may be smaller than the threshold voltage in the P state.

[0061] In some embodiments of the present invention, when the resistance value is 400Ω, the variable element (30) (e.g., SOM element) may exhibit PN characteristics, and when the resistance value is 10kΩ, the variable element (30) (e.g., SOM element) may exhibit NP characteristics.

[0062] The resistance value of the resistor (R) at the point where the SOM element changes from having PN characteristics to having NP characteristics may be a comparison resistance value. In other words, the SOM element may have either PN characteristics or NP characteristics based on the comparison resistance value. The comparison resistance value may not be determined as a specific numerical value. In other words, the magnitude of the comparison resistance value may differ for each condition depending on the material of the SOM element, the type of the resistor (R), etc.

[0063] The part shown in red in Fig. 1b may be the threshold voltage when a positive pulse is applied. In other words, the part shown in red in Fig. 1b may be the threshold voltage of the P state.

[0064] The part shown in blue in Fig. 1b may be the threshold voltage when a negative pulse is applied. In other words, the part shown in blue in Fig. 1b may be the threshold voltage of the N state.

[0065] Logical operations according to some embodiments of the present invention will be described below with reference to the attached drawings.

[0066] FIG. 2 is a graph showing a logic operation circuit according to some embodiments of the present invention.

[0067] Referring to FIG. 2, a logic operation circuit according to some embodiments of the present invention may include a first voltage application unit (111), a read voltage application unit (120), an external resistor (150), a first memory element (131), and a read memory element (140).

[0068] The first voltage application unit (111) can apply an input state determination pulse, a first operation pulse, or an output state determination pulse. The input state determination pulse, the first operation pulse, or the output state determination pulse applied by the first voltage application unit (111) can be applied to the first memory element (131). The voltage applied by the first voltage application unit (111) is V in1 It may be. The first operation pulse may be a voltage applied by the first voltage application unit (111) during the step of performing an operation (e.g., IMPLY operation).

[0069] The read voltage application unit (120) can apply an input state determination pulse, a read operation pulse, or an output state determination pulse. The state determination pulse, read operation pulse, or output state determination pulse applied by the read pulse application unit can be applied to the read memory element (140). The voltage applied by the read pulse application unit is V out It may be. The read operation pulse may be a voltage applied by the read voltage application unit (120) during the step of performing an operation (e.g., IMPLY operation).

[0070] One end of the first memory element (131) may be connected to a reference node (A) and the other end may be connected to a first voltage application unit (111). The first memory element (131) may share the reference node (A) with an external resistor (150). The first memory element (131) may be in either a P state or an N state.

[0071] One end of the read memory element (140) may be connected to a reference node (A) and the other end may be connected to a read voltage application unit (120). The read memory element (140) may share the reference node (A) with an external resistor (150). The read memory element (140) may be in either a P state or an N state.

[0072] Either one of the first memory element (131) and the read memory element (140) may be a SOM element.

[0073] The external resistor (150) is a component that hinders the flow of current, and Ohm's law may be applied. One end of the external resistor (150) may be connected to a reference node (A), and the other end of the resistor (R) may be grounded. The external resistor (150) may have a resistance value. The external resistor (150) may be connected in series to the first memory element (131) or the read memory element (140).

[0074] The external resistance (150) can determine the first memory element (131) and the read memory element (140) as either PN characteristics or NP characteristics.

[0075] When the size of the external resistance (150) is relatively small (e.g., 400Ω), the first memory element (131) and the read memory element (140) may each have PN characteristics. In other words, when the size of the external resistance (150) is less than the resistance value to be compared, the first memory element (131) and the read memory element (140) may each have PN characteristics.

[0076] When the size of the external resistance (150) is relatively large (e.g., 10kΩ), the first memory element (131) and the read memory element (140) may each have NP characteristics. In other words, when the size of the external resistance (150) exceeds the resistance value to be compared, the first memory element (131) and the read memory element (140) may each have NP characteristics.

[0077] The resistance value to be compared may be the magnitude of the resistance of the external resistance (150) at the boundary where each of the first memory element (131) and the read memory element (140) is divided into PN characteristics or NP characteristics.

[0078] Before performing the operation, the first memory element (131) and the read memory element (140) may be set to either a P state or an N state. In other words, before performing the operation, the first memory element (131) and the read memory element (140) may be in a state where a positive pulse is applied or a state where a negative pulse is applied.

[0079] Referring to the description in FIGS. 1a to 1c, the characteristics of the first memory element (131) and the read memory element (140) can be determined by the external resistor (150). More specifically, the first memory element (131) can be determined as either a PN characteristic or an NP characteristic by the magnitude of the resistance value of the external resistor (150).

[0080] When the resistance value of the external resistor (150) connected to the first memory element (131) and the read memory element (140) is small, the external resistor (150) has PN characteristics, but when the resistance value of the external resistor (150) connected to the first memory element (131) and the read memory element (140) is large, the variable element (30) may have NP characteristics.

[0081] FIG. 3a is a diagram illustrating a logical operation method according to some embodiments of the present invention. FIG. 3b is a truth table of an IMPLY operation.

[0082] Referring to FIGS. 2, FIGS. 3a, and FIGS. 3b, the logic operation circuit can be configured such that the first memory element (131) and the read memory element (140) are determined to have PN characteristics by an external resistor (150), and the read memory element (140) is set to an N state to perform an IMPLY operation. In other words, if the size of the external resistor (150) is relatively small so that the first memory element (131) and the read memory element (140) have PN characteristics, and the read memory element (140) is initially set to an N state (i.e., before performing the IMPLY operation), the IMPLY operation can be performed through the logic operation circuit.

[0083] The IMPLY operation can be a logical operation meaning "if A then B." In other words, the IMPLY operation can be a logical operation stating that if A is true, then B must also be true. Therefore, the truth table for the IMPLY operation can be represented as shown in FIG. 3b.

[0084] It can be confirmed through Fig. 3a that the logic operation circuit performs the IMPLY operation.

[0085] Confirming that the logic operation circuit performs an IMPLY operation can be done by i) reading the input, ii) performing an IMPLY operation, and iii) reading the output of the logic operation circuit of FIG. 2. Reading the input, ii) performing an IMPLY operation, and iii) reading the output of the logic operation circuit of FIG. 2 can be done by applying a pulse, and the shape of the pulse applied to perform each step may be as shown in the pulse application signal graph of FIG. 3a.

[0086] In each of the steps of i) reading the input, ii) performing an IMPLY operation, and iii) reading the output, the first voltage application unit (111) inputs a pulse to the first memory element (131), and the reading voltage application unit (120) inputs a pulse to the reading memory element (140).

[0087] In each step of i) reading the input, ii) performing an IMPLY operation, and iii) reading the output, the reading voltage application unit (120) applying a pulse can be performed after the first voltage application unit (111) applying a pulse. Since the pulse applied by the first voltage application unit (111) is applied before the pulse applied by the reading voltage application unit (120), the pulse applied by the reading voltage application unit (120) can be applied after the amount of current flowing in the first memory element (131) is determined by the pulse applied by the first voltage application unit (111). Therefore, the amount of current flowing in the reading memory element (140) can be accurately determined by the pulse applied by the reading voltage application unit (120). In conclusion, by applying the pulse applied by the first voltage application unit (111) before the pulse applied by the voltage application unit, i) reading the input, ii) performing an IMPLY operation, and iii) reading the output can be performed accurately.

[0088] In particular, in the step of ii) performing the IMPLY operation, the reading voltage application unit (120) applies the reading operation pulse after the first voltage application unit (111) applies the first operation pulse, so the IMPLY operation can be performed accurately.

[0089] i) The magnitude of the input state determination pulse applied during the input reading step and iii) the output state determination pulse applied during the output reading step may be such that it does not change the state of the first memory element (131) and the read memory element (140). In other words, when the first memory element (131) or the read memory element (140) is in the N state, when the input state determination pulse or the output state determination pulse is applied to the first memory element (131) or the read memory element (140) during the input reading step and the output reading step, it may not change to the P state. Additionally, when the first memory element (131) or the read memory element (140) is in the P state, when the input state determination pulse or the output state determination pulse is applied to the first memory element (131) or the read memory element (140) during the input reading step and the output reading step, it may not change to the N state.

[0090] In the case of FIG. 3a, cases 1 to 4 can illustrate how much current flows in each of the first memory element (131) and the read memory element (140) when a pulse is input by the first voltage application unit (111) and the read voltage application unit (120) in each of the steps of i) reading the input, ii) performing an IMPLY operation, and iii) reading the output. In particular, the horizontal axis of the graph in cases 1 to 4 and the horizontal axis of the pulse application signal are displayed with the same scale. Therefore, depending on the pulse application signal, it is possible to determine in a time series what kind of current flow each of cases 1 to 4 has.

[0091] In the case of FIG. 3a, the size of the external resistor (150) may be relatively small. In other words, the size of the external resistor (150) is smaller than the resistance value to be compared (for example, the size of the external resistor (150) is 400Ω), so that the first memory element (131) and the read memory element (140) have PN characteristics. Accordingly, the threshold voltage when each of the first memory element (131) and the read memory element (140) is in the N state is greater than the threshold voltage when it is in the P state.

[0092] In case 1, i) in the step of reading the input, the first memory element (131) and the read memory element (140) may be in an N state. Even if an input state determination pulse is applied to the first memory element (131) and the read memory element (140), no current may flow.

[0093] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0094] ii) In the step of performing an IMPLY operation, a first operation pulse may be applied to the first memory element (131) by the first voltage application unit (111). Subsequently, while the first operation pulse is being applied, a read operation pulse may be applied to the read memory element (140) by the read voltage application unit (120).

[0095] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131).

[0096] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage may be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the first operation pulse may be applied to the read memory element (140), and this voltage equal to the difference may be greater than the threshold voltage. Accordingly, current may flow through the read memory element (140).

[0097] In this case, the read memory element (140) may change to a P state after performing an IMPLY operation. As the read memory element (140) changes from an N state to a P state, the read memory element (140) may be in a switched-on state.

[0098] iii) In the step of reading the output, the first memory element (131) may be in the N state and the read memory element (140) may be in the P state. Even if an output state determination pulse is applied to the first memory element (131), current may not flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0099] In conclusion, in case 1, when the state of the first memory element (131) before the operation is 0 and the state of the output memory element is 0, an IMPLY operation can be implemented in which the state of the output memory element is 1 as a result of performing the IMPLY operation.

[0100] In this specification, a state of 0 of the element may be a state in which no current flows, and a state of 1 of the element may be a state in which current flows. Additionally, a state in which no current flows through the element may be a switch-off state, and a state in which current flows through the element may be a switch-on state.

[0101] In case 2, i) in the step of reading the input, the first memory element (131) may be in the N state and the read memory element (140) may be in the P state. Even if an input state determination pulse is applied to the first memory element (131), no current may flow. When an input state determination pulse is applied to the read memory element (140), current may flow.

[0102] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may flow in the read memory element (140).

[0103] ii) In the step of performing an IMPLY operation, a first operation pulse may be applied to the first memory element (131) by the first voltage application unit (111). Subsequently, while the first operation pulse is being applied, a read operation pulse may be applied to the read memory element (140) by the read voltage application unit (120).

[0104] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131).

[0105] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage may be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the first operation pulse may be applied to the read memory element (140), and this voltage equal to the difference may be greater than the threshold voltage. Accordingly, current may flow through the read memory element (140).

[0106] In this case, the read memory element (140) may remain in a P state even after the IMPLY operation is performed. The read memory element (140) may remain in a switched-on state.

[0107] iii) In the step of reading the output, the first memory element (131) may be in the N state and the read memory element (140) may be in the P state. Even if an output state determination pulse is applied to the first memory element (131), current may not flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0108] In conclusion, in case 2, when the state of the first memory element (131) before the operation is 0 and the state of the output memory element is 1, an IMPLY operation can be implemented in which the state of the output memory element is 1 as a result of performing the IMPLY operation.

[0109] In case 3, i) in the step of reading the input, the first memory element (131) may be in a P state and the read memory element (140) may be in an N state. When an input state determination pulse is applied to the first memory element (131), current may flow. Even when an input state determination pulse is applied to the read memory element (140), current may not flow.

[0110] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow to the first memory element. Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow to the read memory element (140).

[0111] ii) In the step of performing an IMPLY operation, a first operation pulse may be applied to the first memory element (131) by the first voltage application unit (111). Subsequently, while the first operation pulse is being applied, a read operation pulse may be applied to the read memory element (140) by the read voltage application unit (120).

[0112] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), a voltage greater than the threshold voltage may be applied to the first memory element (131). Therefore, current may flow through the first memory element (131).

[0113] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0114] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage cannot be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the reference node (A) by the first operation pulse can be applied to the read memory element (140), and this voltage equal to the difference can be less than or equal to the threshold voltage. Therefore, current may not flow through the read memory element (140).

[0115] In this case, the read memory element (140) may remain in an N state even after the IMPLY operation is performed. The read memory element (140) may remain in a switched-off state.

[0116] iii) In the step of reading the output, the first memory element (131) may be in a P state and the read memory element (140) may be in an N state. When an output state determination pulse is applied to the first memory element (131), current may flow. Even when an output state determination pulse is applied to the read memory element (140), current may not flow.

[0117] In conclusion, in case 3, when the state of the first memory element (131) before the operation is 1 and the state of the output memory element is 0, an IMPLY operation can be implemented in which the state of the output memory element is 0 as a result of performing the IMPLY operation.

[0118] In case 4, i) in the step of reading the input, the first memory element (131) and the read memory element (140) may be in a P state. When an input state determination pulse is applied to the first memory element (131) and the read memory element (140), current may flow.

[0119] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current can flow in the read memory element (140).

[0120] ii) In the step of performing an IMPLY operation, a first operation pulse may be applied to the first memory element (131) by the first voltage application unit (111). Subsequently, while the first operation pulse is being applied, a read operation pulse may be applied to the read memory element (140) by the read voltage application unit (120).

[0121] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131).

[0122] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage may be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the first operation pulse may be applied to the read memory element (140), and this voltage equal to the difference may be greater than the threshold voltage. Accordingly, current may flow through the read memory element (140).

[0123] In this case, the read memory element (140) may remain in a P state even after the IMPLY operation is performed. The read memory element (140) may remain in a switched-on state.

[0124] iii) In the step of reading the output, the first memory element (131) and the read memory element (140) may be in a P state. When an output state determination pulse is applied to the first memory element (131), current may flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0125] In conclusion, in case 4, when the state of the first memory element (131) before the operation is 1 and the state of the output memory element is 1, an IMPLY operation can be implemented in which the state of the output memory element is 1 as a result of performing the IMPLY operation.

[0126] FIG. 4 is a graph showing a logic operation circuit according to some embodiments of the present invention.

[0127] Referring to FIG. 4, a logic operation circuit according to some embodiments of the present invention may include a first voltage application unit (111), a second voltage application unit (112), a read voltage application unit (120), an external resistor (150), a first memory element (131), a second memory element (132), and a read memory element (140).

[0128] The first voltage application unit (111) can apply an input state determination pulse, a first operation pulse, or an output state determination pulse. The input state determination pulse, the first operation pulse, or the output state determination pulse applied by the first voltage application unit (111) can be applied to the first memory element (131). The voltage applied by the first voltage application unit (111) is V in1 It may be. The first operation pulse may be a voltage applied by the first voltage application unit (111) during the step of performing an operation (e.g., NAND operation, NOR operation, AND operation or OR operation).

[0129] The second voltage application unit (112) can apply an input state determination pulse, a second operation pulse, or an output state determination pulse. The input state determination pulse, the second operation pulse, or the output state determination pulse applied by the second voltage application unit (112) can be applied to the second memory element (132). The voltage applied by the second voltage application unit (112) is V in2 It may be. The second operation pulse may be a voltage applied by the second voltage application unit (112) during the step of performing an operation (e.g., NAND operation, NOR operation, AND operation or OR operation).

[0130] The read voltage application unit (120) can apply an input state determination pulse, a read operation pulse, or an output state determination pulse. The state determination pulse, read operation pulse, or output state determination pulse applied by the read pulse application unit can be applied to the read memory element (140). The voltage applied by the read pulse application unit is V out It may be. The read operation pulse may be a voltage applied by the read voltage application unit (120) during the step of performing an operation (e.g., NAND operation, NOR operation, AND operation or OR operation).

[0131] One end of the first memory element (131) may be connected to a reference node (A) and the other end may be connected to a first voltage application unit (111). The first memory element (131) may share the reference node (A) with an external resistor (150). The first memory element (131) may be in either a P state or an N state.

[0132] One end of the second memory element (132) may be connected to the reference node (A) and the other end may be connected to the second voltage application unit (112). The second memory element (132) may share the reference node (A) with the external resistor (150). The second memory element (132) may be in either a P state or an N state.

[0133] One end of the read memory element (140) may be connected to a reference node (A) and the other end may be connected to a read voltage application unit (120). The read memory element (140) may share the reference node (A) with an external resistor (150). The read memory element (140) may be in either a P state or an N state.

[0134] Any one of the first memory element (131), the second memory element (132), and the read memory element (140) may be a SOM element.

[0135] The external resistor (150) is a component that hinders the flow of current, and Ohm's law may be applied. One end of the external resistor (150) may be connected to a reference node (A), and the other end of the resistor (R) may be grounded. The external resistor (150) may have a resistance value. The external resistor (150) may be connected in series to the first memory element (131) or the read memory element (140).

[0136] The external resistance (150) can determine the first memory element (131) and the read memory element (140) as either PN characteristics or NP characteristics.

[0137] When the size of the external resistor (150) is relatively small (e.g., 400Ω), the first memory element (131), the second memory element (132), and the read memory element (140) may each have PN characteristics. In other words, when the size of the external resistor (150) is less than the resistance value to be compared, the first memory element (131), the second memory element (132), and the read memory element (140) may each have PN characteristics.

[0138] When the size of the external resistance (150) is relatively large (e.g., 10kΩ), each of the first memory element (131), the second memory element (132), and the read memory element (140) may have NP characteristics. In other words, when the size of the external resistance (150) exceeds the resistance value to be compared, each of the first memory element (131), the second memory element (132), and the read memory element (140) may have NP characteristics.

[0139] The resistance value to be compared may be the magnitude of the resistance of the external resistance (150) at the boundary where each of the first memory element (131), the second memory element (132), and the read memory element (140) is divided into PN characteristics or NP characteristics.

[0140] Before performing the operation, the first memory element (131), the second memory element (132), and the read memory element (140) may be set to either a P state or an N state. In other words, before performing the operation, the first memory element (131), the second memory element (132), and the read memory element (140) may be in a state where a positive pulse is applied or a state where a negative pulse is applied.

[0141] Referring to the description in FIGS. 1a to 1c, the characteristics of the first memory element (131) and the read memory element (140) can be determined by the external resistor (150). More specifically, the first memory element (131) can be determined as either a PN characteristic or an NP characteristic by the magnitude of the resistance value of the external resistor (150).

[0142] When the resistance value of the external resistor (150) connected to the first memory element (131), the second memory element (132), and the read memory element (140) is small, the external resistor (150) has PN characteristics, but when the resistance value of the external resistor (150) connected to the first memory element (131) and the read memory element (140) is large, the variable element (30) may have NP characteristics.

[0143] FIG. 5a is a diagram illustrating a logical operation method according to some embodiments of the present invention. FIG. 5b is a truth table of a NAND operation.

[0144] Referring to FIGS. 4, 5a, and 5b, the logic operation circuit can be configured such that the first memory element (131), the second memory element (132), and the read memory element (140) are determined to have PN characteristics by an external resistor (150), and the read memory element (140) is set to an N state to perform a NAND operation. In other words, if the size of the external resistor (150) is relatively small so that the first memory element (131) and the read memory element (140) have PN characteristics, and the read memory element (140) is initially set to an N state (i.e., before performing a NAND operation), a NAND operation can be performed through the logic operation circuit.

[0145] A NAND operation can be a logical operation that means "it becomes false only when all are true." In other words, a NAND operation can be a logical operation where the output value is 0 only when all input values ​​are 1, and the output value is 1 in all other cases. Therefore, the truth table of a NAND operation can be represented as shown in FIG. 5b.

[0146] It can be confirmed through Fig. 5a that the logic operation circuit performs NAND operations.

[0147] Confirming that the logic operation circuit performs a NAND operation can be done by i) reading the input, ii) performing a NAND operation, and iii) reading the output of the logic operation circuit of FIG. 4. Reading the input, ii) performing a NAND operation, and iii) reading the output of the logic operation circuit of FIG. 4 can be done by applying a pulse, and the shape of the pulse applied to perform each step may be as shown in the pulse application signal graph of FIG. 5a.

[0148] In each of the steps of i) reading the input, ii) performing a NAND operation, and iii) reading the output, the first voltage application unit (111) inputs a pulse to the first memory element (131), the second voltage application unit (112) inputs a pulse to the second memory element (132), and the reading voltage application unit (120) inputs a pulse to the reading memory element (140).

[0149] In each step of i) reading the input, ii) performing a NAND operation, and iii) reading the output, the reading voltage application unit (120) applying a pulse may be performed after the first voltage application unit (111) applying a pulse or the second voltage application unit (112) applying a pulse. Since the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112) is applied before the pulse applied by the reading voltage application unit (120), the pulse applied by the reading voltage application unit (120) may be applied after determining how much current flows in each of the first memory element (131) or the second memory element (132) by the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112). Accordingly, the amount of current flowing through the read memory element (140) can be accurately determined by the pulse applied by the read voltage application unit (120). In conclusion, by applying the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112) before the pulse applied by the voltage application unit, i) reading the input, ii) performing a NAND operation, and iii) reading the output can be performed accurately.

[0150] In FIG. 5a, the results are shown in the order that in each step of i) reading the input and iii) reading the output, the first voltage application unit (111) applies a pulse, then the second voltage application unit (112) applies a pulse, and then the second voltage application unit (112) applies a pulse, and then the reading voltage application unit (120) applies a pulse.

[0151] In addition, in step ii) of performing a NAND operation in FIG. 5a, the result is shown that the first voltage application unit (111) applying the first operation pulse and the second voltage application unit (112) applying the second operation pulse are performed simultaneously.

[0152] In addition, in step ii) of performing NAND operation in FIG. 5a, the result of making the magnitude and duration of the first operation pulse applied by the first voltage application unit (111) and the second operation pulse applied by the second voltage application unit (112) the same is shown.

[0153] In addition, in step ii) of performing a NAND operation in FIG. 5a, the result of the first voltage application unit (111) applying the first operation pulse or the second voltage application unit (112) applying the second operation pulse before the read voltage application unit (120) applies the read operation pulse is shown.

[0154] In particular, in the step of ii) performing a NAND operation, the reading voltage application unit (120) applying a reading operation pulse is performed after the first voltage application unit (111) applying a first operation pulse or the second voltage application unit (112) applying a second operation pulse, so the NAND operation can be performed accurately.

[0155] i) The magnitude of the input state judgment pulse applied during the input reading step and iii) the output state judgment pulse applied during the output reading step may be such that it does not change the state of the first memory element (131), the second memory element (132), and the read memory element (140). In other words, when the first memory element (131), the second memory element (132), or the read memory element (140) is in the N state, if an input state judgment pulse or an output state judgment pulse is applied to the first memory element (131), the second memory element (132), or the read memory element (140) during the input reading step and the output reading step, it may not change to the P state. Additionally, when the first memory element (131), the second memory element (132), or the read memory element (140) is in the P state, in the steps of i) reading the input and iii) reading the output, if an input state judgment pulse or an output state judgment pulse is applied to the first memory element (131), the second memory element (132), or the read memory element (140), it may not change to the N state.

[0156] In the case of FIG. 5a, 1 to 4 can illustrate how much current flows in each of the first memory element (131), the second memory element (132), and the read memory element (140) when a pulse is input by the first voltage application unit (111), the second voltage application unit (112), and the read voltage application unit (120) in each of the steps of i) reading the input, ii) performing a NAND operation, and iii) reading the output. In particular, the horizontal axis of the graph in cases 1 to 4 and the horizontal axis of the pulse application signal are displayed with the same scale. Therefore, it is possible to determine in a time series what kind of current flow each of cases 1 to 4 has according to the pulse application signal.

[0157] In the case of FIG. 5a, the size of the external resistor (150) may be relatively small. In other words, the size of the external resistor (150) is smaller than the resistance value to be compared (for example, the size of the external resistor (150) is 400Ω), so that the first memory element (131), the second memory element (132), and the read memory element (140) have PN characteristics. Accordingly, the threshold voltage when each of the first memory element (131), the second memory element (132), and the read memory element (140) is in the N state is greater than the threshold voltage when it is in the P state.

[0158] In case 1, i) in the step of reading the input, the first memory element (131), the second memory element (132), and the read memory element (140) may be in an N state. Even if an input state determination pulse is applied to the first memory element (131), the second memory element (132), and the read memory element (140), no current may flow.

[0159] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0160] ii) In the step of performing a NAND operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0161] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Additionally, even if a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132).

[0162] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than or equal to the threshold voltage may be applied to the read memory element (140). More specifically, a voltage equal to the magnitude of the read operation pulse may be applied to the read memory element (140), and the voltage equal to this difference may be greater than the threshold voltage. Therefore, current may flow through the read memory element (140).

[0163] In this case, the read memory element (140) can be changed to a P state after performing a NAND operation. As the read memory element (140) changes from an N state to a P state, the read memory element (140) can be in a switched-on state.

[0164] iii) In the step of reading the output, the first memory element (131) may be in an N state, the second memory element (132) may be in an N state, and the read memory element (140) may be in a P state. Even if an output state determination pulse is applied to the first memory element (131), no current may flow. Even if an output state determination pulse is applied to the second memory element (132), no current may flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0165] In conclusion, in case 1, when the state of the first memory element (131) before the operation is 0 and the state of the second memory element (132) is 0, a NAND operation can be implemented in which the state of the output memory element is 1 as a result of performing the NAND operation.

[0166] In case 2, i) in the step of reading the input, the first memory element (131) may be in the N state, the second memory element (132) may be in the P state, and the read memory element (140) may be in the N state. Even if an input state determination pulse is applied to the first memory element (131), no current may flow. When an input state determination pulse is applied to the second memory element (132), current may flow. Even if an input state determination pulse is applied to the read memory element (140), no current may flow.

[0167] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may flow in the second memory element (132). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0168] ii) In the step of performing a NAND operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0169] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Additionally, when a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may flow in the second memory element (132).

[0170] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage may be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the second operation pulse may be applied to the read memory element (140), and this voltage equal to the difference may be greater than the threshold voltage. Accordingly, current may flow through the read memory element (140).

[0171] In this case, the read memory element (140) can change to a state after performing a NAND operation. The read memory element (140) changes from the N state to the P state, and the read memory element (140) can be in a switched-on state.

[0172] iii) In the step of reading the output, the first memory element (131) may be in the N state, the second memory element (132) may be in the P state, and the read memory element (140) may be in the P state. Even if an output state determination pulse is applied to the first memory element (131), no current may flow. When an output state determination pulse is applied to the second memory element (132), current may flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0173] In conclusion, in case 2, when the state of the first memory element (131) before the operation is 0 and the state of the second memory element (132) is 1, a NAND operation can be implemented in which the state of the output memory element is 1 as a result of performing the NAND operation.

[0174] In case 3, i) in the step of reading the input, the first memory element (131) may be in a P state, the second memory element (132) may be in an N state, and the read memory element (140) may be in an N state. When an input state determination pulse is applied to the first memory element (131), current may flow. Even when an input state determination pulse is applied to the second memory element (132), current may not flow. Even when an input state determination pulse is applied to the read memory element (140), current may not flow.

[0175] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0176] ii) In the step of performing a NAND operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0177] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may flow in the first memory element (131). Additionally, even if a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132).

[0178] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage may be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the first operation pulse may be applied to the read memory element (140), and this voltage equal to the difference may be greater than the threshold voltage. Accordingly, current may flow through the read memory element (140).

[0179] In this case, the read memory element (140) can be changed to a P state after performing a NAND operation. As the read memory element (140) changes from an N state to a P state, the read memory element (140) can be in a switched-on state.

[0180] iii) In the step of reading the output, the first memory element (131) may be in a P state, the second memory element (132) may be in an N state, and the read memory element (140) may be in a P state. When an output state determination pulse is applied to the first memory element (131), current may flow. Even when an output state determination pulse is applied to the second memory element (132), current may not flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0181] In conclusion, in case 3, when the state of the first memory element (131) before the operation is 1 and the state of the second memory element (132) is 0, a NAND operation can be implemented in which the state of the output memory element is 1 as a result of performing the NAND operation.

[0182] In case 4, i) in the step of reading the input, the first memory element (131) may be in a P state, the second memory element (132) may be in a P state, and the read memory element (140) may be in an N state. When an input state determination pulse is applied to the first memory element (131), current may flow. When an input state determination pulse is applied to the second memory element (132), current may flow. Even when an input state determination pulse is applied to the read memory element (140), current may not flow.

[0183] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current can flow in the second memory element (132). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0184] ii) In the step of performing a NAND operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0185] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Additionally, when a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current can flow in the second memory element (132).

[0186] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage cannot be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the first operation pulse and the second operation pulse can be applied to the read memory element (140), and this voltage equal to the difference can be less than or equal to the threshold voltage. Therefore, current may not flow through the read memory element (140).

[0187] In this case, the read memory element (140) can be maintained in an N state even after performing a NAND operation. The read memory element (140) can be maintained in a switched-off state.

[0188] iii) In the step of reading the output, the first memory element (131) may be in a P state, the second memory element (132) may be in a P state, and the read memory element (140) may be in an N state. When an output state determination pulse is applied to the first memory element (131), current may flow. When an output state determination pulse is applied to the second memory element (132), current may flow. Even when an output state determination pulse is applied to the read memory element (140), current may not flow.

[0189] In conclusion, in case 4, when the state of the first memory element (131) before the operation is 1 and the state of the second memory element (132) is 1, a NAND operation can be implemented in which the state of the output memory element is 0 as a result of performing the NAND operation.

[0190] FIG. 6a is a diagram illustrating a logical operation method according to some embodiments of the present invention. FIG. 6b is a truth table of a NOR operation.

[0191] Referring to FIGS. 4, 6a, and 6b, the logic operation circuit can be configured such that the first memory element (131), the second memory element (132), and the read memory element (140) are determined to have PN characteristics by an external resistor (150), and the read memory element (140) is set to an N state to perform a NOR operation. In other words, if the size of the external resistor (150) is relatively small so that the first memory element (131) and the read memory element (140) have PN characteristics, and the read memory element (140) is initially set to an N state (i.e., before performing the NOR operation), the logic operation circuit can perform a NOR operation.

[0192] The NOR operation can be a logical operation that means "true only when neither A nor B." In other words, the NOR operation can be a logical operation where the output is 1 only when all input values ​​are 0, and the output is 0 in all other cases. Therefore, the truth table of the NOR operation can be represented as shown in FIG. 6b.

[0193] It can be confirmed through Fig. 6a that the logic operation circuit performs a NOR operation.

[0194] Confirming that the logic operation circuit performs a NOR operation can be done by i) reading the input, ii) performing a NOR operation, and iii) reading the output of the logic operation circuit of FIG. 4. Reading the input, ii) performing a NOR operation, and iii) reading the output of the logic operation circuit of FIG. 4 can be done by applying a pulse, and the shape of the pulse applied to perform each step may be as shown in the pulse application signal graph of FIG. 6a.

[0195] In each of the steps of i) reading the input, ii) performing a NOR operation, and iii) reading the output, the first voltage application unit (111) inputs a pulse to the first memory element (131), the second voltage application unit (112) inputs a pulse to the second memory element (132), and the reading voltage application unit (120) inputs a pulse to the reading memory element (140).

[0196] In each step of i) reading the input, ii) performing a NOR operation, and iii) reading the output, the reading voltage application unit (120) applying a pulse may be performed after the first voltage application unit (111) applying a pulse or the second voltage application unit (112) applying a pulse. Since the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112) is applied before the pulse applied by the reading voltage application unit (120), the pulse applied by the reading voltage application unit (120) may be applied after determining how much current flows in each of the first memory element (131) or the second memory element (132) by the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112). Accordingly, the amount of current flowing through the reading memory element (140) can be accurately determined by the pulse applied by the reading voltage application unit (120). In conclusion, by applying the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112) before the pulse applied by the voltage application unit, i) reading the input, ii) performing a NOR operation, and iii) reading the output can be performed accurately.

[0197] In FIG. 6a, the results are shown in the order that in each step of i) reading the input and iii) reading the output, the first voltage application unit (111) applies a pulse, then the second voltage application unit (112) applies a pulse, and then the second voltage application unit (112) applies a pulse, and then the reading voltage application unit (120) applies a pulse.

[0198] In addition, in step ii) of performing NOR operation in FIG. 6a, the result is shown that the first voltage application unit (111) applying the first operation pulse and the second voltage application unit (112) applying the second operation pulse are performed simultaneously.

[0199] In addition, in step ii) of performing NOR operation in FIG. 6a, the result of making the magnitude and duration of the first operation pulse applied by the first voltage application unit (111) and the second operation pulse applied by the second voltage application unit (112) the same is shown.

[0200] In addition, in step ii) of performing NOR operation in FIG. 6a, the result of the first voltage application unit (111) applying the first operation pulse or the second voltage application unit (112) applying the second operation pulse before the read voltage application unit (120) applies the read operation pulse is shown.

[0201] In particular, in the step of ii) performing a NOR operation, the reading voltage application unit (120) applying a reading operation pulse is performed after the first voltage application unit (111) applying a first operation pulse or the second voltage application unit (112) applying a second operation pulse, so the NOR operation can be performed accurately.

[0202] i) The magnitude of the input state judgment pulse applied during the input reading step and iii) the output state judgment pulse applied during the output reading step may be such that it does not change the state of the first memory element (131), the second memory element (132), and the read memory element (140). In other words, when the first memory element (131), the second memory element (132), or the read memory element (140) is in the N state, if an input state judgment pulse or an output state judgment pulse is applied to the first memory element (131), the second memory element (132), or the read memory element (140) during the input reading step and the output reading step, it may not change to the P state. Additionally, when the first memory element (131), the second memory element (132), or the read memory element (140) is in the P state, in the steps of i) reading the input and iii) reading the output, if an input state judgment pulse or an output state judgment pulse is applied to the first memory element (131), the second memory element (132), or the read memory element (140), it may not change to the N state.

[0203] In the case of FIG. 6a, cases 1 to 4 can illustrate how much current flows in each of the first memory element (131), the second memory element (132), and the read memory element (140) when a pulse is input by the first voltage application unit (111), the second voltage application unit (112), and the read voltage application unit (120) in each of the steps of i) reading the input, ii) performing a NOR operation, and iii) reading the output. In particular, the horizontal axis of the graph in cases 1 to 4 and the horizontal axis of the pulse application signal are displayed with the same scale. Therefore, it is possible to determine in a time series what kind of current flow each of cases 1 to 4 has according to the pulse application signal.

[0204] In the case of FIG. 6a, the size of the external resistor (150) may be relatively small. In other words, the size of the external resistor (150) is smaller than the resistance value to be compared (for example, the size of the external resistor (150) is 400Ω), so that the first memory element (131), the second memory element (132), and the read memory element (140) have PN characteristics. Accordingly, the threshold voltage when each of the first memory element (131), the second memory element (132), and the read memory element (140) is in the N state is greater than the threshold voltage when it is in the P state.

[0205] In case 1, i) in the step of reading the input, the first memory element (131), the second memory element (132), and the read memory element (140) may be in an N state. Even if an input state determination pulse is applied to the first memory element (131), the second memory element (132), and the read memory element (140), no current may flow.

[0206] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0207] ii) In the step of performing a NOR operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0208] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Additionally, even if a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132).

[0209] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than or equal to the threshold voltage may be applied to the read memory element (140). More specifically, a voltage equal to the magnitude of the read operation pulse may be applied to the read memory element (140), and the voltage equal to this difference may be greater than the threshold voltage. Therefore, current may flow through the read memory element (140).

[0210] In this case, the read memory element (140) can be changed to a P state after performing a NOR operation. As the read memory element (140) changes from the N state to the P state, the read memory element (140) can be in a switched-on state.

[0211] iii) In the step of reading the output, the first memory element (131) may be in an N state, the second memory element (132) may be in an N state, and the read memory element (140) may be in a P state. Even if an output state determination pulse is applied to the first memory element (131), no current may flow. Even if an output state determination pulse is applied to the second memory element (132), no current may flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0212] In conclusion, in case 1, when the state of the first memory element (131) before the operation is 0 and the state of the second memory element (132) is 0, a NOR operation can be implemented in which the state of the output memory element is 1 as a result of performing the NOR operation.

[0213] In case 2, i) in the step of reading the input, the first memory element (131) may be in the N state, the second memory element (132) may be in the P state, and the read memory element (140) may be in the N state. Even if an input state determination pulse is applied to the first memory element (131), no current may flow. When an input state determination pulse is applied to the second memory element (132), current may flow. Even if an input state determination pulse is applied to the read memory element (140), no current may flow.

[0214] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may flow in the second memory element (132). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0215] ii) In the step of performing a NOR operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0216] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Additionally, when a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may flow in the second memory element (132).

[0217] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage cannot be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the second operation pulse can be applied to the read memory element (140), and this voltage equal to the difference can be less than or equal to the threshold voltage. Therefore, current may not flow through the read memory element (140).

[0218] In this case, the read memory element (140) can be maintained in an N state even after performing a NOR operation. The read memory element (140) can be maintained in a switched-off state.

[0219] iii) In the step of reading the output, the first memory element (131) may be in the N state, the second memory element (132) may be in the P state, and the read memory element (140) may be in the N state. Even if an output state determination pulse is applied to the first memory element (131), no current may flow. When an output state determination pulse is applied to the second memory element (132), current may flow. Even if an output state determination pulse is applied to the read memory element (140), no current may flow.

[0220] In conclusion, in case 2, when the state of the first memory element (131) before the operation is 0 and the state of the second memory element (132) is 1, a NOR operation can be implemented in which the state of the output memory element is 0 as a result of performing the NOR operation.

[0221] In case 3, i) in the step of reading the input, the first memory element (131) may be in a P state, the second memory element (132) may be in an N state, and the read memory element (140) may be in an N state. When an input state determination pulse is applied to the first memory element (131), current may flow. Even when an input state determination pulse is applied to the second memory element (132), current may not flow. Even when an input state determination pulse is applied to the read memory element (140), current may not flow.

[0222] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0223] ii) In the step of performing a NOR operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0224] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may flow in the first memory element (131). Additionally, even if a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132).

[0225] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage cannot be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the first operation pulse can be applied to the read memory element (140), and this voltage equal to the difference can be less than or equal to the threshold voltage. Therefore, current may not flow through the read memory element (140).

[0226] In this case, the read memory element (140) can be maintained in an N state even after performing a NOR operation. The read memory element (140) can be maintained in a switched-off state.

[0227] iii) In the step of reading the output, the first memory element (131) may be in a P state, the second memory element (132) may be in an N state, and the read memory element (140) may be in an N state. When an output state determination pulse is applied to the first memory element (131), current may flow. Even when an output state determination pulse is applied to the second memory element (132), current may not flow. Even when an output state determination pulse is applied to the read memory element (140), current may not flow.

[0228] In conclusion, in case 3, when the state of the first memory element (131) before the operation is 1 and the state of the second memory element (132) is 0, a NOR operation can be implemented in which the state of the output memory element is 0 as a result of performing the NOR operation.

[0229] In case 4, i) in the step of reading the input, the first memory element (131) may be in a P state, the second memory element (132) may be in a P state, and the read memory element (140) may be in an N state. When an input state determination pulse is applied to the first memory element (131), current may flow. When an input state determination pulse is applied to the second memory element (132), current may flow. Even when an input state determination pulse is applied to the read memory element (140), current may not flow.

[0230] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current can flow in the second memory element (132). Subsequently, even if an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may not flow in the read memory element (140).

[0231] ii) In the step of performing a NOR operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0232] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Additionally, when a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current can flow in the second memory element (132).

[0233] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a voltage greater than the threshold voltage cannot be applied to the read memory element (140). More specifically, a voltage equal to the difference between the magnitude of the read operation pulse and the magnitude of the voltage of the reference node (A) by the first operation pulse and the second operation pulse can be applied to the read memory element (140), and this voltage equal to the difference can be less than or equal to the threshold voltage. Therefore, current may not flow through the read memory element (140).

[0234] In this case, the read memory element (140) can be maintained in an N state even after performing a NOR operation. The read memory element (140) can be maintained in a switched-off state.

[0235] iii) In the step of reading the output, the first memory element (131) may be in a P state, the second memory element (132) may be in a P state, and the read memory element (140) may be in an N state. When an output state determination pulse is applied to the first memory element (131), current may flow. When an output state determination pulse is applied to the second memory element (132), current may flow. Even when an output state determination pulse is applied to the read memory element (140), current may not flow.

[0236] In conclusion, in case 4, when the state of the first memory element (131) before the operation is 1 and the state of the second memory element (132) is 1, a NOR operation can be implemented in which the state of the output memory element is 0 as a result of performing the NOR operation.

[0237] FIG. 7a is a diagram illustrating a logical operation method according to some embodiments of the present invention. FIG. 7b is a truth table of an AND operation.

[0238] Referring to FIGS. 4, 7a, and 7b, the logic operation circuit can be configured such that the first memory element (131), the second memory element (132), and the read memory element (140) are determined to have NP characteristics by an external resistor (150), and the read memory element (140) is set to an N state to perform an AND operation. In other words, if the size of the external resistor (150) is relatively large so that the first memory element (131) and the read memory element (140) have NP characteristics, and the read memory element (140) is initially set to an N state (i.e., before performing the AND operation), an AND operation can be performed through the logic operation circuit.

[0239] The AND operation can be a logical operation meaning "true only when both A and B are true." In other words, the AND operation can be a logical operation where the output value is 1 only when both input values ​​are 1, and the output value is 0 in all other cases. Therefore, the truth table for the AND operation can be represented as shown in FIG. 7b.

[0240] It can be confirmed through Fig. 7a that the logic operation circuit performs an AND operation.

[0241] Confirming that the logic operation circuit performs an AND operation can be done by reading i) the input, ii) performing an AND operation, and iii) reading the output of the logic operation circuit of FIG. 4. Reading i) the input, ii) performing an AND operation, and iii) reading the output of the logic operation circuit of FIG. 4 can be done by applying a pulse, and the shape of the pulse applied to perform each step may be as shown in the pulse application signal graph of FIG. 7a.

[0242] In each of the steps of i) reading the input, ii) performing an AND operation, and iii) reading the output, the first voltage application unit (111) inputs a pulse to the first memory element (131), the second voltage application unit (112) inputs a pulse to the second memory element (132), and the reading voltage application unit (120) inputs a pulse to the reading memory element (140).

[0243] In each step of i) reading the input, ii) performing an AND operation, and iii) reading the output, the reading voltage application unit (120) applying a pulse may be performed after the first voltage application unit (111) applying a pulse or the second voltage application unit (112) applying a pulse. Since the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112) is applied before the pulse applied by the reading voltage application unit (120), the pulse applied by the reading voltage application unit (120) may be applied after determining how much current flows in each of the first memory element (131) or the second memory element (132) by the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112). Accordingly, the amount of current flowing through the reading memory element (140) can be accurately determined by the pulse applied by the reading voltage application unit (120). In conclusion, by applying the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112) before the pulse applied by the voltage application unit, i) reading the input, ii) performing an AND operation, and iii) reading the output can be performed accurately.

[0244] In FIG. 7a, the results are shown in the order that in each step of i) reading the input and iii) reading the output, the first voltage application unit (111) applies a pulse, then the second voltage application unit (112) applies a pulse, and then the second voltage application unit (112) applies a pulse, and then the reading voltage application unit (120) applies a pulse.

[0245] In addition, in step ii) of performing the AND operation in FIG. 7a, the result is shown that the first voltage application unit (111) applying the first operation pulse and the second voltage application unit (112) applying the second operation pulse are performed simultaneously.

[0246] In addition, in step ii) of performing the AND operation in FIG. 7a, the result of making the magnitude and duration of the first operation pulse applied by the first voltage application unit (111) and the second operation pulse applied by the second voltage application unit (112) the same is shown.

[0247] Additionally, in step ii) of performing the AND operation in FIG. 7a, the result of the first voltage application unit (111) applying the first operation pulse or the second voltage application unit (112) applying the second operation pulse before the read voltage application unit (120) applies the read operation pulse is shown.

[0248] In particular, in the step of ii) performing an AND operation, the reading voltage application unit (120) applying a reading operation pulse is performed after the first voltage application unit (111) applying a first operation pulse or the second voltage application unit (112) applying a second operation pulse, so the AND operation can be performed accurately.

[0249] i) The magnitude of the input state judgment pulse applied during the input reading step and iii) the output state judgment pulse applied during the output reading step may be such that it does not change the state of the first memory element (131), the second memory element (132), and the read memory element (140). In other words, when the first memory element (131), the second memory element (132), or the read memory element (140) is in the N state, if an input state judgment pulse or an output state judgment pulse is applied to the first memory element (131), the second memory element (132), or the read memory element (140) during the input reading step and the output reading step, it may not change to the P state. Additionally, when the first memory element (131), the second memory element (132), or the read memory element (140) is in the P state, in the steps of i) reading the input and iii) reading the output, if an input state judgment pulse or an output state judgment pulse is applied to the first memory element (131), the second memory element (132), or the read memory element (140), it may not change to the N state.

[0250] In the case of FIG. 7a, 1 to 4 can illustrate how much current flows in each of the first memory element (131), the second memory element (132), and the read memory element (140) when a pulse is input by the first voltage application unit (111), the second voltage application unit (112), and the read voltage application unit (120) in each of the steps of i) reading the input, ii) performing an AND operation, and iii) reading the output. In particular, the horizontal axis of the graph in cases 1 to 4 and the horizontal axis of the pulse application signal are displayed with the same scale. Therefore, it is possible to determine in a time series what kind of current flow each of cases 1 to 4 has according to the pulse application signal.

[0251] In the case of FIG. 7a, the size of the external resistor (150) may be relatively large. In other words, the size of the external resistor (150) is larger than the resistance value to be compared (for example, the size of the external resistor (150) is 10 kΩ), so that the first memory element (131), the second memory element (132), and the read memory element (140) have NP characteristics. Therefore, the threshold voltage when each of the first memory element (131), the second memory element (132), and the read memory element (140) is in the P state is greater than the threshold voltage when it is in the N state.

[0252] In case 1, i) in the step of reading the input, the first memory element (131) and the second memory element (132) may be in a P state. The read memory element (140) may be in an N state. Even if an input state determination pulse is applied to the first memory element (131) and the second memory element (132), current may not flow. When an input state determination pulse is applied to the read memory element (140), current may flow.

[0253] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may flow in the read memory element (140).

[0254] ii) In the step of performing an AND operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0255] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Additionally, even if a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132).

[0256] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a reverse avalence phenomenon may occur. In other words, the charge accumulated in the trap of the read memory element (140) may be released, and a reverse current may be generated. As time passes, the amount of released charge decreases, and the magnitude of the current may also decrease. When all the charge is released, the trap of the read memory element (140) becomes empty, and the path through which current can flow may be cut off. Therefore, the threshold voltage of the read voltage application unit (120) may be increased.

[0257] In this case, the read memory element (140) may change to a P state after performing an AND operation. As the read memory element (140) changes from an N state to a P state, the read memory element (140) may be in a switched-off state.

[0258] iii) In the step of reading the output, the first memory element (131) may be in a P state, the second memory element (132) may be in a P state, and the read memory element (140) may be in a P state. Even if an output state determination pulse is applied to the first memory element (131), no current may flow. Even if an output state determination pulse is applied to the second memory element (132), no current may flow. Even if an output state determination pulse is applied to the read memory element (140), no current may flow.

[0259] In conclusion, in case 1, when the state of the first memory element (131) before the operation is 0 and the state of the second memory element (132) is 0, an AND operation can be implemented in which the state of the output memory element is 0 as a result of performing the AND operation.

[0260] In case 2, i) in the step of reading the input, the first memory element (131) may be in a P state. The second memory element (132) and the read memory element (140) may be in an N state. Even if an input state determination pulse is applied to the first memory element (131), no current may flow. When an input state determination pulse is applied to the second memory element (132) and the read memory element (140), current may flow.

[0261] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may flow in the second memory element (132). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may flow in the read memory element (140).

[0262] ii) In the step of performing an AND operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0263] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Additionally, when a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may flow in the second memory element (132).

[0264] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a reverse avalence phenomenon may occur. In other words, the charge accumulated in the trap of the read memory element (140) may be released, and a reverse current may be generated. As time passes, the amount of released charge decreases, and the magnitude of the current may also decrease. When all the charge is released, the trap of the read memory element (140) becomes empty, and the path through which current can flow may be cut off. Therefore, the threshold voltage of the read voltage application unit (120) may be increased.

[0265] In this case, the read memory element (140) may change to a P state after performing an AND operation. As the read memory element (140) changes from an N state to a P state, the read memory element (140) may be in a switched-off state.

[0266] iii) In the step of reading the output, the first memory element (131) may be in a P state, the second memory element (132) may be in an N state, and the read memory element (140) may be in a P state. Even if an output state determination pulse is applied to the first memory element (131), no current may flow. When an output state determination pulse is applied to the second memory element (132), current may flow. Even if an output state determination pulse is applied to the read memory element (140), no current may flow.

[0267] In conclusion, in case 2, when the state of the first memory element (131) before the operation is 0 and the state of the second memory element (132) is 1, an AND operation can be implemented in which the state of the output memory element is 0 as a result of performing the AND operation.

[0268] In case 3, i) in the step of reading the input, the first memory element (131) may be in an N state. The second memory element (132) and the read memory element (140) may be in a P state. When an input state determination pulse is applied to the first memory element (131) and the read memory element (140), current may flow. Even when an input state determination pulse is applied to the second memory element (132), current may not flow.

[0269] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may flow in the read memory element (140).

[0270] ii) In the step of performing an AND operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0271] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may flow in the first memory element (131). Additionally, even if a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132).

[0272] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a reverse avalence phenomenon may occur. In other words, the charge accumulated in the trap of the read memory element (140) may be released, and a reverse current may be generated. As time passes, the amount of released charge decreases, and the magnitude of the current may also decrease. When all the charge is released, the trap of the read memory element (140) becomes empty, and the path through which current can flow may be cut off. Therefore, the threshold voltage of the read voltage application unit (120) may be increased.

[0273] In this case, the read memory element (140) may change to a P state after performing an AND operation. As the read memory element (140) changes from an N state to a P state, the read memory element (140) may be in a switched-off state.

[0274] iii) In the step of reading the output, the first memory element (131) may be in the N state, the second memory element (132) may be in the P state, and the read memory element (140) may be in the P state. When an output state determination pulse is applied to the first memory element (131), current may flow. Even when an output state determination pulse is applied to the second memory element (132), current may not flow. Even when an output state determination pulse is applied to the read memory element (140), current may not flow.

[0275] In conclusion, in case 3, when the state of the first memory element (131) before the operation is 1 and the state of the second memory element (132) is 0, an AND operation can be implemented in which the state of the output memory element is 0 as a result of performing the AND operation.

[0276] In case 4, i) in the step of reading the input, the first memory element (131), the second memory element (132), and the read memory element (140) may be in an N state. When an input state determination pulse is applied to the first memory element (131), the second memory element (132), and the read memory element (140), current may flow.

[0277] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current can flow in the second memory element (132). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current can flow in the read memory element (140).

[0278] ii) In the step of performing an AND operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0279] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Additionally, when a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current can flow in the second memory element (132).

[0280] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), the charge accumulated in the trap of the read memory element (140) may not be completely discharged. As time passes, the amount of discharged charge decreases, and the magnitude of the current may also decrease. When all the charge is discharged, the trap of the read memory element (140) is not in an empty state, so a path through which current can flow may still exist. Therefore, the threshold voltage of the read voltage application unit (120) may not increase significantly.

[0281] In this case, the read memory element (140) can be maintained in the N state even after performing an AND operation. The read memory element (140) can be maintained in the switch-on state.

[0282] iii) In the step of reading the output, the first memory element (131) may be in an N state, the second memory element (132) may be in an N state, and the read memory element (140) may be in an N state. When an output state determination pulse is applied to the first memory element (131), current may flow. When an output state determination pulse is applied to the second memory element (132), current may flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0283] In conclusion, in case 4, when the state of the first memory element (131) before the operation is 1 and the state of the second memory element (132) is 1, an AND operation can be implemented in which the state of the output memory element is 1 as a result of performing the AND operation.

[0284] FIG. 8a is a diagram illustrating a logical operation method according to some embodiments of the present invention. FIG. 8b is a truth table of an OR operation.

[0285] Referring to FIGS. 4, FIGS. 8a, and FIGS. 8b, the logic operation circuit can be configured such that the first memory element (131), the second memory element (132), and the read memory element (140) are determined to have NP characteristics by an external resistor (150), and the read memory element (140) is set to an N state to perform an OR operation. In other words, if the size of the external resistor (150) is relatively large so that the first memory element (131) and the read memory element (140) have NP characteristics, and the read memory element (140) is initially set to an N state (i.e., before performing the OR operation), the OR operation can be performed through the logic operation circuit.

[0286] The OR operation can be a logical operation meaning "if either condition A or B is true, the result is true." In other words, the OR operation can be a logical operation where the output is 0 only when both input values ​​are 0, and the output is 1 in all other cases. Therefore, the truth table for the OR operation can be represented as shown in FIG. 8b.

[0287] It can be confirmed through Fig. 8a that the logic operation circuit performs an OR operation.

[0288] Confirming that the logic operation circuit performs an OR operation can be done by reading i) the input, ii) performing an OR operation, and iii) reading the output of the logic operation circuit of FIG. 4. Reading i) the input, ii) performing an OR operation, and iii) reading the output of the logic operation circuit of FIG. 4 can be done by applying a pulse, and the shape of the pulse applied to perform each step may be as shown in the pulse application signal graph of FIG. 8a.

[0289] In each step of i) reading the input, ii) performing an OR operation, and iii) reading the output, the first voltage application unit (111) inputs a pulse to the first memory element (131), the second voltage application unit (112) inputs a pulse to the second memory element (132), and the reading voltage application unit (120) inputs a pulse to the reading memory element (140).

[0290] In each step of i) reading the input, ii) performing an OR operation, and iii) reading the output, the reading voltage application unit (120) applying a pulse may be performed after the first voltage application unit (111) applying a pulse or the second voltage application unit (112) applying a pulse. Since the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112) is applied before the pulse applied by the reading voltage application unit (120), the pulse applied by the reading voltage application unit (120) may be applied after determining how much current flows in each of the first memory element (131) or the second memory element (132) by the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112). Accordingly, the amount of current flowing through the reading memory element (140) can be accurately determined by the pulse applied by the reading voltage application unit (120). In conclusion, by applying the pulse applied by the first voltage application unit (111) or the pulse applied by the second voltage application unit (112) before the pulse applied by the voltage application unit, i) reading the input, ii) performing an OR operation, and iii) reading the output can be performed accurately.

[0291] In FIG. 8a, the results are shown in the order that in each step of i) reading the input and iii) reading the output, the first voltage application unit (111) applies a pulse, then the second voltage application unit (112) applies a pulse, and then the second voltage application unit (112) applies a pulse, and then the reading voltage application unit (120) applies a pulse.

[0292] In addition, in step ii) of performing the OR operation in FIG. 8a, the result is shown that the first voltage application unit (111) applying the first operation pulse and the second voltage application unit (112) applying the second operation pulse are performed simultaneously.

[0293] In addition, in step ii) of performing the OR operation in FIG. 8a, the result of making the magnitude and duration of the first operation pulse applied by the first voltage application unit (111) and the second operation pulse applied by the second voltage application unit (112) the same is shown.

[0294] In addition, in step ii) of performing the OR operation in FIG. 8a, the result of the first voltage application unit (111) applying the first operation pulse or the second voltage application unit (112) applying the second operation pulse before the read voltage application unit (120) applies the read operation pulse is shown.

[0295] In particular, in the step of performing ii) OR operation, the reading voltage application unit (120) applying the reading operation pulse is performed after the first voltage application unit (111) applying the first operation pulse or the second voltage application unit (112) applying the second operation pulse, so the OR operation can be performed accurately.

[0296] i) The magnitude of the input state judgment pulse applied during the input reading step and iii) the output state judgment pulse applied during the output reading step may be such that it does not change the state of the first memory element (131), the second memory element (132), and the read memory element (140). In other words, when the first memory element (131), the second memory element (132), or the read memory element (140) is in the N state, if an input state judgment pulse or an output state judgment pulse is applied to the first memory element (131), the second memory element (132), or the read memory element (140) during the input reading step and the output reading step, it may not change to the P state. Additionally, when the first memory element (131), the second memory element (132), or the read memory element (140) is in the P state, in the steps of i) reading the input and iii) reading the output, if an input state judgment pulse or an output state judgment pulse is applied to the first memory element (131), the second memory element (132), or the read memory element (140), it may not change to the N state.

[0297] In the case of FIG. 8a, 1 to 4 can illustrate how much current flows in each of the first memory element (131), the second memory element (132), and the read memory element (140) when a pulse is input by the first voltage application unit (111), the second voltage application unit (112), and the read voltage application unit (120) in each of the steps of i) reading the input, ii) performing an OR operation, and iii) reading the output. In particular, the horizontal axis of the graph in cases 1 to 4 and the horizontal axis of the pulse application signal are displayed with the same scale. Therefore, it is possible to determine in a time series what kind of current flow each of cases 1 to 4 has according to the pulse application signal.

[0298] In the case of FIG. 8a, the size of the external resistor (150) may be relatively large. In other words, the size of the external resistor (150) is larger than the resistance value to be compared (for example, the size of the external resistor (150) is 10 kΩ), so that the first memory element (131), the second memory element (132), and the read memory element (140) have NP characteristics. Therefore, the threshold voltage when each of the first memory element (131), the second memory element (132), and the read memory element (140) is in the P state is greater than the threshold voltage when it is in the N state.

[0299] In case 1, i) in the step of reading the input, the first memory element (131) and the second memory element (132) may be in a P state. The read memory element (140) may be in an N state. Even if an input state determination pulse is applied to the first memory element (131) and the second memory element (132), current may not flow. When an input state determination pulse is applied to the read memory element (140), current may flow.

[0300] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may flow in the read memory element (140).

[0301] ii) In the step of performing an OR operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0302] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Additionally, even if a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132).

[0303] When a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), a reverse avalence phenomenon may occur. In other words, the charge accumulated in the trap of the read memory element (140) may be released, and a reverse current may be generated. As time passes, the amount of released charge decreases, and the magnitude of the current may also decrease. When all the charge is released, the trap of the read memory element (140) becomes empty, and the path through which current can flow may be cut off. Therefore, the threshold voltage of the read voltage application unit (120) may be increased.

[0304] In this case, the read memory element (140) may change to a P state after performing an OR operation. As the read memory element (140) changes from an N state to a P state, the read memory element (140) may be in a switched-off state.

[0305] iii) In the step of reading the output, the first memory element (131) may be in a P state, the second memory element (132) may be in a P state, and the read memory element (140) may be in a P state. Even if an output state determination pulse is applied to the first memory element (131), no current may flow. Even if an output state determination pulse is applied to the second memory element (132), no current may flow. Even if an output state determination pulse is applied to the read memory element (140), no current may flow.

[0306] In conclusion, in case 1, when the state of the first memory element (131) before the operation is 0 and the state of the second memory element (132) is 0, an OR operation can be implemented in which the state of the output memory element is 0 as a result of performing the OR operation.

[0307] In case 2, i) in the step of reading the input, the first memory element (131) may be in a P state. The second memory element (132) and the read memory element (140) may be in an N state. Even if an input state determination pulse is applied to the first memory element (131), no current may flow. When an input state determination pulse is applied to the second memory element (132) and the read memory element (140), current may flow.

[0308] In other words, even if an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may flow in the second memory element (132). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may flow in the read memory element (140).

[0309] ii) In the step of performing an OR operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0310] Even if a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may not flow in the first memory element (131). Additionally, when a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may flow in the second memory element (132).

[0311] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), the charge accumulated in the trap of the read memory element (140) may not be completely discharged. As time passes, the amount of discharged charge decreases, and the magnitude of the current may also decrease. When all the charge is discharged, the trap of the read memory element (140) is not in an empty state, so a path through which current can flow may still exist. Therefore, the threshold voltage of the read voltage application unit (120) may not increase significantly.

[0312] In this case, the read memory element (140) can be maintained in an N state even after performing an OR operation. The read memory element (140) can be maintained in a switched-on state.

[0313] iii) In the step of reading the output, the first memory element (131) may be in a P state, the second memory element (132) may be in an N state, and the read memory element (140) may be in an N state. Even if an output state determination pulse is applied to the first memory element (131), no current may flow. When an output state determination pulse is applied to the second memory element (132), current may flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0314] In conclusion, in case 2, when the state of the first memory element (131) before the operation is 0 and the state of the second memory element (132) is 1, an OR operation can be implemented in which the state of the output memory element is 1 as a result of performing the OR operation.

[0315] In case 3, i) in the step of reading the input, the first memory element (131) and the read memory element (140) may be in an N state. The second memory element (132) may be in a P state. When an input state determination pulse is applied to the first memory element (131) and the read memory element (140), current may flow. Even when an input state determination pulse is applied to the second memory element (132), current may not flow.

[0316] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current may flow in the first memory element (131). Subsequently, even if an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current may flow in the read memory element (140).

[0317] ii) In the step of performing an OR operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0318] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current may flow in the first memory element (131). Additionally, even if a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current may not flow in the second memory element (132).

[0319] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), the charge accumulated in the trap of the read memory element (140) may not be completely discharged. As time passes, the amount of discharged charge decreases, and the magnitude of the current may also decrease. When all the charge is discharged, the trap of the read memory element (140) is not in an empty state, so a path through which current can flow may still exist. Therefore, the threshold voltage of the read voltage application unit (120) may not increase significantly.

[0320] In this case, the read memory element (140) can be maintained in an N state even after performing an OR operation. The read memory element (140) can be maintained in a switched-on state.

[0321] iii) In the step of reading the output, the first memory element (131) may be in the N state, the second memory element (132) may be in the P state, and the read memory element (140) may be in the N state. When an output state determination pulse is applied to the first memory element (131), current may flow. Even when an output state determination pulse is applied to the second memory element (132), current may not flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0322] In conclusion, in case 3, when the state of the first memory element (131) before the operation is 1 and the state of the second memory element (132) is 0, an OR operation can be implemented in which the state of the output memory element is 1 as a result of performing the OR operation.

[0323] In case 4, i) in the step of reading the input, the first memory element (131), the second memory element (132), and the read memory element (140) may be in an N state. When an input state determination pulse is applied to the first memory element (131), the second memory element (132), and the read memory element (140), current may flow.

[0324] In other words, when an input state determination pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Subsequently, when an input state determination pulse is applied to the second memory element (132) by the second voltage application unit (112), current can flow in the second memory element (132). Subsequently, when an input state determination pulse is applied to the read memory element (140) by the read voltage application unit (120), current can flow in the read memory element (140).

[0325] ii) In the step of performing an OR operation, a first operation pulse may be applied to a first memory element (131) by a first voltage application unit (111). A second operation pulse may be applied to a second memory element (132) by a second voltage application unit (112). The application of the first operation pulse to the first memory element (131) by the first voltage application unit (111) and the application of the second operation pulse to the second memory element (132) by the second voltage application unit (112) may be performed simultaneously. Subsequently, while the first operation pulse and the second operation pulse are being applied, a read operation pulse may be applied to a read memory element (140) by a read voltage application unit (120).

[0326] When a first operation pulse is applied to the first memory element (131) by the first voltage application unit (111), current can flow in the first memory element (131). Additionally, when a second operation pulse is applied to the second memory element (132) by the second voltage application unit (112), current can flow in the second memory element (132).

[0327] Even if a read operation pulse is applied to the read memory element (140) by the read voltage application unit (120), the charge accumulated in the trap of the read memory element (140) may not be completely discharged. As time passes, the amount of discharged charge decreases, and the magnitude of the current may also decrease. When all the charge is discharged, the trap of the read memory element (140) is not in an empty state, so a path through which current can flow may still exist. Therefore, the threshold voltage of the read voltage application unit (120) may not increase significantly.

[0328] In this case, the read memory element (140) can be maintained in an N state even after performing an OR operation. The read memory element (140) can be maintained in a switched-on state.

[0329] iii) In the step of reading the output, the first memory element (131) may be in an N state, the second memory element (132) may be in an N state, and the read memory element (140) may be in an N state. When an output state determination pulse is applied to the first memory element (131), current may flow. When an output state determination pulse is applied to the second memory element (132), current may flow. When an output state determination pulse is applied to the read memory element (140), current may flow.

[0330] In conclusion, in case 4, an OR operation can be implemented in which the state of the output memory element is 1 as a result of performing an OR operation when the state of the first memory element (131) before the operation is 1 and the state of the second memory element (132) is 1.

[0331] Although the present invention has been described above with reference to the illustrated drawings, the present invention is not limited by the embodiments and drawings disclosed in this specification, and it is obvious that various modifications can be made by a person skilled in the art within the scope of the technical concept of the present invention. Furthermore, even if the effects of the configuration of the present invention were not explicitly described while explaining the embodiments of the present invention above, it is natural to acknowledge that the effects predictable by said configuration should also be recognized. Explanation of the symbols

[0332] 10: Voltage application section 20: Oscilloscope 30: Variable component 111: First voltage application unit 112: Second voltage application unit 120: Read voltage application unit 131: First memory element 132: Second memory element 140: Read memory element 150: External resistance A: Reference node N1: Node 1 N2: Node 2 R: Resistance part

Claims

Claim 1 A step of setting a first memory element sharing an external resistor and a reference node to either a P state or an N state; a step of setting a read memory element sharing the external resistor and the reference node to the P state or the N state; a step of a first voltage application unit applying a first operation pulse to the first memory element; A logical operation method comprising the step of applying a read operation pulse to the read memory element by a read voltage application unit, wherein the external resistor determines the first memory element and the read memory element to have either a PN characteristic or an NP characteristic, the P state is a state in which a positive pulse is applied to at least one of the first memory element and the read memory element, the N state is a state in which a negative pulse is applied to at least one of the first memory element and the read memory element, the PN characteristic is a characteristic in which the threshold voltage of the element when the element is in the P state is smaller than the threshold voltage of the element when the element is in the N state, and the NP characteristic is a characteristic in which the threshold voltage of the element when the element is in the N state is smaller than the threshold voltage of the element when the element is in the P state, and the element is either the first memory element or the read memory element. Claim 2 A logical operation method according to claim 1, wherein the step of applying the read operation pulse is performed after the step of applying the first operation pulse. Claim 3 delete Claim 4 A logical operation method according to claim 1, wherein at least one of the first memory element and the read memory element is a SOM element, and the SOM element has either the PN characteristic or the NP characteristic based on a resistance value to be compared. Claim 5 A step of setting a first memory element sharing an external resistor and a reference node to either a P state or an N state, and setting a second memory element sharing the external resistor and the reference node to either the P state or the N state; a step of setting a read memory element sharing the external resistor and the reference node to the P state or the N state; a step of a first voltage application unit applying a first operation pulse to the first memory element; a step of a second voltage application unit applying a second operation pulse to the second memory element; A logical operation method comprising the step of applying a read operation pulse to the read memory element by a read voltage application unit, wherein the external resistor determines the first memory element, the second memory element, and the read memory element as either a PN characteristic or an NP characteristic, the P state is a state in which a positive pulse is applied to at least one of the first memory element, the second memory element, and the read memory element, the N state is a state in which a negative pulse is applied to at least one of the first memory element, the second memory element, and the read memory element, the PN characteristic is a characteristic in which the threshold voltage of the element when the element is in the P state is smaller than the threshold voltage of the element when the element is in the N state, and the NP characteristic is a characteristic in which the threshold voltage of the element when the element is in the N state is smaller than the threshold voltage of the element when the element is in the P state, and the element is any one of the first memory element, the second memory element, and the read memory element. Claim 6 A logical operation method according to claim 5, wherein the step of applying the read operation pulse is performed after the step of applying the first operation pulse or the step of applying the second operation pulse. Claim 7 delete Claim 8 delete Claim 9 A logical operation method according to claim 5, wherein at least one of the first memory element, the second memory element, and the read memory element is a SOM element, and the SOM element has either the PN characteristic or the NP characteristic based on a resistance value to be compared. Claim 10 A first voltage application unit capable of applying a first operation pulse; a read voltage application unit capable of applying a read operation pulse; an external resistor with one end connected to a reference node and the other end grounded; a first memory element with one end connected to the reference node and the other end connected to the first voltage application unit; A logic operation circuit comprising a read memory element, wherein one end is connected to the reference node and the other end is connected to the read voltage application unit, wherein the first memory element and the read memory element are set to either a P state or an N state, and the external resistor determines the first memory element and the read memory element to have either a PN characteristic or an NP characteristic, wherein the P state is a state in which a positive pulse is applied to at least one of the first memory element and the read memory element, and the N state is a state in which a negative pulse is applied to at least one of the first memory element and the read memory element, and the PN characteristic is a characteristic in which the threshold voltage of the element when the element is in the P state is smaller than the threshold voltage of the element when the element is in the N state, and the NP characteristic is a characteristic in which the threshold voltage of the element when the element is in the N state is smaller than the threshold voltage of the element when the element is in the P state, and wherein the element is either the first memory element or the read memory element. Claim 11 In claim 10, a logic operation circuit in which the application of the above-mentioned read operation pulse is performed after the application of the above-mentioned first operation pulse. Claim 12 delete Claim 13 delete Claim 14 A logic operation circuit according to claim 10, further comprising an output measuring unit that detects the current of the reference node and reads the result of a logic operation. Claim 15 A first voltage application unit capable of applying a first operation pulse; a second voltage application unit capable of applying a second operation pulse; a read voltage application unit capable of applying a read operation pulse; an external resistor having one end connected to a reference node and the other end grounded; a first memory element having one end connected to the reference node and the other end connected to the first voltage application unit; a second memory element having one end connected to the reference node and the other end connected to the second voltage application unit; and includes a read memory element, one end of which is connected to the reference node and the other end of which is connected to the read voltage application unit, wherein the first memory element, the second memory element, and the read memory element are set to either a P state or an N state, and the external resistor determines the first memory element, the second memory element, and the read memory element to have either a PN characteristic or an NP characteristic, wherein the P state is a state in which a positive pulse is applied to at least one of the first memory element, the second memory element, and the read memory element, and the N state is a state in which a negative pulse is applied to at least one of the first memory element, the second memory element, and the read memory element, and the PN characteristic is a characteristic in which the threshold voltage of the element when the element is in the P state is smaller than the threshold voltage of the element when the element is in the N state, and the NP characteristic is a characteristic in which the threshold voltage of the element when the element is in the N state is smaller than the threshold voltage of the element when the element is in the P state, and the element includes the first memory element, the second memory element, and the A logic operation circuit that is one of the read memory elements. Claim 16 A logic operation circuit according to claim 15, wherein applying the read operation pulse is performed after applying the first operation pulse or applying the second operation pulse. Claim 17 delete Claim 18 delete Claim 19 In claim 15, at least one of the first memory element, the second memory element, and the read memory element is a SOM element, and the SOM element has either the PN characteristic or the NP characteristic based on a resistance value to be compared, a logic operation circuit. Claim 20 A logic operation circuit according to claim 15, further comprising an output measuring unit that detects the current of the reference node and reads the result of a logic operation.

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