Staircase structure in three-dimensional memory device and method for forming the same

Abstract

An embodiment of a three-dimensional memory device having a step structure and a method for forming the same is disclosed. In one example, the 3D memory device includes a memory array structure and a step structure. The step structure is located in the middle of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along the transverse direction. The step structure includes a plurality of steps extending along the transverse direction and a bridge structure in contact with the memory array structure. The plurality of steps includes steps on one or more dielectric pairs. The step includes a conductive portion electrically connected to the bridge structure and is electrically connected to the memory array structure through the bridge structure. Along a second transverse direction perpendicular to the transverse direction and away from the bridge structure, the width of the conductive portion decreases.

Description

Technology Field

[0001] The present disclosure relates to a three-dimensional (3D) memory device and a method for manufacturing the same. Background Technology

[0002] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar processes and manufacturing technologies become more difficult and costly. As a result, the memory density for planar memory cells approaches an upper limit.

[0003] A 3D memory architecture can overcome the density limitations of planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

[0004] In this specification, embodiments of a memory device having a 3D stepped structure and a method for forming the same are disclosed.

[0005] In one example, the 3D memory device includes a memory array structure and a step structure. The step structure is located in the middle of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along the transverse direction. The step structure includes a plurality of steps extending along the transverse direction and a bridge structure in contact with the first memory array structure and the second memory array structure. The plurality of steps includes steps on one or more dielectric pairs. The step includes a conductor portion that is on the upper surface of the step and is also in contact with the bridge structure and electrically connected to the bridge structure, and a dielectric portion that is at the same level as the conductor portion and is also in contact with the conductor portion. The step is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure. Along a second transverse direction perpendicular to the transverse direction and away from the bridge structure, the width of the conductor portion decreases.

[0006] In another example, the 3D memory device comprises a memory array structure and a landing structure in contact with the memory array structure. The landing structure comprises a plurality of landing regions at each depth extending along the transverse direction, and a bridge structure in contact with the memory array structure. Each of the plurality of landing regions comprises a conductive portion on each upper surface and a dielectric portion at the same level as the conductive portion and in contact with the conductive portion. The conductive portion is electrically connected to the memory array structure through the bridge structure. The width of the conductive portion decreases along a second transverse direction perpendicular to the transverse direction and away from the bridge structure. Each of the plurality of landing regions lies on one or more dielectric pairs.

[0007] In another example, the 3D memory device includes a memory array structure and a step structure. The step structure includes a plurality of steps extending along a transverse direction. The plurality of steps includes a step having a conductive portion on the upper surface of the step, and a dielectric portion that is at the same level as the conductive portion and also contacts the conductive portion. The conductive portion is electrically connected to the memory array structure. Along a second transverse direction perpendicular to the transverse direction, the width of the conductive portion varies.

[0008] In another example, a method for forming a step structure of a 3D memory device comprises the following steps. First, a plurality of steps are formed having a plurality of first sacrificial layers and a plurality of first dielectric layers interleaved with the plurality of steps. A bridge structure in contact with the plurality of steps is formed, and the bridge structure has a plurality of second sacrificial layers and a plurality of second dielectric layers interleaved with the plurality of steps. Each first sacrificial layer contacts each second sacrificial layer at the same level, and each first dielectric layer contacts each second dielectric layer at the same level. A sacrificial portion is formed on the first sacrificial layer corresponding to at least one of the steps. The sacrificial portion is on the upper surface of each step and is cut at the edge of the upper step. The second sacrificial layer and the sacrificial portion are removed by the same etching process to form a plurality of transverse concave portions and a transverse concave portion, respectively. A plurality of conductive layers are formed in the transverse concave portions, and a conductive portion is formed in the transverse concave portions and contacts each of the conductive layers. Brief explanation of the drawing

[0009] The accompanying drawings, incorporated into and forming part of this specification, illustrate embodiments of the present disclosure and, together with the description, additionally explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure. FIG. 1a is a schematic diagram of an exemplary 3D memory device having a stepped structure according to some embodiments of the present disclosure. FIG. 1b is an exemplary top front perspective view of a stepped structure of a three-dimensional memory device shown in FIG. 1a, according to some embodiment of the present disclosure. FIG. 1c is a plan view of an exemplary three-dimensional memory device illustrated in FIG. 1a according to some embodiments of the present disclosure. FIG. 1d is another plan view of the exemplary 3D memory device shown in FIG. 1a according to some embodiments of the present disclosure. FIG. 1e is a detailed top front perspective view of a stepped structure of a three-dimensional memory device shown in FIG. 1a, according to some embodiment of the present disclosure. FIG. 2a is a schematic diagram of another exemplary 3D memory device having a stepped structure according to some embodiments of the present disclosure. FIG. 2b is an exemplary top front perspective view of a stepped structure of a three-dimensional memory device shown in FIG. 2a, according to some embodiment of the present disclosure. FIG. 2c is a plan view of an exemplary three-dimensional memory device shown in FIG. 2a according to some embodiments of the present disclosure. FIG. 3a is a cross-sectional view of an exemplary three-dimensional memory device having a stepped structure according to some embodiments of the present disclosure. FIG. 3b is another cross-sectional view of the 3D memory device shown in FIG. 3a according to some embodiments of the present disclosure. FIG. 3c is another cross-sectional view of the three-dimensional memory device shown in FIG. 3a according to some embodiment of the present disclosure. FIG. 3d is a detailed cross-sectional view of the conductor portion shown in FIG. 3c according to some embodiment of the present disclosure. FIGS. 4a through 4e are drawings illustrating a manufacturing process for forming an exemplary stepped structure of a 3D memory device according to some embodiments of the present disclosure. FIGS. 5A and 5B are drawings illustrating exemplary steps before and after the ion implantation process according to some embodiments. FIG. 6 is a flowchart illustrating a method for forming an exemplary step structure of a three-dimensional memory device according to some embodiments. An embodiment of the present invention will be described with reference to the attached drawings. Specific details for implementing the invention

[0010] While specific configurations and arrangements are discussed, it should be understood that they are done merely for illustrative purposes. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure may be used for various other applications.

[0011] It should be noted that references in the specification such as "one embodiment," "an embodiment," "an exemplary embodiment," or "some embodiments" indicate that while the described embodiments may include specific features, structures, or characteristics, not all embodiments are necessarily capable of including such specific features, structures, or characteristics. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when specific features, structures, or characteristics are described in relation to an embodiment, it will be within the knowledge of those skilled in the art to implement such features, structures, or characteristics in relation to other embodiments, regardless of whether they are explicitly described.

[0012] Generally, terms may be understood at least partially from their contextual usage. For example, the term “one or more” as used herein may, depending on the context, be used to describe a feature, structure, or characteristic in a singular sense, at least partially, or to describe a feature, structure, or combination of features in a plural sense. Similarly, terms such as “one” or “above” may be understood, depending on the context, to convey at least partially a singular usage or to convey a plural usage. Furthermore, the term “based on” may be understood not to convey an exclusive set of factors, but instead may, at least partially, allow for the existence of additional factors not explicitly described, depending on the context.

[0013] It should be immediately understood that the meaning of "on" in the present disclosure should be interpreted most broadly, so that "on" means not only "directly on" something but also includes the meaning of "on" something where there are intermediate features or layers in between, and "on" means not only "on" something but also the meaning of "on" something without intermediate features or layers (i.e., directly on something).

[0014] Additionally, spatially relative terms such as "below," "lower," "above," and "upper" may be used herein for convenience of explanation to describe the relationship of one element or feature to other elements or features illustrated in the drawings. Spatially relative terms are intended to include other directions of the device in use or operation in addition to the directions illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or oriented in a different direction), and spatially relative terms used herein may likewise be interpreted similarly accordingly.

[0015] As used herein, the term “substrate” refers to a material upon which a subsequent layer of material is added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate may be made of an electrically nonconductive material, such as glass, plastic, or a sapphire wafer.

[0016] As used herein, the term “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entire structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness thinner than that of the continuous structure. For example, a layer may be located between the upper and lower surfaces of the continuous structure or between any pair of horizontal planes on the upper and lower surfaces of the continuous structure. A layer may extend transversely, vertically, and / or along a tapered surface. A substrate may be a layer and may contain one or more layers within it, and / or have one or more layers above and / or below it. A layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors (where interconnect lines and / or vertical interconnect access (VIA) contacts are formed), a contact layer, and one or more dielectric layers.

[0017] As used herein, the term “nominal” means a desired or target value of a characteristic or parameter for a component or process operation, set during the design phase of the product or process, with a value range greater than and / or less than the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. The term “approximately” indicates a fixed amount value that may vary based on a specific technical node associated with the target semiconductor device. Based on a specific technical node, the term “approximately” may indicate a fixed amount value that varies, for example, within 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0018] As used herein, the term “3D memory device” refers to a semiconductor device in which a string of memory cell transistors (referred to herein as “memory string,” e.g., NAND memory string) is oriented vertically on a transversely oriented substrate so that the memory string can extend in a direction perpendicular to the substrate. As used herein, the term “vertical” means nominally perpendicular to the transverse surface of the substrate.

[0019] In some 3D memory devices, memory cells for storing data are stacked vertically through a stacked storage structure (e.g., a memory stack). 3D memory devices typically include a stepped structure formed near the stacked storage structure for purposes such as word line fan-out. As the demand for higher storage capacity continues to increase, the number of vertical levels in the stacked storage structure also increases, making it more difficult to form word line via contacts on the steps without punching through the contacts to prevent short circuits. For example, word line via contacts are often formed by creating an opening (e.g., a landing area of ​​the step) that contacts the step within the insulating structure where the stepped structure is placed, and filling the opening with a conductive material. Conventionally, these openings formed to contact the step at different depths / heights were formed using the same etching process. Due to variations in opening depth, these openings are often not etched uniformly or preferably. For example, openings in contact with a lower step (e.g., a deeper opening) and openings in contact with a higher step (e.g., a shallower opening) over-etch the opening in contact with the higher step over the same etching time. Over-etching can cause undesirable damage to the conductor layer (e.g., a word line) on the upper surface of the higher step, or even cause through-etching. Word line via contacts can cause punch-throughs leading to short circuits or undesirable leakage by undesirably contacting other conductor layers beneath each conductor layer. To address this, efforts are being made, such as thickening the conductor layer for landing. However, a thicker landing area still cannot definitively reduce the possibility of punch-throughs and makes the manufacturing process more difficult.

[0020] Various embodiments according to the present invention provide a step structure and a method for manufacturing the same. A step structure having a plurality of steps may include a conductive portion on the upper surface of at least one step and a dielectric structure comprising one or more dielectric pairs located below the conductive portion. The conductive portion covers at least a landing area (e.g., a part of the step) of each step so that a word line via contact can contact each step and be electrically connected to each step. The thickness of the dielectric structure may be equal to the distance from the bottom surface of the conductive portion to the upper surface of the substrate, and is preferably thick to prevent interference between the conductive portions in different steps due to punch-through. Along a transverse direction perpendicular to the direction in which the step extends, the width of each conductive portion may gradually decrease from the end.

[0021] In embodiments of the present disclosure, a conductor portion includes an overlapping portion and a non-overlapping portion. The overlapping portion refers to a part of the conductor portion that overlaps with the step immediately above and / or immediately below the conductor portion (or the conductor portion of the step immediately above or immediately below). The non-overlapping portion refers to a part of the conductor portion that does not overlap with the upper or lower step. A word line VIA contact may be formed in the non-overlapping portion of the conductor portion. The non-overlapping portion of the conductor portion may preferably have a large landing area for each word line VIA contact to be formed. In some embodiments, along the direction in which the step extends, the dimensions of the non-overlapping portion of the conductor portion become equal to the nominal dimensions of the step.

[0022] In some embodiments, the dielectric structure below the conductor portion comprises each dielectric layer and one or more lower dielectric pairs, and each lower dielectric pair comprises a dielectric portion and a dielectric layer in the lower step. In some embodiments, the number of dielectric pairs below the conductor portion of each step is equal to the number of steps / levels below the step. Even if a punch-through occurs in any conductor portion, the word line VIA contact does not come into contact with any conductor portion (or word line) of the lower step, and leakage or short circuits can be reduced / eliminated. Then, it may be less difficult to form an opening.

[0023] In various embodiments, the steps are formed in a step structure located in the middle of the memory array structure or on the side of the memory array structure. The step structure may include a bridge structure interleaved with a plurality of conductive layers and dielectric layers. The conductive layers are conductively connected to memory cells within the memory array structure. In order for a voltage to be applied to the memory cells through the conductive portions and conductive layers of the same level, the conductive portions of each step contact the conductive layers of the same level along a direction perpendicular to the direction in which the steps extend.

[0024] To form a conductive portion, an ion implantation process is performed prior to gate replacement. The ion implantation process is used to form a sacrificial portion, which is the ion-implanted portion of each sacrificial layer located on the upper surface of the step. The ion implantation process can alter the physical properties of the treated portion so that the sacrificial portion can be etched at a higher rate than other portions of the sacrificial layer that are not ion-implanted. Then, a single etching process may be applied to simultaneously remove the sacrificial layer and the sacrificial portion (e.g., to form word lines in the bridge structure) so that a transverse concave portion can be formed. The dielectric structure beneath the sacrificial portion may be preserved. In some embodiments, the transverse concave portion includes an excessively etched portion of the sacrificial layer located directly above the step due to the higher etching rate of the sacrificial portion. Conductive material is deposited to fill the transverse concave portions of each step and the transverse concave portions within the bridge structure. Multiple conductive layers may be formed in the bridge structure. Each of the multiple conductive portions located on each step and also on each dielectric structure may be formed on the step. In some embodiments, the excessively etched portion is filled with a conductor portion and forms an overlapping portion between adjacent conductor portions.

[0025] FIGS. 1a through 1c and FIGS. 2a through 2c are schematic diagrams of 3D memory devices (100, 200) each having a stepped structure according to some embodiments. Specifically, FIGS. 1a through 1c show a layout in which the stepped structure is located in the middle of the memory plane, and FIGS. 2a through 2c show a layout in which the stepped structure is located on both sides of the memory plane. The stepped structure of the present disclosure may be formed on both 3D memory devices (100, 200). As an example to explain the present invention, the embodiment focuses on the structure of the stepped structure within the 3D memory device (100) and the manufacturing process thereof. In some embodiments, the stepped structure of the 3D memory device (200) may be formed by a similar manufacturing process. It should be noted that the x-axis and y-axis are included in FIGS. 1a and FIGS. 2a to represent two orthogonal (vertical) directions in the wafer plane. The x-direction is the word line direction of each 3D memory device, and the y-direction is the bit line direction of each 3D memory device. It should be noted that the structure of the present disclosure is merely an example and does not represent the dimensions, proportions, or shape of an actual product.

[0026] FIG. 1a is a schematic diagram of an exemplary 3D memory device (100) having a stepped structure (102) according to some embodiments of the present disclosure. In some embodiments, the 3D memory device (100) includes a plurality of memory planes. A memory plane may include a first memory array structure (104-1), a second memory array structure (104-2), and a stepped structure (102) located in the middle of the first and second memory array structures (104-1, 104-2). The first and second memory array structures (104-1, 104-2), which are considered together as a memory array structure, may or may not have the same area. In some embodiments, the stepped structure (102) is located in the middle of the first and second memory array structures (104-1, 104-2). For example, the first and second memory array structures (104-1, 104-2) may be symmetric in the x-direction with respect to the stepped structure (102). In some examples, it should be understood that the step structure (102) may be in the middle but not in the middle (center) of the first and second memory array structures (104-1 / 104-2) so that the first and second memory array structures (104-1, 104-2) may have different sizes and / or different numbers of memory cells. In some embodiments, the 3D memory device (100) is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings (not shown in FIG. 1a) within the first and second memory array structures (104-1, 104-2). The first and second memory array structures (104-1, 104-2) may include any other suitable components, including but not limited to gate line slits (GLS), through array contacts (TAC), array common sources (ACS), etc.

[0027] Each word line (not shown in FIG. 1a) of a memory plane extending laterally in the x-direction can be separated by a step structure (102) into two parts: a first word line part crossing a first memory array structure (104-1) and a second word line part crossing a second memory array structure (104-2). The two parts of each word line can be electrically connected by a bridge structure (shown as a bridge structure (108) within the step structure (102) in FIG. 1b and FIG. 1c) at each step within the step structure (102). A row decoder (not shown) can be formed directly above, below, or near each step structure (102). Each row decoder can drive the word line in both directions from the middle of the memory plane.

[0028] FIGS. 1B and FIGS. 1C illustrate the detailed structure of a step structure (102). FIGS. 1B is a plan view of a step structure (102) within a 3D memory device (100). FIGS. 1C is a plan view of the spatial relationship between the step structure (102) and the adjacent first and second memory array structures (104-1, 104-2) and the step structure (102). For convenience of explanation, FIGS. 1C illustrates only one step structure (102). In various embodiments, the 3D memory device (100) includes a plurality of step structures aligned with the step structure (102) between the first and second memory array structures (104-1, 104-2), for example, along the y-direction. For example, other step structures may be identical to the step structure (102) and the mirror step structure (102) along the y-direction. Additionally, other possible structures, such as dummy stairs, are omitted from the stair structure (102) for convenience of explanation.

[0029] FIG. 1b illustrates a step structure (102) having steps (106) and a bridge structure (108) in contact with each other. FIG. 1e is a detailed 3D perspective view of the step structure (102). The step structure (102) may be on a substrate (10) (shown in FIG. 1d) which may include silicon (e.g., single-crystal silicon), or silicon germanium (SiGe), or gallium arsenide (GaAs), or germanium (Ge), or silicon on insulator (SOI), or other suitable materials.

[0030] The steps (106) may include a plurality of steps (114) extending along the word line direction, for example, the x-direction. Each step (114) may have a different depth along the z-direction and a landing area to form contact with, for example, a corresponding word line VIA contact. Each step (114) of the steps (106) (illustrated as a “level”) may include one or more pairs of material layers. In some embodiments, the upper material layer of each step (114) includes a conductive portion for interconnection with the word line VIA contact in the vertical direction. In some embodiments, adjacent steps (114) of the steps (106) are offset by a nominally equal distance in the z-direction and a nominally equal distance in the x-direction for every two steps. Thus, each offset may form a “landing area” for interconnection with the word line contact of the 3D memory device in the z-direction. In some embodiments, each step (114) includes at least one dielectric layer beneath the conductive portion.

[0031] The bridge structure (108) may include a vertically interleaved conductor layer and a dielectric layer (not shown), and the conductor layer (e.g., a metal layer or a polysilicon layer) may function as part of a word line. Unlike the step (106) in which the word line within the step (106) is cut from the memory array structure (e.g., 104-1 and / or 104-2) in the x-direction (e.g., positive x-direction, negative x-direction, or both directions), the word line within the bridge structure (108) is preserved and bridges the word line VIA contacts landed on the step (114) and the memory array structure (e.g., 104-1 and / or 104-2), thereby achieving a bidirectional word line driving method. In some embodiments, at least one step (114) of the steps within the steps (106) is electrically connected to at least one of the first memory array structure (104-1) and the second memory array structure (104-2) through a bridge structure (108). At least one word line may extend laterally in the memory array structure (e.g., 104-1 and / or 104-2) and the bridge structure (108) so that at least one step (114) can be electrically connected to at least one of the first and second memory arrays through the bridge structure (108) by at least one word line. In one example, each step (114) within the steps (106) may be electrically connected to the first memory array structure (104-1) (in the negative x-direction) by each word line portion extending in the negative x-direction through the bridge structure (108), for example by each word line portion extending in the negative and positive x-directions.

[0032] The conductive portion of the step (106) and the conductive layer of the bridge structure (108) may each comprise a conductive material comprising, but not limited to, tungsten (W), or cobalt (Co), or copper (Cu), or aluminum (Al), or polycrystalline silicon (polysilicon), or doped silicon, or silicide, or any combination thereof. In some embodiments, the conductive portion and the conductive layer comprise the same material, for example, a metal such as tungsten, and the dielectric layer comprises the same material, for example, silicon oxide.

[0033] FIGS. 1C and FIGS. 1D illustrate a step structure (102) between the first and second memory array structures (104-1, 104-2). As illustrated in FIGS. 1C and FIGS. 1D, the step (106) may include a plurality of steps (114) extending along the x-direction, and a word line VIA contact (116) is formed on at least one (e.g., each) of the first and second memory array structures (104-1, 104-2) may include one or more memory blocks, and each memory block may include one or more memory fingers (120). In some embodiments, the step structure (102) may be between a pair of memory fingers (120) along the y-direction. Each memory finger (120) may include a plurality of memory strings (112) extending along the z-direction. The memory string (112) may include a channel structure having a blocking layer, a memory layer, a tunneling layer, a semiconductor layer, and optionally a dielectric core that is in the channel hole and is radially arranged from the sidewall toward the center of the channel hole. The memory string (112) may intersect with a plurality of word lines (e.g., a conductor layer within the memory finger (120)) to form a plurality of memory cells. The memory cells may form a memory cell array in each memory array structure. In some embodiments, the GLS (110) extending along the x-direction and z-direction divides the memory cells within the first and second memory array structures (104-1, 104-2) along the y-direction into a plurality of memory fingers (120).

[0034] To achieve a bidirectional word line driving method, according to some embodiments, a bridge structure (108) connects a first memory array structure (104-1) and / or a second memory array structure (104-2) (both physically and electrically). That is, according to some embodiments, a step structure (102) does not completely block the memory array structure in the middle, but instead leaves the first and second memory array structures (104-1, 104-2) connected by the bridge structure (108). Thus, each word line can be driven bidirectionally (in positive and negative x-directions) from each word line VIA contact (116) in the middle of the 3D memory device (100) through the bridge structure (108). FIGS. 1C and 1D illustrate exemplary current paths for a bidirectional word line driving method having a step structure (102). Current paths indicated by arrows represent currents passing through individual word lines at different levels.

[0035] FIGS. 2a through 2c are schematic diagrams of a 3D memory device (200) having step structures (202-1, 202-2) on each side of a memory array structure (204). The step structures (202-1, 202-2) and the memory array structure (204) may be on a substrate (101) similar to that of the 3D memory device (100). The 3D memory device (200) may include a memory plane having a memory cell array in the memory array structure (204). Unlike the 3D memory device (100), the 3D memory device (200) includes two step structures (202-1, 202-2) on both sides in the x-direction of the memory array structure (204). Each word line of the memory plane extends laterally in the x-direction across the entire memory plane to each step (level) within the step structure (202-1) or step structure (202-2). Row decoders (not shown) are formed immediately above, below, or adjacent to each step structure. That is, each row decoder drives half of the memory cells through half of the word line unilaterally (in either the positive or negative x-direction, but not both), and each word line crosses the entire memory plane.

[0036] The step structure (202-1, 202-2) may have a similar / identical structure. FIG. 2b is a front plan view of the step structure that may show each of the step structures (202-1, 202-2). The step structure may include a step (206) having a plurality of steps (214) extending along the x-direction similar to the step (106). The step structure also includes a bridge structure (208) electrically and physically connected to the step (206). The bridge structure (208) may include interleaved conductor layers and dielectric layers similar to the bridge structure (108). In some embodiments, the bridge structure (208) includes a plurality of steps extending along the x-direction, and each step corresponds to each step of the step (206). For example, at least one step (214) includes a conductor portion on the upper surface and is electrically connected to a conductor layer at the same level of the bridge structure (208). The step (206) may be similar to the step (106). For example, at least one step (214) includes a conductive portion electrically connected to a conductive layer at the same level in the bridge structure (208) on the upper surface. The conductive layer in the bridge structure (208) may be a word line portion (e.g., a conductive layer) electrically connected to a word line in the memory array structure (204).

[0037] FIG. 2c illustrates each of the step structures (202-1, 202-2) on each side of the memory array structure (204). As illustrated in FIG. 2c, the step (206) may include a plurality of steps (214) extending along the x-direction, and a word line VIA contact (216) is formed on at least one (e.g., each) step (214). The memory array structure (204) may include one or more memory blocks, and each memory block includes one or more memory fingers (220). Each memory finger (220) may include a plurality of memory strings (212) similar to the memory string (112) in the 3D memory device (200). A memory string (212) may intersect with a plurality of word lines (e.g., a conductive layer within a memory finger (220)) to form a plurality of memory cells, and the plurality of memory cells form a memory cell array in each memory array structure. In some embodiments, a GLS (210) extending along the x-direction and z-direction divides the memory cells within the memory array structure (204) along the y-direction into a plurality of memory fingers (220).

[0038] To achieve a unilateral word line-driving scheme, according to some embodiments, each of the bridge structures (208) connects the memory array structures (204) (physically and electrically). Thus, each word line can be unilaterally driven (in the positive or negative x-direction) from each word line VIA contact (216) on one side of the 3D memory device (200) through the bridge structures (208). In FIG. 2c, the current paths indicated by arrows represent current passing through two separate word lines at different levels.

[0039] FIGS. 3a through 3d are three cross-sectional views of a step structure (e.g., 102) that are each orthogonal to one another. Specifically, FIGS. 3a and 3b each illustrate cross-sectional views of the step structure (102) cut along the AA' direction and the BB' direction, as shown in FIG. 3b. FIG. 3a is a cross-sectional view of a step (106) showing a non-overlapping portion of the conductor part. As shown in FIG. 1b, the AA' direction represents the xz plane, and the BB' direction represents the zy plane. FIG. 3c illustrates an xy cross-sectional view of a step / level of the step structure (102). FIG. 3d illustrates a detailed cross-sectional view of an exemplary conductor part. Except that the bridge structure may have a different number of conductor / dielectric layer pairs along the z-direction, FIGS. 3a through 3d may also be cross-sectional views of a stepped structure (202-1 / 202-2) cut along the same direction (as shown in FIG. 2b).

[0040] As described above, in a 3D memory device, a step structure may include steps and a bridge structure in contact with the steps. As illustrated in FIGS. 3a and 3b, the step structure may include steps (306) and a bridge structure (308) in contact with the steps (306) (only a portion shown in FIG. 3b). The step structure may be formed on a substrate (302) similarly to that in a 3D memory device (100). The insulating structure (350) may be positioned on at least the steps (306) so that at least the steps (306) can be located on the insulating structure (350). Word line VIA contacts (316) may be formed on the insulating structure (350) and land on the landing area of ​​each step. For convenience of explanation, only one word line VIA contact (316) is shown. The insulating structure (350) may include any suitable dielectric material, such as silicon oxide, silicon nitride, and / or silicon nitride. The word line VIA contact (316) may include tungsten, or cobalt, or copper, or aluminum, or polysilicon, or doped silicon, silicide, or any combination thereof. The bridge structure (308) may include a plurality of interleaved conductor layers (330) and dielectric layers (336) similar to those in a 3D memory device (100).

[0041] As illustrated in FIGS. 3a and 3b, the steps (306) comprise a plurality of steps (314) extending along the x-direction, e.g., the word line direction. Each step (314) may have a different depth along the z-direction. In some embodiments, except for the upper step, the steps (306) comprise a conductor portion (320) that is on the upper surface of at least one step (314) and is electrically and physically connected to a conductor layer (330) at the same level within the bridge structure (308). In some embodiments, each step (314) of the steps (306) may comprise a conductor portion (320). The conductor portion (320) may come into contact with a dielectric portion (324) at the same level (e.g., extending along the x-direction). Optionally, at each step (314), the conductor portion (320) may be on the dielectric layer (326) below it and may be on another dielectric portion in contact with the dielectric layer (326). In some embodiments, at each step (314), the conductor portion (320) may be on the dielectric layer (326) without any other dielectric portion in between and may be in contact with the dielectric layer (326). In some embodiments, each dielectric layer (326) within the step (306) is in contact with the dielectric layer (336) at the same level of the bridge structure (308). In some embodiments, the conductor portion (320) may be on one or more dielectric layers (336) within each step (314).

[0042] As illustrated in FIG. 3a, along the x-direction, the conductor portion (320) extends from the landing area of ​​each step (314). The non-overlapping portion of the conductor portion (320) (illustrated in FIG. 3d) may be cut at the edge of the upper step (314) (e.g., the step immediately above (314)). That is, along the x-direction, little or no overlap is formed between adjacent non-overlapping portions of the conductor portion (320). In some embodiments, along the x-direction, no overlap is formed between any non-overlapping portions of the conductor. In some embodiments, along the x-direction, the width (d) of the non-overlapping portion of the conductor portion (320) may be less than or equal to the dimensions of the step (314). Each word line VIA contact may be formed over the non-overlapping portion of the conductor portion (320).

[0043] In some embodiments, in the step (314), the other dielectric portion (if formed) and the dielectric portion (324) may have the same material as the material of the dielectric layer (326). In some embodiments, the dielectric layer (326) comprises silicon oxide. In some embodiments, the dielectric portion (324) comprises silicon nitride. In some embodiments, the other dielectric portion (if formed) has the same dimensions as the conductor portion (320) along the x-direction. In the step (314), the bottom surface of the dielectric portion (324) and the other dielectric portion may be coplanar along the z-direction. Along the z-direction, the thickness of the conductor portion (320) may be less than or equal to the thickness of the dielectric portion (324), and the thickness of the other dielectric portion (if formed) may be less than the thickness of the dielectric portion (324).

[0044] As illustrated in FIG. 3b, along the y-direction, the length (D) of the conductor portion (320) may be less than or equal to the dimension of each step (314). In some embodiments, the length (D) is equal to the dimension of each step (314) along the y-direction. In some embodiments, the length (D) is less than the dimension of each step (314), and the second dielectric portion (323) is formed at the end of the step (314) away from the bridge structure (308). The second dielectric portion (323) may have the same thickness as the dielectric portion (324) along the z-direction and may have the same material as the dielectric portion (324). Along the x-direction, the width of the second dielectric portion (323) may be smaller than the width (d) of the conductor portion (320), or equal to the width (d) of the conductor portion (320), or larger than the width (d) of the conductor portion (320). The length (D) and width (d) of the conductor portion (320) may each be large enough to cover the landing area of ​​each step (314) and to form each word line VIA contact (316) at a desired location.

[0045] As illustrated in FIGS. 3a and 3b, the conductor portion (320) may be on at least each dielectric layer (326) within the same step (314). In some embodiments, at each step (314), the conductor portion (320) is in contact with and on each dielectric layer (326). Meanwhile, the dielectric portion (324) may extend from the boundary with each conductor portion (320) at the step (306), for example along the x-direction (e.g., along the negative x-direction), to the boundary between the step (306) and the memory array structure. In some embodiments, along the z-direction, at least one conductor portion (320) is on a plurality of interleaved dielectric layers (326) and dielectric portions (324). For example, the dielectric layer (326) may include each dielectric layer (326) at the same step and one or more dielectric layers (326) at the lower step (314). The dielectric portion (324) may include one or more dielectric portions (324) in the lower step (314). In some embodiments, along the z-direction, at least one conductor portion (320) is also above another dielectric portion within the same step (314). As illustrated in FIG. 3b, all dielectric portions (324) and dielectric layers (326) below the conductor portion (320) may be referred to as a dielectric structure (340), and the thickness of the dielectric structure (340) along the z-direction is equal to the distance between the bottom surface of each conductor portion (320) and the top surface of the substrate (302). In some embodiments, the length of the dielectric structure (340) along the y-direction is equal to the length of the conductor portion (320) (e.g., length (D)). In some embodiments, the width of the dielectric structure (340) along the x-direction is equal to the width (d) of the conductor portion (320).In some embodiments, except for the bottom step (314) (e.g., the step (314) at the bottom of the step (306)), the dielectric structure (340) comprises a lower step (314) (e.g., at least one pair of dielectric portions (324) and dielectric layers (326) corresponding to the step (314) at a lower elevation / greater depth along the negative z-direction). In some embodiments, except for the bottom step (314), each dielectric structure (340) comprises at least one pair of dielectric portions (324) and dielectric layers (326) corresponding to the lower step (314), and dielectric layers (326) within each step (314).

[0046] FIG. 3c is a transverse cross-sectional view of a step structure showing the spatial relationship of the GLS (310), the conductor layer (330), the conductor portion (320), and the dielectric portion (324). As illustrated in FIG. 3b and FIG. 3c, in some embodiments, the step (306) includes a connecting structure (321) in contact with the bridge structure (308). The connecting structure (321), which is part of the step (306) and extends along the x-direction, may include at least one interleaved conductor strip and at least one dielectric strip on the substrate (302). In some embodiments, the length (L) of the connecting structure (321) is greater than or equal to 0 along the y-direction. For each step (314), the dimension of the connecting structure (321) may be the length of each dielectric layer (326) along the x-direction (e.g., the sum of the width (d) of the dielectric portion (324) and the conductor portion (320). That is, along the x-direction, the dimensions of the connection structure (321) may be equal to the length of the contact area between the step (314) and the bridge structure (308). The thickness of the connection structure (321) along the z-direction may be equal to the height of each step (314). That is, the thickness of the connection structure (321) may be equal to the distance from the upper surface of the step (314) / conductor part (320) to the upper surface of the substrate (302). Each conductor strip may be in contact with the conductor layer (330) and dielectric part (324) at the same level, and each dielectric strip may be in contact with the dielectric layer (336) and dielectric layer (326) at the same level. The material of the conductor strip may be the same as the material of the conductor layer (330), and the material of the dielectric strip may be the same as the material of the dielectric layer (336).

[0047] For each step (314), the upper conductor strip may also come into contact with each conductor portion (320), and thus electrically connect the conductor portion (320) and the conductor layer (330) at the same level. Along the z-direction, the thickness of each conductor strip may be equal to the thickness of each conductor layer (330). In some embodiments, the conductor and dielectric strips that are part of the step (306) may be considered as an extension of the conductor layer (330) and dielectric layer (336) along the y-direction and into the step (306). In some embodiments, the dielectric structure (340) of each step (314) comes into contact with each connection structure (321).

[0048] As illustrated in FIG. 3c, the GLS (310) may extend along the x-direction and come into contact with the bridge structure (308) (e.g., or the conductor layer (330) within the bridge structure (308)). In some embodiments, the bridge structure (308) may be located between the GLS (310) and the step (306). In some embodiments, along the negative y-direction, the width (d) of the conductor portion (320) may decrease. In various embodiments, along the negative y-direction, the width (d) may continue to decrease by a first distance (d1) (e.g., from the boundary of the bridge structure (308) or the connecting structure (321) (if present)) and may remain unchanged by a second distance (d2). As illustrated in FIG. 3c, the sum of d1 and d2 may be D if the connection structure (321) is not formed, and (DL) if the connection structure (321) is formed. In some embodiments, it is preferable that d1 be negligibly small compared to d2. For example, d1 may be about 2% to about 20% of d2 (e.g., 2%, 3%, 5%, 8%, 10%, 15%, 18%, 20%).

[0049] FIG. 3d illustrates the detailed structure of the conductor portion (320). For convenience of explanation, different patterns / shading are used in FIG. 3d to depict various parts of the conductor portion (320). In some embodiments, the conductor portion (320) may be divided into a non-overlapping portion (320-1) and an overlapping portion (320-2, 320-3). The overlapping portion (320-2) may represent a part of the conductor portion (320) that overlaps with the step immediately above (or the conductor portion (320) of the step immediately above) along the z-direction. The overlapping portion (320-3) may represent a part of the conductor portion (320) that overlaps with the step immediately below (or the conductor portion (320) of the step immediately below) along the z-direction. The non-overlapping portion (320-1) may represent a part of the conductor portion (320) that does not overlap with any upper or lower step. The non-overlapping portion (320-1) and the overlapping portion (320-3) together may form a part of the conductor portion (320) exposed on the upper surface of the stairs (314). The boundary between the overlapping portion (320-2) and the non-overlapping portion (320-1) may be the edge of the stairs (314) immediately above, even if it is not physically formed. As illustrated in FIGS. 3c and 3d, the non-overlapping portion (320-1) contacts each of the overlapping portions (320-2, 320-3). The total area of ​​the conductor portion (320) may be the sum of the non-overlapping portion (320-1) and the overlapping portions (320-2, 320-3) along the xy plane.

[0050] In some embodiments, the overlapping portions (320-2, 320-3) may have nominally the same shape and / or nominally the same dimensions. In some embodiments, as illustrated in FIG. 3c, the overlapping portion (320-2) has the shape of a right triangle in which the boundary of the dielectric portion (324) is perpendicular to the edge of the step (314) immediately above along the x-direction. The transverse dimensions of the overlapping portion (320-2) may gradually decrease along the negative y-direction. In some embodiments, the boundary of the dielectric portion (324) may include the hypotenuse of the right triangle (e.g., the overlapping portion (320-2)) as well as the boundary along the y-direction and along the x-direction (e.g., in conjunction with the connecting structure (321) or the bridge structure (308)) (e.g., aligned with the edge of the step (314) immediately above). In some embodiments, the non-overlapping portion (320-1) may have a rectangular trapezoidal shape. The transverse dimension of the non-overlapping portion (320-1) may increase along the negative y-direction. That is, the width (d) of the conductor portion may decrease and may remain unchanged along the negative y-direction.

[0051] FIGS. 4a through 4d illustrate a manufacturing process for forming an exemplary stepped structure of a three-dimensional memory device according to various embodiments of the present disclosure. FIGS. 5a and 5b illustrate steps before and after an ion implantation process according to some embodiments. FIG. 6 is a flowchart of a method (600) for forming an exemplary stepped structure of a 3D memory device according to some embodiments. It should be understood that the steps illustrated in the method (600) for forming an exemplary stepped structure of a 3D memory device are not complete and that other steps may be performed before, after, or between any of the illustrated steps. Additionally, some of the steps may be performed simultaneously and in a different order than illustrated in FIG. 6.

[0052] Referring to FIG. 6, a method (600) for forming an exemplary step structure of a 3D memory device begins at step 602, in which a step structure having a step and a bridge structure is formed. FIG. 4a illustrates a corresponding structure.

[0053] As illustrated in FIG. 4a, a step structure having a step (406) and a bridge structure (408) is formed on a substrate (402). The step (406) may be in contact with the bridge structure (408). The step (406) may include a plurality of interleaved sacrificial layers (429) and a plurality of dielectric layers (426) and form a plurality of steps (414) extending along the x-direction (e.g., see step (314) in FIG. 3a). Each step (414) may include at least one pair of sacrificial layers (429) / dielectric layers (426). The bridge structure (408) may include a plurality of interleaved sacrificial layers (439) and a plurality of dielectric layers (436). In some embodiments, each sacrificial layer (439) is in contact with each sacrificial layer (429) at the same level, and each dielectric layer (436) is in contact with each dielectric layer (436) at the same level. In some embodiments, the sacrificial layer (439, 429) comprises the same material as silicon nitride. In some embodiments, the dielectric layer (436, 426) comprises the same material as silicon oxide.

[0054] To form a stack structure, a material stack may be formed first. The material stack may include a first dielectric material layer and a second dielectric material layer that are vertically interleaved. In some embodiments, the material stack is a dielectric stack, and the first material layer and the second material layer include different dielectric materials. The interleaved first dielectric material layer and the second dielectric material layer may be deposited alternately on the substrate (402). In some embodiments, the first dielectric material layer includes a silicon nitride layer, and the second dielectric material layer includes a silicon oxide layer. The material stack may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0055] A portion of the material stack may be patterned to form a stack structure. In some embodiments, steps (406) and bridge structures (408) may be formed using a separate mask, e.g., a separate etching process. In some embodiments, the formation of steps (406) involves repeatedly etching the material stack using an etch mask (e.g., a patterned photoresist or PR layer) over the material stack. The etch mask may be repeatedly trimmed inward from all directions and often progressively to expose a portion of the material stack to be etched. The amount of trimmed PR may be directly related to the dimensions of the steps (e.g., may be a determining factor). For example, the amount of trimmed PR along the x-direction may determine the width of the steps (414) along the x-direction. Trimming of the PR layer may be achieved using appropriate etching, such as isotropic etching, e.g., wet etching. To form the steps, one or more PR layers may be formed and trimmed in succession. In some embodiments, etching the material stack using a suitable etching process, such as dry etching and / or wet etching, follows the trimming of the PR layer. In some embodiments, the material stack is etched along the z-direction by a step depth after each trimming of the PR layer. The step depth may be equal to the number of pairs of dielectric material layers included in the step (e.g., the number of first dielectric material layers / second dielectric material layers). In some embodiments, the number of pairs of dielectric material layers is 1. The trimming process of the photoresist mask and the subsequent etching process of the material stack are referred to herein as a trim-etch cycle. The number of trim-etch cycles may determine the number of steps formed in the material along the y-axis. In some embodiments, after forming the steps, the first dielectric material layer may form a sacrificial layer (429), and the second dielectric material layer may form a dielectric layer (426). Steps (406) may be formed.Each step (414) includes a pair of sacrificial layers (429) and a lower genome layer (426) (e.g., one sacrificial / genome pair).

[0056] In various embodiments, the bridge structure (408) may be formed by patterning other parts of the material stack. Depending on the design of the bridge structure (408), an etch mask may or may not be used. In various embodiments, the bridge structure (408) may have a "wall-shaped" structure as shown in FIG. 1b, or a step shape as shown in FIG. 2b. The bridge structure (408) may be formed together with the step (406) by the same etching process or a different etching process. In some embodiments, the formation of the bridge structure (408) involves a photolithography process followed by a suitable etching process, such as dry etching and / or wet etching. A step structure having the step (406) and the bridge structure (408) may be formed.

[0057] In some embodiments, after the formation of the step (406), a sacrificial layer (429) is exposed on the upper surface of each step (414). In each step (414), a dielectric layer (426) may be located beneath the sacrificial layer (429). In some embodiments, as illustrated in FIG. 4a, a protective layer (425) may be formed on the upper surface of the step (414) to provide buffering and protection during a subsequent ion implantation process over the step (414) so ​​that the lower sacrificial layer (429) may have optimized physical properties. The protective layer (425) may cover at least a portion of the step (414) that will undergo the ion implantation process (i.e., the sacrificial layer (429)). For example, the protective layer (425) may cover at least a landing area (or possible landing area) of the step (414) (e.g., the sacrificial layer (429)). The protective layer (425) may comprise any suitable material having a suitable thickness along the z-direction and may be formed by any suitable method. In some embodiments, the protective layer (425) comprises a layer of dielectric material(s). In some embodiments, the protective layer (425) comprises a portion of a second dielectric material layer (e.g., silicon oxide) that is not completely etched while forming the step (414). That is, at least a portion of the second dielectric material layer immediately above the first dielectric material layer within the step (406) may be retained while etching the material stack. In some embodiments, the etching time for forming the step (414) is controlled so that the protective layer (425) has a desired thickness. In some embodiments, the protective layer (425) may also deposit a layer of dielectric material, such as silicon oxide, on the step (414) (i.e., the sacrificial layer (429)) by a suitable deposition process, e.g., CVD, ALD, and / or PVD, either alone or in addition to controlled etching.

[0058] FIG. 5a is an enlarged view (500) of a step (414) prior to the ion implantation process. As shown in FIG. 5a, in some embodiments, a sacrificial layer (429) within each step (414) may be covered with a protective layer (425), and the protective layer (425) comprises an entire layer of a second dielectric material immediately above the sacrificial layer (429). In some embodiments, prior to the ion implantation process, the step (414) comprises a protective layer (425) and a lower sacrificial layer (429). A dielectric layer (426) may be located below each sacrificial layer (429) and may be in contact with the protective layer (425) of the step (414) immediately below.

[0059] Referring to FIG. 6, a method (600) for forming an exemplary step structure of a 3D memory device proceeds to step 604, which involves performing an ion implantation process to form a sacrificial portion on the upper surface of each step. FIG. 4b illustrates a corresponding structure.

[0060] As illustrated in FIG. 4b, an ion implantation process may be performed to form a sacrificial portion (419) on the upper surface of at least one step (414). In some embodiments, a plurality of sacrificial portions (419) are formed on each step (414). The sacrificial portion (419) may cover at least the landing area of ​​each step (414). In some embodiments, the sacrificial portion (419) covers the entire width (d) of each step (414) (e.g., along the x-direction, see FIG. 3a again). To ensure that the sacrificial portion (419) does not extend below the upper step (414) along the x-direction, the sacrificial portion (419) is cut at the edge of the step (414) immediately above. In various embodiments, the sacrificial portion (419) having length (D) may or may not cover the entire length of each step (414) (e.g., along the y-direction, see FIG. 3b again). Depending on the ion implantation process, the sacrificial portion (419) may or may not be cut at the boundary between the bridge structure (408) and the step (406). Along the z-direction, the thickness of the sacrificial portion (419) may be less than or equal to the thickness of the sacrificial layer (429). In some embodiments, the thickness of the sacrificial portion (419) is equal to the thickness of the sacrificial layer (429).

[0061] Ion implantation can alter the physical properties of the treated portion of the sacrificial layer (429) (i.e., the sacrificial portion (419)). In some embodiments, the sacrificial portion (419) may be impacted by ions to have higher porosity so that the ethant for removing the sacrificial layer (429) may have a higher etching rate for the sacrificial portion (419) on the sacrificial layer (429) during a subsequent gate replacement process. That is, the ethant for removing the sacrificial layer (429) may selectively etch the sacrificial portion (419) on the sacrificial layer (429). In some embodiments, the sacrificial portion (419) has a lower density than the sacrificial layer (429) to facilitate etching. In some embodiments, the ratio between the etching rate of the sacrificial portion (419) and the etching rate of the sacrificial layer (429) may be approximately 3:1. In various embodiments, the ion implantation process uses a tilted ion implantation process at any appropriate energy and with appropriate ions. In some embodiments, the gradient ion implantation process may also implant ions into the bridge structure (408). In some embodiments, the ions include boron (B) ions. Optionally, a heat treatment such as an annealing process may be performed after ion implantation.

[0062] In some embodiments, a portion of the sacrificial layer (429) located below the upper step (414) (see FIG. 3A again) may form a dielectric portion on each step (414) without undergoing an ion implantation process. The dielectric portion may come into contact with the sacrificial portion (419) at the edge of the step (414) immediately above. In some embodiments, if the thickness of the sacrificial portion (419) is smaller than the thickness of the sacrificial layer (429), an initial other dielectric portion (not shown) is formed below the sacrificial portion (419). The initial other dielectric portion may be formed by the portion of the sacrificial layer (429) below the sacrificial portion (419) and may not undergo an ion implantation process. In some embodiments, the width of the initial other dielectric portion along the x-direction is equal to that of each sacrificial portion (419), and the thickness of the initial other dielectric portion along the z-direction is smaller than the thickness of each dielectric portion (or sacrificial layer (429)). In some embodiments, the length of the initial other dielectric portion along the y-direction may be equal to the length of the conductor portion (420) (e.g., length (D)). In some embodiments, along the z-direction, each step (414) includes a sacrificial portion (419) and at least a lower dielectric layer (426) (and the initial other dielectric portion when formed). Additionally, except for the bottom step (414), each step (414) may be on one or more pairs of the dielectric portion of the lower step (414) and the dielectric layer (426).

[0063] Optionally, the sacrificial portion (419) may not completely cover the step (414) along the y-direction, and the second dielectric portion (423) may be formed from a portion of the sacrificial layer (429) outside the portion that underwent the ion implantation process. In some embodiments, the width of the second dielectric portion (423) along the x-direction may be smaller than the width of each step (414) (e.g., width (d)), equal to the width of each step (414), or greater than the width of each step (414). In some embodiments, the thickness of the second dielectric portion (423) along the z-direction may be smaller than or equal to the thickness of each sacrificial layer (429).

[0064] FIG. 5b is an enlarged view (502) of the step (414) after the ion implantation process. As illustrated in FIG. 5b, a sacrificial portion (419) may be formed on each step (414) located beneath each protective layer (425). The sacrificial portions (419) of adjacent steps (414) may not overlap along any direction. Optionally, the protective layer (425) may be removed after the ion implantation process to expose the sacrificial portion (419) underneath. In some embodiments, a suitable etching process, e.g., dry etching and / or wet etching, is performed to remove the protective layer (425). Thus, the dielectric layer (426) of each step (414) may be cut off at the edge of each step (414). In some embodiments, the protective layer (425) is retained.

[0065] Referring to FIG. 6, a method (600) for forming an exemplary stepped structure of a 3D memory device proceeds to step 606, in which a plurality of transverse concave portions are formed in a bridge structure and transverse concave portions are formed from each sacrificial portion. FIG. 4c illustrates a corresponding structure.

[0066] As illustrated in FIG. 4c, a plurality of transverse concave portions (428) may be formed in the bridge structure (408), and A transverse concave portion (418) may be formed from each sacrificial portion (419). In some embodiments, a GLS (e.g., a slit structure, see again the GLS (310) in FIG. 3C) may be formed by contacting a bridge structure (408) before forming the transverse concave portion (428) and the transverse concave portion (418). The GLS may extend in a stepped structure in the xz plane to expose the substrate (402) and the sacrificial / dielectric pair (439 / 436) within the bridge structure (408). The sacrificial layer (439) and the sacrificial portion (419) may be removed through the GLS using an etching process using a suitable etchant such as phosphoric acid. In some embodiments, the etching process includes an isotropic etching process such as wet etching. The etchant removes all sacrificial layers (439) exposed on the sidewalls of the GLS as well as the sacrificial portion (419) in the same etching process, for example, simultaneously. The dielectric layer (436) may be retained. The transverse concave portion (428) may be formed by removing the sacrificial layer (439), and the transverse concave portion (418) may be formed by removing the sacrificial portion (419).

[0067] In some embodiments, if the protective layer (425) is removed prior to the etching process, each transverse concave portion (418) is exposed on the upper surface of each step (414). In some embodiments, if the protective layer (425) is retained, the transverse concave portion (418) is formed beneath each protective layer (425). In some embodiments, the transverse concave portion (418) contacts the second dielectric portion (423) transversely (along the negative y-direction). In some embodiments, the transverse concave portion (418) contacts the dielectric layer (426) underneath it.

[0068] In some embodiments, the etching rate of the sacrificial portion (419) is higher than that of the sacrificial layer (439). The ratio of the etching rate of the sacrificial portion (419) to the sacrificial layer (439) may be in the range of about 5:1 to about 2:1. In some embodiments, the ratio is about 3:1. Because the etching solution approaches the step (406) from the GLS, a portion of the dielectric portion may be over-etched as a result of the higher etching rate of the sacrificial portion (419). The over-etched portion of the dielectric portion may overlap with the step (414) immediately above and correspond to the overlapping portion of the conductor portion formed thereafter (e.g., see again the overlapping portion (320-2) in FIG. 3d). The over-etched portion may be part of the transverse concave portion (418). In some embodiments, the etching time is controlled so that at least a desired portion of the dielectric material (e.g., a desired length along the y-direction) is below each transverse concave portion (418). In some embodiments, the etching time is controlled so that at least a desired portion (e.g., a desired length along the y-direction) of the dielectric material below each transverse concave portion (418) can be retained. The retained dielectric material below the transverse concave portion (418) can form each dielectric structure below the landing area where each word line VIA contact is to be formed (e.g., see FIG. 3a again).

[0069] In some embodiments, a portion of the step (406) below the sacrificial portion (419) may be removed during the etching process. As illustrated in FIG. 4c, the removed portion of the step (406) may include a portion of the dielectric layer (426) below the sacrificial portion (419) (e.g., within the lower step (414)) and a portion of the dielectric layer (426). In some embodiments, the removed portion of the step (406) may nominally have a length (L) along the y-direction and may have the same length as the sacrificial layer (429) along the x-direction. In some embodiments, along the z-direction, if the thickness of the sacrificial portion (419) is less than the thickness of the sacrificial layer (429), the etchant also removes a portion of each of the other initial dielectric portions to form each of the other dielectric portions that are below the transverse concave portion (418) and in contact with the transverse concave portion (418).

[0070] In some embodiments, the insulating structure (450) is formed on the step structure prior to the etching process so that at least the step (406) may be present in the insulating structure (450). The insulating structure (450) may include a suitable dielectric material and may be deposited by any suitable deposition method such as CVD, ALD, and / or PVD. In some embodiments, the insulating structure (450) includes silicon oxide and is deposited by CVD. In some embodiments, if the protective layer (425) is removed before forming the insulating structure (450), the dielectric material may be deposited to contact the sacrificial portion (419) to form the insulating structure (450). In some embodiments, if the protective layer (425) is retained, the deposited dielectric material may accumulate on the protective layer (425). The insulating structure (450) may include the protective layer (425) and any dielectric material deposited on the protective layer. It should be noted that the insulating structure (450) may be formed at any appropriate time after the step (406) is formed and before the word line VIA contact is formed. The specific timing for forming the insulating structure (450) should not be limited by the embodiments of the present disclosure.

[0071] Referring to FIG. 6, a method (600) for forming an exemplary stepped structure of a 3D memory device proceeds to step 608, in which a plurality of conductive layers are formed in a transverse concave portion and a conductive portion is formed in each transverse concave portion. FIG. 4d shows a corresponding structure.

[0072] As illustrated in FIG. 4c, a plurality of conductive layers (430) may be formed in the bridge structure (408), and conductive portions (420) may be formed in each step (414) of the step (406). In some embodiments, a suitable conductive material is deposited by performing a suitable deposition process such as ALD, CVD, and / or PVD to fill the transverse recess (428) and the transverse recess (418) in the same process. The conductive material may fill the transverse recess (428) and the transverse recess (418) from the GLS. The excessively etched portion of each transverse recess (418) may be filled with the conductive material to form an overlapping portion of the conductive portion (420) located directly above the step (414). Other parts of the transverse concave portion (418) may be filled with a conductor to form a non-overlapping portion and other overlapping portions (e.g., refer again to the non-overlapping portion (320-1) and overlapping portion (320-3) of FIG. 3d, respectively), and both the non-overlapping portion and the other overlapping portions are on the upper surface of each step (414). In some embodiments, the conductor material may also form a connecting structure (421) by filling the removed portion of the step (406) below the sacrificial portion (419) (or conductor portion (420)) (see FIG. 3c). The conductor material may include tungsten, or cobalt, or copper, or aluminum, or polysilicon, or doped silicon, or silicide, or any combination thereof.

[0073] As illustrated in FIG. 6, a method (600) for forming an exemplary stepped structure of a 3D memory device proceeds to step 610, in which word line VIA contacts are formed by contacting each conductor portion. FIG. 4e illustrates a corresponding structure.

[0074] As illustrated in FIG. 4e, word line VIA contacts (416) are formed in the insulating structure (450) and contact each conductor portion (420). In some embodiments, the word line VIA contacts (416) are formed over non-overlapping portions of each conductor portion (420). The word line VIA contacts (416) may be formed by patterning the insulating structure (450) to form openings that expose the conductor portions (420) and depositing a suitable conductive material to fill the openings. In some embodiments, the patterning of the insulating structure (450) includes a photolithography process followed by a suitable etching process, e.g., dry etching and / or wet etching. The conductive material includes tungsten, or cobalt, or copper, or aluminum, or polysilicon, or doped silicon, or silicide, or any combination thereof. In some embodiments, after the conductor layer (430) and the conductor portion (420) are formed, the ACS is formed in the GLS.

[0075] An embodiment of the present disclosure provides a 3D memory device. The 3D memory device includes a memory array structure and a step structure. The step structure is located in the middle of the memory array structure and divides the memory array structure into a first memory array structure and a second memory array structure along the transverse direction. The step structure includes a plurality of steps extending along the transverse direction and a bridge structure in contact with the first memory array structure and the second memory array structure. The plurality of steps includes steps on one or more dielectric pairs. The step includes a conductor portion located on the upper surface of the step and in contact with the bridge structure and electrically connected to the bridge structure, and a dielectric portion located at the same level as the conductor portion and in contact with the conductor portion. The step is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure. Along a second transverse direction perpendicular to the transverse direction and away from the bridge structure, the width of the conductor portion decreases.

[0076] In some embodiments, a portion of the conductor overlaps with the upper stairs.

[0077] In some embodiments, the transverse dimension of a portion of the conductor part is reduced along the second transverse direction.

[0078] In some embodiments, a portion of the conductor part has a transverse shape of a right triangle.

[0079] In some embodiments, the steps further include a dielectric layer below the conductor portion and the dielectric portion.

[0080] In some embodiments, the conductor portion and the dielectric layer are each on one or more dielectric pairs.

[0081] In some embodiments, along the transverse direction, the width of another part of the conductor is the same as the dimensions of the stairs.

[0082] In some embodiments, along the second transverse direction, the length of the conductor portion is less than or equal to the second dimension of the step.

[0083] In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

[0084] In some embodiments, the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

[0085] In some embodiments, the bridge structure includes a plurality of interleaved conductor layers in contact with each of the first and second memory array structures. In some embodiments, the conductor portions are electrically connected to each conductor layer by contacting each conductor layer at the same level.

[0086] In some embodiments, each of one or more dielectric pairs includes a dielectric portion corresponding to a lower step and a dielectric layer.

[0087] Embodiments of the present disclosure provide a 3D memory device. The 3D memory device includes a memory array structure and a landing structure in contact with the memory array structure. The landing structure includes a plurality of landing regions at each depth extending along the transverse direction, and a bridge structure in contact with the memory array structure. Each of the plurality of landing regions includes a conductive portion on each upper surface and a dielectric portion at the same level as the conductive portion and in contact with the conductive portion. The conductive portion is electrically connected to the memory array structure through the bridge structure. The width of the conductive portion decreases along a second transverse direction perpendicular to the transverse direction and away from the bridge structure. Each of the plurality of landing regions lies on one or more dielectric pairs.

[0088] In some embodiments, a portion of the conductor overlaps with the upper landing area.

[0089] In some embodiments, the transverse dimension of a portion of the conductor part is reduced along the second transverse direction.

[0090] In some embodiments, a portion of the conductor part has a transverse shape of a right triangle.

[0091] In some embodiments, a plurality of landing regions further include a dielectric layer below the conductor portion and the dielectric portion.

[0092] In some embodiments, the conductor portion and the dielectric layer are each on one or more dielectric pairs.

[0093] In some embodiments, along the transverse direction, the width of different parts of the conductor portion is equal to the dimensions of each landing area.

[0094] In some embodiments, along the second transverse direction, the length of the conductor portion is smaller than or equal to the second dimension of each landing area.

[0095] In some embodiments, the landing structure includes a plurality of steps extending along the transverse direction. In some embodiments, each of the plurality of landing areas is located on the upper surface of each step.

[0096] In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

[0097] In some embodiments, the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

[0098] In some embodiments, the bridge structure includes a plurality of interleaved conductor layers that each contact the memory array structure. In some embodiments, the conductor portions contact each of the second conductors at the same level and are electrically connected to each of the second conductors.

[0099] In some embodiments, each of one or more dielectric pairs includes a dielectric portion and a dielectric layer corresponding to a lower landing region.

[0100] An embodiment of the present disclosure provides a 3D memory device. The 3D memory device includes a memory array structure and a step structure. The step structure includes a plurality of steps extending along a transverse direction. The plurality of steps includes a step having a conductive portion on the upper surface of the step and a dielectric portion that is at the same level as the conductive portion and contacts the conductive portion. The conductive portion is electrically connected to the memory array structure. Along a second transverse direction perpendicular to the transverse direction, the width of the conductive portion varies.

[0101] In some embodiments, a portion of the conductor overlaps with the upper stairs.

[0102] In some embodiments, the transverse dimension of a portion of the conductor part is reduced along the second transverse direction.

[0103] In some embodiments, a portion of the conductor part has a transverse shape of a right triangle.

[0104] In some embodiments, the step structure further includes a dielectric layer below the conductor portion and the dielectric portion.

[0105] In some embodiments, the conductor portion and the dielectric layer are each on one or more dielectric pairs.

[0106] In some embodiments, along the transverse direction, the width of another part of the conductor is the same as the dimensions of the stairs.

[0107] In some embodiments, along the second transverse direction, the length of the conductor portion is less than or equal to the second dimension of the step.

[0108] In some embodiments, the thickness of the conductor portion is less than or equal to the thickness of the dielectric portion along the vertical direction.

[0109] In some embodiments, the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicide, and polysilicon. In some embodiments, the dielectric portion comprises silicon nitride. In some embodiments, the dielectric layer comprises silicon oxide.

[0110] In some embodiments, the 3D memory device further includes a bridge structure in contact with a step structure and a memory array structure. The bridge structure includes a plurality of interleaved conductive layers, each in contact with a memory array structure. A conductive portion contacts one of the conductive layers at the same level and is electrically connected to one of the conductive layers. The step structure is electrically connected to the memory array structure through the bridge structure.

[0111] In some embodiments, each of one or more dielectric pairs includes a dielectric portion corresponding to a lower step and a dielectric layer.

[0112] Embodiments of the present disclosure provide a method for forming a stepped structure of a 3D memory device. The method for forming a stepped structure of a 3D memory device comprises the following steps. First, a plurality of steps are formed having a plurality of first sacrificial layers and a plurality of first dielectric layers interleaved with a plurality of steps. A bridge structure in contact with the plurality of steps is formed, and the bridge structure has a plurality of second sacrificial layers and a plurality of second dielectric layers interleaved with each other. Each first sacrificial layer contacts each second sacrificial layer at the same level, and each first dielectric layer contacts each second dielectric layer at the same level. A sacrificial portion is formed on a first sacrificial layer corresponding to at least one of the steps. The sacrificial portion is on the upper surface of each step and is cut at the edge of the upper step. The second sacrificial layer and the sacrificial portion are removed by the same etching process to form a plurality of transverse concave portions and a transverse concave portion, respectively. A plurality of conductive layers are formed in the transverse concave portions, and a conductive portion is formed in the transverse concave portions and contacts each of the conductive layers.

[0113] In some embodiments, a method for forming a stepped structure of a 3D memory device further includes the step of forming a dielectric portion on each first sacrificial layer. The sacrificial portion is in contact with the sacrificial portion and is at the same level as the sacrificial portion.

[0114] In some embodiments, in the etching process, the etching rate of the sacrificial part is higher than the etching rate of the second sacrificial layer.

[0115] In some embodiments, the ratio of the etching rate of the sacrificial portion to the etching rate of the second sacrificial layer is approximately 3:1.

[0116] In some embodiments, the step of forming a transverse concave portion further includes the step of removing a portion of the dielectric portion below the upper step by an etching process.

[0117] In some embodiments, the step of forming a sacrificial portion includes the step of performing an ion implantation process on at least one exposed portion of the first sacrificial layer to change the etching rate of the exposed portion of the first sacrificial layer in the etching process.

[0118] In some embodiments, the ion implantation process includes a gradient ion implantation process using boron (B).

[0119] In some embodiments, a method for forming a stepped structure of a 3D memory device further includes the step of forming a protective layer on a first sacrificial layer prior to an ion implantation process.

[0120] In some embodiments, the method for forming a stepped structure of a 3D memory device further includes the step of removing a protective layer after an ion implantation process.

[0121] In some embodiments, a method for forming a step structure of a 3D memory device further includes the step of maintaining a first sacrificial layer and a first dielectric layer corresponding to a lower step below a sacrificial portion.

[0122] In some embodiments, a method for forming a step structure of a 3D memory device further includes the step of removing a first sacrificial layer and another part of a first dielectric layer below a sacrificial portion by an etching process.

[0123] In some embodiments, a method for forming a step structure of a 3D memory device further includes the step of forming a slit structure in the step structure and removing a plurality of second sacrificial layers and sacrificial parts through the slit structure.

[0124] In some embodiments, the step of forming a plurality of conductors and conductor portions includes the step of depositing a conductor material to fill the transverse concave portions.

[0125] In some embodiments, the method for forming a step structure of a 3D memory device further includes the step of forming a contact on a conductor portion.

[0126] The foregoing description of specific embodiments will reveal the general nature of the present disclosure so that others may immediately modify and / or adapt various applications, such as specific embodiments, by applying knowledge within the art, without excessive experimentation and without departing from the general concept of the present disclosure. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments based on the teachings and guidelines set forth in this specification. It should be understood that phrases or terms in this specification are for descriptive purposes only and that such terms or phrases should be interpreted by a person skilled in the art in consideration of the teachings and guidelines.

[0127] Embodiments of the present disclosure have been described above with the help of functional building blocks that exemplify the implementation of designated functions and the relationships between these functions. The boundaries of these functional building blocks are arbitrarily defined in this specification for convenience of explanation. Alternative boundaries may be defined as long as the designated functions and their relationships are properly performed.

[0128] The summary and summary section may describe one or more embodiments, but not all exemplary embodiments of the present disclosure, as considered by the inventor, and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0129] The breadth and scope of the present disclosure shall not be limited by any of the exemplary embodiments described above, but shall be defined only by the following claims and their equivalents.

Claims

Claim 1 A three-dimensional (3D) memory device comprising: a memory array structure; and a step structure including a plurality of steps extending along a first transverse direction, wherein the plurality of steps include a step having a conductive portion on the upper surface of the step, the conductive portion is connected to the memory array structure, and the width of the conductive portion differs from each other in a second transverse direction perpendicular to the first transverse direction, and the step further includes a dielectric portion that is at the same level as the conductive portion and contacts the conductive portion, and the step further includes a dielectric layer below the conductive portion and the dielectric portion. Claim 2 A 3D memory device according to claim 1, wherein the thickness of the conductor portion along the vertical direction is less than or equal to the thickness of the dielectric portion. Claim 3 A 3D memory device according to claim 1, wherein the thickness of the dielectric layer is smaller than the dielectric portion. Claim 4 A 3D memory device according to claim 1, wherein the conductor portion and the dielectric layer each have one or more dielectric pairs. Claim 5 A 3D memory device according to claim 1, wherein a portion of the conductor part overlaps with the upper stairs. Claim 6 A 3D memory device according to claim 5, wherein a portion of the conductor part has a transverse shape of a right triangle. Claim 7 A three-dimensional (3D) memory device comprising: a memory array structure; and a step structure including a plurality of steps extending along a first transverse direction, wherein the plurality of steps include a step having a conductive portion on the upper surface of the step, the conductive portion is connected to the memory array structure, and in a second transverse direction perpendicular to the first transverse direction, the width of the conductive portion decreases from top to bottom along the height of the plurality of steps, and the step structure includes a dielectric portion that is at the same level as the conductive portion and contacts the conductive portion, and the step structure further includes a dielectric layer below the conductive portion and the dielectric portion. Claim 8 A 3D memory device according to claim 7, wherein the thickness of the dielectric layer is smaller than the dielectric portion. Claim 9 A 3D memory device according to claim 7, wherein the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicide, or polysilicon, and the dielectric portion comprises silicon nitride. Claim 10 A three-dimensional (3D) memory device comprising: a first memory array structure; a second memory array structure; and a step structure located between the first memory array structure and the second memory array structure, wherein the first memory array structure and the second memory array structure each comprise a plurality of memory cells and are located on one side of the step structure along the transverse direction, and the step structure comprises a plurality of steps extending along the transverse direction and a bridge structure in contact with the first memory array structure and the second memory array structure, and wherein the steps of the plurality of steps include a conductor portion located on the upper layer of the steps and connected to the first memory array structure and the second memory array structure through the bridge structure. Claim 11 A 3D memory device according to claim 10, wherein the conductor portion is connected through the bridge structure to the first word line portion of the first memory array structure and the second word line portion of the second memory array structure which is at the same level as the first word line portion. Claim 12 A 3D memory device according to claim 10, wherein the step is at the same level as the conductor portion and includes a dielectric portion in contact with the conductor portion. Claim 13 A 3D memory device according to claim 12, wherein the length of the conductor portion is smaller than the length of the dielectric portion in a second transverse direction perpendicular to the transverse direction. Claim 14 A 3D memory device according to claim 12, wherein the conductor portion comprises at least one of tungsten, cobalt, copper, aluminum, silicide, or polysilicon, and the dielectric portion comprises silicon nitride. Claim 15 A 3D memory device according to claim 12, wherein the steps further comprise a dielectric layer located below the conductor portion and the dielectric portion and in contact with the conductor portion and the dielectric portion, and the dielectric layer comprises silicon dioxide. Claim 16 A 3D memory device according to claim 11, wherein the bridge structure comprises a plurality of conductive layers, each of which contacts the first word line portion and the second word line portion. Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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