Pipeline clock drive circuit, compute chip, hash board, and compute unit

Abstract

The present disclosure relates to a pipeline clock driving circuit, a computing chip, a hash board, and a computing device. A pipeline clock driving circuit is disclosed, comprising a plurality of stages of clock driving circuits, each stage of which provides a pulse clock signal to a corresponding operation stage of the pipeline, and a clock source connected to the input of a first stage clock driving circuit. Each stage of the clock driving circuit comprises: a first delay submodule including a flip-flop connected to the input of the first stage clock driving circuit, which delays a pulse signal output by the flip-flop and feeds back the delayed pulse clock signal to the flip-flop as a feedback pulse signal; and a combinational logic module that generates a pulse clock signal by performing a combinational logic operation on the pulse signal and the feedback pulse signal and provides the pulse clock signal to a corresponding operation stage. The delay module further comprises a second delay submodule that delays the pulse signal and outputs the delayed pulse signal to the next stage clock driving circuit.

Description

Technology Field

[0001] This application claims priority based on Chinese patent application No. 202310130858.9, filed on February 2, 2023, and the entire contents of said Chinese patent application are incorporated into this application.

[0002] The present disclosure relates to a circuit for performing a hash algorithm. More specifically, it relates to a pipeline clock driving circuit, and to a computing chip, a hash board, and a computing device comprising the pipeline clock driving circuit. Background Technology

[0003] Chips used for virtual currency production typically have a pipeline structure containing multiple computational stages. Depending on the algorithm used, the computational logic can be divided into several stages, and each stage may have a similar functional design and computational structure. In particular, when a latch is used as a timing device in each operation stage of the pipeline, the latch in each operation stage requires a single working clock (i.e., a pulse clock). Therefore, for each operation stage, a single pulse clock is input through a corresponding clock driving circuit. Generally, the working clock used in each operation stage originates from the same clock source, and the clock signal generated by that clock source is transmitted step by step through the pipeline clock driving circuit.

[0004] The basic principle for generating the working clock used by the latch for each operation stage is to input two signals—the input clock signal of the current stage's clock drive circuit and a delayed input clock signal—into a gate circuit (e.g., NOR gate, NAND gate, etc.) to generate a pulse clock; the delayed input clock signal is generated after the input clock signal passes through a delay module. The width of the pulse clock is fundamentally determined by the delay time of the delay module. Additionally, the delayed input clock signal is output to the next stage's clock drive circuit as the input clock signal for the next stage's clock drive circuit. Consequently, the width of the generated pulse clock and the delay between the input clock signals of two adjacent stages' clock drive circuits are identical; that is, the width of the pulse clock and the delay between the pulse clocks of two adjacent operation stages are identical. The problem to be solved

[0005] The object of the present disclosure is to provide an improved pipeline clock drive circuit. means of solving the problem

[0006] According to one aspect of the present disclosure, each stage of a clock driving circuit provides a pulse clock signal to a corresponding operation stage among a plurality of operation stages of a pipeline, and comprises a clock source connected to the input of a first stage clock driving circuit to provide a basic clock signal, wherein the input of each stage clock driving circuit other than the first stage clock driving circuit among the plurality of stage clock driving circuits is connected to the output of a previous stage clock driving circuit, and each stage of the clock driving circuit comprises a flip-flop connected to the input of the current stage clock driving circuit; A pipeline clock driving circuit for providing a pulse clock signal to a pipeline comprising a plurality of operation stages is provided, the pipeline comprising a plurality of operation stages, the pipeline comprising a pipeline clock driving circuit for providing a pulse clock signal, the pipeline comprising a pipeline comprising a plurality of operation stages, the pipeline comprising a

[0007] According to another aspect of the present disclosure, a computing chip comprising one or more of the pipeline clock driving circuits is provided.

[0008] According to another aspect of the present disclosure, a hash board using one or more of the above-mentioned computing chips is provided.

[0009] According to another aspect of the present disclosure, a computing device comprising one or more of the hash boards is provided.

[0010] Other features and advantages of the present disclosure will become clear from the description below with reference to the drawings. Brief explanation of the drawing

[0011] The included drawings are for illustrative purposes only and are intended to provide examples of possible structures and arrangements of the inventive device disclosed herein and the method of applying it to a computing device. These drawings do not limit any modifications in form and detail that can be made to the embodiment by those skilled in the art, provided that they do not depart from the nature and scope of the embodiment. The embodiment will be more easily understood through the following detailed description with reference to the drawings, and similar reference numerals indicate similar components. Figure 1 is a schematic diagram of a pipeline clock driving circuit of the related technology. FIG. 2A is a schematic diagram of a pipeline clock driving circuit according to one embodiment of the present disclosure. FIG. 2B is a timing diagram of a pulse clock signal generated by a pipeline clock driving circuit according to one embodiment of the present disclosure. FIG. 3A is a schematic diagram of a pipeline clock driving circuit according to another embodiment of the present disclosure. FIG. 3B is a timing diagram of a pulse clock signal generated by a pipeline clock driving circuit according to another embodiment of the present disclosure. FIG. 4 is a schematic diagram of a delay module of a pipeline clock driving circuit according to one embodiment of the present disclosure. FIG. 5 is a schematic diagram of a delay module of a pipeline clock driving circuit according to another embodiment of the present disclosure. Please note that in the embodiments described below, if the same reference numerals are used between different drawings to denote the same part or part having the same function, redundant descriptions are omitted. In this specification, similar items are indicated using similar reference numerals and characters; therefore, once an item is defined in one drawing, there is no need to discuss it further in subsequent drawings. For ease of understanding, the location, size, and scope of each structure depicted in the drawings may not represent the actual location, size, and scope. Accordingly, the described invention is not limited to the location, size, and scope disclosed in the drawings. Furthermore, the drawings are not necessarily drawn in proportion, and some features may be exaggerated to show details of specific elements. Specific details for implementing the invention

[0012] The output signal (S204) of the sub-module (242-1) is changed to a high level. After that, after T2 elapsed from time t5 (at which time the signal (S202) is changed to a high level), the output signal (S204) of the second delay sub-module (242-1) is changed to a low level.

[0013] Thus, a pulse clock signal (S205) with a period of T and a pulse width of T1 is generated at the output terminal of the combinational logic module (250-1). The pulse clock signal (S205) is provided as a work clock to the corresponding operation step (201-N).

[0014] Additionally, at the output terminal of the second delay sub-module (242-1), a clock driving signal (S204) is generated as an input circuit for the next stage clock driving circuit (corresponding to the input signal (S201) of the first stage clock driving circuit (220-1). The rising edge of the clock driving signal (S204) triggers the flip-flop of the next stage clock driving circuit. As shown in FIG. 2B, the rising edge of the clock driving signal (S204) is delayed by T2 compared to the rising edge of the input signal (S201). Correspondingly, the pulse clock signal generated by each stage clock driving circuit is all delayed by T2 compared to the pulse clock signal generated by the previous stage clock driving circuit.

[0015] In the example illustrated in FIG. 2B, the time interval T1 is longer than T2, which means that the pulse width (T1) of the pulse clock signal (S205) generated by one stage clock driving circuit is greater than the delay time (T2) between the rising edges of the input clocks (i.e., S201 and S204) of two adjacent stages clock driving circuits, that is, the pulse width of the pulse clock signal is greater than the delay between the pulse clock signals of two adjacent operation stages. However, in another embodiment, the time interval T1 may be shorter than T2, which means that the pulse width of the pulse clock signal is smaller than the delay between the pulse clock signals of two adjacent operation stages.

[0016] Thus, the pulse width of the pulse clock signal and the delay between the pulse clock signals of two adjacent computation stages are respectively set according to actual demand, thereby allowing computational efficiency to be maximized and system performance to be optimized by more precisely controlling and optimizing the pulse clock signals of the pipeline.

[0017] FIG. 3A is a schematic diagram of a pipeline clock driving circuit (300) according to another embodiment of the present disclosure. FIG. 3B is a timing diagram of a pulse clock signal generated by the pipeline clock driving circuit (300).

[0018] The pipeline clock driving circuit (300) is intended to provide a pulse clock signal to a pipeline (301) comprising a plurality of operation stages (301-1, …, 301-N). As illustrated in FIG. 3A, the pipeline clock driving circuit (300) includes a clock source (310) and a plurality of clock driving circuits (320-1, …, 320-N).

[0019] The clock source (310) is connected to the input of the first stage clock driving circuit (320-1) to provide a basic clock signal. Among the multiple stage clock driving circuits (320-1, …, 320-N), the input of the other stage clock driving circuit, excluding the first stage clock driving circuit (320-1), is connected to the output of the previous stage clock driving circuit, and each stage clock driving circuit (320-1, …, 320-N) provides a pulse clock signal to a corresponding operation stage among the multiple operation stages (301-N, …, 301-1) of the pipeline (310).

[0020] Here, the clock driving circuit (320-1, …, 320-N) of each stage includes a flip-flop (330-1, …, 330-N), a delay module (340-1, …, 340-N), and a combinational logic module (350-1, …, 350-N).

[0021] The flip-flops (330-1, …, 330-N) are connected to the input of the current stage clock driving circuit. That is, the flip-flop (330-1) of the first stage clock driving circuit (320-1) is connected to the output of the clock source (310), and the flip-flop of the other stage clock driving circuit is connected to the output of the previous stage clock driving circuit.

[0022] FIG. 3A illustrates an embodiment in which the flip-flops (330-1, …, 330-N) are falling-edge D flip-flops. In the embodiment illustrated in FIG. 3A, the RESET terminal of the flip-flops (330-1, …, 330-N) is connected to the output of the delay module (340-1, …, 340-N), the D terminal is fixed at a high level (i.e., logic "1"), the CPN terminal is connected to the output of the previous stage clock drive circuit, and the output terminal (Q) is connected as an input to the delay module (340-1, …, 340-N). When the RESET terminal signal of the falling-edge D flip-flop is at a low level, the output terminal (Q) remains at a low level. When the signal of the RESET terminal is at a high level, whenever the falling edge of the CPN terminal signal is reached, the output terminal (Q) changes to the signal value of the D terminal.

[0023] The input of the delay module (340-1, …, 340-N) is connected to the output of the flip-flop (330-1, …, 330-N). The delay module (340-1, …, 340-N) includes a first delay sub-module (341-1, …, 341-N) which is connected to the output of the flip-flop (330-1, …, 330-N) to delay the pulse signal output by the flip-flop (330-1, …, 330-N) and feed back the delayed pulse signal to the flip-flop (330-1, …, 330-N) as a feedback pulse signal.

[0024] In a clock driving circuit of a different stage other than the last stage clock driving circuit (320-N) among a plurality of stage clock driving circuits (320-1, …, 320-N), the delay module (340-1, …) includes a second delay sub-module (342-1, …) connected to the output of a flip-flop (330-1, …) to delay the pulse signal output by the flip-flop (330-1, …) and output the delayed pulse signal as a clock driving signal to the next stage clock driving circuit.

[0025] In a preferred embodiment, the first delay submodule (341-1, …, 341-N) and the second delay submodule (342-1, …) each invert the phase of the pulse signal output by the flip-flop (330-1, …, 330-N). In a preferred embodiment, the first delay submodule (341-1, …, 341-N) and the second delay submodule (342-1, …) each delay the pulse signal output by the flip-flop (330-1, …, 330-N) differently. In a more preferred embodiment, the delay time of the first delay submodule (341-1, …, 341-N) for the pulse signal output by the flip-flop (330-1, …, 330-N) may be longer than the delay time of the second delay submodule (342-1, …) for the pulse signal output by the flip-flop (330-1, …).

[0026] The first delay sub-module (341-1, …, 341-N) and the second delay sub-module (342-1, …) may be implemented by several buffers and / or inverters. In a preferred embodiment, as shown in FIG. 3A, the first delay sub-module (341-1, …, 341-N) and the second delay sub-module (342-1, …) may each be composed of an odd number of inverters. In another embodiment, the first delay sub-module (341-1, …, 341-N) and the second delay sub-module (342-1, …) may be composed of several buffers and an odd number of inverters. In another preferred embodiment, the number of inverters constituting the first delay sub-module (341-1, …, 341-N) may be greater than the number of inverters constituting the second delay sub-module (342-1, …).

[0027] The combinational logic module (350-1, …, 350-N) is connected to the outputs of the flip-flop (330-1, …, 330-N) and the first delay sub-module (341-1, …, 341-N). The combinational logic module (350-1, …, 350-N) generates a pulse clock signal by performing combinational logic operations on the pulse signal output by the flip-flop (330-1, …, 330-N) and the delayed pulse signal (feedback pulse signal) output by the first delay sub-module (341-1, …, 341-N), and provides this to the corresponding operation stage (301-N, …, 301-1) of the pipeline (301). In the embodiment illustrated in FIG. 3A, when the flip-flops (330-1, …, 330-N) are falling-edge D flip-flops, the combinational logic module (350-1, …, 350-N) can be composed of NAND gates.

[0028] Referring to FIG. 3B, the sequence for generating a pulse clock signal is explained using the first stage clock driving circuit (320-1) as an example.

[0029] The CPN terminal of the flip-flop (330-1) receives a basic clock signal (S301) as an input signal from the clock source (310) (correspondingly, the CPN terminal of each subsequent stage flip-flop receives a clock driving signal (S304) as an input signal from the output of the second delay sub-module of the previous stage clock driving circuit), and provides a pulse signal (S302) from the output terminal (Q) to one input terminal of the delay module (340-1) and the combinational logic module (350-1) (a NAND gate in this embodiment). The first delay sub-module (341-1) of the delay module (340-1) inverts and delays the pulse signal (S302) to obtain a feedback pulse signal (S303) and provides it to the RESET terminal of the flip-flop (330-1) and the other input terminal of the combinational logic module (350-1). The second delay sub-module (342-1) of the delay module (340-1) inverts and delays the pulse signal (S302) to obtain a clock driving signal (S304) and outputs it to the clock driving circuit of the subsequent stage as an input signal to the clock driving circuit of the subsequent stage. The combinational logic module (350-1) receives the signal (S302) and the signal (S303) as inputs, obtains the output pulse clock signal (S305), and outputs the pulse clock signal (S305) to the operation stage (301-N).

[0030] After the entire system is turned on, if the clock source (310) has not yet output the basic clock signal (S301), the pulse signal (S302) at the output terminal (Q) of the flip-flop (330-1) will stabilize at a low level. The output signal (S303) of the first delay sub-module (341-1) will stabilize at a high level. That is, the RESET terminal of the flip-flop (330-1) is at a high level, and the input signal of the clock driving circuit of the subsequent stage is also at a high level (corresponding to the input signal (S301) of the first stage clock driving circuit (320-1)). Accordingly, the input signals of the combinational logic module (350-1) (NAND gate) are at a low level (S302) and a high level (S303), respectively, and the output pulse clock signal (S305) is at a high level.

[0031] At time t1, the clock source (310) starts outputting the basic clock signal (S301). The period of the basic clock signal (S301) is T.

[0032] As illustrated in FIG. 3B, when the signal (S301) changes from a high level to a low level, the falling edge of the signal is reached at the CPN terminal of the flip-flop (330-1), and since the RESET terminal signal (S303) remains at a high level, the signal (S302) at the output terminal (Q) of the flip-flop (330-1) changes to the signal value of the D terminal, i.e., a high level. Therefore, the input signals of the combinational logic module (350-1) (NAND gate) are at a high level (S302) and a high level (S303), respectively, and the output pulse clock signal (S305) is at a low level.

[0033] After T1, at time t2, the output signal (S303) of the first delay submodule (341-1) is at a low level. T1 is the delay between the signal (S303) and the signal (S302), and is determined by the arrangement of the first delay submodule (341-1). In the embodiment illustrated in FIG. 3A, T1 is the sum of the delay times of a plurality of flip-flops of the first delay submodule (341-1).

[0034] Accordingly, as illustrated in FIG. 3B, in one aspect, the RESET terminal of the flip-flop (330-1) is changed to a low level, and the signal (S302) of the output terminal (Q) of the flip-flop (330-1) is changed to a low level. In another aspect, the input signals of the combinational logic module (350-1) (NAND gate) are low level (S302) and low level (S303), respectively, and the output pulse clock signal (S305) is high level.

[0035] Again, after T1 has passed, at time t3, the output signal (S303) of the first delay submodule (341-1) is at a high level.

[0036] Accordingly, as illustrated in FIG. 3B, in one aspect, the RESET terminal of the flip-flop (330-1) changes to a high level, but since the signal falling edge has not yet reached the CPN terminal, the signal (S302) of the output terminal (Q) of the flip-flop (330-1) remains at a high level. In another aspect, the input signals of the combinational logic module (350-1) (NAND gate) are at a low level (S302) and a high level (S303), respectively, and the output pulse clock signal (S305) is at a high level.

[0037] In another aspect, after T2 elapsed from time t1 (at which time the signal (S302) is changed to a high level), the output signal (S304) of the second delay submodule (342-1) is changed to a low level. Subsequently, after T2 elapsed from time t2 (at which time the signal (S302) is changed to a low level), the output signal (S304) of the second delay submodule (342-1) is changed to a high level. T2 is the delay between the signal (S304) and the signal (S302) and is determined by the arrangement of the second delay submodule (342-1). In the embodiment illustrated in FIG. 3A, T2 is the sum of the delay times of a plurality of flip-flops of the second delay submodule (342-1).

[0038] Afterwards, the values ​​of the signals (S302, S303, S304, S305) remain unchanged. At time t4, the next cycle of the basic clock signal (S301) begins. One cycle (T) of the basic clock signal (S301) elapses from time t1 to time t4.

[0039] At time t4, the signal (S301) changes to a low level.

[0040] As illustrated in FIG. 3B, when the signal (S301) changes from a high level to a low level, a signal falling edge is reached at the CPN terminal of the flip-flop (330-1), and the signal (S302) at the output terminal (Q) of the flip-flop (330-1) becomes a high level. Therefore, the pulse clock signal (S305) at the output terminal of the combinational logic module (350-1) (NAND gate) changes to a low level.

[0041] After T1, at time t5, the output signal (S303) of the first delay submodule (341-1) is at a low level.

[0042] Accordingly, as illustrated in FIG. 3B, in one aspect, the RESET terminal of the flip-flop (330-1) is changed to a low level, and the signal (S302) of the output terminal (Q) of the flip-flop (330-1) is changed to a low level. In another aspect, the pulse clock signal (S305) of the output terminal of the combinational logic module (350-1) is changed to a high level.

[0043] Again, after T1 has passed, at time t6, the output signal (S303) of the first delay submodule (341-1) changes to a high level.

[0044] Therefore, as shown in FIG. 3B, the signal (S302) of the output terminal (Q) of the flip-flop (330-1) remains at a low level, and the pulse clock signal (S305) of the output terminal of the combinational logic module (350-1) remains at a high level.

[0045] In another aspect, after T2 elapsed from time t4 (at this time, the signal (S302) is changed to a high level), the output signal (S304) of the second delay submodule (342-1) is changed to a low level. Subsequently, after T2 elapsed from time t5 (at this time, the signal (S302) is changed to a low level), the output signal (S304) of the second delay submodule (342-1) is changed to a high level.

[0046] Thus, a pulse clock signal (S305) with a period of T and a pulse width of T1 is generated at the output terminal of the combinational logic module (350-1). The pulse clock signal (S305) is provided as a work clock to the corresponding operation step (301-N).

[0047] Additionally, at the output terminal of the second delay sub-module (342-1), a clock driving signal (S304) is generated as an input signal for the next stage clock driving circuit (corresponding to the input signal (S301) of the first stage clock driving circuit (320-1). The falling edge of the clock driving signal (S304) triggers the flip-flop of the next stage clock driving circuit. As shown in FIG. 3B, the falling edge of the clock driving signal (S304) is delayed by T2 compared to the falling edge of the input signal (S301). Correspondingly, the pulse clock signal generated by each stage clock driving circuit is all delayed by T2 compared to the pulse clock signal generated by the previous stage clock driving circuit.

[0048] As described above, the pulse width of the pulse clock generated by the pipeline clock driving circuit according to the present disclosure is determined by the time T1 that the first delay submodule delays, and the delay between the pulse clocks of two adjacent operation stages is determined by the time T2 that the second delay submodule delays. In a preferred embodiment, the first delay submodule and the second delay submodule are composed of inverters. The longer the delay time to be used, the greater the number of inverters required. To further optimize the circuit and reduce the number of inverters used, the present disclosure provides an improved delay module.

[0049] FIG. 4 is a schematic diagram of a delay module (440) of a pipeline clock driving circuit according to one embodiment of the present disclosure.

[0050] The input of the delay module (440) is connected to a pulse signal (S402) output by a flip-flop (not shown). The delay module (440) includes a first delay sub-module (441) and a second delay sub-module (442). At this time, the first delay sub-module (441) delays the signal (S402) and feeds back the delayed pulse signal (S403) to the flip-flop as a feedback pulse signal. The second delay sub-module (442) delays the signal (S402) and outputs the delayed pulse signal (S404) as a clock driving signal to the next stage clock driving circuit. At this time, some of the plurality of inverters constituting the first delay sub-module (441) constitute the second delay sub-module (442), so that the time T1 delayed by the first delay sub-module becomes longer than the time T2 delayed by the second delay sub-module. In another embodiment, some of the plurality of inverters constituting the second delay sub-module constitute the first delay sub-module, so that the time T2 delayed by the second delay sub-module is longer than the time T1 delayed by the first delay sub-module.

[0051] In the delay module (440) shown in Fig. 4, the inverter in the circuit is utilized more effectively, reducing the number of inverters used.

[0052] In the implementation of the process, it is expected that the operating frequency of the pipeline can be maximized while each parameter satisfies actual requirements by flexibly adjusting the delay of the delay module. To this end, the present disclosure provides an improved pipeline clock driving circuit in which the number of inverters constituting the delay module can be flexibly adjusted.

[0053] FIG. 5 is a schematic diagram of a delay module (540) of a pipeline clock driving circuit according to another embodiment of the present disclosure.

[0054] The input of the delay module (540) is connected to a pulse signal (S502) output by a flip-flop (not shown). The delay module (540) includes a first delay sub-module (541) and a second delay sub-module (542). At this time, the first delay sub-module (541) delays the signal (S502) and feeds back the delayed pulse signal (S503) to the flip-flop as a feedback pulse signal. The second delay sub-module (542) delays the signal (S502) and outputs the delayed pulse signal (S504) as a clock driving signal to the next stage clock driving circuit.

[0055] At this time, the first delay sub-module (541) and the second delay sub-module (542) are each composed of a plurality of inverters and one or more data selectors, and one or more of the data selectors cause the inverters of the first delay sub-module (541) and the second delay sub-module (542) to form signal channels including a different number of inverters, and the number of inverters in each signal channel of the first delay sub-module (541) and the second delay sub-module (542) is odd.

[0056] In the embodiment illustrated in FIG. 5, the first delay submodule (541) is composed of three data selectors and several inverters forming four signal channels, and the second delay submodule (542) is composed of six data selectors and several inverters forming sixteen signal channels. Accordingly, in the embodiment illustrated in FIG. 5, by changing the state of the data selectors, each of the signals (S503) and (S504) can be adjusted with respect to the signal (S502), thereby allowing adjustment of the pulse width of the generated clock pulse signal and the delay between the clock pulse signals of two adjacent operation stages.

[0057] Thus, the delay of the delay module can be flexibly and easily adjusted according to actual work demand, thereby improving the efficiency and accuracy of chip operations.

[0058] In a preferred embodiment, the first delay submodule (541) (indicated by a dotted line) and the second delay submodule (542) (indicated by a dashed line) may jointly include a common delay submodule (543) (indicated by a solid line) composed of a plurality of inverters and one or more data selectors. In this case, at least one of the first delay submodule (541) and the second delay submodule (542) further includes a plurality of inverters connected in series with the common delay submodule (543). In the embodiment illustrated in FIG. 5, the common delay submodule (543) is composed of 12 inverters and 4 data selectors, and the first delay submodule (541) and the second delay submodule (542) each further include a plurality of inverters connected in series with the common delay submodule (543). This allows for better utilization of the inverters and data selectors within the circuit and reduces the number of circuit elements used.

[0059] The configuration of the delay module (54) illustrated in FIG. 5 is merely an example. In another embodiment, the delay module (540) and its first delay sub-module (541) and second delay sub-module (542) (and any joint delay sub-module (543)) are configured in any appropriate arrangement with any appropriate number of inverters and data selectors to form a plurality of signal channels, so that each signal channel includes an appropriate number of inverters. In a preferred embodiment, the number of inverters in each signal channel is different.

[0060] The computational circuit according to the present disclosure may be implemented in various suitable ways, such as software, hardware, or a combination of software and hardware. In one embodiment, the computational chip may include one or more of the pipeline clock driving circuits. In one embodiment, the hash board may include one or more computational chips. In one embodiment, the computational device may include one or more hash boards. A plurality of hash boards may perform computational tasks in parallel.

[0061] In all examples illustrated and described in the text, any specific value should be interpreted as merely illustrative and not restrictive. Accordingly, other examples of exemplary embodiments may have different values.

[0062] In addition, it will be understood that when the word “include” is used in the text, it describes the presence of the mentioned features, whole, steps, operations, units and / or elements, and is not intended to exclude one or more other features, wholes, steps, operations, units and / or elements and / or combinations thereof.

[0063] Although some specific embodiments of the present disclosure have already been described in detail through the examples, it will be understood by those skilled in the art that the examples are for illustrative purposes only and not intended to limit the scope of the present disclosure. It will be understood by those skilled in the art that the foregoing embodiments may be modified without departing from the scope and essence of the present disclosure. The scope of the present disclosure is defined by the claims set forth below.

Claims

Claim 1 A pipeline clock driving circuit for providing a pulse clock signal to a pipeline comprising a plurality of operation stages, wherein the pipeline clock driving circuit comprises: a plurality of stage clock driving circuits configured such that each stage of the clock driving circuit provides a pulse clock signal to a corresponding operation stage among the plurality of operation stages of the pipeline; and a clock source configured to provide a basic clock signal and connected to the input of a first stage clock driving circuit, wherein the input of each stage clock driving circuit other than the first stage clock driving circuit among the plurality of stage clock driving circuits is connected to the output of a previous stage clock driving circuit, and each stage of the clock driving circuit comprises: a flip-flop connected to the input of the current stage clock driving circuit; and a delay module comprising a first delay sub-module connected to the output terminal of the flip-flop to delay a pulse signal output by the flip-flop and feed back the delayed pulse signal to the flip-flop as a feedback pulse signal. A pipeline clock driving circuit comprising a combinational logic module connected to the output of the flip-flop and the first delay submodule, and generating a pulse clock signal by performing a combinational logic operation on a pulse signal output by the flip-flop and a feedback pulse signal output by the first delay submodule and providing the pulse clock signal to a corresponding operation stage of the pipeline, wherein in each stage clock driving circuit other than the last stage clock driving circuit among the plurality of stage clock driving circuits, the delay module further comprises a second delay submodule connected to the output of the flip-flop to delay the pulse signal output by the flip-flop and outputting the delayed pulse signal as a clock driving signal to the next stage clock driving circuit, wherein the pulse width of the pulse clock signal generated by the pipeline clock driving circuit is determined by the time the first delay submodule delays, and the delay between pulse clock signals of two adjacent operation stages is determined by the time the second delay submodule delays. Claim 2 A pipeline clock driving circuit according to claim 1, wherein the flip-flop is a rising-edge flip-flop. Claim 3 In paragraph 2, the combinational logic module is a pipeline clock driving circuit that is an OR gate or a NOR gate. Claim 4 A pipeline clock driving circuit according to claim 1, wherein the flip-flop is a falling-edge flip-flop. Claim 5 In paragraph 4, the combinational logic module is a pipeline clock driving circuit that is an AND gate or a NAND gate. Claim 6 A pipeline clock driving circuit according to claim 1, wherein the first delay submodule and the second delay submodule are each composed of an odd number of inverters. Claim 7 A pipeline clock driving circuit according to claim 6, wherein some of the plurality of inverters constituting the first delay sub-module constituting the second delay sub-module, or some of the plurality of inverters constituting the second delay sub-module constituting the first delay sub-module. Claim 8 A pipeline clock driving circuit according to claim 1, wherein the first delay submodule and the second delay submodule are each composed of a plurality of inverters and one or more data selectors, and the one or more data selectors cause the inverters of the first delay submodule and the second delay submodule to each form a plurality of signal channels including a different number of inverters, and the number of inverters in each signal channel of the first delay submodule and the second delay submodule is odd. Claim 9 A pipeline clock driving circuit according to claim 8, wherein the first delay submodule and the second delay submodule commonly comprise a common delay submodule composed of a plurality of inverters and one or more data selectors, and at least one of the first delay submodule and the second delay submodule further comprises a plurality of inverters connected in series with the common delay submodule. Claim 10 A computing chip comprising one or more pipeline clock driving circuits according to any one of claims 1 to 9. Claim 11 A hash board comprising one or more computation chips according to paragraph 10. Claim 12 A computing device comprising one or more hash boards according to paragraph 11.

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