3D NAND memory and method of manufacturing the same

Abstract

The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method comprises the step of placing alternating dielectric stacks on a substrate, wherein the alternating dielectric stacks include a first dielectric layer and a second dielectric layer alternately stacked on the substrate. The method further comprises the step of forming a channel structure that penetrates the alternating dielectric stacks and extends into the substrate, wherein the channel structure includes a channel layer placed on the sidewall of a memory film. The method further comprises the step of removing a portion of the substrate and a portion of the memory film extending into the substrate so as to expose a portion of the channel layer, and the step of placing an array common source (ACS) on the exposed portion of the channel layer.

Description

Technology Field

[0001] The present disclosure generally relates to the field of semiconductor technology, and more specifically, to a three-dimensional NAND flash memory and a method for manufacturing the same. Background Technology

[0002] As memory devices shrink to smaller die sizes to reduce manufacturing costs and increase storage density, the scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] In 3D NAND flash memory, multiple layers of memory cells can be stacked vertically, which can significantly increase storage density per unit area. Storage capacity can be further increased by substantially increasing the number of vertically stacked layers. However, manufacturing high aspect ratio structures is very difficult. For example, channel holes may be etched through the stacked structure, and the memory film and channel layer may be positioned on the sidewalls of the channel holes. To form a source contact on the channel layer, it is necessary to remove the memory film located at the bottom of the channel hole. However, there is a problem in removing the memory film from the bottom of the channel hole without damaging the channel layer on the sidewall. Pinholes in the channel layer cause reliability issues and reduce product yield. Therefore, there is a need to provide a method for forming a source contact on the channel layer.

[0004] In this disclosure, embodiments of a three-dimensional (3D) memory device and a method for forming the same are described.

[0005] One aspect of the present disclosure provides a method for forming a three-dimensional (3D) memory device. The method comprises the steps of: sequentially forming a first etching stop layer, a second etching stop layer, and alternating dielectric stacks on a substrate; forming a channel hole that penetrates the alternating dielectric stacks and extends into the substrate; placing a memory film and then a channel layer on the sidewall of the channel hole to form a channel structure; removing the substrate and stopping on the first etching stop layer to expose a portion of the memory film extending into the substrate; removing the first etching stop layer and the exposed portion of the memory film and stopping on the second etching stop layer to expose a portion of the channel layer extending into the substrate; and forming an array common source (ACS) on the back side of the second etching stop layer separated from the alternating dielectric stacks to cover the exposed portion of the channel layer.

[0006] In some embodiments, the first etching stop layer comprises silicon oxide and the second etching stop layer comprises polycrystalline silicon.

[0007] In some embodiments, the substrate comprises a handle wafer, an insulator layer (e.g., a sacrificial silicon oxide layer), and a semiconductor layer (e.g., a sacrificial polycrystalline silicon layer).

[0008] In some embodiments, removing the substrate and stopping on the first etching stop layer includes removing the substrate by wet etching.

[0009] In some embodiments, removing the exposed portion of the first etching stop layer and the memory film includes removing the exposed portion of the first etching stop layer and the memory film by wet etching.

[0010] In some embodiments, the alternating dielectric stacks include a stepped region, and the method also includes forming a dummy channel hole in the stepped region, wherein the dummy channel hole penetrates at least a portion of the alternating dielectric stacks and extends into a substrate.

[0011] In some embodiments, the alternating dielectric stack comprises an alternatingly stacked first dielectric layer and a second dielectric layer (i.e., a sacrificial layer). Additionally, the method comprises the steps of: forming a slit opening that penetrates the alternating dielectric stack and extends into a substrate—the slit opening being located away from the channel structure—; removing the sacrificial layer through the slit opening to form a transverse tunnel; forming a conductive layer within the transverse tunnel; and placing an insulating material within the slit opening to form a slit structure.

[0012] In some embodiments, the step of forming a conductive layer within a transverse tunnel includes placing a gate dielectric layer on the sidewalls and slit openings of the transverse tunnel; and placing a gate adhesive layer on the gate dielectric layer within the transverse tunnel.

[0013] In some embodiments, the substrate further comprises a peripheral region covered with an insulating layer. The method also comprises forming a through-silicon via (TSV) in the peripheral region that penetrates the front insulating layer and extends into the substrate.

[0014] In some embodiments, the formation of the TSV includes the formation of a TSV interface layer covering the sidewalls of the TSV.

[0015] In some embodiments, the method also includes sequentially removing a substrate and a first etching stop layer through a wet etching process to expose a portion of a dummy channel hole extending into the substrate, a portion of a slit structure extending into the substrate, and a portion of a TSV extending into the substrate.

[0016] In some embodiments, forming an ACS on the back side of the second etching stop layer includes positioning the ACS to cover an exposed portion of a dummy channel hole extending into the substrate, an exposed portion of a slit structure extending into the substrate, and an exposed portion of a TSV extending into the substrate.

[0017] In some embodiments, forming the ACS further comprises: placing a first polycrystalline silicon layer on the back side of a second etching stop layer; doping and annealing the first polycrystalline silicon layer; placing a second polycrystalline silicon layer on the back side of the first polycrystalline silicon layer separated from an alternating dielectric stack; and doping and annealing the second polycrystalline silicon layer.

[0018] In some embodiments, the method further comprises forming an interlayer dielectric layer on the back side of an ACS separated from an alternating dielectric stack.

[0019] In some embodiments, forming an interlayer dielectric layer comprises: forming a dielectric filled layer on the back side of an ACS separated from an alternating dielectric stack; forming a back side deep trench insulation (BDTI) penetrating the ACS on the dielectric filled layer; removing a portion of the dielectric filled layer corresponding to a channel structure to form a first contact opening and expose the ACS; and removing a portion of the dielectric filled layer corresponding to a TSV to form a second contact opening and expose the TSV.

[0020] In some embodiments, this method also includes forming a back interconnect layer separated from an alternating dielectric stack on an interlayer dielectric layer.

[0021] In some embodiments, forming a back interconnect layer comprises: placing a conductive material inside a first contact opening and a second contact opening, and covering the back surface of an interlayer dielectric layer separated from an alternating dielectric stack to form an ACS contact structure inside the first contact opening and a TSV contact structure inside the second contact opening; and forming an insulating gap between the ACS contact structure and the TSV contact structure.

[0022] Another aspect of the present disclosure provides a three-dimensional (3D) memory device. The three-dimensional memory device comprises an array common source (ACS); a film stack in which a conductive layer and a dielectric layer are alternately stacked and provided on a first side of the ACS; and a channel structure that penetrates the film stack and extends into the ACS. Each channel structure comprises a core filling film; a channel layer covering the sidewall of the core filling film; and a memory film disposed on a portion of the channel layer penetrating the film stack. The ACS surrounds a portion of the channel layer extending from the film stack into the ACS, so that the ACS is in contact with the portion of the channel layer extending from the film stack into the ACS.

[0023] In some embodiments, the ACS comprises a p-type or n-type doped polycrystalline silicon layer.

[0024] In some embodiments, a film stack in which a conductive layer and a dielectric layer are alternately stacked includes a stepped region.

[0025] In some embodiments, the 3D memory device also includes a dummy channel hole that penetrates at least a portion of the membrane stack and extends into the ACS. The ACS surrounds the portion of the dummy channel hole extending from the membrane stack into the ACS.

[0026] In some embodiments, the 3D memory device also includes a slit structure (i.e., a gate line slit) that penetrates the film stack and extends into the ACS. The slit structure is located away from the channel structure, and the ACS surrounds a portion of the slit structure extending from the film stack into the ACS.

[0027] In some embodiments, the slit structure includes a gate dielectric layer disposed on the sidewall of the slit structure.

[0028] In some embodiments, the film stack also includes a gate dielectric layer covering the sidewalls of the conductive layer. The film stack also includes a gate adhesive layer disposed between the gate dielectric layer and the conductive layer.

[0029] In some embodiments, the 3D memory device also includes a peripheral region covered with an insulating layer. The peripheral region is located on the front side of the ACS close to the film stack. Additionally, the 3D memory device also includes a through-silicon via (TSV) penetrating the insulating layer in the peripheral region. The TSV is not in contact with the ACS.

[0030] In some embodiments, the TSV includes a TSV interface layer.

[0031] In some embodiments, the 3D memory device also includes an interlayer dielectric layer on the back side of the ACS separated from the film stack.

[0032] In some embodiments, the interlayer dielectric layer includes back-side deep trench insulation (BDTI) penetrating the ACS in the region having TSVs.

[0033] In some embodiments, the 3D memory device also includes a back-side interconnect layer on the back side of an interlayer dielectric layer separated from the film stack. The back-side interconnect layer includes an ACS contact structure connected to an ACS and corresponding to a channel structure, a TSV contact structure connected to a TSV, and an insulating gap located between the TSV contact structure and the ACS contact structure.

[0034] Another aspect of the present disclosure provides a memory storage system. The memory storage system comprises a three-dimensional (3D) NAND memory comprising an array common source (ACS), and a film stack of alternately stacked conductive layers and dielectric layers comprising a conductive layer and a first dielectric layer alternately stacked on a first side of the ACS. Additionally, the 3D NAND memory comprises a back interconnect layer disposed on a second side opposite to the first side of the ACS, wherein the back interconnect layer comprises an ACS contact structure. The 3D NAND memory further comprises a memory string penetrating the film stack, wherein the memory string comprises a channel layer having a first portion covered by a memory film and a second portion in contact with the ACS and electrically connected to the ACS contact structure.

[0035] Another aspect of the present disclosure may be understood by a person skilled in the art in light of the description of the present disclosure, the claims, and the drawings. Brief explanation of the drawing

[0036] The accompanying drawings, incorporated herein and forming part of this specification, serve to illustrate embodiments of the present disclosure and, together with the description, additionally explain the principles of the present disclosure and enable a person skilled in the art to practice and use the present disclosure. FIG. 1 is a schematic plan view of an exemplary three-dimensional (3D) memory die according to some embodiments of the present disclosure. FIG. 2 is a schematic plan view of one area of ​​a 3D memory die according to some embodiments of the present disclosure. FIG. 3 is a perspective view of part of an exemplary 3D memory array structure according to some embodiments of the present disclosure. FIG. 4 is a drawing illustrating a method for forming a 3D memory device according to some embodiments of the present disclosure. FIGS. 5, 6a-6b, and 7-16 are cross-sectional views of a 3D memory structure at a specific process step according to some embodiments of the present disclosure. FIGS. 17 and 18a-18b illustrate a storage system having one or more memory chips according to some embodiments of the present disclosure. FIG. 19 is a schematic diagram of a three-dimensional (3D) memory die according to some embodiments of the present disclosure. The features and advantages of the present invention become more apparent from the following detailed description when considered in conjunction with the drawings, in which similar reference numerals identify corresponding elements throughout. In the drawings, similar reference numerals generally represent identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the number(s) to the left of the corresponding reference numeral. An embodiment of the present disclosure will be described with reference to the accompanying drawings. Specific details for implementing the invention

[0037] While specific configurations and arrangements are discussed, it should be understood that they are for illustrative purposes only. A person skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will also be apparent to a person skilled in the art that the present disclosure may be utilized in various other applications.

[0038] Note that references in the specification such as “one embodiment,” “an embodiment,” “an exemplary embodiment,” or “some embodiments” indicate that while the described embodiments may include specific features, structures, or characteristics, not all embodiments are required to include specific features, structures, or characteristics. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, where specific features, structures, or characteristics are described in relation to an embodiment, achieving such features, structures, or characteristics in relation to other embodiments would be within the level of knowledge of a person skilled in the art, regardless of whether it is explicitly described.

[0039] Generally, terms may be understood at least in part from their usage in the context. For example, the term “one or more” as used herein may, at least in part depending on the context, be used to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, the singular term may be understood, at least in part depending on the context, to convey either a singular usage or a plural usage. Additionally, the term “based on” may not be understood to convey an exclusive set of factors, but instead may, at least in part depending on the context, allow for the existence of additional factors that are not necessarily explicitly described.

[0040] It should be fully understood that in the present disclosure, the meanings of “on,” “above,” and “over” should be interpreted most broadly to include not only the meaning of “immediately above” something, but also the meaning of “above” something with an intermediate feature or layer in between. Furthermore, “above” or “over” may include not only the meaning of “above” or “over” something, but also the meaning of “above” or “over” something without an intermediate feature or layer in between (i.e., immediately above something).

[0041] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used in this specification for ease of description to explain the relationship between one element or feature illustrated in the drawings and other element(s) or feature(s). Spatially relative terms are intended to include different orientations of the device during use or process steps, in addition to the orientations depicted in the drawings. The device may be oriented differently (it may be rotated 90 degrees or be in a different orientation), and spatially relative descriptors used in this specification may be interpreted accordingly.

[0042] As used herein, the term “substrate” refers to a material upon which subsequent material layers are added. The substrate comprises a “top surface” and a “bottom surface.” The top surface of the substrate is typically where a semiconductor device is formed; therefore, unless otherwise noted, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite to the top surface, and thus the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on the substrate may be patterned or unpatterned. Additionally, the substrate may comprise a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of an electrically non-conductive material such as glass, plastic, or a sapphire wafer.

[0043] As used herein, the term “layer” refers to a portion of material comprising a region having thickness. A layer has an upper side and a lower side, where the lower side of the layer is relatively close to the substrate and the upper side is relatively far from the substrate. A layer may extend over the entire structure placed below or above, or may have a range smaller than that of the structure placed below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the upper and lower surfaces of the continuous structure, or between any pair of horizontal planes located between the upper and lower surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers on, above, and / or below it. A layer may include a plurality of layers. For example, the interconnect layer may include one or more contact layers (where contacts, interconnect lines and / or vertical interconnect access (via) are formed), a conductor, and one or more dielectric layers.

[0044] In the present disclosure, for ease of explanation, the term “tier” is used to refer to elements of substantially the same height along the vertical direction. For example, a word line and the gate insulating layer below it may be called a “tier,” the word line and the insulating layer below it may be collectively called a “tier,” and word lines of substantially the same height may be called a “tier of word lines” or similarly, etc.

[0045] As used herein, the term “nominal” refers to a desired or target value of a characteristic or parameter for a component or process step, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term “about” refers to a value of a given quantity that may vary based on a specific technical node associated with the target semiconductor device. Based on a specific technical node, the term “about” may refer to a value of a given quantity that varies within, for example, 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0046] In the present disclosure, the terms “horizontal / horizontal direction / transverse / transverse direction” mean nominally parallel to the transverse surface of the substrate, and the terms “vertical” or “vertical direction” mean nominally perpendicular to the transverse surface of the substrate.

[0047] As used in this specification, the term “3D memory” refers to a three-dimensional (3D) semiconductor device in which a string of memory cell transistors (hereinafter referred to as “memory string,” such as a NAND string) is arranged vertically on a substrate oriented laterally so that the memory string extends in a direction perpendicular to the substrate.

[0048] FIG. 1 shows a plan view of an exemplary three-dimensional (3D) memory device (100) according to some embodiment of the present disclosure. A 3D memory device (100), such as a 3D NAND flash memory, may be a memory chip (package), a memory die, or any part of a memory die and may include one or more memory planes (101), each memory plane may include a plurality of memory blocks (103). In each memory plane (101), identical and simultaneous operations may occur. A memory block (103), which may be a megabyte (MB) size, is the minimum size for performing an erase operation. As shown in FIG. 1, an exemplary 3D memory device (100) includes four memory planes (101), and each memory plane (101) includes six memory blocks (103). Each memory block (103) may include a plurality of memory cells, and each memory cell may be addressed through interconnections such as bit lines and word lines. Bit lines and word lines may be laid out vertically (e.g., in rows and columns, respectively) to form an array of metal lines. The orientation of bit lines and word lines is labeled “BL” and “WL” in FIG. 1. In this disclosure, memory blocks (103) are also referred to as “memory arrays” or “arrays.” A memory array is a core area in a memory device that performs storage functions.

[0049] The 3D memory device (100) also includes a peripheral region (105) which is a region surrounding the memory plane (101). The peripheral region (105) includes many digital, analog, and / or mixed-signal circuits to support the function of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuits use active and / or passive semiconductor devices such as transistors, diodes, capacitors, and resistors, as is obvious to a person skilled in the art.

[0050] It should be noted that the arrangement of memory planes (101) in the three-dimensional memory device (100) illustrated in FIG. 1 and the arrangement of memory blocks (103) in each memory plane (101) are used merely as examples and do not limit the scope of the present disclosure.

[0051] Referring to FIG. 2, an enlarged plan view of the region (108) of FIG. 1 according to some embodiment of the present disclosure is shown. The region (108) of the 3D memory device (100) may include a step region (210) and a channel structure region (211). The channel structure region (211) may include an array of memory strings (212), each comprising a plurality of stacked memory cells. The step region (210) may include a step structure and an array of contact structures (214) formed on the step structure. In some embodiments, a plurality of slit structures (216) extending in the WL direction across the channel structure region (211) and the step region (210) may divide the memory block into a plurality of memory fingers (218). At least some of the slit structures (216) can function as a common source contact (e.g., array common source or ACS) for an array of memory strings (212) within a channel structure region (211). A top select gate cut (220) may be positioned, for example, at the center of each memory finger (218) to divide the top select gate (TSG) of the memory finger (218) into two parts, thereby dividing the memory finger into two memory slices (224), and memory cells within the memory slices (224) sharing the same word line form a programmable (read / write) memory page. The erase operation of the 3D NAND memory may be performed at the memory block level, and the read and write operations may be performed at the memory page level. The size of the memory page may be kilobytes (KB). In some embodiments, the region (108) also includes a dummy memory string (222) for controlling process variation during manufacturing and / or for additional mechanical support.

[0052] FIG. 3 is a perspective view of part of an exemplary three-dimensional (3D) memory array structure (300) according to some embodiments of the present disclosure. The memory array structure (300) comprises a substrate (330), an insulating film (331) on the substrate (330), a tier of lower select gates (LSG) (332) on the insulating film (331), and a plurality of tiers of control gates (333), also called "word lines (WL)," which are stacked on top of the LSG (332) and form a film stack (335) in which a conductive layer and a dielectric layer are alternately stacked. A dielectric layer adjacent to a tier of control gates is not shown in FIG. 3 for clarity.

[0053] The control gates of each tier are separated by slit structures (216-1 and 216-2) penetrating the film stack (335). The memory array structure (300) also includes a tier of top select gates (TSG) (334) on top of a stack of control gates (333). The stack of TSG (334), control gates (333), and LSG (332) is also referred to as "gate electrodes". The memory array structure (300) also includes source line regions (344) and memory strings (212) doped in a portion of the substrate (330) between adjacent LSGs (332). Each memory string (212) includes a channel hole (336) extending through an insulating film (331) and a film stack (335) in which a conductive layer and a dielectric layer are alternately stacked. The memory string (212) also includes a memory film (337) on the sidewall of the channel hole (336), a channel layer (338) on the memory film (337), and a core filling film (339) surrounded by the channel layer (338). A memory cell (340) (e.g., 340-1, 340-2, 340-3) may be formed at the intersection of the control gate (333) (e.g., 333-1, 333-2, 333-3) and the memory string (212). A portion of the channel layer (338) corresponding to each control gate is also referred to as the channel layer (338) of the memory cell. The memory array structure (300) further includes a plurality of bit lines (BL) (341) connected to the memory string (212) on the TSG (334). The memory array structure (300) also includes a plurality of metal interconnect lines (343) connected to the gate electrode through a plurality of contact structures (214). The edge of the film stack (335) is configured in a stepped shape to allow electrical connection to each tier of the gate electrode.

[0054] In FIG. 3, for illustrative purposes, three tiers of control gates (333-1, 333-2, 333-3) are shown together with one tier of TSG (334) and one tier of LSG (332). In this example, each memory string (212) may include three memory cells (340-1, 340-2, 340-3) corresponding to each control gate (333-1, 333-2, 333-3). In some embodiments, the number of control gates and the number of memory cells may be greater than three to increase storage capacity. The memory array structure (300) may include other structures, such as TSG cuts, common source contacts (i.e., array common sources), and dummy memory strings. These structures are not shown in FIG. 3 for simplification.

[0055] FIG. 4 illustrates a method (400) for forming a three-dimensional (3D) memory device according to some embodiments of the present disclosure. It should be understood that the process steps shown in the method (400) are not exhaustive, and that other steps may likewise be performed before, after, or between any of the steps shown. In some embodiments, some process steps of the method (400) may be omitted, or other process steps may also be included, but this is not described herein for the sake of simplification. In some embodiments, the process steps of the method (400) may be performed in a different order and / or may vary.

[0056] FIGS. 5, 6a-6b, 7-16 show exemplary structures of a 3D memory device in a specific process step according to method (400).

[0057] Referring to FIG. 4, in process step (S405), a first etching stop layer and a second etching stop layer can be placed on a substrate. A cross-sectional view of an exemplary 3D memory structure (500) according to process step (S405) is shown in FIG. 5.

[0058] As shown in FIG. 5, the 3D memory structure (500) includes a first etching stop layer (550) and a second etching stop layer (552) disposed on a substrate (330).

[0059] The substrate (330) may provide a platform for forming a subsequent structure. In some embodiments, the substrate (330) may be any suitable semiconductor substrate having any suitable semiconductor material such as a single crystal, a polycrystalline or single-crystal semiconductor. For example, the substrate (330) may include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, II-VI compounds, or any combination thereof.

[0060] In some embodiments, the substrate (330) may have a composite structure and may include a semiconductor layer (547) formed on a handle wafer (545). The substrate (330) may also include an insulator layer (546) located between the semiconductor layer (547) and the handle wafer (545). The handle wafer (545) may include glass, plastic, or other semiconductor substrates. The semiconductor layer (547) may include any suitable single-crystal, polycrystalline, or single-crystal semiconductor, such as silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), gallium nitride, silicon carbide, III-V compounds, II-VI compounds, or any combination thereof. The insulator layer (546) may include silicon oxide, silicon nitride, silicon oxynitride, TEOS, or any combination thereof. In some embodiments, the insulator layer (546) is silicon oxide and is also called a sacrificial silicon oxide layer. In some embodiments, the semiconductor layer (547) is polycrystalline silicon and is also called a sacrificial polycrystalline silicon layer. In some embodiments, the substrate (330) may be silicon-on-insulator (SOI), germanium-on-insulator (GOI), or silicon germanium-on-insulator (SGOI), and the semiconductor layer (547) may be crystalline silicon, crystalline germanium, or crystalline silicon germanium.

[0061] In some embodiments, the semiconductor layer (547) may be deposited on the insulator layer (546) and the handle wafer (545) by using deposition methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermochemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), sputtering, organo-metal chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density plasma CVD (HDP-CVD), sputtering, evaporation, and / or combinations thereof. In some embodiments, the semiconductor layer (547) may be formed on the insulator layer (546) and the handle wafer (545) through wafer bonding, SIMOX, etc.

[0062] The front surface (330f) of the substrate (330) is also referred to in this specification as the “main surface” or “top surface” of the substrate. A layer of material may be disposed on the front surface (330f) of the substrate (330). The “top layer” or “upper layer” is the layer furthest or furthest from the front surface (330f) of the substrate. The “bottom layer” or “lower layer” is the layer closest or closer to the front surface (330f) of the substrate.

[0063] In process step (S405), a first etching stop layer (550) may be formed on the front surface (330f) of the substrate (330), and a second etching stop layer (552) may be formed on the first etching stop layer (550). In some embodiments, the first etching stop layer (550) and the second etching stop layer (552) may be formed on the semiconductor layer (547) of the substrate (330). The first etching stop layer (550) and the second etching stop layer (552) extend in a transverse direction parallel to the front surface (330f) of the substrate (330).

[0064] The first etching stop layer (550) and the second etching stop layer (552) may be used as etching stop layers in a subsequent etching process. The first etching stop layer (550) and the second etching stop layer (552) may be formed by a thin film deposition process such as CVD, PVD, ALD, sputtering, evaporation, and / or any combination thereof. In some embodiments, the first etching stop layer (550) may comprise silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. In some embodiments, the second etching stop layer (552) may comprise amorphous or polycrystalline silicon. Note that the first etching stop layer (550) and the second etching stop layer (552) may comprise any suitable material having a certain etching selectivity (i.e., ratio of etching rate) with respect to the material to be etched.

[0065] Referring to FIG. 4, in process step (S410), alternating dielectric stacks may be placed on a second etching stop layer on a substrate. In process step (S415), a step structure may be formed on the alternating dielectric stacks. In process step (S420), an insulating layer may be placed on the substrate and may cover the step structure and the alternating dielectric stacks. A cross-sectional view of an exemplary 3D memory structure (600) according to process steps (S410 to S420) is shown in FIG. 6a.

[0066] As shown in FIG. 6a, the 3D memory structure (600) includes an alternating dielectric stack (654) having a first dielectric layer (656) and a second dielectric layer (658) alternately stacked on a second etching stop layer (552).

[0067] In some embodiments, the alternating dielectric stack (654) comprises a plurality of pairs of dielectric layers alternately stacked along a vertical direction (i.e., z-direction) perpendicular to the front surface (330f) of the substrate (330), and each pair of dielectric layers comprises a first dielectric layer (656) (also called a “dielectric layer”) and a second dielectric layer (658) (also called a “sacrificial layer”) different from the first dielectric layer (656). The alternating dielectric stack (654) extends in a transverse direction parallel to the front surface (330f) of the substrate (330).

[0068] In the alternating dielectric stack (654), the first dielectric layer (656) and the second dielectric layer (658) are alternately arranged in a vertical direction perpendicular to the substrate (330). In other words, each second dielectric layer (658) can be sandwiched between two first dielectric layers (656), and each first dielectric layer (656) can be sandwiched between two second dielectric layers (658) (excluding the bottom and top layers).

[0069] Formation of alternating dielectric stacks (654) may include arranging the first dielectric layers (656) so that they each have the same thickness or different thicknesses. An exemplary thickness of the first dielectric layer (656) may be in the range of 10 nm to 500 nm, preferably about 25 nm. Likewise, the second dielectric layer (658) may each have the same thickness or different thicknesses. An exemplary thickness of the second dielectric layer (658) may be in the range of 10 nm to 500 nm, preferably about 35 nm. It should be understood that the number of dielectric layer pairs in FIG. 6a is merely for illustrative purposes, and any suitable number of layers may be included in the alternating dielectric stack (654).

[0070] In some embodiments, the first dielectric layer (656) comprises any suitable insulating material, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide containing F-, C-, N-, and / or H-. The first dielectric layer (656) may also comprise a high dielectric constant material, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, or lanthanum oxide film. In some embodiments, the first dielectric layer (656) may be any combination of the above materials.

[0071] The formation of the first dielectric layer (656) may include any suitable deposition method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), rapid thermochemical vapor deposition (RTCVD), low-pressure chemical vapor deposition (LPCVD), sputtering, organo-metal chemical vapor deposition (MOCVD), atomic layer deposition (ALD), high-density plasma CVD (HDP-CVD), sputtering, evaporation, thermal oxidation, nitridation, other suitable deposition methods, and / or combinations thereof.

[0072] In some embodiments, the second dielectric layer (658) comprises any suitable material that is different from the first dielectric layer (656) and can be selectively removed from the first dielectric layer (656). For example, the second dielectric layer (658) may comprise silicon oxide, silicon oxynitride, silicon nitride, TEOS, polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any combination thereof. In some embodiments, the second dielectric layer (658) also comprises an amorphous semiconductor material such as amorphous silicon or amorphous germanium. The second dielectric layer (658) may be formed using the same technology as the first dielectric layer (656), such as CVD, PVD, ALD, sputtering, evaporation, thermal oxidation or nitridation, or any combination thereof.

[0073] In some embodiments, the first dielectric layer (656) may be silicon oxide and the second dielectric layer (658) may be silicon nitride.

[0074] In some embodiments, the alternating dielectric stack (654) may include layers in addition to the first dielectric layer (656) and the second dielectric layer (658), and may be made of different materials and / or different thicknesses.

[0075] As shown in FIG. 6a, the 3D memory structure (600) also includes a step structure (657) having a plurality of step steps (659) formed in alternating dielectric stacks (654) of a step region (210). A step step (659), or “step layer,” refers to a stack of layers having the same transverse dimension in a plane parallel to the substrate surface (330f). Each of the step steps (659) has a transverse dimension “a” as shown in FIG. 6a and ends with a length shorter than the step step below.

[0076] In some embodiments, each step step (659) comprises a pair of a first dielectric layer (656) and a second dielectric layer (658). In some embodiments, each step step (659) may comprise two or more pairs of a first dielectric layer (656) and a second dielectric layer (658). As shown in FIG. 6a, each step step (659) comprises a pair of a first dielectric layer (656) and a second dielectric layer (658), with the second dielectric layer (658) situated above the first dielectric layer (656). Each step step (659) exposes a portion of the second dielectric layer (658) at the end of the alternating dielectric stack (654).

[0077] A step structure (657) can be formed by applying a repetitive etch-trim process on alternating dielectric stacks (654). The etch-trim process includes an etching process and a trimming process. During the etching process, a portion of the step step (659) with the surface exposed may be removed. The remainder of the step step (659) that is covered by the upper level of the step step or by a patterning mask is not etched. The etching depth is the thickness of the step step (659). In some embodiments, the thickness of the step step (659) is the thickness of a pair of the first dielectric layer (656) and the second dielectric layer (658). The etching process for the first dielectric layer (656) may have high selectivity for the second dielectric layer (658) and / or vice versa. Accordingly, the pair of dielectric layers placed underneath may function as etch stop layers. By switching the etching process for each layer, the step steps (659) can be etched during one etching cycle. And as a result, one of the step steps (659) can be formed during each etching-trim cycle.

[0078] In some embodiments, the step steps (659) may be etched using anisotropic etching, such as reactive ion etching (RIE) or other dry etching processes. In some embodiments, the first dielectric layer (656) is silicon oxide. In this example, the etching of the silicon oxide may involve RIE using a fluorine-based gas, such as carbon-fluorine (CF4), hexafluoroethane (C2F6), CHF3, or C3F6 and / or any other suitable gas. In some embodiments, the silicon oxide layer may be removed by wet chemistry, such as hydrofluoric acid or a mixture of hydrofluoric acid and ethylene glycol. In some embodiments, a timed etching method may be used. In some embodiments, the second dielectric layer (658) is silicon nitride. In this example, the etching of silicon nitride may include an RIE using O2, N2, CF4, NF3, Cl2, HBr, BCl3, and / or a combination thereof. The method and etchant for removing a single-layer stack should not be limited by the embodiments of the present disclosure.

[0079] The trimming process includes applying a suitable etching process (e.g., isotropic dry etching or wet etching) onto the patterning mask so that the patterning mask can be retracted laterally. The retraction dimension laterally determines the lateral dimension “a” of each step of the step structure (657). After trimming the patterning mask, a portion of the uppermost step (659) is exposed, and another portion of the uppermost step (659) remains covered by the patterning mask. The next cycle of the etching-trim process resumes as an etching process. In some embodiments, the patterning mask trimming process may include dry etching such as RIE using O2, Ar, N2, etc. Note that the number of step structures and the number of dielectric layer pairs in the 3D memory structure (600) are not limited to the examples herein.

[0080] As shown in FIG. 6a, the 3D memory structure (600) also includes an insulating layer (660) disposed on a substrate and covering a portion of a step structure (657), an alternating dielectric stack (654), and a second etching stop layer (552). The insulating layer (660) may include any suitable insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-on-glass, carbon-doped oxide (CDO or SiOC or SiOC:H), or fluorine-doped oxide (SiOF), or a low dielectric constant material. The insulating layer (660) may be disposed by CVD, PVD, ALD, sputtering, evaporation, etc. In some embodiments, the insulating layer (660) may have a planar top surface over the step structure (760) and the alternating dielectric stack (654). The insulating layer (660) may be planarized using CMP and / or RIE etchback.

[0081] In some embodiments, prior to laying the insulating layer (660), a barrier layer (not shown in FIG. 6a) may be laid on the stepped structure and the alternating dielectric stacks. The barrier layer may cover the stepped structure (657) and the alternating dielectric stacks (654) on both the transverse surface and the vertical sidewall. The barrier layer on the transverse surface and the vertical sidewall may have the same thickness or different thicknesses. The barrier layer may function as an etching stop to form a contact structure on the stepped steps.

[0082] Upon completion of process step (S420), a step structure (657) is formed in the step region (210), which can be used to form electrical contacts to word lines in a subsequent process. In the peripheral region (105), an insulating layer (660) covers the first / second etching stop layer (550 / 552) and the substrate (330), and electrical contacts to peripheral circuits can be formed in a subsequent process. In some embodiments, peripheral devices may be formed in the peripheral region (105) on the front surface (330f) of the substrate (330). Peripheral devices may include any suitable semiconductor device, such as a metal oxide semiconductor field-effect transistor (MOSFET), a diode, a resistor, a capacitor, etc. Peripheral devices may be used in the design of digital, analog and / or mixed-signal circuits that support storage functions of the memory core, such as row and column decoders, drivers, page buffers, sense amplifiers, timing and control, etc.

[0083] FIG. 6b shows an exemplary peripheral circuit (600B) within a peripheral region (105) according to some embodiments of the present disclosure. The peripheral circuit (600B) may be part of the 3D memory structure (600) shown in FIG. 6a. The peripheral circuit (600B) may be formed before the alternating dielectric stack (654) is placed. The peripheral circuit (600B) may also be formed after the step structure (657) is formed. Note that the order of forming the peripheral circuit (600B) in the peripheral region (105) and forming the step structure (657) in the step region (210) is not limited to the examples discussed above.

[0084] The peripheral circuit (600B) may include one or more peripheral devices (50) on the front surface of the substrate (330) (e.g., semiconductor layer (547)). The peripheral devices (50) may be formed "on" the substrate (330), such that all or part of the peripheral devices (50) are formed on the substrate (330) (e.g., below the front surface (330f) of the substrate (330)) and / or directly on the substrate (330). The peripheral devices (50) may include any suitable semiconductor devices, such as metal oxide semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), diodes, resistors, capacitors, inductors, etc. Among the semiconductor devices, p-type and / or n-type MOSFETs (i.e., CMOS) are widely implemented in logic circuit designs and are used as examples of peripheral devices (50) in this disclosure.

[0085] The peripheral device (50) may be either a p-channel MOSFET or an n-channel MOSFET and may include, but is not limited to, an active device region surrounded by shallow trench isolation (STI) (52), a well (54) formed in the active device region with n-type or p-type doping, and a gate stack (56) including a gate dielectric, a gate conductor, and / or a gate hard mask. The peripheral device (50) may also include a source / drain extension and / or a halo region (not shown in FIG. 6b), a source / drain (60) located on both sides of the gate stack, and a gate spacer (58). The peripheral device (50) may further include a silicide contact region (not shown) on top of the source / drain. Other known devices may also be formed on the substrate (330). The structure and method of manufacturing the peripheral device (50) are known to a person skilled in the art and are incorporated herein in their entirety.

[0086] A peripheral device (50) may be formed on a substrate (330) having a planar active device region (as shown in FIG. 6b) in which the direction of the channel and current flow of the MOSFET is parallel to the front surface (330f) of the substrate (330). In some embodiments, the peripheral device (50) may be formed on a substrate (330) having a 3D active device region, for example, a so-called “FINFET” (not shown) with a shape such as a “FIN,” the gate stack of the MOSFET is wound around the FIN, and the channel of the MOSFET is laid along three sides of the FIN (top and two sidewalls below the gate). The structure and method of the FINFET device are known to a person skilled in the art and are not further described in this disclosure.

[0087] In some embodiments, the peripheral circuit (600B) may include a peripheral interconnect layer (62) on top of the peripheral device (50) to provide electrical connection between another peripheral device (50) and an external device (e.g., power supply, other chip, I / O device, etc.). In some embodiments, the peripheral interconnect layer (62) may be formed on an insulating layer (660). In some embodiments, the peripheral interconnect layer (62) may be formed on an insulating layer different from the insulating layer (660) of FIG. 6a.

[0088] The peripheral interconnect layer (62) may include one or more interconnect structures, for example, one or more vertical contact structures (64) and one or more transverse conductive lines (66). The contact structures (64) and conductive lines (66) may broadly include any suitable type of interconnect, such as middle-of-line (MOL) interconnects and back-end-of-line (BEOL) interconnects. The contact structures (64) and conductive lines (66) of the peripheral circuit (600B) may be tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicide (WSix , CoSi x , NiSi x , AlSi x Any suitable conductive material may be included, such as metal alloys, or any combination thereof. The conductive material may be deposited by one or more thin film deposition processes, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, sputtering, evaporation, or any combination thereof.

[0089] In FIG. 6b, two conductive levels (70-1 and 70-2) (also referred to as “metal levels”) are shown as an example, and each metal level (70) (e.g., 70-1 or 70-2) includes a contact structure (64) and a conductive line (66). Conductive lines (66) of the same metal level are placed at equal distances from the substrate (330). The number of metal levels (70) for the peripheral circuit (600B) is not limited and can be any number optimized for the performance of the 3D memory.

[0090] The peripheral interconnect layer (62) can be formed by stacking metal levels (70) from the bottom to the top of the peripheral circuit (600B). In the example of the peripheral circuit (600B) of FIG. 6b, a bottom metal level (70-1) can be formed first, and then a top metal level (70-2) can be formed on top of the bottom metal level (70-1).

[0091] In some embodiments, the peripheral circuit (600B) also includes one or more substrate contacts (72), and the substrate contacts (72) provide electrical connection to the substrate (330). The substrate contacts (72) may include one or more conductive levels (70) having a plurality of tiers of a vertical contact structure (64) and a transverse conductive line (66). In FIG. 6b, a substrate contact (72) having a contact structure and a tier of a conductive line is illustrated as an example, wherein the vertical contact structure of the substrate contact (72) extends through an insulating layer (660) and electrically contacts the substrate (330).

[0092] However, the peripheral device (50) is not limited to a MOSFET. Other devices, such as diodes, resistors, capacitors, inductors, BJTs, etc., may be formed simultaneously during MOSFET manufacturing through different mask designs and layouts. To form devices other than MOSFETs, process steps in the MOSFET process flow may be added or changed, for example, to obtain different impurity profiles, film thicknesses, or material stacks. In some embodiments, peripheral devices other than MOSFETs (50) may be manufactured at the level of additional designs and / or lithography masks to achieve specific circuit requirements. Peripheral devices (50) may be used to form any digital, analog, and / or mixed-signal circuits for the operation of the peripheral circuit (600B). The peripheral circuit (600B) may perform, for example, row / column decoding, timing and control, reading, writing, and erasing data of a memory array.

[0093] Referring to FIG. 4, in process step (S425), a plurality of channel holes and a plurality of dummy channel holes may be formed in the channel structure region and the step region, respectively. A memory film and a channel layer may be placed on the sidewalls of each channel hole. According to process step (S425), a cross-sectional view of an exemplary 3D memory structure (700) is shown in FIG. 7.

[0094] As shown in FIG. 7, the 3D memory structure (700) includes a plurality of channel holes (336) in a channel structure region (211). The plurality of channel holes (336) vertically penetrate an insulating layer (660) and alternating dielectric stacks (654). In some embodiments, the plurality of channel holes (336) further penetrate a second etching stop layer (552) and a first etching stop layer (550) and extend into a substrate (330), for example, into a semiconductor layer (547).

[0095] Techniques used to form channel holes (336) may include processes such as photolithography and etching. Etching processes for forming channel holes (336) may also include dry etching, wet etching, or a combination thereof. In some embodiments, alternating dielectric stacks (654) may be etched using anisotropic etching such as reactive ion etching (RIE). In some embodiments, fluorine or chlorine-based gases such as carbon fluorine (CF4), hexafluoroethane (C2F6), CHF3, C3F6, Cl2, BCl3, etc., or any combination thereof may be used. Methods and etchings for etching the first dielectric layer (656) and the second dielectric layer (658) should not be limited by the embodiments of the present disclosure. In some embodiments, the semiconductor layer (547) can function as an etching stop during the etching process for the channel hole (336) so that the channel hole (336) does not extend further into the insulator layer (546) and the handle wafer (545).

[0096] After forming the channel hole (336), a memory film (337) may be disposed on the side wall of the channel hole (336). In some embodiments, the memory film (337) may be a composite layer comprising a tunnel layer (3373), a storage layer (3372) (also called a "charge trap / storage layer"), and a blocking layer (3371). In some embodiments, the tunnel layer (3373), the storage layer (3372), and the blocking layer (3371) are arranged in the above order along the direction from the center of the channel hole (336) toward the outside of the channel hole (336). The tunnel layer (3373) may comprise silicon oxide, silicon nitride, or any combination thereof. The blocking layer (3371) may comprise silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof. The storage layer (3372) may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In some embodiments, the memory film (337) comprises an ONO dielectric (e.g., a tunnel layer (3373) comprising silicon oxide, a storage layer (3372) comprising silicon nitride, and a blocking layer (3371) comprising silicon oxide). The memory film (337) may be formed using a thin film deposition process such as ALD, CVD, PVD, sputtering, or any other suitable process. In some embodiments, the thickness of the memory film (337) may be in the range of about 10 nm to about 50 nm.

[0097] Subsequently, a channel layer (338) and a core filling film (339) may be disposed in the channel hole (336), and the channel layer (338) covers the sidewall of the memory film (337) inside the channel hole (336). The channel layer (338) may be any suitable semiconductor material such as silicon. In some embodiments, the channel layer (338) may be amorphous, polysilicon, or single-crystal silicon. The channel layer (338) may be formed by any suitable thin film deposition process including, but not limited to, CVD, PVD, ALD, sputtering, evaporation, or a combination thereof. In some embodiments, the thickness of the channel layer (338) may be in the range of about 10 nm to about 30 nm.

[0098] In some embodiments, the core filling film (339) may be positioned to fill the channel hole (336) and form a channel structure (761). In some embodiments, the central portion of the core filling film (339) may include one or more seams (860). The core filling film (339) may be any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, spin-on-glass, silicon oxide doped with boron or phosphorus, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. The core filling film (339) may be deposited using, for example, ALD, PVD, CVD, spin-coating, sputtering, or any other suitable film deposition technique. Additionally, the core filling film (339) may be formed by a repeated deposition and etch-back process. The etch-back process may include, but is not limited to, wet etching, dry etching, or a combination thereof. In some embodiments, one or more seams may be formed in the core filling film (339) to reduce mechanical stress.

[0099] In some embodiments, the 3D memory structure (700) also includes a channel top plug (762) at the top of the channel structure (761). The channel top plug (762) may form electrical contact with the channel layer (338) inside the channel hole (336). The channel top plug (762) may be amorphous or polycrystalline silicon and may include a metal, metal alloy and / or metal silicide, for example, tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, or a combination thereof. The channel top plug (762) may be formed by thin film deposition followed by a recess etching process. The recess etching process includes wet etching, dry etching, or a combination thereof. Thin film deposition includes CVD, PVD, ALD, sputtering, or any other suitable process.

[0100] In some embodiments, the 3D memory device (700) may include an epitaxial plug (not shown) at the bottom of the channel structure (761). The epitaxial plug may include any suitable semiconductor material such as silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, III-V compounds, or any combination thereof. The epitaxial plug may be epitaxially grown from a substrate (330) (e.g., a semiconductor layer (547)). In some embodiments, the epitaxial plug may include a polycrystalline semiconductor material, e.g., polycrystalline silicon. In some embodiments, a portion of the memory film (337) may be removed at the bottom of the channel hole (336) so that the channel layer (338) can come into direct contact with the epitaxial plug.

[0101] Note that the number and arrangement of channel structures (761) in the channel structure region (211) can be designed according to actual storage requirements and are not limited to the example shown in FIG. 7. As described above with respect to FIG. 2, the channel structure region (211) provides storage functions for three-dimensional memory.

[0102] As shown in FIG. 7, the 3D memory structure (700) also includes a plurality of dummy channel holes (DCH) (764) in the step region (210). The DCH (764) penetrates the insulating layer (660), part of the step structure (657) (i.e., part of the alternating dielectric stack (654)), the second etching stop layer (552), and the first etching stop layer (550), and extends into the substrate (330) (e.g., the semiconductor layer (547)). The formation of the DCH (764) involves lithography and etching, and the etching process may include dry etching, wet etching, and / or a combination thereof. In some embodiments, the etching process for the DCH (764) includes anisotropic etching such as RIE.

[0103] After forming the DCH (764), a DCH filler (765) may be placed within the DCH (764) to form a dummy channel structure (763). The DCH filler (765) comprises any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, high dielectric constant materials (Al2O3, HfO2, Ta2O3, ZrO2, La2O3, etc.), or any combination thereof. The DCH filler (765) may be placed by any suitable thin film deposition technique such as CVD, ALD, PVD, sputtering, or evaporation. In some embodiments, one or more seams may be formed in the DCH filler (765) to reduce mechanical stress. The dummy channel structure (763) formed in the stepped region (210) may be configured to provide mechanical support for the 3D memory structure in a subsequent process.

[0104] In some embodiments, the channel structure (761) and the dummy channel structure (763) may be flattened to have coplanarity. The flattening process includes RIE etchback, CMP, or a combination thereof.

[0105] The 3D memory structure (700) also includes a first capping layer (766) disposed on an insulating layer (660) to cover a channel structure (761) in a channel structure region (211) and a dummy channel structure (763) in a step region (210). The first capping layer (766) may include silicon oxide, silicon nitride, silicon oxynitride, TEOS, or a combination thereof. The first capping layer (766) may be deposited by CVD, PVD, ALD, sputtering, etc.

[0106] Referring to FIG. 4, in process step (S430), gate line slit (GLS) openings may be formed in alternating dielectric stacks. In process step (S435), the second dielectric layer of the alternating dielectric stack may be replaced with a conductive layer to form a film stack in which the conductive layer and the dielectric layer are alternately stacked. In process step (S440), a GLS filler may be placed within the GLS openings to form a GLS. A cross-sectional view of an exemplary 3D memory structure (800) according to process steps (S430 to S440) is shown in FIG. 8.

[0107] As shown in FIG. 8, the 3D memory structure (800) includes gate line slit (GLS) openings (869) formed in alternating dielectric stacks (654). The GLS openings (869) penetrate the insulating layer (660) and the alternating dielectric stacks (654). In some embodiments, the GLS openings (869) also penetrate the second etching stop layer (552) and the first etching stop layer (550) and further extend into the substrate (330) (e.g., into the semiconductor layer (547)). The GLS openings (869) can be formed by a lithography process and an etching process. The etching process may include any suitable dry etching, wet etching, and / or a combination thereof. In the subsequent process, the GLS opening (869) can be used to form a slit structure (216) as shown in FIG. 2.

[0108] In process step (S435), the second dielectric layer (658) of the alternating dielectric stack (654) and the step structure (657) (in FIG. 7) can be removed through the GLS opening (869) to form a transverse tunnel. The transverse tunnel can extend transversely between adjacent first dielectric layers (656). Note that the term “transverse / transversely” as used herein means a plane parallel to the top surface (330f) of the substrate (330). The second dielectric layer (658) in the alternating dielectric stack (654), also called a sacrificial layer, can be selectively removed from between the first dielectric layers (656). In other words, the etching process of the second dielectric layer (658) can have minimal effect on the first dielectric layer (656). The second dielectric layer (658) may be removed by isotropic dry etching and / or wet etching. The plasma and / or chemicals used in the dry / wet etching may be moved vertically and transversely from the GLS opening (869). In some embodiments, the second dielectric layer (658) may be silicon nitride and the first dielectric layer (656) may be silicon oxide. In this example, the second dielectric layer (658) may be removed by RIE using one or more etchants such as CF4, CHF3, C4F8, C4F6, and CH2F2. In some embodiments, the second dielectric layer (658) may be removed using wet etching such as phosphoric acid.

[0109] Next, a conductive layer (870) can be placed inside a transverse tunnel through a GLS opening (869). The conductive layer (870) can be placed between adjacent first dielectric layers (656), and the conductive layer (870) and the first dielectric layer (656) can form a film stack (335) in which the conductive layer and the dielectric layer are alternately stacked (as in FIG. 3).

[0110] In some embodiments, the conductive layer (870) may be formed by filling a transverse tunnel with a suitable conductive material. The conductive material for the conductive layer (870) may include a metal or metal alloy such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. In some embodiments, the conductive material of the conductive layer (870) may also include a polycrystalline semiconductor such as polycrystalline silicon, polycrystalline germanium, polycrystalline germanium-silicon, and any other suitable material, and / or combinations thereof. In some embodiments, the polycrystalline material may contain any suitable type of impurity such as boron, phosphorus, arsenic, or combinations thereof. In some embodiments, the conductive layer (870) may also be an amorphous semiconductor such as amorphous silicon. In some embodiments, the conductive material may be deposited using a suitable deposition method such as chemical vapor deposition (CVD) (e.g., LPCVD, PECVD, MOCVD, RTCVD, etc.), physical vapor deposition (PVD), sputtering, evaporation, atomic layer deposition (ALD), or any combination thereof. In some embodiments, the conductive layer (870) comprises tungsten (W) deposited by CVD.

[0111] As described above, by substituting the second dielectric layer (658) with the conductive layer (870), the alternating dielectric stack (654) is transformed into a film stack (335) in which the conductive layer and the dielectric layer are alternately stacked. Accordingly, the channel structure (761) formed in the alternating dielectric stack (654) becomes a memory string (212), and the intersection of the memory string (212) and the film stack (335) forms a memory cell (340) that is vertically stacked. Here, the film stack (335) is formed by a substitution method (i.e., substituting the second dielectric layer (658) with the conductive layer (870)), but it should be understood that the film stack (335) can also be formed by other approaches, such as, for example, by placing the conductive layer (870) and the first dielectric layer (656) directly on the substrate (330).

[0112] In some embodiments, prior to laying the conductive layer (870), a gate dielectric layer (872) may be laid within the transverse tunnel. The gate dielectric layer (872) may comprise any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer (872) may comprise a high dielectric constant material, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. The gate dielectric layer (872) may be laid by one or more suitable deposition processes such as CVD, PVD, and / or ALD.

[0113] In some embodiments, a gate adhesive layer (874) may be placed on the gate dielectric layer (872) prior to placing the conductive layer (870). The gate adhesive layer (874) may be used to promote adhesion between the gate dielectric layer (872) and the conductive layer (870). The gate adhesive layer (874) may comprise, for example, tantalum nitride (TaN) and / or titanium nitride (TiN).

[0114] In some embodiments, an etching and cleaning process may be used to remove excess conductive material on the sidewalls of the GLS opening (869). Thus, each conductive layer (870) of the film stack (335) can be electrically insulated from one another. In some embodiments, the conductive layer (870) may be recessed from the sidewalls of the GLS opening (869). In some embodiments, excess conductive material on the top of the first capping layer (766) may also be removed, for example, by CMP.

[0115] Next, as shown in FIGS. 2-3 and FIGS. 8, a GLS filler (871) may be placed inside the GLS opening (869) and a slit structure (216) (also called GLS) may be formed. The GLS (216) vertically penetrates a film stack (335) in which an insulating layer (660), a conductive layer, and a dielectric layer are alternately stacked, and extends into the substrate (330). The GLS filler (871) may comprise any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxide doped with boron or phosphorus, carbon-doped oxide (CDO or SiOC or SiOC:H), or fluorine-doped oxide (SiOF), or any combination thereof. The GLS filler (871) may be deposited using, for example, ALD, CVD (e.g., PECVD, RTCVD, LPCVD, etc.), PVD, sputtering, evaporation, or any other suitable deposition technique. In some embodiments, the GLS filler (871) outside the GLS opening (869) may be removed by etching (e.g., RIE) and / or CMP. Thus, the GLS (216) may be coplanar with the first capping layer (766). As described above, the GLS (216) may divide the memory block into a number of functional units (e.g., memory fingers). Additionally, the GLS (216) may provide mechanical support in the channel structure region (211).

[0116] In some embodiments, a second capping layer (868) may be disposed on the first capping layer (766) to cover the GLS (216). The second capping layer (868) may comprise silicon oxide, silicon nitride, silicon oxynitride, TEOS, or a combination thereof. The second capping layer (868) may be deposited by CVD, PVD, ALD, sputtering, etc.

[0117] Referring to FIG. 4, in process step (S445), through-silicon vias (TSVs) may be formed in the peripheral region. According to process step (S445), a cross-sectional view of an exemplary 3D memory structure (900) is shown in FIG. 9.

[0118] As shown in FIG. 9, the 3D memory structure (900) includes a TSV (976) that vertically penetrates a second capping layer (868), a first capping layer (766), and an insulating layer (660). In some embodiments, the TSV (976) also penetrates a second etching stop layer (552) and a first etching stop layer (550) and extends into a substrate (330) (e.g., a semiconductor layer (547)). In some embodiments, one or more of the TSVs (976) may be electrically connected to any of the contact structure (64), conductive line (66), or substrate contact (72) of the peripheral circuit (600B) (shown in FIG. 6bB) and may provide electrical connection to a peripheral device (50). The number and layout of the TSVs (976) are correspondingly adjustable and are not limited to the example shown in FIG. 9.

[0119] To form a TSV (976), a TSV opening may be formed by lithography and etching. The etching process for the TSV (976) may include dry etching, wet etching, and / or a combination thereof. If the insulating layer (660) is silicon oxide, anisotropic RIE by chemical etchants such as CF4, CHF3, C2F6, C3F6, and / or any combination thereof may be used for etching the silicon oxide. The etching processes and chemicals listed herein are merely examples and are not limited to these. Next, a conductive material may be placed within the TSV opening. The TSV (976) may comprise any suitable conductive material, such as a metal or metal compound, such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), and / or any combination thereof. The metal or metal compound may be placed using a suitable deposition method such as CVD, PVD, ALD, sputtering, evaporation, etc.

[0120] In some embodiments, the TSV (976) may have a shape similar to a cylinder, a cube, or any other shape. In some embodiments, before placing the conductive material, the TSV interface layer (978) may be placed on the sidewall of the TSV opening by a suitable thin film deposition technique, such as CVD, PVD, ALD, or sputtering. The TSV interface layer (978) may include TiN, TaN, etc.

[0121] In some embodiments, the formation of the TSV (976) may also include a planarization process, such as CMP, to remove excess conductive material on top of the second capping layer (868). As shown in FIG. 9, the TSV (976) may be coplanar with the second capping layer (868).

[0122] It can be seen that the channel hole (336) (or memory string (212)), dummy channel hole (764) (or dummy channel structure (763)), GLS (216) and TSV (976) may have the same depth or a different depth inside the substrate (330).

[0123] Referring to FIG. 4, in process step (S450), the substrate is removed so that a portion of the memory film extending into the substrate can be exposed and can be stopped on the first etching stop layer. A cross-sectional view of an exemplary 3D memory structure (1000) according to process step (S450) is shown in FIG. 10.

[0124] As shown in FIGS. 9 and 10, the 3D memory structure (1000) is the 3D memory structure (900) rotated 180°, and the substrate (330) can be removed from the back side of the substrate (330) (i.e., the side far from the film stack (335) and opposite to the front side (330f). In some embodiments, the handle wafer (545) of the substrate (330) is first removed by a process such as wafer polishing, CMP and / or dry / wet etching and is left on the insulator layer (546). In other words, the process of removing the handle wafer (545) may be optional for the insulator layer (546). For example, the etching rate of the handle wafer (545) may be much higher than the etching rate of the insulator layer (546). Next, the insulator layer (546) can be removed by, for example, a dry etching or wet etching process and stopped on the semiconductor layer (547). In other words, the process of removing the insulator layer (546) may be optional for the semiconductor layer (547). For example, the etching rate of the insulator layer (546) may be much higher than the etching rate of the semiconductor layer (547). Subsequently, the semiconductor layer (547) can be removed by a dry etching or wet etching process and stopped on the first etching stop layer (550). In other words, the process of removing the semiconductor layer (547) may be optional for the first etching stop layer (550). For example, the etching rate of the semiconductor layer (547) may be much higher than the etching rate of the first etching stop layer (550).

[0125] In some embodiments, the process of removing the substrate (330) and / or the process of removing the semiconductor layer (547) may be optional for the memory film (337) (e.g., blocking layer (3371)) of the memory string (212). Accordingly, after removing the substrate (330), a portion of the memory film (337) (e.g., blocking layer (3371)) extending into the substrate (330) may be exposed. The memory string (212) having the exposed portion of the memory film (337) protrudes out of the first etching stop layer (550) from the back side of the film stack (335) (i.e., the side of the film stack (335) closer to the substrate (330) or the first etching stop layer (550). Similarly, a portion of the TSV (976) extending into the substrate (330), a portion of the dummy channel structure (763), and a portion of the GLS (216) may be exposed from the back side of the film stack (335) after the substrate (330) is removed.

[0126] By adding an etching stop layer and using a selective etching process, the uniformity of the substrate removal process can be significantly improved.

[0127] Referring to FIG. 4, in process step (S455), the exposed portion of the first etching stop layer and the memory film can be removed and a portion of the channel layer can be exposed. A cross-sectional view of an exemplary 3D memory structure (1100) according to process step (S455) is shown in FIG. 11.

[0128] As shown in FIGS. 10 and 11, the first etching stop layer (550) can be removed from the 3D memory structure (1000) to form the 3D memory structure (1100). The first etching stop layer (550) can be removed by, for example, a dry etching or wet etching process, and the etching process can be stopped at the second etching stop layer (552). In other words, the process of removing the first etching stop layer (550) can be optional for the second etching stop layer (552). For example, the etching rate of the first etching stop layer (550) can be much higher than the etching rate of the second etching stop layer (552).

[0129] In some embodiments, the etching process of the first etching stop layer (550) may also remove an exposed portion of the memory film (337) (i.e., a portion extending into the substrate (330)) and may be selective with respect to the channel layer (338) of the memory string (212). In other words, the exposed portion of the memory film (337) may be removed by stopping at the channel layer (338) placed underneath. For example, the etching rate of the memory film (337) may be much higher than the etching rate of the channel layer (338). Thus, a portion of the channel layer (338) of the memory string (212) may be exposed from the back side of the film stack (335).

[0130] In some embodiments, the memory film (337) may be recessed (or recessed) further into the film stack (335) so that the exposed portion of the channel layer (338) from the back side of the film stack (335) becomes larger.

[0131] In some embodiments, the etching process of the first etching stop layer (550) and the memory film (337) may also be optional for the dummy channel structure (763), GLS (216), and TSV (976). Accordingly, a portion of the dummy channel structure (763), a portion of the GLS (216), and a portion of the TSV (976) may be exposed from the back side of the film stack (335). The exposed portion of the dummy channel structure (763), the exposed portion of the GLS (216), and the exposed portion of the TSV (976) protrude out of the second etching stop layer (552) from the back side of the film stack (335).

[0132] By implementing the second etching stop layer (552), the exposed portion of the memory film (337) can be controlledly removed from the back side of the film stack without affecting the film stack (335) placed underneath. Additionally, the uniformity of the exposed portion of the channel layer (338) can be improved. By controllingly retracting the memory film (337) downward of the second etching stop layer (552) (i.e., into the film stack (335)), the exposed portion of the channel layer (338) can be controlled.

[0133] Referring to FIG. 4, in process step (S460), an array common source (ACS) can be formed on the back side of the second etching stop layer. A cross-sectional view of an exemplary 3D memory structure (1200) according to process step (S460) is shown in FIG. 12.

[0134] As shown in FIG. 12, the 3D memory structure (1200) comprises an ACS (1280) disposed on the back side of a second etching stop layer (552), and the back side of the second etching stop layer (552) is the side far from the film stack (335). In some embodiments, the ACS (1280) comprises one or more polycrystalline silicon layers.

[0135] As shown in FIG. 12, the ACS (1280) comprises a first polycrystalline silicon layer (1281) and a second polycrystalline silicon layer (1282). A thin film deposition process such as CVD, PVD, ALD, sputtering, evaporation, or any combination thereof may be used to deposit the first polycrystalline silicon layer (1281) on the back side of the second etching stop layer (552) and cover the exposed portions of the memory string (212), GLS (216), dummy channel structure (763), and TSV (976). Next, the first polycrystalline silicon layer (1281) may be doped with p-type or n-type impurities using, for example, an ion implantation process, and then an annealing process (e.g., laser annealing, rapid thermal annealing, etc.) may be used to activate the impurities and reduce defects caused by the ion implantation process. Similarly, a second polycrystalline silicon layer (1282) may be disposed on the first polycrystalline silicon layer (1281) from the back side using similar techniques (e.g., ion implantation and annealing). The second polycrystalline silicon layer (1282) may have different impurities and / or impurity concentrations than the first polycrystalline silicon layer (1281). In some embodiments, the ACS (1280) may comprise one or more polycrystalline silicon layers that are in-situ doped during deposition (e.g., CVD, PVD, ALD, etc.).

[0136] In a three-dimensional memory structure (1200), the ACS (1280) can contact an exposed portion of the channel layer (338) and thereby provide electrical connection to the channel layer (338) of the memory string (212). As previously described, the exposed portion of the channel layer (338) can be increased by recessing the memory film (337). Additionally, the contact area between the ACS (1280) and the channel layer (338) can also be increased. Therefore, the contact resistance between the channel layer (338) of the memory string (212) and the ACS (1280) can be reduced, thereby improving the performance of the 3D memory. Note that the ACS can contact the channel layer (338) of a plurality of memory strings (212). In some embodiments, the ACS can provide electrical connection to all memory strings (212) within the same memory block. In some embodiments, the ACS (1280) may cover the exposed portions of the dummy channel structure (763), GLS (216), and TSV (976).

[0137] In some embodiments, the second etching stop layer (552) may also be used as a spacer between the film stack (335) and the ACS (1280). By adjusting the thickness of the second etching stop layer (552), the distance between the ACS (1280) and the conductive layer (870) (i.e., the word line (333) as in FIG. 3) can be effectively controlled.

[0138] Referring to FIG. 4, in process step (S465), a dielectric filling layer can be placed on the back side of the ACS. A cross-sectional view of an exemplary 3D memory structure (1300) according to process step (S465) is shown in FIG. 13.

[0139] As shown in FIG. 13, the dielectric packing layer (1384) may be placed on the back side of the ACS (1280) (i.e., the side away from the film stack (335)). The dielectric packing layer (1384) may be placed by any suitable thin film deposition technique, for example, CVD (e.g., high-density plasma chemical vapor deposition), PVD, ALD, sputtering, evaporation, or a combination thereof. The dielectric packing layer (1384) may comprise silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. In some embodiments, the back side of the dielectric packing layer (1384) (the side away from the film stack (335)) may be flattened using a CMP process.

[0140] Referring to FIG. 4, in process step (S470), a first contact opening and a second contact opening may be formed in the dielectric filling layer and the ACS and TSV may be exposed, respectively. A cross-sectional view of an exemplary 3D memory structure (1400) according to process step (S470) is shown in FIG. 14.

[0141] As shown in FIG. 14, the 3D memory structure (1400) includes a first contact opening (1490) formed in the dielectric filling layer (1384) to expose at least a portion of the ACS (1280). The first contact opening (1490) penetrates the dielectric filling layer (1384) and the ACS (1280). In some embodiments, the first contact opening (1490) further penetrates the second etching stop layer (552) and enters the insulating layer (660). The first contact opening (1490) exposes the TSV (976) from the back side of the film stack (335), removes a portion of the ACS (1280) surrounding the TSV (976), and electrically insulates the TSV (976) from the ACS (1280). The first contact opening (1490) can be formed by an etching process including lithography and dry etching or wet etching.

[0142] In some embodiments, an insulating spacer (1491) may be formed on the sidewall of the first contact opening (1490). The insulating spacer (1491) may comprise any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. The insulating spacer (1491) may be formed by thin film deposition (e.g., CVD, PCV, ALD, sputtering, etc.) and anisotropic etching (e.g., RIE).

[0143] The 3D memory structure (1400) also includes a second contact opening (1492) formed in the dielectric filling layer (1384). The second contact opening (1492) penetrates the dielectric filling layer (1384) and exposes the ACS (1280). The second contact opening (1492) may be formed by an etching process including lithography and dry etching or wet etching. Unlike the first contact opening (1490), the etching process for the second contact opening (1492) does not remove the ACS (1280). In some embodiments, the first contact opening (1490) and the second contact opening (1492) may be formed sequentially through different lithography and etching processes. In some embodiments, the first contact opening (1490) may be formed before the second contact opening (1492), or vice versa. Note that FIG. 14 illustrates only one first contact opening (1490) and one second contact opening (1492). However, the number and arrangement of the first contact opening (1490) and the second contact opening (1492) are not so limited and may be any appropriate number or arrangement as needed.

[0144] After forming a first contact opening (1490) and a second contact opening (1492) in the dielectric filling layer (1384), an interlayer dielectric (ILD) layer (1486) may be formed. The ILD layer (1486) (also referred to as an "intermetallic dielectric (IMD) layer") may include one or more insulating materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, TEOS, polyimide, spin-on-glass, etc.), which may provide insulation for metal interconnections formed in a subsequent process.

[0145] In some embodiments, the ILD layer (1486) also includes a back-side deep trench insulation (BDTI) (1488). The BDTI (1488) may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. In some embodiments, the BDTI (1488) may include a dielectric material different from the dielectric filling layer (1384) and the insulating spacer (1491), such as a high-dielectric constant material (high-k dielectric).

[0146] In some embodiments, the BDTI (1488) may be deposited on the sidewall of the first contact opening (1490) before the insulating spacer (1491) is deposited. In this example, the BDTI (1488) may be formed by anisotropic etching followed by thin film deposition. In some embodiments, the BDTI (1488) may be formed anywhere in the dielectric filling layer (1384). The BDTI (1488) may penetrate the dielectric filling layer (1384) and the ACS (1280) and may extend further into the insulating layer (660). In this example, the BDTI (1488) may be formed by a thin film deposition process (e.g., CVD, PVD, ALD, etc.) following an etching process (e.g., dry / wet etching). BDTI (1488) may be coplanar with the ILD layer (1486) on the back side (the side away from the film stack (335)) through a planarization process (e.g., CMP).

[0147] Referring to FIG. 4, in process step (S475), a back interconnect layer having an ACS contact structure and a TSV contact structure can be formed on the back side of the ILD layer. A cross-sectional view of an exemplary 3D memory structure (1500) according to process step (S475) is shown in FIG. 15.

[0148] As shown in FIG. 15, the 3D memory structure (1500) includes a back interconnect layer (1594) having an ACS contact structure (1595) and a TSV contact structure (1596). The back interconnect layer (1594) may be formed on the back side of the ILD layer (1486) on the side far from the film stack (335). The back interconnect layer (1594) may be any suitable conductive material, for example, tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, silicide (WSi x , CoSi x , NiSi x , AlSi x It may include metals or metal alloys, or any combination thereof. The conductive material may be deposited by one or more thin film deposition processes, such as CVD, PVD, ALD, sputtering, plating, evaporation, or a combination thereof. After placing the conductive material inside the first contact opening (1490) and the second contact opening (1492) (in FIG. 14), the conductive material may be patterned and may form an ACS contact structure (1595) and a TSV contact structure (1596) having an insulating gap (1597) between the contact structures through processes such as lithography, etching, planarization (e.g., CMP).

[0149] The ACS contact structure (1595) can provide an electrical connection to the channel layer (338) of the memory string (212) from the back side of the ACS (1280) (the side away from the membrane stack (335)). The connection to the ACS (1280) drawn from the back side can save area and thereby increase the storage capacity of the 3D memory.

[0150] The TSV contact structure (1596) can provide an electrical connection to the TSV (976) from the back side of the ILD layer (1486) (the side far from the film stack (335)). As previously mentioned, the TSV (976) can provide an electrical connection to a peripheral device (50) in the peripheral circuit (600B) via the contact structure (64) and / or the conductive line (66) (see FIG. 6b). Accordingly, the electrical connection to the peripheral device can be wired from the back side of the ILD layer (1486). Similarly, the connection to the peripheral device drawn from the back side can save area and thus increase the storage capacity of the 3D memory.

[0151] In some embodiments, the insulating gap (1597) may be formed through a dry / wet etching process to separate the ACS contact structure (1595) and the TSV contact structure (1596). In some embodiments, to further avoid crosstalk between the ACS contact structure (1595) and the TSV contact structure (1596) when receiving and transmitting signals, a dielectric material may be placed inside the insulating gap (1597), the dielectric material may be silicon oxide, silicon nitride, silicon oxynitride, TEOS, polyimide, spin-on-glass, etc., and may be placed by any suitable process such as CVD, PVD, ALD, sputtering, evaporation, spinning-on, etc.

[0152] In some embodiments, the back interconnect layer (1594) (including the TSV contact structure (1596) and the ACS contact structure (1595)) may be coplanar with the ILD layer (1486) through a planarization process (e.g., CMP). In this example, the back interconnect layer (1594) may be embedded inside or recessed into the ILD layer (1486).

[0153] In addition, the present disclosure provides a 3D memory device manufactured using the method (400) described above.

[0154] FIG. 16 illustrates a 3D memory device (1600) according to some embodiments of the present disclosure. The 3D memory device (1600) includes a film stack (335) in which a conductive layer and a dielectric layer are alternately stacked, an ILD layer (1486), and an ACS (1280) located between the film stack (335) and the ILD layer (1486).

[0155] The film stack (335) comprises a conductive layer (870) and a first dielectric layer (656) that are alternately stacked in a vertical direction. The first dielectric layer (656) comprises any suitable insulating material, for example, silicon oxide, silicon oxynitride, silicon nitride, TEOS, or silicon oxide containing F-, C-, N-, and / or H-. The first dielectric layers (656) may have the same thickness or different thicknesses, and the thicknesses may be in the range between 10 nm and 500 nm. In some embodiments, the first dielectric layer (656) may be silicon oxide having a thickness of about 25 nm. The conductive layer (870) comprises any suitable metal or metal alloy such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), cobalt (Co), nickel (Ni), titanium nitride (TiN), tungsten nitride (WN), tantalum (Ta), tantalum nitride (TaN), AlTi, or any combination thereof. The conductive layers (870) may have the same thickness or different thicknesses, and the thickness may be in the range of 10 nm to 500 nm. In some embodiments, the conductive layer (870) comprises W with a thickness of about 35 nm.

[0156] Additionally, the film stack (335) may include a gate dielectric layer (872) surrounding a conductive layer (870). The gate dielectric layer (872) may include any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, and / or any suitable combination thereof. The gate dielectric layer (872) may also include a high dielectric constant material, for example, hafnium oxide, zirconium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, and / or any combination thereof. In some embodiments, the film stack (335) may also include a gate adhesive layer (874) sandwiched between the gate dielectric layer (872) and the conductive layer (870). The gate adhesive layer (874) may be used to promote adhesion between the gate dielectric layer (872) and the conductive layer (870). The gate adhesive layer (874) may include, for example, tantalum nitride (TaN) and / or titanium nitride (TiN).

[0157] Additionally, the 3D memory device (1600) includes a step structure (657) formed in a film stack (335) in a step region (210). The step structure (657) includes a plurality of step steps (659). A step step (659), or “step layer,” refers to a stack of layers having the same transverse dimensions parallel to the conductive layer (870) and the first dielectric layer (656). Each of the step steps (659) ends with a length shorter than the step step below.

[0158] Additionally, the 3D memory device (1600) includes an insulating layer (660) disposed on a step structure (657) and a film stack (335). The insulating layer (660) may also be disposed on the ACS (1280) in the peripheral region (105). The insulating layer (660) includes low dielectric constant materials such as silicon oxide, silicon oxynitride, silicon nitride, TEOS, spin-on-glass, carbon-doped oxide (CDO or SiOC or SiOC:H), or fluorine-doped oxide (SiOF). In some embodiments, the insulating layer (660) may have a flat surface on the step structure (657) in the step region (210), the film stack (335) in the channel structure region (211), and the ACS (1280) in the peripheral region (105).

[0159] The 3D memory device (1600) also includes a plurality of memory strings (212) in a channel structure region (211), and the memory strings (212) penetrate vertically through the film stack (335). In some embodiments, the memory strings extend into the ACS (1280) and the ILD layer (1486). In some embodiments, the memory strings (212) may be cylindrical in shape. The memory strings (212) may include a core filling film (339) at the center, and the core filling film (339) may be surrounded by the channel layer (338). The core filling film (339) may include any suitable insulator, for example, silicon oxide, silicon nitride, silicon oxynitride, spin-on-glass, silicon oxide doped with boron or phosphorus, carbon-doped oxide (CDO or SiOC or SiOC:H), fluorine-doped oxide (SiOF), or any combination thereof. The channel layer (338) may comprise any suitable semiconductor, such as polycrystalline silicon, having a thickness in the range of about 10 nm to about 30 nm. The memory string (212) may also comprise a memory film (337) that covers the sidewalls of the channel layer (338), i.e., surrounds the channel layer (338). The memory film (337) may be a composite layer comprising a tunnel layer, a storage layer (also called a "charge trap / storage layer"), and a blocking layer. In some embodiments, the tunnel layer, the storage layer, and the blocking layer are arranged in the above order along a direction from the center of the memory string (212) toward the outside of the memory string (212). The tunnel layer may comprise silicon oxide, silicon nitride, or any combination thereof. The blocking layer may comprise silicon oxide, silicon nitride, a high-k dielectric, or any combination thereof. The storage layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof.In some embodiments, the memory film (337) comprises an ONO dielectric (e.g., a tunnel layer including silicon oxide, a storage layer including silicon nitride, and a blocking layer including silicon oxide). In some embodiments, the thickness of the memory film (337) may be within the range of about 10 nm to about 50 nm. The three-dimensional memory device (1600) comprises a plurality of vertically stacked memory cells (340). The memory cells (340) are formed at the intersection between the conductive layer (870) and the memory string (212). The conductive layer (870) may form the word line (333) of FIG. 3 to address the memory cells (340).

[0160] In some embodiments, the memory string (212) also includes an epitaxial plug (not shown in FIG. 16) at the bottom of the memory string (212) (closer to the ACS (1280)). The epitaxial plug may include any suitable semiconductor material such as silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, III-V compounds, or any combination thereof. In some embodiments, the epitaxial plug may include a polycrystalline semiconductor material, for example, polycrystalline silicon. The epitaxial plug may be connected to the channel layer (338) of the memory string (212).

[0161] In some embodiments, the memory string (212) may also include a channel top plug (762) configured to provide electrical contact to the channel layer (338). A bit line (not shown) of the 3D memory device (1600) may address a memory cell (340) through the channel top plug (762). The channel top plug (762) may be amorphous or polycrystalline silicon and may include a metal, metal alloy and / or metal silicide, for example, tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, or a combination thereof.

[0162] The 3D memory device (1600) also includes a GLS (216) that penetrates vertically through the film stack (335). In some embodiments, the GLS (216) extends further into the ACS (1280) and ILD layer (1486). The GLS (216) may include a GLS filler (871), and the GLS filler (871) may include any suitable insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc.

[0163] In some embodiments, the 3D memory device (1600) also includes a dummy channel structure (763) in the step region (210). The dummy channel structure (763) extends vertically through the insulating layer (660) and the step structure (657). In some embodiments, the dummy channel structure (763) extends into the ACS (1280) and the ILD layer (1486). The dummy channel structure (763) may be configured to provide mechanical support to the 3D memory device (1600) during various manufacturing processes. The dummy channel structure (763) may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, a high dielectric constant material (Al2O3, HfO2, Ta2O3, ZrO2, La2O3, etc.), or any combination thereof.

[0164] The 3D memory device (1600) further includes a TSV (976) penetrating the insulating layer (660). In some embodiments, the TSV (976) extends into the ILD layer (1486) through the ACS (1280). The TSV (976) may comprise any suitable conductive material, such as a metal or metal alloy including tungsten, titanium, tantalum, tungsten nitride, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tungsten silicide, titanium silicide, or a combination thereof. In some embodiments, the TSV (976) may be configured to provide electrical connections to peripheral devices in the surrounding area.

[0165] The ACS (1280) comprises one or more polycrystalline silicon layers (e.g., a first polycrystalline silicon layer (1281) and a second polycrystalline silicon layer (1282)). One or more polycrystalline silicon layers may be doped with n-type or p-type impurities. The ACS (1280) is in contact with the channel layer (338) of the memory string (212). The ACS (1280) surrounds a portion of the memory string (212) that extends to the ILD layer (1486), and the memory film (337) is removed from this portion of the memory string (212) so that the ACS (1280) is in contact with the channel layer (388). In other words, the memory film (337) covers a first portion of the channel layer (388), and the ACS (1280) covers a second portion of the channel layer (388). The contact area between the channel layer (388) and the ACS (1280) can be increased by further retracting the memory film (337) in a direction away from the ACS (1280) (or toward the film stack (335)). Thus, the contact resistance between the ACS (1280) and the channel layer (388) can be reduced and the performance of the 3D memory device (1600) can be improved.

[0166] Similarly, the ACS (1280) may also surround a portion of the GLS (216) extending into the ILD layer (1486). The ACS (1280) may also surround a portion of the dummy channel structure (763) extending into the ILD layer (1486). In some embodiments, the ACS (1280) is separated from the TSV (976) by electrical insulation provided by an insulating spacer (1491) and / or a BDTI (1488). The ACS (1280) may provide mechanical support for the membrane stack (335).

[0167] The three-dimensional memory device (1600) further comprises a back interconnect layer (1594) formed on the back side of the ACS (1280) on the side far from the film stack (335). The back interconnect layer (1594) comprises an ACS contact structure (1595) and a TSV contact structure (1596), and an insulating gap (1597) may be formed between the ACS contact structure (1595) and the TSV contact structure (1596). The back interconnect layer (1594) may be any suitable conductive material, for example, tungsten (W), cobalt (Co), copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), nickel, or silicide (WSi x , CoSi x , NiSi x , AlSi x It includes metals or metal alloys such as (etc.), or any combination thereof. The ACS contact structure (1595) contacts the ACS (1280), and the TSV contact structure (1596) contacts the TSV (976). The ACS contact structure (1595) can provide electrical connection to the channel layer (388) of the memory string (212) through the ACS (1280). The TSV contact structure (1596) can provide electrical connection to a peripheral device through the TSV (976).

[0168] The ILD layer (1486) comprises one or more insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, TEOS, polyimide, spin-on-glass, etc., which can provide insulation for the back interconnect layer (1594). The ILD layer (1486) may comprise an insulating spacer (1491) and a BDTI (1488). The BDTI (1488) may comprise any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS, etc. In some embodiments, the BDTI (1488) may comprise a dielectric material different from the insulating spacer (1491), for example, a high dielectric constant material.

[0169] In some embodiments, the 3D memory device (1600) also includes a second etching stop layer (552) disposed between the film stack (335) and the ACS (1280). In some embodiments, the second etching stop layer (552) may also be disposed between the insulating layer (660) and the ACS (1280). The distance between the film stack (335) and the ACS (1280) may be determined by the thickness of the second etching stop layer (552).

[0170] In some embodiments, the 3D memory device (1600) also includes a first capping layer (766) and a second capping layer (868) disposed on the front side of the insulating layer (660) over the memory string (212), GLS (216), and dummy channel structure (763). The front side of the insulating layer is the side away from the ACS (1280) and ILD layer (1486). In some embodiments, the memory string (212) and the dummy channel structure (763) are coplanar with the insulating layer (660). In some embodiments, the GLS (216) is coplanar with the first capping layer (766). In some embodiments, the TSV (976) is coplanar with the second capping layer (868).

[0171] As described above, the channel layer (338) of the memory string (212) can be connected via an ACS contact structure (1595) on the back side of the membrane stack (335), which can be called a source terminal. The channel layer (338) of the memory string (212) can also be connected via a channel top plug (762) on the front side of the membrane stack (335), which can be called a drain terminal. The drain terminal of the memory string (212) can be connected to a bit line, and the source terminal of the memory string (212) of the same memory block (or sub-block) can be connected together via an ACS (1486). The ACS contact structure (1595) through the back side of the membrane stack (335) can save area and increase storage capacity for the 3D memory device (1600).

[0172] Conventionally, in order to form an electrical connection to the channel layer (338) from the bottom of the memory string (212) (at the source terminal), it was necessary to remove the memory film (337) from the bottom surface of the channel hole (336). By removing the memory film (337) and providing electrical contact to the channel layer (338) through the ACS contact structure (1595) from the back surface, it is possible to avoid etching the memory film (337) from the bottom of the channel hole (336) having a high aspect ratio. Furthermore, it is possible to avoid filling a portion of the GLS (216) with a conductive material to provide an electrical connection to the ACS (1280). Thus, a leak path from the conductive layer (870) to the GLS (216) filled with a conductive material can be eliminated. In addition, by using the first etching stop layer (550) and the second etching stop layer (552), the substrate (330) and the memory film (337) can be controlledly removed from the back side. Process uniformity and yield can be greatly improved.

[0173] FIG. 17 shows a block diagram of an exemplary system (S1) having a storage system (10) according to some embodiments of the present disclosure. The system (S1) may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. The storage system (10) (also called a NAND storage system) comprises a memory controller (20) and one or more semiconductor memory chips (25-1, 25-2, 25-3, ..., 25- n It may include ). Each semiconductor memory chip (25) (hereinafter simply "memory chip") may be a NAND chip (i.e., "flash," "NAND flash," or "NAND"). The storage system (10) may communicate with the host computer (15) through the memory controller (20), and the memory controller (20) may have one or more memory channels (30-1, 30-2, 30-3, ..., 30- n One or more memory chips (25-1, 25-2, 25-3, ..., 25-) through ) n It can be accessed via ). In some embodiments, each memory chip (25) can be managed by a memory controller (20) through a memory channel (30).

[0174] In some embodiments, the host computer (15) may include a processor of an electronic device such as a central processing unit (CPU), or a system-on-chip (SoC) such as an application processor (AP). The host computer (15) transmits data to be stored in a NAND storage system or a storage system (10), or reads from the storage system (10) to retrieve data.

[0175] The memory controller (20) can process I / O requests received from the host computer (15), ensure data consistency and efficient storage, and manage the memory chip (25). To perform these tasks, the controller executes firmware (21), and this firmware (21) can be executed by one or more processors (22) (e.g., a microcontroller unit, a CPU) inside the controller (20). For example, the controller (20) executes firmware (21) to map a logical address (i.e., an address utilized by the host related to host data) to a physical address (i.e., the actual location where the data is stored) within the memory chip (25). Additionally, the controller (20) executes firmware (21) to manage a defective memory block within the memory chip (25), and the firmware (21) can remap the logical address to a different physical address, i.e., move the data to a different physical address. The controller (20) may also include one or more memories (23) (e.g., DRAM, SRAM, EPROM, etc.), which may be used to store various metadata used by the firmware (21). In some embodiments, the memory controller (20) may perform error recovery through an error correction code (ECC) engine (29). The ECC is used to detect and correct raw bit errors occurring within each memory chip (25).

[0176] The memory channel (30) can provide data and control communication between the memory controller (20) and each memory chip (25) via a data bus. The memory controller (20) can select one of the memory chips (25) according to a chip enable signal.

[0177] In some embodiments, each memory chip (25) of FIG. 17 may include one or more memory dies (100), and each memory die may be a 3D NAND memory (100) as shown in FIG. 1 to 3. In some embodiments, each of the one or more memory dies (100) may include a 3D memory device (1600) as shown in FIG. 16, which may be manufactured using the method (400) of FIG. 4.

[0178] The memory controller (20) and one or more memory chips (25) may be integrated within various types of storage devices, such as being included in the same package, for example, a Universal Flash Storage (UFS) package or an eMMC package. That is, the storage system (10) may be mounted and packaged in different types of end electronic products. In one example as shown in FIG. 18a, the memory controller (20) and a single memory chip (25) may be integrated into a memory card (26). The memory card (26) may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card (26) may further include a memory card connector (24) that couples the memory card (26) to a host (for example, the host computer (15) of FIG. 17). In another embodiment as shown in FIG. 18b, a memory controller (20) and a plurality of memory chips (25) can be integrated into a solid-state drive (SSD) (27). The SSD (27) may further include an SSD connector (28) that couples the SSD (27) to a host (e.g., the host computer (15) of FIG. 17).

[0179] FIG. 19 shows a schematic diagram of a memory die (100) according to some embodiment of the present disclosure. The memory die (100) includes one or more memory blocks (103) (e.g., 103-1, 103-2, 103-3). Each memory block (103) includes a plurality of memory strings (212). Each memory string (212) includes a plurality of memory cells (340). Memory cells (340) sharing the same word line form a memory page (432). Additionally, the memory string (212) may include at least one field-effect transistor (e.g., MOSFET) at both ends, which is controlled by a lower select gate (LSG) (332) and a top select gate (TSG) (334), respectively. The drain terminal of the top select transistor (334-T) can be connected to the bit line (341), and the source terminal of the lower select transistor (332-T) can be connected to the array common source (ACS) (430). The ACS (430) can be shared by the memory string (212) of the entire memory block and is also called the common source line.

[0180] In some embodiments, the ACS (430) may include the ACS (1280) shown in FIG. 16 and may be manufactured using the method (400) shown in FIG. 4. In this example, the memory die (100) may include the 3D memory device (1600) shown in FIG. 16.

[0181] Additionally, the memory die (100) may include many digital, analog, and / or mixed-signal circuits to support the function of the memory block (103), such as a page buffer / sense amplifier (50), a row decoder / word line driver (40), a column decoder / bit line driver (52), a control circuit (70), a voltage generator (65), and an input / output buffer (55). These circuits may include active and / or passive semiconductor devices such as transistors, diodes, capacitors, and resistors, as would be obvious to a person skilled in the art.

[0182] The memory block (103) can be coupled to a row decoder / word line driver (40) through a word line ("WL") (333), a lower select gate ("LSG") (332), and a top select gate ("TSG") (334). The memory block (103) can be coupled to a page buffer / sense amplifier (50) through a bit line ("BL") (341). The row decoder / word line driver (40) can select one of the memory blocks (103) on the memory die (100) in response to an X-path control signal supplied from a control circuit (70). The row decoder / word line driver (40) can transmit a voltage supplied from a voltage generator (65) to the word line according to the X-path control signal. During the read and program operation, the row decoder / word line driver (40) reads the voltage V according to the X-path control signal received from the control circuit (70). read and program voltage V pgm Transmit to the selected word line, and pass voltage V pass It can be sent to unselected word lines.

[0183] The column decoder / bit line driver (52) receives a Y-path control signal from the control circuit (70), and the inhibitor voltage V inhibitIt can transmit to an unselected bit line and connect the selected bit line to ground. In other words, the column decoder / bit line driver (52) may be configured to select or deselect one or more memory strings (212) according to a Y-path control signal from the control circuit (70). The page buffer / sense amplifier (50) may be configured to read data from the memory block (103) and program (write) data into the memory block (103) according to the control signal Y-path control from the control circuit (70). For example, the page buffer / sense amplifier (50) may store data of one page to be programmed in one memory page (432). In another embodiment, the page buffer / sense amplifier (50) may perform a verify operation to ensure that data is properly programmed in each memory cell (340). In another example, during a read operation, the page buffer / sense amplifier (50) can detect the current flowing through the bit line (341) that reflects the logic state (i.e., data) of the memory cell (340) and amplify the small signal to a measurable scale.

[0184] The input / output buffer (55) can transmit I / O data from / to the page buffer / sense amplifier (50) and an address ADDR or command CMD to the control circuit (70). In some embodiments, the input / output buffer (55) can function as an interface between the memory controller (20) (Fig. 1) and the memory die (100) on the memory chip (25).

[0185] The control circuit (70) can control the page buffer / sense amplifier (50) and the row decoder / word line driver (40) in response to a command CMD transmitted by the input / output buffer (55). During a program operation, the control circuit (70) can control the row decoder / word line driver (40) and the page buffer / sense amplifier (50) and program a selected memory cell. During a read operation, the control circuit (70) can control the row decoder / word line driver (40) and the page buffer / sense amplifier (50) and read a selected memory cell. The X-path control signal and the Y-path control signal include a row address X-ADDR and a column address Y-ADDR that can be used to specify the location of a selected memory cell of the memory block (103). The row address X-ADDR may include a page index (PD), a block index (BD), and a plane index (PL) to identify a memory page (432), a memory block (103), and a memory plane (101) (in the case of FIG. 1), respectively. The column address Y-ADDR may identify a byte or word of data in the memory page (432).

[0186] The voltage generator (65) can generate a voltage to be supplied to the word line and bit line under the control of the control circuit (70). As the voltage generated by the voltage generator (65), the read voltage V read , program voltage V pgm , pass voltage V pass , inhibitor voltage V inhibit There are others.

[0187] In summary, the present disclosure provides a method for forming a three-dimensional (3D) memory device. The method comprises: placing alternating dielectric stacks on a substrate—the alternating dielectric stacks include a first dielectric layer and a second dielectric layer alternately stacked on the substrate—; forming a channel structure extending into the substrate through the alternating dielectric stacks—the channel structure includes a channel layer placed on the sidewall of a memory film—; removing a portion of the substrate and the memory film extending into the substrate to expose a portion of the channel layer; and placing an array common source (ACS) on the exposed portion of the channel layer.

[0188] The present disclosure also provides a three-dimensional (3D) memory device. The three-dimensional memory device comprises an array common source (ACS); a film stack of alternatingly stacked conductive layers and dielectric layers comprising a conductive layer and a first dielectric layer alternately stacked on a first side of the ACS; a back interconnect layer disposed on a second side opposite to the first side of the ACS—the back interconnect layer comprises an ACS contact structure—; and a memory string penetrating the film stack. The memory string comprises a channel layer having a first portion covered by a memory film; and a second portion in contact with the ACS and electrically connected to the ACS contact structure.

[0189] The present disclosure also provides a memory storage system. The memory storage system comprises a three-dimensional (3D) NAND memory comprising an array common source (ACS); and a film stack of alternately stacked conductive layers and dielectric layers, comprising a conductive layer and a first dielectric layer alternately stacked on a first side of the ACS. Additionally, the 3D NAND memory comprises a back interconnect layer disposed on a second side of the ACS opposite to the first side, and the back interconnect layer comprises an ACS contact structure. The 3D NAND memory comprises a memory string penetrating the film stack, and the memory string comprises a channel layer having a first portion covered by a memory film; and a second portion in contact with the ACS and electrically connected to the ACS contact structure.

[0190] The foregoing description of specific embodiments will fully reveal the general nature of the present disclosure so that others, by applying their knowledge within the art, can easily modify and / or adapt these specific embodiments for various applications without departing from the general concept of the present disclosure and without excessive experimentation. Accordingly, based on the disclosure and guidance set forth in this specification, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the terminology or language of this specification is for descriptive purposes and not limiting, so that it may be interpreted by a person skilled in the art in light of the present disclosure and guidance.

[0191] The embodiments of the disclosure above have been described with the help of functional building blocks that exemplify the implementation of specific functions and their relationships. The boundaries of these functional building blocks have been defined arbitrarily for convenience of description in this specification. Alternative boundaries may be defined as long as the specific functions and their relationships are properly performed.

[0192] The sections of the description and summary of the invention may describe one or more (but not all) exemplary embodiments of the present disclosure as considered by the inventor(s) and are therefore not intended to limit the present disclosure and the appended claims in any way.

[0193] The scope and range of the present disclosure shall not be limited by any of the exemplary embodiments described above, but shall be defined only by the following claims and their equivalents.

Claims

Claim 1 A method for forming a three-dimensional (3D) memory device, comprising: a step of placing alternating dielectric stacks on a substrate — said alternating dielectric stacks include a first dielectric layer and a second dielectric layer alternately stacked on said substrate —; a step of placing an insulating layer covering said alternating dielectric stacks on said substrate; a step of forming a channel structure penetrating said alternating dielectric stacks and extending into said substrate — said channel structure includes a channel layer placed on a sidewall of a memory film —; and a step of removing said substrate and a portion of said memory film extending into said substrate so as to expose a portion of said channel layer. The method comprises the steps of: placing an array common source (ACS) on an exposed portion of the channel layer — said ACS comprises a first doped semiconductor layer and a second doped semiconductor layer —; forming a through-silicon-via (TSV) in a peripheral region — said TSV extends into the substrate by penetrating the insulating layer —; placing a dielectric filling layer on the backside of the ACS — said backside of the ACS is the side further away from the alternating dielectric stack —; placing an ACS contact structure to contact the ACS; and placing a TSV contact structure to contact the TSV from the backside of the dielectric filling layer, wherein the step of placing the TSV contact structure includes the step of forming a first contact opening in the dielectric filling layer to expose at least a portion of the ACS; A method for forming a three-dimensional memory device comprising the step of forming an insulating spacer on the sidewall of the first contact opening, wherein the insulating spacer formed on the sidewall of the TSV contact structure extends through the ACS and insulates the TSV and the ACS. Claim 2 A method for forming a three-dimensional memory device according to claim 1, further comprising the steps of: placing a first etching stop layer on the substrate; placing a second etching stop layer on the first etching stop layer; and placing the alternating dielectric stack on the second etching stop layer. Claim 3 A method for forming a three-dimensional memory device according to claim 2, wherein the step of removing the portion of the memory film extending into the substrate and the portion of the memory film extending into the substrate comprises: removing the substrate to expose the portion of the memory film extending into the substrate and stopping it on the first etching stop layer; and removing the first etching stop layer and the exposed portion of the memory film to expose the portion of the channel layer and stopping it on the second etching stop layer. Claim 4 A method for forming a three-dimensional memory device according to claim 1, wherein the step of forming the TSV contact structure includes the step of electrically connecting the TSV contact structure to a peripheral device in the peripheral region through the TSV. Claim 5 A method for forming a three-dimensional memory device according to claim 1, further comprising the step of forming a step structure in the alternating genome stack. Claim 6 A method for forming a three-dimensional memory device according to claim 5, further comprising: forming a dummy channel structure penetrating the step structure and extending into the substrate; removing the substrate to expose a portion of the dummy channel structure extending into the substrate; and placing an ACS on the exposed portion of the dummy channel structure. Claim 7 A method for forming a three-dimensional memory device according to claim 1, further comprising: forming a gate line slit (GLS) opening that penetrates the alternating dielectric stack and extends into the substrate; replacing the second dielectric layer with a conductive layer to form a film stack in which a conductive layer and a dielectric layer are alternately stacked — the film stack comprises the conductive layer and the first dielectric layer alternately stacked on the substrate —; and placing a GLS filler inside the GLS opening to form the GLS. Claim 8 A method for forming a three-dimensional memory device according to claim 7, further comprising the steps of: removing the substrate to expose a portion of the GLS extending into the substrate; and placing the ACS on the exposed portion of the GLS. Claim 9 A three-dimensional (3D) memory device comprising: an array common source (ACS) including a first doped semiconductor layer and a second doped semiconductor layer; a film stack in which a conductive layer and a dielectric layer are alternately stacked—the film stack includes a conductive layer and a first dielectric layer alternately stacked on a first side of the ACS—; an interlevel dielectric (ILD) layer disposed on a second side of the ACS facing the first side; an insulating spacer extending through the first doped semiconductor layer and the second doped semiconductor layer; and a back interconnect layer disposed on a second side of the ACS opposite to the first side—the back interconnect layer includes an ACS contact structure in contact with the ACS and a TSV contact structure in contact with a through-silicon-via (TSV), wherein an insulating spacer formed on the sidewall of the TSV contact structure extends through the ACS and the A 3D memory device comprising: a TSV contact structure and insulating the ACS; and a memory string penetrating the film stack, wherein the memory string comprises a channel layer, and the channel layer comprises: a first portion covered with a memory film; and a second portion in contact with the ACS and electrically connected to the ACS contact structure. Claim 10 A 3D memory device according to claim 9, further comprising an insulating layer disposed on the first surface of the membrane stack and the ACS. Claim 11 A 3D memory device according to claim 10, further comprising the TSV penetrating the insulating layer, wherein the back interconnect layer comprises the TSV contact structure electrically connected to the TSV. Claim 12 In claim 11, the TSV contact structure is a 3D memory device electrically connected to a peripheral device via the TSV. Claim 13 A 3D memory device according to claim 9, wherein the ILD layer further comprises backside deep trench isolation (BDTI) comprising a dielectric material different from the insulating spacer. Claim 14 In claim 9, the ACS is a 3D memory device comprising a p-type or n-type doped polycrystalline silicon layer. Claim 15 A 3D memory device according to claim 9, wherein the first side of the TSV contact structure is located below the first side of the ACS contact structure, the first side of the ACS contact structure is in contact with the ACS, and the first side of the TSV contact structure is in contact with the TSV. Claim 16 A 3D memory device according to claim 15, wherein the second side of the TSV contact structure includes a groove, and the second side of the TSV contact structure is located on the opposite side of the first side of the TSV contact structure. Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete Claim 26 delete Claim 27 delete Claim 28 delete Claim 29 delete Claim 30 delete Claim 31 delete Claim 32 delete Claim 33 delete Claim 34 delete Claim 35 delete Claim 36 delete Claim 37 delete Claim 38 delete

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