Semiconductor device comprising two-dimensional electron gas and method of manufacturing the same

Abstract

The present invention relates to a semiconductor device, and more specifically, to a semiconductor device that forms a two-dimensional electron gas (2DEG) in an Al2O3 / In2O3 stacked structure and a method for manufacturing the same. The present invention provides a semiconductor device comprising: a substrate; a first oxide layer formed on the substrate; and a second oxide layer formed on the first oxide layer, wherein a two-dimensional electron gas (2DEG) is formed at the interface between the first oxide layer and the second oxide layer, wherein the first oxide layer comprises one or more of Al2O3, HfO2, and ZrO2, and the second oxide layer comprises one or more of In2O3, ZnO, and TiO2.

Description

Technology Field

[0001] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device that forms a two-dimensional electron gas (2DEG) in an Al2O3 / In2O3 stacked structure and a method for manufacturing the same. Background Technology

[0002] Two-dimensional electron gas (2DEG) is receiving significant attention in the field of next-generation electronic devices due to its high electron mobility and excellent conductivity, and can potentially be utilized in applications such as conductive bridge random access memory (CBRAM) and thin-film transistors (TFT).

[0003] Early 2DEG research focused on single-crystal LaAlO3 / SrTiO3, where a "polar catastrophe" induces electronic reconstruction and generates quantized 2DEG. However, these systems have limitations in that they are difficult to apply to CMOS applications because they rely on complex epitaxial growth and crystalline perovskite underoxides.

[0004] Recently, atomic layer deposition (ALD)-based oxide heterostructures have emerged as a practical alternative. By depositing an Al2O3 (AO) layer on a base oxide (e.g., TiO2, ZnO, In2O3) with relatively low oxide formation energy, the strong reducing chemistry of trimethylaluminum (TMA) promotes oxygen vacancies (VO), enabling strong 2DEG conductivity even under polycrystalline or amorphous base oxide conditions.

[0005] However, such "reduction-process-induced" 2DEG formation generally assumes a channel-leading approach (i.e., Al2O3 deposition using TMA over a pre-formed oxide channel). With the emergence of 3D memory technology, a channel-backward process has become necessary, in which the oxide channel is deposited after the gate oxide is formed to enable vertical stacking and back-gate designs. Therefore, demonstrating 2DEG formation on post-deposited oxide channels is crucial for expanding 2DEG applications beyond existing planar or channel-leading device architectures.

[0006] Among candidate bottom oxides for ALD-based 2DEGs, In2O3 (IO3) is attracting attention due to its high electron mobility attributed to the large overlap of In 5s orbitals. However, bulk In2O3 has many oxygen vacancies acting as donors, which leads to a critical voltage (V) in TFT applications. th There is a problem of shifting ) to very negative values. Strategies to mitigate this problem include reducing channel thickness or doping In2O3 with elements having higher oxide dissociation energies (e.g., W, Ga). Forming a 2DEG on the In2O3 surface confines carriers to the sub-nanometer region, enabling effective gate control and positive V th It can induce movement. Prior art literature

[0007] Republic of Korea Registered Patent Publication No. 10-2508546 The problem to be solved

[0008] The objective of the present invention is to provide a semiconductor device that forms a two-dimensional electron gas (2DEG) in an Al2O3 / In2O3 stacked structure and a method for manufacturing the same. In particular, the invention aims to provide a structure and a method in which a 2DEG can be formed not only in the conventional channel-leading method but also in the channel-following method. means of solving the problem

[0009] The present invention comprises a substrate; a first oxide layer formed on the substrate; and a second oxide layer formed on the first oxide layer, wherein a two-dimensional electron gas (2DEG) is formed at the interface between the first oxide layer and the second oxide layer, and the first oxide layer is Al2O3, A semiconductor device is provided that comprises one or more of HfO2 and ZrO2, and the second oxide layer comprises one or more of In2O3, ZnO, and TiO2.

[0010] It further comprises a third oxide layer formed on the second oxide layer, wherein the third oxide layer is Al2O3, It includes one or more of HfO2 and ZrO2, and an additional two-dimensional electron gas (2DEG) may be formed at the interface between the second oxide layer and the third oxide layer.

[0011] The above two-dimensional electron gas may be induced by the difference in oxide formation Gibbs free energy between the oxide contained in the first oxide layer and the oxide contained in the second oxide layer, for example, Al2O3 and In2O3.

[0012] The present invention also comprises the steps of: forming a first oxide layer on a substrate; and forming a second oxide layer on the first oxide layer; wherein the first oxide layer is Al2O3, A method for manufacturing a semiconductor device is provided, wherein the second oxide layer comprises one or more of HfO2 and ZrO2, and the second oxide layer comprises one or more of In2O3, ZnO, and TiO2, and a two-dimensional electron gas (2DEG) is formed at the interface between the first oxide layer and the second oxide layer.

[0013] The present invention further comprises the step of forming a third oxide layer on the second oxide layer; wherein the third oxide layer is Al2O3, A method for manufacturing a semiconductor device is provided, comprising one or more of HfO2 and ZrO2, wherein an additional two-dimensional electron gas (2DEG) is formed at the interface between the second oxide layer and the third oxide layer.

[0014] The thickness of the first oxide layer may be 0.5 nm to 20 nm.

[0015] The thickness of the second oxide layer may be 0.5 nm to 20 nm.

[0016] The present invention also provides a transistor comprising the semiconductor element.

[0017] The present invention also provides a memory device including the semiconductor element. Effects of the invention

[0018] According to the present invention, 2DEG formation is possible in an Al2O3 / In2O3 stacked structure in both a channel-leading and channel-lagging manner, thereby greatly improving the flexibility of semiconductor device manufacturing. In particular, 2DEG is formed even when In2O3 is deposited on Al2O3 (POST-IO), so it can be utilized in various application fields such as backend-of-line (BEOL) transistors or 3D hole-channel fill architectures.

[0019] The POST-IO 2DEG of the present invention occurs only from "material-based" thermodynamic driving forces—particularly the difference in oxide formation Gibbs free energy between Al2O3 and In2O3—so it is distinguished from the reduction pathway of pre-deposited In2O3 (PRE-IO) based on conventional TMA processes. Brief explanation of the drawing

[0020] FIG. 1 is a cross-sectional TEM image of an Al2O3 / In2O3 / Al2O3 / In2O3 / Al2O3 nanolayer structure according to one embodiment of the present invention, wherein (a) is a full cross-sectional TEM image of an Al2O3 / In2O3 / Al2O3 / In2O3 / Al2O3 / SiO2 structure, (b) is a high-resolution TEM image of (a), (c) is an FFT pattern showing the crystal structure of the In2O3 layer, and (d) and (e) are surface AFM images of the In2O3-terminated and Al2O₃-terminated nanolayers, respectively. Figure 2 shows the results of angle-resolved X-ray photoelectron spectroscopy (ARXPS) analysis for a 10 nm In2O3 / 10 nm Al2O3 bilayer structure, where (a) is In measured at an 80° angle 3d Spectrum, (b) is In measured at an angle of 0° 3d Spectra, (c) shows the change in the chemical state of In according to the stage angle, and (d) shows the change in Gibbs free energy per oxygen atom of In2O3 and Al2O3 according to temperature. Figure 3 shows the results of energy band alignment analysis at the In2O3 / Al2O3 interface, where (a) is In in various samples 3d and Al 2p (b) shows the core level binding energy, the valence band structure of 15 nm In2O3 and 15 nm Al2O3 films, and (c) shows the calculated energy band alignment diagram. Figure 4 shows the results of measuring the electrical properties of various Al2O3 / In2O3 stacked structures, where (a)-(c) show the change in electron mobility according to In2O3 thickness, Al2O3 thickness, and number of interfaces, respectively, and (d)-(f) show the change in electrical resistivity according to In2O3 thickness, Al2O3 thickness, and number of interfaces, respectively. Figure 5 is a conceptual diagram showing the mechanism of 2DEG formation in the Al2O3 / In2O3 / Al2O3 structure of the present invention. The process of 2DEG formation and the movement of oxygen ions in both PRE-In2O3 and POST-In2O3 are schematically illustrated. Specific details for implementing the invention

[0021] The present invention comprises a substrate; a first oxide layer formed on the substrate; and a second oxide layer formed on the first oxide layer, wherein a two-dimensional electron gas (2DEG) is formed at the interface between the first oxide layer and the second oxide layer, and the first oxide layer is Al2O3, A semiconductor device is provided that comprises one or more of HfO2 and ZrO2, and the second oxide layer comprises one or more of In2O3, ZnO, and TiO2.

[0022] The embodiments described herein are subject to various modifications and may have various forms; specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the scope of specific embodiments and should be understood to include various modifications, equivalents, and / or alternatives of the embodiments of the present disclosure. In relation to the description of the drawings, similar reference numerals may be used for similar components.

[0023] In describing the present disclosure, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the present disclosure, such detailed description is omitted.

[0024] Additionally, the following embodiments may be modified in various other forms, and the scope of the technical concept of the present disclosure is not limited to the following embodiments. Rather, these embodiments are provided to make the present disclosure more faithful and complete and to fully convey the technical concept of the present disclosure to those skilled in the art.

[0025] The terms used in this disclosure are used merely to describe specific embodiments and are not intended to limit the scope of the rights. The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0026] In the present disclosure, expressions such as “have,” “may have,” “include,” or “may include” indicate the presence of such features (e.g., numerical values, functions, actions, or components such as parts) and do not exclude the presence of additional features.

[0027] In the present disclosure, expressions such as “A or B,” “at least one of A or / and B,” or “one or more of A or / and B” may include all possible combinations of items listed together. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” may refer to cases including (1) at least one A, (2) at least one B, or (3) both at least one A and at least one B.

[0028] Expressions such as "first," "second," "first," or "second" used in this disclosure may modify various components regardless of order and / or importance, and are used only to distinguish one component from another and do not limit said components.

[0029] Where it is stated that a component (e.g., Component 1) is "(operatively or communicatively) coupled with / to" or "connected to" another component (e.g., Component 2), it should be understood that the component may be directly connected to the other component or connected through the other component (e.g., Component 3).

[0030] On the other hand, when it is stated that a certain component (e.g., a first component) is "directly connected" or "directly coupled" to another component (e.g., a second component), it may be understood that no other component (e.g., a third component) exists between the certain component and the other component.

[0031] The expression “configured to” as used in this disclosure may be replaced, depending on the context, with, for example, “suitable for,” “having the capacity to,” “designed to,” “adapted to,” “made to,” or “capable of.” The term “configured to” may not necessarily mean only “specifically designed to” in hardware.

[0032] In the embodiment, the 'module' or 'part' performs at least one function or operation and may be implemented in hardware or software, or a combination of hardware and software.

[0033] Meanwhile, the various elements and areas in the drawings are depicted schematically. Accordingly, the technical concept of the present invention is not limited by the relative sizes or spacing depicted in the attached drawings.

[0034] Furthermore, it should be noted in advance that expressions such as upper side, top, lower side, bottom, side, front, and rear in the following description are based on the direction depicted in the drawings, and may be expressed differently if the direction of the object changes. The shapes and sizes of elements in the drawings may be exaggerated for clearer explanation.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0036] The terms “part” or “module” as used in the specification refer to software or hardware components, such as FPGAs or ASICs, and “part” or “module” perform certain roles. However, “part” or “module” is not limited to software or hardware. “Part” or “module” may be configured to reside in an addressable storage medium or configured to run on one or more processors. Thus, by example, “part” or “module” includes components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and “parts” or “modules” may be combined into a smaller number of components and “parts” or “modules,” or further separated into additional components and “parts” or “modules.”

[0037] Spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used to facilitate the description of the relationship between one component and other components as illustrated in the drawings. Spatially relative terms should be understood as encompassing different orientations of components during use or operation, in addition to the orientations depicted in the drawings. For example, if a component depicted in a drawing is inverted, a component described as "below" or "beneath" of another component may be placed "above" of that component. Therefore, the exemplary term "below" may encompass both the lower and upper directions. Components may also be oriented in other directions, and accordingly, spatially relative terms may be interpreted according to the orientation.

[0038] Hereinafter, embodiments according to the present disclosure are described in detail with reference to the attached drawings so that those skilled in the art can easily implement them.

[0039] The 'substrate' used in the present invention is a basic platform for manufacturing semiconductor devices, and generally, silicon (Si) wafers, glass substrates, sapphire substrates, flexible substrates, gallium nitride substrates, and germanium substrates may be used, but are not limited thereto. In a preferred embodiment of the present invention, a Si wafer with a thickness of 100 nm of SiO2 deposited thereon was used as the substrate. The substrate not only serves as a mechanical support for the semiconductor device but can also serve as a gate electrode. In particular, a highly doped Si wafer can serve as a gate electrode in a back-gate transistor structure.

[0040] The 'first oxide layer' is a layer formed directly on the substrate, such as Al2O3, It includes one or more of HfO2 and ZrO2. This layer is formed via atomic layer deposition (ALD) using trimethylaluminum (TMA) and water (H2O) as precursors. The thickness of the first oxide layer is in the range of 0.5 nm to 20 nm, preferably 1 nm to 4 nm. In particular, it was confirmed that a thickness of 2 nm exhibits optimal electrical properties.

[0041] Al2O3 has high oxide formation energy and acts as a thermodynamic sink for oxygen. This characteristic is a key factor in the formation of a 2DEG at the interface with the second oxide layer (In2O3). Additionally, Al2O3 generally has an amorphous structure and is characterized by a high dielectric constant and a wide band gap (approx. 6.7 eV).

[0042] The 'second oxide layer' is formed on the first oxide layer and contains one or more of In2O3, ZnO, and TiO2. This layer is also formed via atomic layer deposition (ALD), using (3-dimethylaminopropyl)dimethylindium (DADI) and ozone (O3) as precursors. The thickness of the second oxide layer is in the range of 0.5 nm to 20 nm, preferably 5 nm to 20 nm. Experimental results showed that at thicknesses of 15 nm or less, conduction was mainly dominated by the interface, and mobility remained almost constant.

[0043] In2O3 has high electron mobility due to the overlap of large In 5s orbitals. The In2O3 used in the present invention has a polycrystalline structure and is characterized by a band gap of about 3.2 eV. A single In2O3 layer exhibits an electron mobility of about 22.3 cm² / Vs, whereas a heterostructure with Al2O3 can achieve enhanced mobility of up to 48.6 cm² / Vs.

[0044] The 'third oxide layer' is an optional layer additionally formed on the second oxide layer and contains Al2O3. The formation method and characteristics of this layer are similar to those of the first oxide layer. The presence of the third oxide layer enables the formation of an additional 2DEG at the interface with the second oxide layer (In2O3). This can further enhance the overall conductivity in the nanolayered structure.

[0045] The semiconductor device of the present invention additionally comprises, on a third oxide layer, one or more oxides selected from In2O3, ZnO, and TiO2, and Al2O3, One or more oxides of HfO2 and ZrO2 may be alternately stacked. The thickness of the additional oxide layer may be 0.5 nm to 20 nm.

[0046] '2DEG' refers to a quantum mechanical state in which electrons can move freely only within a specific plane and are restricted in other directions. In the present invention, 2DEG is formed at the Al2O3 / In2O3 and In2O3 / Al2O3 interfaces. In the present invention, it was confirmed that 2DEG can also be formed at the In2O3 / Al2O3 interface. This suggests the possibility of applying 2DEG to 3D memory technology and the like, which requires a channel-backward process.

[0047] The Al2O3 / In2O3 nanolayer structure of the present invention can be utilized in various transistor applications. In particular, the high electron mobility characteristics of 2DEG are advantageous for realizing high-performance thin-film transistors (TFTs).

[0048] Furthermore, the Al2O3 / In2O3 nanolayer structure of the present invention can be applied to various memory devices. In particular, the characteristic of forming a 2DEG even in the channel-lagging method disclosed in the present invention is highly suitable for memory devices with a three-dimensional structure.

[0049] In vertical stacked structures such as 3D NAND flash memory, a hole-channel fill architecture is primarily used, which requires a channel-backward process in which a gate structure is formed first and then a channel material is deposited. When the Al2O3 / In2O3 structure of the present invention is applied to these vertical holes, high mobility channels can be formed, thereby improving read / write speeds and power efficiency.

[0051] Example 1: Al 2 O 3 / In 2 O 3 Formation of a stacked structure

[0052] In this embodiment, Al2O3 and In2O3 thin films were deposited on a 100 nm SiO2 / Si substrate using atomic layer deposition (ALD). For the deposition of In2O3, (3-dimethylaminopropyl)dimethylindium (DADI) and ozone (O3, 200 g / m³) were used. 3 ) were used as the In precursor and reactant, respectively, and TMA and H2O were used for Al2O3 deposition.

[0053] Both processes followed a conventional ALD sequence consisting of a supercycle of alternating injection of precursors and reactants at 300°C. For In2O3 deposition, the sequence included In precursor injection (3 sec), Ar purge (10 sec), O3 injection (5 sec), and Ar purge (5 sec). For Al2O3 deposition, the cycle included Al precursor injection (0.5 sec), Ar purge (10 sec), H2O injection (1 sec), and Ar purge (5 sec).

[0054] Example 2: Al 2 O 3 / In 2 O 3 / Al 2 O3 Analysis of nanolayered structure

[0055] In this embodiment, a double-stacked nanolayered structure composed of alternately stacked 5 nm In2O3 / 2 nm Al2O3 layers was formed, and additionally, a 12 nm thick Al2O3 capping layer was formed on the top. Figure 1 shows a cross-sectional TEM image of the Al2O3 / In2O3 / Al2O3 / In2O3 / Al2O3 nanolayered structure of this embodiment.

[0056] Transmission electron microscopy (TEM) analysis revealed that each layer was flat and continuous, with no voids or hill formations over a wide area. In high-resolution images, the In2O3 layer exhibited a clear polycrystalline structure, while the Al2O3 layer maintained an amorphous state. Additionally, distinct interfaces were identified, demonstrating the effectiveness of ALD for the fabrication of stacked nanolayers.

[0057] Analysis of atomic force microscopy (AFM) images revealed that both the top 5 nm In2O3 and 2 nm Al2O3 terminal nanolayers exhibited an RMS roughness of approximately 0.1 nm, confirming that the surface is smooth regardless of the terminal layer. This low roughness ensures uniform stacking of the In2O3 / Al2O3 nanolayers and provides a viable design window for 3D device structures.

[0058] Example 3: In 2 O 3 / Al 2 O 3 Confirmation of 2DEG formation at the interface

[0059] In this embodiment, angle-resolved X-ray photoelectron spectroscopy (ARXPS) analysis was performed on a bilayer sample composed of 10 nm In2O3 / 10 nm Al2O3 on a SiO2 / Si substrate. The results are shown in Figure 2.

[0060] At higher stage angles (e.g., 80°), measurements are more sensitive to the surface, whereas at lower angles (e.g., 0°), signals from deeper layers (~10 nm) are captured. In 3d at each angle 5 / 2 The peaks are In-OH, In 3+ , In 2+ , In 1+ It was broken down into components, which correspond to binding energies of 445.2 eV, 444.7 eV, 444.0 eV, and 443.5 eV, respectively.

[0061] As the stage angle decreases, In 3+ The intensity decreases and In 1+ - In 2+ The composition increased, suggesting the gradual formation of oxygen vacancies (VO) toward the In2O3 / Al2O3 interface. The faint In-OH peak (< 0.039) indicates that the OH-related effect enhancing mobility at the hetero-oxide interface was minimized here. Instead, the main mechanism for the formation of the conductive region in post-deposited In2O3 (POST-IO) appears to be due to VO.

[0062] The Gibbs free energies of In2O3 and Al2O3 per oxygen atom are shown in Fig. 2(d). This demonstrates that Al2O3 provides a more favorable thermodynamic absorbent for oxygen at the relevant device operating temperatures of 0–800°C, inducing oxygen migration from In2O3 to Al2O3 and consequently creating a VO-rich region at the interface. This "matter-driven" driving force provides a compelling explanation for the observed interfacial redox behavior. This interfacial redox process supports the formation of a 2DEG observed at the In2O3 / Al2O3 interface.

[0063] Example 4: In 2 O 3 / Al 2 O 3 Analysis of energy band alignment at the interface

[0064] In this embodiment, XPS measurements were performed to investigate the energy band alignment at the In2O / Al2O3 interface, and the results are shown in FIG. 3.

[0065] The binding energies of the In 3d and Al 2p core levels of 15 nm In2O3, 10 nm In2O3 / 5 nm Al2O3, 10 nm Al2O3 / 5 nm In2O3, and 15 nm Al2O3 films were measured. In addition, the valence band structure of 15 nm In2O3 and Al2O3 films was analyzed.

[0066] Since In2O3 and Al2O3 coexist in the X-ray photoelectron spectroscopy spectrum, the valence band offset (VBO) at the heterointerface cannot be obtained directly from the VBM value. Instead, it was calculated using the following equation:

[0067] VBO = (BE Al2p -VBM) AO,bulk - (BE In2d -VBM) IO,bulk - (BE Al2p -BE IO3d ) AO / IO,interface

[0068] Here, BE represents the binding energy of the core level indicated by each subscript, and the subscript to the right of the parentheses indicates the sample structure used to test the corresponding properties.

[0069] An energy band alignment diagram was constructed using the measured VBM value, VBO at the interface, and the reported band gap (3.2 eV for In2O3; 6.7 eV for amorphous Al2O3).

[0070] For bulk In2O3, the conduction band offset (CBO) is located at 1.45 eV above the Fermi level, suggesting the relatively low conductivity of bulk In2O3 due to the use of O3 during In2O3ALD. This supports the idea that the conductivity of the In2O3 / Al2O3 structure is dominated by the interface rather than the bulk region.

[0071] At the pre-deposited In2O3 (PRE-IO) interface, a significant band bend of 0.85 eV was observed, promoting strong 2DEG formation. At the post-deposited In2O3 (POST-IO) interface, a distinct band bend of 0.3 eV was also observed. This is somewhat smaller than in the PRE-IO case, which is because the reducing power of the TMA precursor used in Al2O3ALD further enhances 2DEG formation in the PRE-IO case. Nevertheless, this still significant band curvature in the POST-IO structure confirms that 2DEG can arise from thermodynamic relationships based purely on material composition, without relying on ALD-induced reduction.

[0072] Example 5: Evaluation of Electrical Properties of Nanolayered Structure

[0073] In this embodiment, In2O3(t IO ) and Al2O3(t AO Hall effect measurements were performed on a series of samples with varying thicknesses and different interface numbers, and the results are shown in Figure 4.

[0074] As a result of investigating mobility while varying the thickness of In2O3 from 5 nm to 20 nm on a 1 nm Al2O3 layer, the mobility remained almost constant up to 15 nm, indicating low t IO It was confirmed that conduction is dominated by the interface. Beyond 15 nm, the relatively insulating bulk In2O3 (CBO 1.45 eV in Fig. 3(c)) begins to contribute more significantly, resulting in mobilities of 23.1 to 20.3 cm⁻¹. 2 Decreases to / Vs.

[0075] Fixed t of 5 nm IO from t AO As a result of varying from 0 to 4 nm, the maximum mobility in the double-stacked In2O3 / Al2O3 with a thickness equivalent to the Al2O3 capping layer is t AO Single 10 nm In2O3 layer (22.3 cm) at 2 nm 2 Compared to / Vs) 217.9% (48.6 cm 2Reaching / Vs) suggests optimal 2DEG formation at the interface.

[0076] Analysis of mobility changes according to the number of interfaces revealed that mobility enhancement by POST-IO (transition from 2 to 3 interfaces) was higher than that by PRE-IO (3 to 4 interfaces). This demonstrates that the POST-IO configuration can provide mobility enhancement similar to the existing PRE-IO approach. Beyond this point (4 to 6 interfaces), mobility reached an upper limit and did not increase further due to the inherent scattering effects of the nanolayered structure.

[0077] Example 6: Al 2 O 3 / In 2 O 3 / Al 2 O 3 transistor using a nanolayered structure

[0078] In this embodiment, a thin-film transistor (TFT) was fabricated using an Al2O3 / In2O3 / Al2O3 nanolayered structure as the channel. This transistor has a back-gate structure and was fabricated using a channel-backward process.

[0079] A highly doped Si wafer serving as the gate electrode was used as the substrate, and a 100 nm thick SiO2 was used as the gate insulating layer. On top of this, a 2 nm thick Al2O3, a 5 nm thick In2O3, and finally another 2 nm thick Al2O3 were sequentially deposited.

[0080] Source and drain electrodes were formed by thermal deposition of Ti / Au (10 nm / 100 nm). The electrical characteristics of the completed transistor were evaluated, and it showed high electron mobility and an excellent on / off ratio, which was confirmed to be due to the 2DEG formed at the Al2O3 / In2O3 interface.

Claims

Claim 1 A substrate; a first oxide layer formed on the substrate; and a second oxide layer formed on the first oxide layer, wherein the first oxide layer is Al2O3, A semiconductor device comprising one or more of HfO2 and ZrO2, wherein the second oxide layer comprises one or more of In2O3, ZnO, and TiO2, wherein the first oxide layer is formed before the second oxide layer, so that the second oxide layer is subsequently deposited on the first oxide layer, and wherein the oxide formation Gibbs free energy of the first oxide layer is lower than the oxide formation Gibbs free energy of the second oxide layer, so that oxygen migration from the second oxide layer to the first oxide layer is induced, and an oxygen vacancy is formed at the interface between the first oxide layer and the second oxide layer, thereby forming a two-dimensional electron gas (2DEG), wherein the formation of the two-dimensional electron gas does not depend on the reduction reaction of the precursor used during atomic layer deposition of the first oxide layer. Claim 2 In claim 1, further comprising a third oxide layer formed on the second oxide layer, wherein the third oxide layer is Al2O3, A semiconductor device comprising one or more of HfO2 and ZrO2, wherein an additional two-dimensional electron gas (2DEG) is formed at the interface between the second oxide layer and the third oxide layer. Claim 3 delete Claim 4 A semiconductor device according to claim 1, wherein the thickness of the first oxide layer is 0.5 nm to 20 nm. Claim 5 A semiconductor device according to claim 1, wherein the thickness of the second oxide layer is 0.5 nm to 20 nm. Claim 6 The method comprises the steps of: forming a first oxide layer on a substrate; and forming a second oxide layer on the first oxide layer; wherein the first oxide layer is Al2O3, A method for manufacturing a semiconductor device comprising one or more of HfO2 and ZrO2, wherein the second oxide layer comprises one or more of In2O3, ZnO, and TiO2, wherein the first oxide layer is formed before the second oxide layer, so that the second oxide layer is subsequently deposited on the first oxide layer, wherein the oxide formation Gibbs free energy of the first oxide layer is lower than the oxide formation Gibbs free energy of the second oxide layer, so that oxygen migration from the second oxide layer to the first oxide layer is induced, and an oxygen vacancy is formed at the interface between the first oxide layer and the second oxide layer, thereby forming a two-dimensional electron gas (2DEG), wherein the formation of the two-dimensional electron gas does not depend on the reduction reaction of the precursor used during atomic layer deposition of the first oxide layer. Claim 7 In claim 6, the method further comprises the step of forming a third oxide layer on the second oxide layer; wherein the third oxide layer is Al2O3, A method for manufacturing a semiconductor device comprising one or more of HfO2 and ZrO2, wherein an additional two-dimensional electron gas (2DEG) is formed at the interface between the second oxide layer and the third oxide layer. Claim 8 A method for manufacturing a semiconductor device according to claim 6, wherein the thickness of the first oxide layer is 0.5 nm to 20 nm. Claim 9 delete Claim 10 A memory device comprising the semiconductor element of claim 1.

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