Pixel and display device including the same

Abstract

A pixel according to one embodiment of the present invention comprises: a light-emitting region including a central portion and an outer portion; a non-light-emitting region surrounding the light-emitting region; a first electrode and a second electrode spaced apart from each other in the light-emitting region; and a first light-emitting element aligned between the first electrode and the second electrode. The first electrode and the second electrode are spaced apart from each other at a first interval from the central portion, spaced apart from each other at an interval greater than the first interval from the outer portion, and spaced apart from each other at an interval that gradually increases as they move away from the central portion.

Description

Technology Field

[0001] An embodiment of the present invention relates to a pixel and a display device including the same. Background Technology

[0003] Recently, interest in information displays has been rising. Accordingly, research and development on display devices is continuously being carried out. The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide a pixel including a light-emitting element and a display device including the same.

[0006] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] A pixel according to one embodiment of the present invention comprises: a light-emitting region including a central portion and an outer portion; a non-light-emitting region surrounding the light-emitting region; a first electrode and a second electrode spaced apart from each other in the light-emitting region; and a first light-emitting element aligned between the first electrode and the second electrode. The first electrode and the second electrode are spaced apart from each other at a first interval from the central portion, spaced apart from each other at an interval greater than the first interval from the outer portion, and spaced apart from each other at an interval that gradually increases as they move away from the central portion.

[0009] In one embodiment, the first electrode and the second electrode may be spaced apart from each other at a linearly increasing interval from the outer portion.

[0010] In one embodiment, the first electrode and the second electrode may be spaced apart from each other at a distance that increases non-linearly at the outer portion.

[0011] In one embodiment, the first electrode and the second electrode may be spaced apart from each other at a discontinuously varying interval at the outer portion.

[0012] In one embodiment, the first electrode and the second electrode may have shapes that are symmetrical to each other with respect to the first light-emitting element.

[0013] In one embodiment, the first electrode and the second electrode, respectively, may each have a shape symmetrical with respect to the central portion.

[0014] In one embodiment, the first electrode and the second electrode have a shape that is symmetrical to each other with respect to the first light-emitting element, and each may have a shape that is symmetrical to the top and bottom with respect to the central part.

[0015] In one embodiment, the first electrode and the second electrode may have a diagonal shape, a curved shape, or a stepped shape on each of their respective faces.

[0016] In one embodiment, the first electrode and the second electrode are spaced apart from each other along a first direction in the light-emitting region, and each may extend along a second direction.

[0017] In one embodiment, the first electrode and the second electrode are spaced apart from each other by a first interval along the first direction at the central portion and spaced apart from each other by a greater interval than the first interval along the first direction at the outer portion, and the distance along the first direction may gradually increase as they move away from the central portion.

[0018] In one embodiment, the central portion includes an area corresponding to the central point of the light-emitting region in the second direction, and may include a predetermined range of areas extending in both directions from the central point toward the outer portion.

[0019] In one embodiment, the first electrode and the second electrode may be spaced apart from each other by a uniform distance with a first spacing from the central portion.

[0020] In one embodiment, the first electrode and the second electrode may be spaced apart from each other at a distance that gradually increases as they move away from the central point, even in the central portion.

[0021] In one embodiment, the first electrode and the second electrode may be spaced apart from each other at a continuously increasing interval, having a constant slope or curvature centered on the central point on each of their respective facing surfaces.

[0022] In one embodiment, the light-emitting region may further include an unaligned region located between the outer region and the non-light-emitting region. The first electrode and the second electrode may be spaced apart from each other in the unaligned region with a larger gap compared to the central region and the outer region, and each may have a reduced width.

[0023] In one embodiment, the first light-emitting element may be electrically connected between the first electrode and the second electrode.

[0024] In one embodiment, the pixel may further include a third electrode and a fourth electrode separated from the first electrode and the second electrode and spaced apart from each other in the light-emitting region; and a second light-emitting element aligned between the third electrode and the fourth electrode.

[0025] In one embodiment, the third electrode and the fourth electrode may be spaced apart from each other at a second interval from the central portion, spaced apart from each other at an interval greater than the second interval from the outer portion, and spaced apart from each other at an interval that gradually increases as they move away from the central portion.

[0026] In one embodiment, the pixel may further include: a first contact electrode electrically connecting the first electrode and the first end of the first light-emitting element; a second contact electrode electrically connecting the second electrode, the second end of the first light-emitting element, the third electrode, and the first end of the second light-emitting element; and a third contact electrode electrically connecting the fourth electrode and the second end of the second light-emitting element.

[0027] A display device according to one embodiment of the present invention includes a pixel disposed in a display area. The pixel includes: a light-emitting region including a central portion and an outer portion; a non-light-emitting region surrounding the light-emitting region; a first electrode and a second electrode disposed spaced apart from each other in the light-emitting region; and a first light-emitting element aligned between the first electrode and the second electrode. The first electrode and the second electrode are spaced apart from each other at a first interval from the central portion, spaced apart from each other at an interval greater than the first interval from the outer portion, and spaced apart from each other at an interval that gradually increases as they move away from the central portion.

[0028] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0030] According to the pixel and the display device including the same according to the embodiments of the present invention, the phenomenon in which light-emitting elements are clustered at the outer edge of the light-emitting region is prevented, and the light-emitting elements can be stably aligned between the first electrode and the second electrode. Accordingly, the utilization rate of the light-emitting elements can be increased, and the light-emitting characteristics of the pixel can be improved.

[0031] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0033] FIG. 1 is a perspective view showing a light-emitting element according to one embodiment of the present invention. FIG. 2 is a cross-sectional view showing a light-emitting element according to one embodiment of the present invention. FIG. 3 is a plan view showing a display device according to one embodiment of the present invention. FIGS. 4 and FIGS. 5 are circuit diagrams showing a pixel according to one embodiment of the present invention. FIGS. 6a to 6c are plan views showing pixels according to one embodiment of the present invention. FIGS. 7a and FIGS. 7b are cross-sectional views showing a pixel according to one embodiment of the present invention. FIGS. 8A and FIGS. 8B are cross-sectional views showing a pixel according to one embodiment of the present invention. FIGS. 9 to 15 are plan views showing pixels according to one embodiment of the present invention. Specific details for implementing the invention

[0034] The present invention is susceptible to various modifications and may take various forms; therefore, specific embodiments are illustrated in the drawings and described in detail in the text. In the following description, singular expressions include plural expressions unless the context clearly indicates that they include only the singular.

[0035] Meanwhile, the present invention is not limited to the embodiments disclosed below and may be implemented with various modifications. Additionally, each embodiment disclosed below may be implemented alone or combined with at least one other embodiment to be implemented in a complex manner.

[0036] In the drawings, some components that are not directly related to the features of the present invention may be omitted to clearly illustrate the invention. Additionally, the size or proportions of some components in the drawings may be depicted somewhat exaggerated. Throughout the drawings, identical or similar components are assigned the same reference numbers and symbols whenever possible, even if they are shown in different drawings, and redundant descriptions are omitted.

[0038] FIG. 1 is a perspective view showing a light-emitting element (LD) according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing a light-emitting element (LD) according to an embodiment of the present invention. For example, FIG. 1 shows an example of a light-emitting element (LD) that can be used as a light source for a pixel according to an embodiment of the present invention, and FIG. 2 shows an example of a cross-section of a light-emitting element (LD) along lines I to I' of FIG. 1.

[0039] Referring to FIGS. 1 and 2, a light-emitting element (LD) comprises a first semiconductor layer (SCL1), an active layer (ACT), and a second semiconductor layer (SCL2) arranged sequentially along one direction, and an insulating film (INF) covering the outer surface (e.g., a side surface) of the first semiconductor layer (SCL1), the active layer (ACT), and the second semiconductor layer (SCL2). Additionally, the light-emitting element (LD) may optionally further include an electrode layer (ETL) disposed on the second semiconductor layer (SCL2). In this case, the insulating film (INF) may at least partially cover or not cover the outer surface of the electrode layer (ETL). Furthermore, according to an embodiment, the light-emitting element (LD) may further include another electrode layer disposed on one surface (e.g., a bottom surface) of the first semiconductor layer (SCL1).

[0040] In one embodiment, the light-emitting element (LD) is provided in the shape of a rod (or, rod) extending along one direction and may have a first end (EP1) and a second end (EP2) at both ends in the length (L) direction (or thickness direction). The first end (EP1) may be a first bottom surface (or top surface) of the light-emitting element (LD), and the second end (EP2) may be a second bottom surface (or bottom surface) of the light-emitting element (LD).

[0041] In describing embodiments of the present invention, the term "rod shape" encompasses rod-like shapes or bar-like shapes that are long in the length (L) direction (i.e., have an aspect ratio greater than 1), such as cylindrical columns or polygonal columns, and the shape of the cross-section is not particularly limited. For example, the length (L) of a light-emitting element (LD) may be larger than its diameter (D) (or the width of the cross-section).

[0042] The first semiconductor layer (SCL1), the active layer (ACT), the second semiconductor layer (SCL2), and the electrode layer (ETL) may be arranged sequentially from the second end (EP2) of the light-emitting element (LD) toward the first end (EP1). That is, the first semiconductor layer (SCL1) may be arranged at the second end (EP2) of the light-emitting element (LD), and the electrode layer (ETL) may be arranged at the first end (EP1) of the light-emitting element (LD). In another embodiment, at least one other electrode layer may be arranged at the second end (EP2) of the light-emitting element (LD).

[0043] The first semiconductor layer (SCL1) may be a semiconductor layer of the first conductivity type. For example, the first semiconductor layer (SCL1) may be an N-type semiconductor layer containing an N-type dopant. As an example, the first semiconductor layer (SCL1) may be an N-type semiconductor layer that includes any one of the semiconductor materials InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a dopant such as Si, Ge, Sn, etc. However, the material constituting the first semiconductor layer (SCL1) is not limited to this, and the first semiconductor layer (SCL1) may be composed of various other materials.

[0044] The active layer (ACT) is disposed on the first semiconductor layer (SCL1) and can be formed as a single-quantum well or multi-quantum well structure. The position of the active layer (ACT) can be varied depending on the type of light-emitting device (LD). The active layer (ACT) can emit light having a wavelength of 400 nm to 900 nm and can use a double heterostructure.

[0045] A clad layer (not shown) doped with a conductive dopant may be optionally formed on the upper and / or lower portions of the active layer (ACT). For example, the clad layer may be formed as an AlGaN layer or an InAlGaN layer. According to the embodiments, materials such as AlGaN and AlInGaN may be used to form the active layer (ACT), and various other materials may also constitute the active layer (ACT).

[0046] When a voltage greater than the threshold voltage is applied across the ends of a light-emitting element (LD), electron-hole pairs combine in the active layer (ACT), causing the light-emitting element (LD) to emit light. By controlling the light emission of the light-emitting element (LD) using this principle, the light-emitting element (LD) can be used as a light source for various light-emitting devices, including pixels of display devices.

[0047] The second semiconductor layer (SCL2) is disposed on the active layer (ACT) and may be a semiconductor layer of a second conductivity type different from the first semiconductor layer (SCL1). For example, the second semiconductor layer (SCL2) may include a P-type semiconductor layer containing a P-type dopant. As an example, the second semiconductor layer (SCL2) may be a P-type semiconductor layer doped with a dopant such as Mg, and may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN. However, the material constituting the second semiconductor layer (SCL2) is not limited to this, and various other materials may also constitute the second semiconductor layer (SCL2).

[0048] In one embodiment, the first semiconductor layer (SCL1) and the second semiconductor layer (SCL2) may have different lengths (or thicknesses) along the length (L) direction of the light-emitting element (LD). For example, along the length (L) direction of the light-emitting element (LD), the first semiconductor layer (SCL1) may have a longer length (or a thicker thickness) than the second semiconductor layer (SCL2). Accordingly, the active layer (ACT) may be located closer to the first end (EP1) than to the second end (EP2).

[0049] The electrode layer (ETL) may be disposed on the second semiconductor layer (SCL2). The electrode layer (ETL) protects the second semiconductor layer (SCL2) and may be a contact electrode for smoothly connecting the second semiconductor layer (SCL2) to a predetermined electrode or wiring. For example, the electrode layer (ETL) may be an ohmic contact electrode or a Schottky contact electrode.

[0050] In describing embodiments of the present invention, the term “connection (or connection)” may comprehensively mean physical and / or electrical connection (or connection). Additionally, it may comprehensively mean direct or indirect connection (or connection) and integral or non-integral connection (or connection).

[0051] The electrode layer (ETL) may be substantially transparent or translucent. Accordingly, light generated from the light-emitting element (LD) may pass through the electrode layer (ETL) and be emitted to the outside of the light-emitting element (LD). In another embodiment, the electrode layer (ETL) may be formed to be opaque so that light generated from the light-emitting element (LD) is emitted to the outside of the light-emitting element (LD) without passing through the electrode layer (ETL).

[0052] In one embodiment, the electrode layer (ETL) may include a metal or a metal oxide. For example, the electrode layer (ETL) may be formed by a combination of a metal such as chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), or copper (Cu), an oxide or alloy thereof, a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), or In2O3 (Indium Oxide), or a mixture thereof.

[0053] The insulating film (INF) can expose the electrode layer (ETL) and the first semiconductor layer (SCL1) at the first and second ends (EP1, EP2) of the light-emitting element (LD), respectively.

[0054] If an insulating film (INF) is provided to cover the surface of the light-emitting element (LD), particularly the outer surface of the first semiconductor layer (SCL1), the active layer (ACT), the second semiconductor layer (SCL2), and / or the electrode layer (ETL), short-circuit defects through the light-emitting element (LD) can be prevented. Accordingly, electrical stability of the light-emitting element (LD) can be ensured.

[0055] When an insulating film (INF) is provided on the surface of a light-emitting element (LD), surface defects of the light-emitting element (LD) can be minimized, thereby improving lifespan and efficiency. In addition, when an insulating film (INF) is formed on each light-emitting element (LD), short circuit defects between the light-emitting elements (LDs) can be prevented even when multiple light-emitting elements (LDs) are arranged in close proximity to each other.

[0056] In one embodiment of the present invention, the light-emitting element (LD) may be manufactured through a surface treatment process. For example, when a plurality of light-emitting elements (LDs) are mixed in a fluid solution (or solvent) and supplied to each light-emitting region (e.g., the light-emitting region of each pixel), each light-emitting element (LD) may be surface-treated so that the light-emitting elements (LDs) are uniformly dispersed within the solution without unevenly aggregating. As a non-limiting embodiment related thereto, the insulating film (INF) itself may be formed as a hydrophobic film using a hydrophobic material, or a hydrophobic film made of a hydrophobic material may be additionally formed on the insulating film (INF).

[0057] The insulating film (INF) may comprise a transparent insulating material. Accordingly, light generated in the active layer (ACT) can pass through the insulating film (INF) and be emitted to the outside of the light-emitting device (LD). For example, the insulating film (INF) may be SiO2 or silicon oxide (SiOx) not otherwise determined, Si3N4 or silicon nitride (SiNx) not otherwise determined, Al2O3 or aluminum oxide (Al2O3) not otherwise determined. x O y ), and TiO2 or titanium oxide not determined thereto (Ti x O y It may include at least one insulating material among ), but is not limited thereto.

[0058] The insulating film (INF) can be composed of a single layer or multiple layers. For example, the insulating film (INF) can be made of a double film.

[0059] In one embodiment, the insulating film (INF) may be partially etched in at least one region, for example, in at least one of the upper region and the lower region. In this case, the insulating film (INF) may have a rounded shape in the at least one region, but the shape of the insulating film (INF) is not limited thereto. For example, in at least one of the upper region and the lower region of the insulating film (INF), the insulating film (INF) may be partially or wholly removed. Accordingly, the first semiconductor layer (SCL1), the second semiconductor layer (SCL2), the electrode layer (ETL), or other electrode layers (for example, other electrode layers disposed at the second end (EP2) of the light-emitting element (LD)) may be partially exposed.

[0060] In one embodiment, the light-emitting element (LD) may have a size small to the nanoscale or microscale. For example, the light-emitting element (LD) may each have a diameter (D) (or width of the cross-section) and / or length (L) in the nanoscale to microscale range. As an example, the light-emitting element (LD) may have a diameter (D) in the range of several hundred nanometers and a length (L) in the range of several micrometers. However, the size of the light-emitting element (LD) in the present invention is not limited thereto. For example, the size of the light-emitting element (LD) may be varied depending on the design conditions of various light-emitting devices that utilize the light-emitting element (LD) as a light source.

[0061] Additionally, the structure, shape, and / or type of the light-emitting element (LD) may be changed according to the embodiment. For example, the light-emitting element (LD) may not include an electrode layer (ETL). Additionally, the light-emitting element (LD) may further include another electrode layer disposed at one end of the first semiconductor layer (SCL1). Additionally, the light-emitting element (LD) may be formed with a core-shell structure.

[0062] A light-emitting device including a light-emitting element (LD) can be used in various types of devices requiring a light source, including display devices. For example, a plurality of light-emitting elements (LDs) can be arranged within each pixel of a display panel, and said light-emitting elements (LDs) can be used as the light source for each pixel. However, the application fields of the light-emitting element (LD) are not limited to the examples described above. For example, the light-emitting element (LD) can also be used in other types of devices requiring a light source, such as lighting devices.

[0064] FIG. 3 is a plan view showing a display device (DD) according to an embodiment of the present invention. As an example, FIG. 3 discloses a display device (DD) as an example of a device that can utilize a light-emitting element (LD) described in the embodiment of FIG. 1 and FIG. 2 as a light source, and in particular, the structure of the display device (DD) is disclosed with respect to a display panel (DP). For example, each pixel (PXL) of the display panel (DP) may include at least one light-emitting element (LD).

[0065] In FIG. 3, the structure of the display panel (DP) is briefly illustrated with the display area (DA) as the center. However, depending on the embodiment, at least one driving circuit, wiring, and / or pads not illustrated may be additionally provided on the display panel (DP).

[0066] Referring to FIG. 3, the display panel (DP) may include a base layer (BSL) and pixels (PXL) provided on the base layer (BSL).

[0067] A display panel (DP) and a base layer (BSL) for forming the same may include a display area (DA) for displaying an image and a non-display area (NA) excluding the display area (DA). The display area (DA) may constitute a screen on which an image is displayed, and the non-display area (NA) may be the remaining area excluding the display area (DA).

[0068] The display panel (DP) may be provided in various shapes. For example, the display panel (DP) may be provided in the form of a rectangular plate, but is not limited thereto. For example, the display panel (DP) may have a shape such as a circle or an ellipse. Additionally, the display panel (DP) may include angled corners and / or curved corners.

[0069] For convenience, in FIG. 3, the display panel (DP) is depicted as having a rectangular plate shape including a pair of short sides and a pair of long sides, and the direction of extension of the short side is indicated as the first direction (DR1), the direction of extension of the long side as the second direction (DR2), and the direction perpendicular to the direction of extension of the short side and the long side (for example, the thickness or height direction of the display panel (DP)) as the third direction (DR3). However, this may be changed depending on the shape of the display panel (DP).

[0070] The display area (DA) may have various shapes. For example, the display area (DA) may have various shapes, including a rectangle, a circle, or an ellipse. In one embodiment, the display area (DA) may have a shape that corresponds to the shape of the display panel (DP), but is not limited thereto.

[0071] Pixels (PXL) may be placed in a display area (DA) on the base layer (BSL). For example, the display area (DA) may include a plurality of pixel areas in which each pixel (PXL) is placed.

[0072] A non-display area (NA) may be disposed around a display area (DA). Various wirings, pads, and / or embedded circuits connected to pixels (PXL) of the display area (DA) may be disposed in the non-display area (NA).

[0073] According to an embodiment, at least two types of pixels (PXL) emitting different colors of light may be arranged in a display area (DA). Then, pixels of different colors (PXL) arranged adjacent to each other may form a single pixel unit capable of emitting various colors of light.

[0074] In one embodiment, each pixel (PXL) is set as a pixel (or subpixel) of a predetermined color and may include a light-emitting element (LD) that generates light of the predetermined color. In another embodiment, at least some of the pixels (PXL) include a light-emitting element (LD) that generates light of a first color, and a light conversion layer that converts the first color light into a second color light may be disposed on top of the pixels (PXL). Accordingly, the second color light can be generated using at least some of the pixels (PXL).

[0075] A pixel (PXL) may include at least one light source driven by a predetermined control signal (e.g., a scan signal and a data signal) and / or a predetermined power source (e.g., a first power source and a second power source). In one embodiment, the light source may include at least one light-emitting element (LD) according to the embodiment of FIGS. 1 and 2, for example, a rod-shaped light-emitting element (LD) having a size small to the nanoscale or microscale. In addition, various types of light-emitting elements may be used as light sources for the pixel (PXL). For example, in another embodiment, the light source of each pixel (PXL) may be configured using a core-shell structured light-emitting element.

[0076] Additionally, the pixel (PXL) may have a structure according to at least one of the embodiments described below. For example, each pixel (PXL) may have a structure to which any one of the embodiments described below is applied, or a structure to which at least two embodiments are applied in combination.

[0077] The pixel (PXL) may be an active pixel, but is not limited thereto. For example, the pixel (PXL) may be a passive pixel.

[0079] FIGS. 4 and FIGS. 5 are circuit diagrams illustrating a pixel (PXL) according to an embodiment of the present invention. For example, FIGS. 4 and FIGS. 5 illustrate pixels (PXL) including light-emitting units (EMUs) of different structures.

[0080] According to an embodiment, each pixel (PXL) shown in FIGS. 4 and FIGS. 5 may be any one of the pixels (PXL) placed in the display area (DA) of FIGS. 3. Additionally, the pixels (PXL) placed in the display area (DA) may have substantially the same or similar structures.

[0081] Referring to FIGS. 4 and 5, the pixel (PXL) includes an emitting unit (EMU) for generating light of a luminance corresponding to a data signal. Additionally, the pixel (PXL) may optionally include a pixel circuit (PXC) for driving the emitting unit (EMU).

[0082] The pixel circuit (PXC) can be connected between the first power supply (VDD) and the light-emitting unit (EMU). Additionally, the pixel circuit (PXC) is connected to the scan line (SL) and data line (DL) of the corresponding pixel (PXL), and can control the operation of the light-emitting unit (EMU) in response to the scan signal and data signal supplied from the scan line (SL) and data line (DL). Furthermore, the pixel circuit (PXC) can be optionally further connected to the sensing signal line (SSL) and the sensing line (SENL).

[0083] The pixel circuit (PXC) may include at least one transistor and a capacitor. For example, the pixel circuit (PXC) may include a first transistor (M1), a second transistor (M2), a third transistor (M3), and a storage capacitor (Cst).

[0084] The first transistor (M1) is connected between the first power supply (VDD) and the first electrode (ELT1) of the light-emitting unit (EMU). The gate electrode of the first transistor (M1) is connected to the first node (N1). The first transistor (M1) controls the driving current supplied to the light-emitting unit (EMU) in response to the voltage of the first node (N1). That is, the first transistor (M1) may be a driving transistor that controls the driving current of the pixel (PXL).

[0085] In one embodiment, the first transistor (M1) may optionally include a bottom metal layer (BML) (also referred to as a "bottom electrode," "back gate electrode," or "bottom light-blocking layer"). The gate electrode of the first transistor (M1) and the bottom metal layer (BML) may overlap each other with an insulating layer in between. In one embodiment, the bottom metal layer (BML) may be connected to one electrode of the first transistor (M1), for example, a source electrode (or drain electrode).

[0086] In an embodiment in which the first transistor (M1) includes a lower metal layer (BML), a back-biasing technique (or a sync technique) can be applied to the lower metal layer (BML) of the first transistor (M1) to shift the threshold voltage of the first transistor (M1) in a negative or positive direction when driving the pixel (PXL). As an example, a source-sync technique can be applied by connecting the lower metal layer (BML) to the source electrode of the first transistor (M1). Additionally, if the lower metal layer (BML) is placed below the semiconductor pattern constituting the channel of the first transistor (M1), the lower metal layer (BML) can act as a light-blocking pattern and stabilize the operating characteristics of the first transistor (M1). However, the function and / or method of utilization of the lower metal layer (BML) is not limited to this.

[0087] The second transistor (M2) is connected between the data line (DL) and the first node (N1). The gate electrode of the second transistor (M2) is connected to the scan line (SL). The second transistor (M2) is turned on when a scan signal of gate-on voltage (e.g., high level voltage) is supplied from the scan line (SL), thereby connecting the data line (DL) and the first node (N1).

[0088] For each frame period, a data signal of the corresponding frame is supplied to the data line (DL), and the data signal is transmitted to the first node (N1) through the second transistor (M2) which is turned on during the period when a scan signal of the gate-on voltage is supplied. That is, the second transistor (M2) may be a switching transistor for transmitting each data signal into the pixel (PXL).

[0089] One electrode of the storage capacitor (Cst) is connected to the first node (N1), and the other electrode is connected to the second electrode of the first transistor (M1). The storage capacitor (Cst) charges a voltage corresponding to the data signal supplied to the first node (N1) during each frame period.

[0090] The third transistor (M3) is connected between the second electrode of the first transistor (M1) (and / or the first electrode (ELT1) of the light-emitting unit (EMU)) and the sensing line (SENL). The gate electrode of the third transistor (M3) is connected to the sensing signal line (SSL). The third transistor (M3) can transmit the voltage value applied to the second electrode of the first transistor (M1) to the sensing line (SENL) according to the sensing signal supplied to the sensing signal line (SSL). The voltage value transmitted through the sensing line (SENL) can be provided to an external circuit (e.g., a timing control unit), and the external circuit can extract characteristic information of each pixel (PXL) (e.g., the threshold voltage of the first transistor (M1)) based on the provided voltage value. The extracted characteristic information can be used to convert image data so that the characteristic deviation of the pixels (PXL) is compensated.

[0091] Meanwhile, in FIGS. 4 and 5, the transistors included in the pixel circuit (PXC) are all depicted as N-type transistors, but the present invention is not limited thereto. For example, at least one of the first, second, and third transistors (M1, M2, M3) may be changed to a P-type transistor.

[0092] In addition, the structure and driving method of the pixel (PXL) can be varied. For example, the pixel circuit (PXC) may be composed of pixel circuits with various structures and / or driving methods, in addition to the embodiments shown in FIGS. 4 and 5.

[0093] For example, the pixel circuit (PXC) may not include a third transistor (M3). Additionally, the pixel circuit (PXC) may further include other circuit elements, such as a compensation transistor for compensating the threshold voltage of the first transistor (M1), an initialization transistor for initializing the voltage of the first electrode (ELT1) of the first node (N1) and / or the light-emitting unit (EMU), a light-emitting control transistor for controlling the period during which a driving current is supplied to the light-emitting unit (EMU), and / or a boosting capacitor for boosting the voltage of the first node (N1).

[0094] In another embodiment, if the pixel (PXL) is a pixel of a passive light-emitting display device, the pixel circuit (PXC) may be omitted. In this case, the light-emitting unit (EMU) may be directly connected to a scan line (SL), a data line (DL), a first power line (PL1), a second power line (PL2), and / or other signal lines or power lines.

[0095] The light-emitting unit (EMU) may include at least one light-emitting element (LD) connected between a first power source (VDD) and a second power source (VSS), for example, a plurality of light-emitting elements (LDs). The first power source (VDD) and the second power source (VSS) may have different potentials so that the light-emitting elements (LDs) can emit light. For example, the first power source (VDD) may be set to a high potential power source, and the second power source (VSS) may be set to a low potential power source.

[0096] In one embodiment, the light-emitting unit (EMU) may include a plurality of light-emitting elements (LDs) connected in parallel with each other as shown in FIG. 4.

[0097] Referring to FIG. 4, the light-emitting unit (EMU) may include a first electrode (ELT1) and a second electrode (ELT2), and a plurality of light-emitting elements (LDs) connected in parallel between the first and second electrodes (ELT1, ELT2). The first electrode (ELT1) may be connected to a first power source (VDD) via a pixel circuit (PXC) and / or a first power line (PL1), and the second electrode (ELT2) may be connected to a second power source (VSS) via a second power line (PL2). Each light-emitting element (LD) may include a first end (EP1) (e.g., a P-type end) connected to the first power source (VDD) through the first electrode (ELT1) and / or the pixel circuit (PXC), and a second end (EP2) (e.g., an N-type end) connected to the second power source (VSS) through the second electrode (ELT2). That is, light-emitting elements (LDs) can be connected in parallel in the forward direction between the first and second electrodes (ELT1, ELT2).

[0098] In another embodiment, the light-emitting unit (EMU) may include a plurality of light-emitting elements (LDs) connected in series or in series / parallel. As an example, the light-emitting unit (EMU) may include a plurality of light-emitting elements (LDs) connected to two series terminals, as shown in FIG. 5.

[0099] Referring to FIG. 5, the light-emitting unit (EMU) may include a first series section including at least one first light-emitting element (LD1) and a second series section including at least one second light-emitting element (LD2).

[0100] The first series section may include a first electrode (ELT1) and a second electrode (ELT2), and at least one first light-emitting element (LD1) connected between the first and second electrodes (ELT1, ELT2). For example, the first series section may include first light-emitting elements (LD1) connected in parallel with each other between the first and second electrodes (ELT1, ELT2).

[0101] The first electrode (ELT1) may be connected to the first power source (VDD) via the pixel circuit (PXC) and / or the first power line (PL1), and the second electrode (ELT2) may be connected to the second power source (VSS) via the second series terminal and / or the second power line (PL2). Each first light-emitting element (LD1) may be connected in the forward direction between the first and second electrodes (ELT1, ELT2). For example, the first end (EP1) of the first light-emitting element (LD1) may be connected to the first electrode (ELT1), and the second end (EP2) of the first light-emitting element (LD1) may be connected to the second electrode (ELT2).

[0102] The second series section may include a third electrode (ELT3) and a fourth electrode (ELT4), and at least one second light-emitting element (LD2) connected between the third and fourth electrodes (ELT3, ELT4). For example, the second series section may include second light-emitting elements (LD2) connected in parallel with each other between the third and fourth electrodes (ELT3, ELT4).

[0103] The third electrode (ELT3) is connected integrally or non-integrally to the second electrode (ELT2), and the second and third electrodes (ELT2, ELT3) can form a single intermediate electrode (IET) connecting the first series terminal and the second series terminal. The fourth electrode (ELT4) can be connected to the second power source (VSS) via the second power line (PL2). Each second light-emitting element (LD2) can be connected in the forward direction between the third and fourth electrodes (ELT3, ELT4). For example, the first end (EP1) of the second light-emitting element (LD2) can be connected to the third electrode (ELT3), and the second end (EP2) of the second light-emitting element (LD2) can be connected to the fourth electrode (ELT4).

[0104] Meanwhile, the number of series terminals constituting each light-emitting unit (EMU) may vary depending on the embodiment. For example, the light-emitting unit (EMU) may include light-emitting elements (LDs) connected in three or more series terminals.

[0105] That is, in embodiments of the present invention, the light-emitting unit (EMU) may include at least one series section. Each series section may include a pair of electrodes and at least one light-emitting element (LD) connected in the forward direction between the pair of electrodes. Here, the number of series sections constituting the light-emitting unit (EMU) and the number of light-emitting elements (LDs) constituting each series section are not particularly limited. For example, the number of light-emitting elements (LDs) constituting each series section may be the same or different from one another.

[0106] The first electrode of the light-emitting unit (EMU), for example, the first electrode (ELT1), may be the anode electrode of the light-emitting unit (EMU). The last electrode of the light-emitting unit (EMU), for example, the second electrode (ELT2) or the fourth electrode (ELT4), may be the cathode electrode of the light-emitting unit (EMU).

[0107] As in the embodiment of FIG. 4, when light-emitting elements (LDs) are connected only in parallel, the structure of the pixel (PXL) can be simplified. As in the embodiment of FIG. 5, when light-emitting elements (LDs) are connected in series / parallel (or series), power efficiency can be improved compared to the embodiment in which the same number of light-emitting elements (LDs) are connected only in parallel (for example, the embodiment of FIG. 4). In addition, in a pixel (PXL) in which light-emitting elements (LDs) are connected in series or in series / parallel, even if a short circuit defect occurs in some series terminals, a certain amount of brightness can be expressed through the light-emitting elements (LDs) in the remaining series terminals, so the possibility of dark spot defects in the pixel (PXL) can be reduced.

[0108] Meanwhile, FIGS. 4 and 5 illustrate embodiments in which light-emitting elements (LDs) are connected in parallel or in series / parallel, but the present invention is not limited thereto. For example, in other embodiments, light-emitting elements (LDs) may be connected only in series to form a light-emitting unit (EMU).

[0109] Each light-emitting element (LD) connected in the forward direction between the first power supply (VDD) and the second power supply (VSS) can constitute an effective light source. These effective light sources can be combined to form an light-emitting unit (EMU) (or light source unit) of a pixel (PXL).

[0110] The light-emitting elements (LDs) can emit light with a brightness corresponding to the driving current when the driving current is supplied through the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can supply a driving current corresponding to the grayscale value to be expressed in the frame to the light-emitting unit (EMU). Accordingly, as the light-emitting elements (LDs) emit light with a brightness corresponding to the driving current, the light-emitting unit (EMU) becomes able to express a brightness corresponding to the driving current.

[0111] In one embodiment, the light-emitting unit (EMU) may further include at least one non-effective light source in addition to the light-emitting elements (LDs) constituting each effective light source. For example, at least one non-effective light-emitting element may be further connected to at least one series terminal, which is arranged in reverse or has at least one end floating. The non-effective light-emitting element remains in a deactivated state even when a forward driving voltage is applied between a pair of electrodes, and thus can maintain a substantially non-luminous state.

[0113] FIGS. 6a to 6c are plan views illustrating a pixel (PXL) according to an embodiment of the present invention. For example, FIGS. 6a to 6c illustrate different embodiments regarding the connection structure between the first and second electrodes (ELT1, ELT2) and the first and second contact electrodes (CNE1, CNE2).

[0114] In FIGS. 6a to 6c, the structure of the pixel (PXL) is to be illustrated with the light-emitting unit (EMU) of the pixel (PXL) as the center. For example, FIGS. 6a to 6c illustrates an exemplary structure of a light-emitting unit (EMU) including a first electrode (ELT1) and a second electrode (ELT2) and light-emitting elements (LD) connected in parallel between the first and second electrodes (ELT1, ELT2), as in the embodiment of FIG. 4.

[0115] Additionally, FIGS. 6a to 6c illustrate an embodiment in which each light-emitting unit (EMU) is connected to a predetermined power line (e.g., first and / or second power lines (PL1, PL2)), a circuit element (e.g., at least one circuit element constituting a pixel circuit (PXC)), and / or a signal line (e.g., a scan line (SL) and / or a data line (DL)) through first and second contact holes (CH1, CH2). However, the present invention is not limited thereto. For example, in another embodiment, at least one of the first and second electrodes (ELT1, ELT2) of each pixel (PXL) may be directly connected to a predetermined power line and / or signal line without passing through a contact hole and / or intermediate wiring.

[0116] Referring to FIGS. 6a through 6c, a pixel (PXL) is provided in each pixel region (PXA). The pixel region (PXA) may comprehensively refer to a pixel circuit region where circuit elements for constituting the pixel (PXL) are arranged, and a light-emitting region (EA) where the light-emitting unit (EMU) of the pixel (PXL) is arranged.

[0117] Additionally, the pixel area (PXA) includes a light-emitting area (EA) and a non-light-emitting area (NEA) surrounding the light-emitting area (EA), and may further include a separation area (SPA) spaced apart from the light-emitting area (EA) with the non-light-emitting area (NEA) interposed therebetween. A bank (BNK) is provided in the non-light-emitting area (NEA), and a bank (BNK) may not be provided in the light-emitting area (EA) and / or the separation area (SPA).

[0118] The light-emitting region (EA) may be an area where at least one light-emitting element (LD) constituting the light-emitting unit (EMU) of each pixel (PXL) is supplied and aligned. Hereinafter, the configuration of each embodiment will be described by assuming that a plurality of light-emitting elements (LDs) are provided in each light-emitting region (EA).

[0119] Additionally, in the light-emitting region (EA), certain electrodes (e.g., first and second electrodes (ELT1, ELT2), and / or first and second contact electrodes (CNE1, CNE2)) or a region of said electrodes connected to the light-emitting elements (LD) may be disposed. In one embodiment, the light-emitting region (EA) may be surrounded by a bank (BNK).

[0120] A pixel (PXL) may include a first electrode (ELT1) and a second electrode (ELT2) spaced apart from each other in a light-emitting region (EA), and light-emitting elements (LD) disposed and / or aligned between the first and second electrodes (ELT1, ELT2). Here, the statement that the light-emitting elements (LD) are disposed and / or aligned between the first and second electrodes (ELT1, ELT2) may mean that, when viewed in a plane, at least one region of each of the light-emitting elements (LD) is located in the region between the first and second electrodes (ELT1, ELT2).

[0121] Additionally, the pixel (PXL) may further include a first contact electrode (CNE1) and a second contact electrode (CNE2) connected to the first ends (EP1) and second ends (EP2) of the light-emitting elements (LD). Furthermore, the pixel (PXL) may further include at least one other electrode, a conductive pattern and / or an insulating pattern, etc. For example, the pixel (PXL) may further include at least one pattern (for example, the first and second patterns (BNP1, ​​BNP2) of FIGS. 7a to 8b) disposed below the first and second electrodes (ELT1, ELT2) so as to overlap with one region of each of the first and second electrodes (ELT1, ELT2).

[0122] The first electrode (ELT1) and the second electrode (ELT2) are spaced apart from each other along a first direction (DR1) in each light-emitting region (EA), and each may extend along a second direction (DR2). The first direction (DR1) and the second direction (DR2) may be directions that intersect each other (e.g., orthogonal). In one embodiment, the first direction (DR1) may be the horizontal direction (or row direction) of the display region (DA), and the second direction (DR2) may be the vertical direction (or column direction) of the display region (DA), but is not limited thereto.

[0123] The first and second electrodes (ELT1, ELT2) may have various shapes and / or sizes. Meanwhile, although FIGS. 6a to 6c disclose an embodiment in which one first electrode (ELT1) and one second electrode (ELT2) are disposed in each light-emitting region (EA), the number of first and second electrodes (ELT1, ELT2) disposed in each pixel (PXL) may be changed.

[0124] When multiple first electrodes (ELT1) are disposed within a single pixel (PXL), the first electrodes (ELT1) may be connected to each other either integrally or non-integrally. Similarly, when multiple second electrodes (ELT2) are disposed within a single pixel (PXL), the second electrodes (ELT2) may be connected to each other either integrally or non-integrally.

[0125] In one embodiment, the first and second electrodes (ELT1, ELT2) may have shapes that are symmetrical to each other with respect to the light-emitting elements (LD) (or, a light-emitting element alignment region in which the light-emitting elements (LD) are aligned). For example, the first and second electrodes (ELT1, ELT2) may have shapes that are symmetrical to each other (or horizontally symmetrical) with respect to the light-emitting elements (LD) in between, at least in the light-emitting region (EA).

[0126] Additionally, in one embodiment, each of the first and second electrodes (ELT1, ELT2) may have a shape that is symmetric with respect to the central portion (CEA) of the light-emitting region (EA). For example, the light-emitting region (EA) includes a central portion (CEA) and an outer portion (OEA) in the second direction (DR2), and each of the first and second electrodes (ELT1, ELT2) may have a shape that is vertically symmetric (or vertically symmetric) with respect to the central portion (CEA). The outer portion (OEA) may include first and second outer portions (OEA1, OEA2) located on both sides of the central portion (CEA) in the second direction (DR2). For example, the outer portion (OEA) may include a first outer portion (OEA1) located at the top of the central portion (CEA) and a second outer portion (OEA2) located at the bottom of the central portion (CEA).

[0127] The first electrode (ELT1) and / or the second electrode (ELT2) may have a pattern separated by pixel (PXL) or a pattern that is commonly connected across multiple pixels (PXL). For example, the first and second electrodes (ELT1, ELT2) may be separated at a separation region (SPA) located outside the corresponding light-emitting region (EA). In another embodiment, at least one of the first and second electrodes (ELT1, ELT2) may have an independent pattern separated within the light-emitting region (EA). For example, the first electrode (ELT1) may be separated within the light-emitting region (EA), or both the first and second electrodes (ELT1, ELT2) may be separated within the light-emitting region (EA). Alternatively, the first electrode (ELT1) may be separated at the separation region (SPA), or both the first and second electrodes (ELT1, ELT2) may be separated at the separation region (SPA). In another embodiment, the first electrode (ELT1) has an independent pattern that is broken within the separation region (SPA) or the light-emitting region (EA), and the second electrode (ELT2) has one end extended along the first direction (DR1) or the second direction (DR2) and can be integrally connected to the second electrode (ELT2) of an adjacent pixel (PXL) on the first direction (DR1) or the second direction (DR2). That is, at least one of the first and second electrodes (ELT1, ELT2) may have a pattern separated by pixel (PXL).

[0128] Meanwhile, prior to the process of forming pixels (PXL), particularly the alignment of light-emitting elements (LD), the first electrodes (ELT1) of the pixels (PXL) placed in the display area (DA) may be connected to each other, and the second electrodes (ELT2) of the pixels (PXL) may be connected to each other. For example, prior to the alignment of the light-emitting elements (LD), the first electrodes (ELT1) of the pixels (PXL) may be connected to each other integrally or non-integrally to form a first alignment wiring, and the second electrodes (ELT2) of the pixels (PXL) may be connected to each other integrally or non-integrally to form a second alignment wiring.

[0129] The first alignment wiring and the second alignment wiring may each receive a first alignment signal (or a first alignment voltage) and a second alignment signal (or a second alignment voltage) during the alignment stage of the light-emitting elements (LD). For example, either of the first and second alignment wirings may receive an alignment signal in the form of an alternating current, and the other may receive an alignment voltage having a constant voltage level (for example, a ground voltage).

[0130] In the alignment step of the light-emitting elements (LDs), the first and second alignment wires may receive different alignment signals. Accordingly, an electric field is formed between the first and second alignment wires, allowing the light-emitting elements (LDs) supplied to each light-emitting region (EA) to be aligned between the first and second alignment wires. After the alignment of the light-emitting elements (LDs) is completed, at least the first alignment wire can be cut at a separation region (SPA), etc., to separate them into respective first electrodes (ELT1), thereby forming the pixels (PXL) in a form that allows for individual driving.

[0131] The first electrode (ELT1) may be electrically connected through the first contact hole (CH1) to a predetermined circuit element (e.g., at least one transistor constituting a pixel circuit (PXC)), a power line (e.g., a first power line (PL1)), and / or a signal line (e.g., a scan line (SL), a data line (DL), or a predetermined control line). In another embodiment, the first electrode (ELT1) may be directly connected to a predetermined power line or signal line.

[0132] In one embodiment, the first electrode (ELT1) may be electrically connected to a predetermined circuit element disposed below it through a first contact hole (CH1) and may be electrically connected to a first wiring through said circuit element. The first wiring may be a first power line (PL1) for supplying a first power source (VDD), but is not limited thereto.

[0133] The second electrode (ELT2) may be electrically connected through the second contact hole (CH2) to a predetermined circuit element (e.g., at least one transistor constituting a pixel circuit (PXC)), a power line (e.g., a second power line (PL2)), and / or a signal line (e.g., a scan line (SL), a data line (DL), or a predetermined control line). In another embodiment, the second electrode (ELT2) may be directly connected to a predetermined power line or signal line.

[0134] In one embodiment, the second electrode (ELT2) may be electrically connected to a second wiring positioned below it through a second contact hole (CH2). The second wiring may be a second power line (PL2) for supplying a second power source (VSS), but is not limited thereto.

[0135] Each of the first and second contact holes (CH1, CH2) may or may not overlap with the bank (BNK). For example, as shown in FIGS. 6a through 6c, the first and second contact holes (CH1, CH2) are placed in a non-emissive region (NEA) between the emissive region (EA) and the separation region (SPA), and may overlap with the bank (BNK). In another embodiment, at least one of the first and second contact holes (CH1, CH2) may be placed within the emissive region (EA) or the separation region (SPA).

[0136] Each of the first and second electrodes (ELT1, ELT2) may be composed of a single layer or multiple layers. For example, the first electrode (ELT1) comprises at least one reflective electrode layer including a reflective conductive material, and may optionally further comprise at least one transparent electrode layer and / or a conductive capping layer. Similarly, the second electrode (ELT2) comprises at least one reflective electrode layer including a reflective conductive material, and may optionally further comprise at least one transparent electrode layer and / or a conductive capping layer. The reflective conductive material may be at least one of various metal materials, including, for example, aluminum (Al), gold (Au), and silver (Ag), which have a high reflectivity in the visible light wavelength band, but is not limited thereto.

[0137] Light-emitting elements (LDs) may be placed and / or aligned between the first electrode (ELT1) and the second electrode (ELT2). For example, the light-emitting elements (LDs) may be arranged in parallel between the first electrode (ELT1) and the second electrode (ELT2). As an example, each light-emitting element (LD) may be aligned in a first direction (DR1) between the first electrode (ELT1) and the second electrode (ELT2) and electrically connected between the first and second electrodes (ELT1, ELT2).

[0138] Meanwhile, in FIGS. 6a to 6c, the light-emitting elements (LDs) are all shown as being uniformly aligned in the first direction (DR1), but the present invention is not limited thereto. For example, at least one of the light-emitting elements (LDs) may be arranged in a diagonal direction inclined with respect to the first and second directions (DR1, DR2) between the first and second electrodes (ELT1, ELT2).

[0139] According to the embodiment, each light-emitting element (LD) may be a micro-sized light-emitting element using a material with an inorganic crystal structure, for example, a nano-scale to a micro-scale, but is not limited thereto. In addition, each light-emitting element (LD) may be a rod-type light-emitting element as shown in FIGS. 1 and 2, but is not limited thereto.

[0140] Each light-emitting element (LD) may include a first end (EP1) and a second end (EP2). The first end (EP1) may be positioned adjacent to a first electrode (ELT1), and the second end (EP2) may be positioned adjacent to a second electrode (ELT2). For example, it may be positioned toward the first end (EP1), and the second end (EP2) may be positioned toward the second electrode (ELT2). The first end (EP1) may or may not overlap with the first electrode (ELT1). The second end (EP2) may or may not overlap with the second electrode (ELT2).

[0141] Each light-emitting element (LD) can be electrically connected between the first electrode (ELT1) and the second electrode (ELT2).

[0142] In one embodiment, a first end (EP1) of each of the light-emitting elements (LD) may be connected to a first electrode (ELT1) through a first contact electrode (CNE1), and a second end (EP2) of each of the light-emitting elements (LD) may be connected to a second electrode (ELT2) through a second contact electrode (CNE2).

[0143] For example, the first contact electrode (CNE1) may be connected to the first electrode (ELT1) by contacting it in a peripheral area of ​​the region where the light-emitting elements (LD) are arranged, such as in FIG. 6a (for example, the AR1 region adjacent to the first ends (EP1) of the light-emitting elements (LD)). Alternatively, the first contact electrode (CNE1) may be electrically connected to the first electrode (ELT1) through at least one third contact hole (CH3) located in the light-emitting region (EA) and / or the separation region (SPA), as shown in FIG. 6b and 6c. If the third contact hole (CH3) is located in the separation region (SPA), as shown in FIG. 6c, the first contact electrode (CNE1) may extend from the light-emitting region (EA) through the non-light-emitting region (NEA) to the separation region (SPA).

[0144] Similarly, the second contact electrode (CNE2) may be connected to the second electrode (ELT2) by contacting it in a peripheral area of ​​the region where the light-emitting elements (LD) are arranged, such as in FIG. 6a (for example, the AR2 region adjacent to the second ends (EP2) of the light-emitting elements (LD)). Alternatively, the second contact electrode (CNE2) may be electrically connected to the second electrode (ELT2) through at least one fourth contact hole (CH4) located in the light-emitting region (EA) and / or the separation region (SPA), as shown in FIG. 6b and 6c. If the fourth contact hole (CH4) is located in the separation region (SPA), as shown in FIG. 6c, the second contact electrode (CNE2) may extend from the light-emitting region (EA) through the non-light-emitting region (NEA) to the separation region (SPA).

[0145] In another embodiment, the first end (EP1) of each light-emitting element (LD) may be directly connected to the first electrode (ELT1), and the second end (EP2) of each light-emitting element (LD) may be directly connected to the second electrode (ELT2). In yet another embodiment, the first and / or second ends (EP1, EP2) of the light-emitting elements (LD) may be connected only to the first and / or second contact electrodes (CNE1, CNE2) and not to the first and / or second electrodes (ELT1, ELT2). In this case, the first and / or second contact electrodes (CNE1, CNE2) may constitute the respective pixel electrodes instead of the first and / or second electrodes (ELT1, ELT2).

[0146] Light-emitting elements (LDs) are prepared in a dispersed form within a predetermined solution and can be supplied to the light-emitting region (EA) of each pixel (PXL) through various methods, including inkjet or slit coating methods. For example, the light-emitting elements (LDs) can be mixed with a volatile solvent and supplied to each light-emitting region (EA). At this time, when predetermined alignment signals are applied to the first and second electrodes (ELT1, ELT2) (or first and second alignment wires) of the pixels (PXL) to form an electric field, the light-emitting elements (LDs) are aligned between the first and second electrodes (ELT1, ELT2). After the light-emitting elements (LDs) are aligned, the solvent can be removed by performing a drying process, etc.

[0147] In one embodiment, the light-emitting elements (LDs) can be biased aligned so that the light-emitting elements (LDs) can be aligned in a more specific direction. For example, the alignment direction of the light-emitting elements (LDs) can be controlled by adjusting alignment signals or forming a magnetic field so that a greater number and / or proportion of the light-emitting elements (LDs) supplied to each light-emitting region (EA) during the alignment step of the light-emitting elements (LDs) can be connected in the forward direction between the first and second electrodes (ELT1, ELT2). For example, the light-emitting elements (LDs) can be biased aligned so that the first ends (EP1) of the light-emitting elements (LDs) are more directed toward the first electrode (ELT1) (or the first alignment wiring before being separated from the first electrode (ELT1)), and the second ends (EP2) of the light-emitting elements (LDs) are more directed toward the second electrode (ELT2) (or the second alignment wiring before being separated from the second electrode (ELT2)). Subsequently, a drying process to remove the solvent can be performed while the light-emitting elements (LDs) are aligned. By aligning the light-emitting elements (LDs) in the desired direction in this manner, the utilization rate of the light-emitting elements (LDs) supplied to each light-emitting region (EA) can be increased. Accordingly, the manufacturing cost of the pixel (PXL) can be reduced and the brightness improved.

[0148] Meanwhile, when alignment signals including alternating current (AC) signals are applied to the first and second electrodes (ELT1, ELT2) (or the first and second alignment wires) to align the light-emitting elements (LDs), the light-emitting elements (LDs) may be driven to the outer edge (OEA) of the light-emitting region (EA) or deviate from the aligned position due to solvent flow caused by the ACEO (AC electro-osmosis) effect. Consequently, the alignment characteristics and utility of the light-emitting elements (LDs) are reduced, and the light-emitting characteristics and light efficiency of the pixel (PXL) may be reduced.

[0149] Accordingly, in an embodiment of the present invention, by widening the spacing between the first and second electrodes (ELT1, ELT2) in the outer part (OEA) of the light-emitting region (EA) compared to the central part (CEA), the strength of the electric field formed in the outer part (OEA) during the alignment step of the light-emitting elements (LD) can be weakened compared to the central part (CEA). As a result, the flow of the solvent due to the ACEO effect can be reduced or minimized, and the deviation of the light-emitting elements (LD) from their aligned positions can be prevented or minimized. According to this embodiment of the present invention, the proportion of light-emitting elements (LD) aligned in the central part (CEA) of the light-emitting region (EA) is increased, thereby improving the alignment characteristics and utility of the light-emitting elements (LD), and improving the light-emitting characteristics and light efficiency of the pixel (PXL).

[0150] Specifically, in a pixel (PXL) according to an embodiment of the present invention, the light-emitting region (EA) may include a central portion (CEA) and first and second outer portions (OEA1, OEA2) located on both sides of the central portion (CEA) with respect to a second direction (DR2). According to an embodiment, the central portion (CEA) may include an area corresponding to a central point (CP) of the light-emitting region (EA) on the second direction (DR2), and may include an area of ​​a section corresponding to a predetermined range of length (or distance) on both sides from the central point (CP). As an example, the central portion (CEA) may include a predetermined range of area extending in both directions toward the first and second outer portions (OEA1, OEA2) centered on the central point (CP) on the second direction (DR2).

[0151] The first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other by different intervals (or distances) in the central part (CEA) and the outer part (OEA) of the light-emitting region (EA). For example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other by a first interval (d1) in the central part (CEA) of the light-emitting region (EA), and spaced apart from each other by a greater interval than the first interval (d1) in the outer part (OEA) of the light-emitting region (EA). Additionally, in the outer part (OEA) of the light-emitting region (EA), the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other by an interval that gradually increases as they move away from the central part (CEA). At this time, in the outer part (OEA) of the light-emitting region (EA), the interval between the first electrode (ELT1) and the second electrode (ELT2) may vary continuously or discontinuously.

[0152] For example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other by a first distance (d1) along the first direction (DR1) in the central part (CEA) of the light-emitting region (EA). Additionally, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other by a distance greater than the first distance (d1) along the first direction (DR1) in the outer part (OEA) of the light-emitting region (EA).

[0153] In one embodiment, the first gap (d1) may be maintained at a constant value. For example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other by a uniform distance with the first gap (d1) in the center (CEA) of the light-emitting region (EA).

[0154] The first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other such that the distance in the first direction (DR1) gradually increases as it moves away from the center (CEA) at the outer edge (OEA) of the light-emitting region (EA). For example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at a distance that increases linearly and / or continuously at the outer edge (OEA) of the light-emitting region (EA). For example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at a distance that gradually increases as it moves away from the center (CEA), with each of their facing surfaces at the outer edge (OEA) of the light-emitting region (EA) having a diagonal shape.

[0155] A first contact electrode (CNE1) and a second contact electrode (CNE2) may be provided on the first end (EP1) and the second end (EP2) of the light-emitting elements (LD), respectively. Accordingly, the light-emitting elements (LD) can be stably connected between the first and second electrodes (ELT1, ELT2).

[0156] The first contact electrode (CNE1) is disposed on the first ends (EP1) of the light-emitting elements (LD) and the first electrode (ELT1), and can electrically connect the first ends (EP1) of the light-emitting elements (LD) and the first electrode (ELT1). Additionally, the first contact electrode (CNE1) can stably fix the first ends (EP1) of the light-emitting elements (LD).

[0157] The second contact electrode (CNE2) is disposed on the second ends (EP2) of the light-emitting elements (LD) and the second electrode (ELT2), and can electrically connect the second ends (EP2) of the light-emitting elements (LD) and the second electrode (ELT2). Additionally, the second contact electrode (CNE2) can stably fix the second ends (EP2) of the light-emitting elements (LD).

[0158] In another embodiment, at least one of the first and second contact electrodes (CNE1, CNE2) may not be provided. In this case, the light-emitting elements (LD) may be directly connected to the first and / or second electrodes (ELT1, ELT2).

[0159] A bank (BNK) may be positioned around the light-emitting region (EA) to surround the light-emitting region (EA) of each pixel (PXL). For example, a bank (BNK) may be positioned in the outer region of each pixel region (PXA) and / or in the region between adjacent pixel regions (PXA) to surround each light-emitting region (EA). For example, a bank (BNK) may include a first opening (OPA1) corresponding to the light-emitting region (EA) of each pixel (PXL) and may have a mesh shape over the entire display region (DA).

[0160] In one embodiment, the bank (BNK) may further include a second opening (OPA2) corresponding to a separation region (SPA) between adjacent pixels (PXL) in a first direction (DR1) and / or a second direction (DR2). Accordingly, alignment wires in the separation region (SPA) can be easily disconnected to separate the alignment wires to the first and second electrodes (ELT1, ELT2) of each pixel (PXL).

[0161] Bank (BNK) may partially overlap or not overlap with the first and / or second electrodes (ELT1, ELT2). For example, the first and / or second electrodes (ELT1, ELT2) may extend into a non-emissive region (NEA) to overlap with Bank (BNK), or be interrupted within an emissive region (EA) to not overlap with Bank (BNK).

[0162] Additionally, the bank (BNK) may or may not overlap with the first and / or second contact holes (CH1, CH2). For example, the first and / or second contact holes (CH1, CH2) may be formed in a non-emissive region (NEA) so as to overlap with the bank (BNK), or formed in an emissive region (EA) or a separating region (SPA) so as not to overlap with the bank (BNK).

[0163] A bank (BNK) is configured to include at least one light-blocking and / or reflective material to prevent light leakage between adjacent pixels (PXL). For example, the bank (BNK) may include at least one black matrix material and / or a color filter material of a specific color. As an example, the bank (BNK) may be formed with a black opaque pattern to block the transmission of light.

[0164] Additionally, the bank (BNK) can also function as a dam structure that defines each light-emitting region (EA) to which light-emitting elements (LDs) are to be supplied during the step of supplying light-emitting elements (LDs) to each pixel (PXL). For example, by partitioning each light-emitting region (EA) by the bank (BNK), a desired type and / or amount of light-emitting element ink (e.g., a solution containing at least one type of light-emitting element (LD)) can be supplied to each light-emitting region (EA).

[0165] According to the above-described embodiment, by widening the gap between the first electrode (ELT1) and the second electrode (ELT2) in the outer part (OEA) of the light-emitting region (EA), the phenomenon of light-emitting elements (LDs) gathering in the outer part (OEA) of the light-emitting region (EA) due to the ACEO effect is prevented, and the light-emitting elements (LDs) can be more stably aligned between the first electrode (ELT1) and the second electrode (ELT2). For example, by differentially adjusting the gap between the first electrode (ELT1) and the second electrode (ELT2) in the light-emitting region (EA), a weak electric field can be formed in the outer part (OEA) compared to the central part (CEA) of the light-emitting region (EA) during the alignment stage of the light-emitting elements (LDs). Accordingly, the flow and clustering of light-emitting elements (LDs) due to the ACEO (AC electro-osmosis) effect are prevented, and the utilization rate and alignment characteristics of the light-emitting elements (LDs) can be improved.

[0166] Meanwhile, FIGS. 6a to 6c disclose an embodiment in which light-emitting elements (LDs) are arranged between the first electrode (ELT1) and the second electrode (ELT2) in the entire light-emitting region (EA), including the central part (CEA) and the outer part (OEA), based on the second direction (DR2), but the present invention is not limited thereto. For example, in other embodiments, only a part of the light-emitting region (EA) and / or a section may be defined as the light-emitting element arrangement region, and the first electrode (ELT1) and the second electrode (ELT2) may be formed with a spacing sufficient to allow the light-emitting elements (LDs) to be aligned only in the light-emitting element arrangement region. In this case, the alignment and / or distribution characteristics of the light-emitting elements (LDs) within the light-emitting element arrangement region can be controlled by dividing the light-emitting element arrangement region into a predetermined central part and outer part and adjusting the spacing between the first electrode (ELT1) and the second electrode (ELT2).

[0168] FIGS. 7a and 7b, and FIGS. 8a and 8b are cross-sectional views illustrating a pixel (PXL) according to an embodiment of the present invention. For example, FIGS. 7a and 7b illustrate different embodiments of a cross-section of a pixel (PXL) along lines II to II' of FIG. 6a. Compared to the embodiment of FIG. 7a, the embodiment of FIG. 7b further comprises a third insulating layer (INS3) interposed between a first contact electrode (CNE1) and a second contact electrode (CNE2). Meanwhile, FIG. 8a illustrates an embodiment of a cross-section of a pixel (PXL) along lines III to III' of FIG. 6b, and FIG. 8b illustrates an embodiment of a cross-section of a pixel (PXL) along lines IV to IV' of FIG. 6c. For example, FIGS. 8a and 8b show different modified embodiments of the embodiment of FIG. 7a with respect to the connection structure between the first and second electrodes (ELT1, ELT2) and the first and second contact electrodes (CNE1, CNE2).

[0169] In FIGS. 7a to 8b, as an example of circuit elements that can be placed in the circuit layer (PCL), any transistor (M) (for example, a first transistor (M1) including a lower metal layer (BML) connected to a first electrode (ELT1) through a first contact hole (CH1) and a bridge pattern (BRP)). Additionally, as an example of wiring that can be placed in the circuit layer (PCL), a second power line (PL2) connected to a second electrode (ELT2) through a second contact hole (CH2) is to be shown.

[0170] Referring to FIGS. 3 to 8b, a pixel (PXL) and a display device (DD) including the same according to one embodiment of the present invention may include a circuit layer (PCL) and a display layer (DPL) arranged to overlap each other on one surface of a base layer (BSL). For example, a display area (DA) may include a circuit layer (PCL) arranged on one surface of a base layer (BSL) and a display layer (DPL) arranged on the circuit layer (PCL). However, the relative positions of the circuit layer (PCL) and the display layer (DPL) on the base layer (BSL) may vary depending on the embodiment.

[0171] In each pixel area (PXA) of the circuit layer (PCL), circuit elements (e.g., transistors (M) and storage capacitors (Cst)) constituting the pixel circuit (PXC) of the corresponding pixel (PXL) and various wirings connected thereto may be disposed. Additionally, in each pixel area (PXA) of the display layer (DPL), first and second electrodes (ELT1, ELT2), light-emitting elements (LD), and / or first and second contact electrodes (CNE1, CNE2) constituting the light-emitting unit (EMU) of the corresponding pixel (PXL) may be disposed.

[0172] The circuit layer (PCL) may include a plurality of insulating layers in addition to circuit elements and wiring. For example, the circuit layer (PCL) may include a buffer layer (BFL), a gate insulating layer (GI), a first interlayer insulating layer (ILD1), a second interlayer insulating layer (ILD2), and / or a passivation layer (PSV) sequentially stacked on one side of the base layer (BSL).

[0173] Additionally, the circuit layer (PCL) may optionally further include a first conductive layer including at least one light-blocking layer (e.g., a lower metal layer (BML)) disposed below at least some of the transistors (M).

[0174] For example, the first conductive layer may include a lower metal layer (BML) disposed between the base layer (BSL) and the buffer layer (BFL) and overlapping with the gate electrode (GE) and / or semiconductor pattern (SCP) of at least one transistor (M).

[0175] In one embodiment, the lower metal layer (BML) may be connected to one electrode of the corresponding transistor (M). For example, as in the embodiments of FIGS. 4 and 5, when the first transistor (M1) includes the lower metal layer (BML), the lower metal layer (BML) may be connected to the source electrode (or drain electrode) of the first transistor (M1).

[0176] A buffer layer (BFL) may be disposed on one side of a base layer (BSL) including a first conductive layer. The buffer layer (BFL) can prevent impurities from diffusing into each circuit element.

[0177] A semiconductor layer may be disposed on the buffer layer (BFL). The semiconductor layer may include a semiconductor pattern (SCP) of each transistor (M). The semiconductor pattern (SCP) may include a channel region that overlaps with a gate electrode (GE) and first and second conductive regions (e.g., a source region and a drain region) disposed on both sides of the channel region.

[0178] The semiconductor pattern (SCP) may be a semiconductor pattern composed of polysilicon, amorphous silicon, or oxide semiconductor, etc. The first and second conductive regions of the semiconductor pattern (SCP) may each be doped with a predetermined impurity.

[0179] In one embodiment, the semiconductor patterns (SCP) of the transistors (M) constituting each pixel circuit (PXC) may be made of substantially the same or similar material. For example, the semiconductor patterns (SCP) of the transistors (M) may be made of any one of the same material among polysilicon, amorphous silicon, and oxide semiconductor.

[0180] In another embodiment, some of the transistors (M) and some of the others may include semiconductor patterns (SCPs) made of different materials. For example, the semiconductor pattern (SCP) of some of the transistors (M) may be made of polysilicon or amorphous silicon, and the semiconductor pattern (SCP) of the others of the transistors (M) may be made of oxide semiconductor.

[0181] A gate insulating layer (GI) may be disposed on the semiconductor layer. Additionally, a second conductive layer may be disposed on the gate insulating layer (GI).

[0182] The second conductive layer may include the gate electrode (GE) of each transistor (M). Additionally, the second conductive layer may further include one electrode of the storage capacitor (Cst) and / or a predetermined wiring (e.g., a scan line (SL)).

[0183] A first interlayer insulating layer (ILD1) may be disposed on the second conductive layer. Additionally, a third conductive layer may be disposed on the first interlayer insulating layer (ILD1).

[0184] The third conductive layer may include the first and second transistor electrodes (TE1, TE2) of each transistor (M). Here, the first and second transistor electrodes (TE1, TE2) may be source and drain electrodes. Additionally, the third conductive layer may further include one electrode of a storage capacitor (Cst) and / or a certain wiring (e.g., a data line (DL)).

[0185] A second interlayer insulating layer (ILD2) may be disposed on the third conductive layer. Additionally, a fourth conductive layer may be disposed on the second interlayer insulating layer (ILD2).

[0186] Each of the buffer layer (BFL), gate insulating layer (GI), first interlayer insulating layer (ILD1), and second interlayer insulating layer (ILD2) may be composed of a single layer or multiple layers and may include at least one inorganic insulating material and / or organic insulating material. For example, each of the buffer layer (BFL), gate insulating layer (GI), first interlayer insulating layer (ILD1), and second interlayer insulating layer (ILD2) may be silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO₂ x N y It may include various types of organic / inorganic insulating materials, including ) etc.

[0187] The fourth conductive layer may include a bridge pattern (BRP) connecting the circuit layer (PCL) and the display layer (DPL) and / or a predetermined wiring (e.g., a first power line (PL1) and / or a second power line (PL2)). The bridge pattern (BRP) may be connected to the first electrode (ELT1) of the light-emitting unit (EMU) through the first contact hole (CH1), etc. The second power line (PL2) may be connected to the second electrode (ELT2) of the light-emitting unit (EMU) through the second contact hole (CH2), etc.

[0188] Each of the conductive patterns, electrodes, and / or wiring constituting the first to fourth conductive layers may have conductivity by including at least one conductive material, and the constituent material is not particularly limited. For example, each of the conductive patterns, electrodes, and / or wiring constituting the first to fourth conductive layers may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), but is not limited thereto.

[0189] In another embodiment, the fourth conductive layer may be omitted. In this case, the bridge pattern (BRP) may not be provided, and the first electrode (ELT1) may be directly connected to a predetermined circuit element through the first contact hole (CH1). For example, the first electrode (ELT1) may be directly connected to the first transistor electrode (TE1) (or the second transistor electrode (TE2)) of the first transistor (M1) through the first contact hole (CH1).

[0190] If the fourth conductive layer is omitted, the second interlayer insulating layer (ILD2) may be provided optionally. For example, if the fourth conductive layer is omitted, the second interlayer insulating layer (ILD2) may also be omitted so that the passivation layer (PSV) is formed directly on the third conductive layer, or even if the fourth conductive layer is omitted, the second interlayer insulating layer (ILD2) and the passivation layer (PSV) may be formed sequentially on the third conductive layer.

[0191] Additionally, the positions of the first and / or second power lines (PL1, PL2) may vary depending on the embodiment. For example, if the second interlayer insulation layer (ILD2) and / or the fourth conductive layer are omitted, each of the first and second power lines (PL1, PL2) may be provided in the first conductive layer, the second conductive layer, or the third conductive layer. Additionally, if the first and / or second power lines (PL1, PL2) are provided in multiple layers, the first and / or second power lines (PL1, PL2) may include multiple layers of wiring provided in at least two of the first to third conductive layers (or the first to fourth conductive layers if the fourth conductive layer is provided).

[0192] A passivation layer (PSV) may be disposed on the fourth conductive layer. According to an embodiment, the passivation layer (PSV) may include at least an organic insulating layer and may substantially flatten the surface of the circuit layer (PCL). A display layer (DPL) may be disposed on top of the passivation layer (PSV).

[0193] The passivation layer (PSV) may be composed of a single layer or multiple layers and may include at least one inorganic insulating material and / or an organic insulating material. For example, the passivation layer (PSV) may include at least one organic insulating film and may substantially flatten the surface of the circuit layer (PCL). In one embodiment, the organic insulating film may include, but is not limited to, at least one of an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, and a benzocyclobutene resin.

[0194] The display layer (DPL) may include a light-emitting unit (EMU) of each pixel (PXL). For example, the display layer (DPL) may include first and second electrodes (ELT1, ELT2) disposed in a light-emitting region (EA) of each pixel (PXL), a plurality of light-emitting elements (LD) arranged between the first and second electrodes (ELT1, ELT2), and first and second contact electrodes (CNE1, CNE2) connecting the first and second electrodes (ELT1, ELT2) and the light-emitting elements (LD).

[0195] Additionally, the display layer (DPL) may further include at least one pattern (BNP) for protruding one region of each of the first and second electrodes (ELT1, ELT2) in an upward direction, and / or a bank (BNK) surrounding each light-emitting region (EA). In addition, the display layer (DPL) may further include at least one conductive layer and / or insulating layer, etc.

[0196] For example, the display layer (DPL) may include first and second patterns (BNP1, ​​BNP2), first and second electrodes (ELT1, ELT2), a first insulating layer (INS1), a bank (BNK), light-emitting elements (LD), a second insulating layer (INS2), and first and second contact electrodes (CNE1, CNE2), which are sequentially arranged and / or formed on top of the circuit layer (PCL). Additionally, the display layer (DPL) may optionally include a third insulating layer (INS3).

[0197] In one embodiment, the first and second contact electrodes (CNE1, CNE2) may be disposed on the same layer as shown in FIG. 7a, FIG. 8a, and FIG. 8b. In another embodiment, the first and second contact electrodes (CNE1, CNE2) may be disposed separately on different layers as shown in FIG. 7b. In this case, the display layer (DPL) may further include a third insulating layer (INS3) interposed between the first and second contact electrodes (CNE1, CNE2). For example, the third insulating layer (INS3) covers the first contact electrode (CNE1), and one end of the third insulating layer (INS3) may be interposed between the first contact electrode (CNE1) and the second contact electrode (CNE2).

[0198] Meanwhile, in the case of the bank (BNK), its position on the cross-section may vary depending on the embodiment. In one embodiment, the bank (BNK) may be formed on the first insulating layer (INS1). In another embodiment, the bank (BNK) may be placed on the same layer as the first and second patterns (BNP1, ​​BNP2). Additionally, the bank (BNK) may be formed integrally or non-integrally with the first and / or second patterns (BNP1, ​​BNP2), and may or may not overlap with the first and / or second patterns (BNP1, ​​BNP2).

[0199] The first and second patterns (BNP1, ​​BNP2) (also referred to as "wall patterns" or "protrusion patterns") may be optionally formed on one side of a base layer (BSL) on which a circuit layer (PCL), etc., is formed. The first and second patterns (BNP1, ​​BNP2) may protrude in the height direction of the base layer (BSL) (e.g., a third direction (DR3)) on one side of the base layer (BSL) on which the circuit layer (PCL) is formed. The first and second patterns (BNP1, ​​BNP2) may be disposed below the first and second electrodes (ELT1, ELT2) respectively so as to overlap with one region of each of the first and second electrodes (ELT1, ELT2). Accordingly, the first and second electrodes (ELT1, ELT2) may protrude upward in the region overlapping with the first and second patterns (BNP1, ​​BNP2).

[0200] The first and second patterns (BNP1, ​​BNP2) are intended to form a reflective wall structure around the light-emitting elements (LDs) and may be formed as separate or integrated patterns. For example, the first pattern (BNP1) and the second pattern (BNP2) may be separated from each other. The first pattern (BNP1) may be placed below the first electrode (ELT1) so as to overlap with a region of the first electrode (ELT1), and the second pattern (BNP2) may be placed below the second electrode (ELT2) so as to overlap with a region of the second electrode (ELT2). In another embodiment, the first and second patterns (BNP1, ​​BNP2) may be connected to each other, having an opening or groove corresponding to the region where the light-emitting elements (LDs) are placed, and may be formed as an integrated pattern that surrounds the region where the light-emitting elements (LDs) are placed. In this case, the first and second patterns (BNP1, ​​BNP2) may be different parts (or regions) of the integrated pattern.

[0201] When the first and second patterns (BNP1, ​​BNP2) are placed below one region of each of the first and second electrodes (ELT1, ELT2), the first and second electrodes (ELT1, ELT2) may protrude upward from the region where the first and second patterns (BNP1, ​​BNP2) are formed. Accordingly, the first and second patterns (BNP1, ​​BNP2) can form a reflective wall structure together with the first and second electrodes (ELT1, ELT2).

[0202] For example, the first and second electrodes (ELT1, ELT2) and / or the first and second patterns (BNP1, ​​BNP2) may be formed of a reflective material, or a reflective film may be formed on the protruding sidewalls of the first and second electrodes (ELT1, ELT2) and / or the first and second patterns (BNP1, ​​BNP2). Accordingly, light emitted from the first and second ends (EP1, EP2) of the light-emitting elements (LD) facing the first and second electrodes (ELT1, ELT2) may be directed toward the front direction of the display panel (DP). Here, the front direction of the display panel (DP) may include a direction perpendicular to the display panel (DP) (for example, a third direction (DR3)), and may also comprehensively refer to a direction within a predetermined viewing angle range. In this way, when one region of the first and second electrodes (ELT1, ELT2) is protruded upward using the first and second patterns (BNP1, ​​BNP2), the light efficiency of the pixel (PXL) can be improved.

[0203] Meanwhile, in another embodiment, the pixel (PXL) may not include the first and / or second patterns (BNP1, ​​BNP2). In this case, the first and / or second electrodes (ELT1, ELT2) may have a substantially flat surface or an uneven surface formed with different thicknesses depending on the region.

[0204] The first and second patterns (BNP1, ​​BNP2) may include an insulating material comprising at least one inorganic material and / or an organic material. As an example, the first and second patterns (BNP1, ​​BNP2) are silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO₂ x N y It may include at least one layer of inorganic film comprising various inorganic insulating materials, such as ). Alternatively, the first and second patterns (BNP1, ​​BNP2) may include at least one layer of organic film comprising various types of organic insulating materials, or may be composed of a single layer or a multilayer insulator comprising a combination of organic and inorganic materials.

[0205] A reflective wall may be formed around the light-emitting elements (LD) by the first and second patterns (BNP1, ​​BNP2) and the first and second electrodes (ELT1, ELT2) disposed thereon. For example, if the first and second electrodes (ELT1, ELT2) include a reflective electrode layer, light emitted from the first and second ends (EP1, EP2) of the light-emitting elements (LD) may be reflected by the reflective electrode layer and emitted in the upward direction of each pixel (PXL).

[0206] The first and second patterns (BNP1, ​​BNP2) may have various shapes. In one embodiment, the first and second patterns (BNP1, ​​BNP2) may be formed to have sidewalls inclined at a predetermined range of angles with respect to the base layer (BSL), as shown in FIGS. 7a to 8b. In another embodiment, the sidewalls of the first and second patterns (BNP1, ​​BNP2) may have curved surfaces or stepped shapes, etc. As an example, each of the first and second patterns (BNP1, ​​BNP2) may have a cross-section such as a semicircle or a semi-ellipse shape.

[0207] First and second electrodes (ELT1, ELT2) may be disposed on top of the first and second patterns (BNP1, ​​BNP2). The first and second electrodes (ELT1, ELT2) have a surface profile corresponding to the first and second patterns (BNP1, ​​BNP2) and may protrude in the height direction of the base layer (BSL) in the area overlapping with the first and second patterns (BNP1, ​​BNP2).

[0208] Each of the first and second electrodes (ELT1, ELT2) may include at least one conductive material. For example, the first and second electrodes (ELT1, ELT2) are at least one metal or an alloy containing the same among various metallic materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., conductive oxides such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), ZTO (Zinc Tin Oxide), GTO (Gallium Tin Oxide), and FTO (Fluorine-doped Tin Oxide), and conductive polymers such as PEDOT At least one conductive material may be included, but is not limited thereto. For example, the first and second electrodes (ELT1, ELT2) may include other conductive materials, such as carbon nanotubes or graphene. That is, the first and second electrodes (ELT1, ELT2) may have conductivity by including at least one of various conductive materials, and the constituent materials of the first and second electrodes (ELT1, ELT2) are not particularly limited. Additionally, the first and second electrodes (ELT1, ELT2) may include the same or different conductive materials.

[0209] Each of the first and second electrodes (ELT1, ELT2) may be composed of a single layer or multiple layers. For example, the first and second electrodes (ELT1, ELT2) may include a reflective electrode layer comprising a reflective conductive material (for example, a metal). Additionally, the first and second electrodes (ELT1, ELT2) may optionally further include at least one of a transparent electrode layer disposed above and / or below the reflective electrode layer and a conductive capping layer covering the reflective electrode layer and / or the top of the transparent electrode layer.

[0210] A first insulating layer (INS1) may be disposed on the first and second electrodes (ELT1, ELT2). For example, the first insulating layer (INS1) may be formed to cover one area of ​​each of the first and second electrodes (ELT1, ELT2) and may include an opening that exposes another area of ​​each of the first and second electrodes (ELT1, ELT2). As an example, the first insulating layer (INS1) may include a plurality of openings formed on the upper surface of the first and second patterns (BNP1, ​​BNP2) as shown in FIGS. 7a and 7b. Through the openings, the first and second contact electrodes (CNE1, CNE2) may be contacted and connected to the first and second electrodes (ELT1, ELT2), respectively. In another embodiment, the first insulating layer (INS1) may include third and fourth contact holes (CH3, CH4) for connecting the first and second electrodes (ELT1, ELT2) to the first and second contact electrodes (CNE1, CNE2), respectively, as shown in FIG. 8a and 8b.

[0211] The first insulating layer (INS1) may be composed of a single layer or multiple layers and may include at least one inorganic insulating material and / or an organic insulating material. In one embodiment, the first insulating layer (INS1) is silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO₂ x Ny It may include at least one layer of inorganic insulating film comprising at least one type of inorganic insulating material including ).

[0212] In the area where the first insulating layer (INS1) is open (or, the area where the third and fourth contact holes (CH3, CH4) are formed in the first insulating layer (INS1)), the first and second electrodes (ELT1, ELT2) can be connected to the first and second contact electrodes (CNE1, CNE2), respectively.

[0213] As the first and second electrodes (ELT1, ELT2) are covered by the first insulating layer (INS1), damage to the first and second electrodes (ELT1, ELT2) can be prevented during a subsequent process. Additionally, it can prevent short circuit defects caused by improper connection between the first and second electrodes (ELT1, ELT2) and the light-emitting elements (LD).

[0214] In the light-emitting region (EA) where the first insulating layer (INS1), etc. is formed, light-emitting elements (LDs) can be supplied and aligned. Each light-emitting element (LD) can be aligned between the first electrode (ELT1) and the second electrode (ELT2) such that it overlaps with or does not overlap with the first electrode (ELT1) and / or the second electrode (ELT2).

[0215] Meanwhile, prior to supplying the light-emitting elements (LDs), a bank (BNK) may be formed around the light-emitting region (EA). For example, a bank (BNK) may be formed in the display region (DA) to surround each light-emitting region (EA). Accordingly, each light-emitting region (EA) to which the light-emitting elements (LDs) are supplied may be defined.

[0216] A second insulating layer (INS2) may be disposed on a region of the light-emitting elements (LD). For example, the second insulating layer (INS2) may be locally disposed on a region of the light-emitting elements (LD) to expose the first and second ends (EP1, EP2) of each of the light-emitting elements (LD). The second insulating layer (INS2) may be formed in an independent pattern on the light-emitting region (EA) of each pixel (PXL), but is not limited thereto.

[0217] The second insulating layer (INS2) may be composed of a single layer or multiple layers and may include at least one inorganic insulating material and / or an organic insulating material. For example, the second insulating layer (INS2) may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ), aluminum oxide (Al X O Y It may include various types of organic / inorganic insulating materials, such as photoresist (PR) materials.

[0218] After the alignment of the light-emitting elements (LDs) is completed, if a second insulating layer (INS2) is formed on the light-emitting elements (LDs), the light-emitting elements (LDs) can be stably fixed.

[0219] In one embodiment, when a gap exists between the first insulating layer (INS1) and the light-emitting elements (LD) due to a step formed by the first and second electrodes (ELT1, ELT2), at least a portion of the gap may be filled with an insulating material introduced during the process of forming the second insulating layer (INS2). However, depending on the embodiment, the gap may not be completely filled.

[0220] Both ends of the light-emitting elements (LD) not covered by the second insulating layer (INS2), namely the first and second ends (EP1, EP2), can be covered by the first and second contact electrodes (CNE1, CNE2), respectively.

[0221] The first and second contact electrodes (CNE1, CNE2) may be formed separately from each other. For example, the first and second contact electrodes (CNE1, CNE2) may be spaced apart from each other on the first and second ends (EP1, EP2) of at least one light-emitting element (LD), with a second insulating layer (INS2) interposed between them.

[0222] Additionally, the first and second contact electrodes (CNE1, CNE2) may be positioned on top of the first and second electrodes (ELT1, ELT2) to cover the exposed areas (or, third and fourth contact holes (CH3, CH4)) of each of the first and second electrodes (ELT1, ELT2). For example, the first and second contact electrodes (CNE1, CNE2) may be positioned on the first and second electrodes (ELT1, ELT2) to contact the first and second electrodes (ELT1, ELT2) respectively on top of or around the first and second patterns (BNP1, ​​BNP2), as shown in FIGS. 7a and 7b.

[0223] Alternatively, the first and second contact electrodes (CNE1, CNE2) may be placed on the first and second electrodes (ELT1, ELT2) so as to overlap with the third and fourth contact holes (CH3, CH4), respectively, as shown in FIG. 8a and 8b, and may be connected to the first and second electrodes (ELT1, ELT2), respectively, by the third and fourth contact holes (CH3, CH4). In one embodiment, the formation location of the third and fourth contact holes (CH3, CH4) may be selected considering the light efficiency of the pixel (PXL), and the first and second contact electrodes (CNE1, CNE2) may be connected to the first and second electrodes (ELT1, ELT2), respectively, by the third and fourth contact holes (CH3, CH4).

[0224] Accordingly, the first and second contact electrodes (CNE1, CNE2) can be connected to the first and second electrodes (ELT1, ELT2), respectively. And, through the first and second contact electrodes (CNE1, CNE2), each of the first and second electrodes (ELT1, ELT2) can be connected to the first or second end (EP1, EP2) of at least one adjacent light-emitting element (LD).

[0225] As in the example of FIG. 7a, when the first and second contact electrodes (CNE1, CNE2) are formed on the same layer, the first and second contact electrodes (CNE1, CNE2) may be formed simultaneously or sequentially in the same process, and the third insulating layer (INS3) may be omitted. In this case, the manufacturing process of the pixels (PXL) can be simplified.

[0226] Meanwhile, as in the embodiment of FIG. 7b, when the first and second contact electrodes (CNE1, CNE2) are formed on different layers with a third insulating layer (INS3) interposed between them, the first and second contact electrodes (CNE1, CNE2) can be separated more stably.

[0227] In another embodiment, at least one of the first and second contact electrodes (CNE1, CNE2) may be omitted. In this case, the first and / or second ends (EP1, EP2) of the light-emitting elements (LD) may be directly contacted and / or connected to the first and / or second electrodes (ELT1, ELT2).

[0228] The third insulating layer (INS3) may be composed of a single layer or multiple layers and may include at least one inorganic insulating material and / or an organic insulating material. In one embodiment, the third insulating layer (INS3) is silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO₂ x N y It may include at least one layer of inorganic insulating film comprising at least one type of inorganic insulating material including ).

[0229] By forming a second insulating layer (INS2) and / or a third insulating layer (INS3) on top of the light-emitting elements (LD), electrical stability between the first and second ends (EP1, EP2) of the light-emitting elements (LD) can be secured. Accordingly, it is possible to prevent short circuit defects from occurring between the first and second ends (EP1, EP2) of the light-emitting elements (LD).

[0230] In one embodiment, the first and second contact electrodes (CNE1, CNE2) may be composed of various transparent conductive materials. For example, the first and second contact electrodes (CNE1, CNE2) may include at least one of various transparent conductive materials including ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), ITZO (Indium Tin Zinc Oxide), ZnO (Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), GZO (Gallium-doped Zinc Oxide), ZTO (Zinc Tin Oxide), GTO (Gallium Tin Oxide), and FTO (Fluorine-doped Tin Oxide), and may be implemented to be substantially transparent or translucent to satisfy a predetermined light transmittance. Accordingly, light emitted from the light-emitting elements (LD) through each of the first and second ends (EP1, EP2) can pass through the first and second contact electrodes (CNE1, CNE2) and be emitted to the outside of the display panel (DP).

[0231] On the first and second contact electrodes (CNE1, CNE2) and / or the third insulating layer (INS3), at least one insulating layer and / or light conversion layer not illustrated may be provided. For example, the third insulating layer (INS3) may be formed entirely on the display area (DA) to cover the first and second patterns (BNP1, ​​BNP2), the first and second electrodes (ELT1, ELT2), the first insulating layer (INS1), the bank (BNK), the light-emitting elements (LD), the second insulating layer (INS2), the first and second contact electrodes (CNE1, CNE2) and / or the third insulating layer (INS3).

[0232] The insulating layer may comprise at least one layer of inorganic film and / or organic film. For example, the insulating layer may be composed of a single layer or multiple layers and may comprise at least one inorganic insulating material and / or organic insulating material. As an example, the insulating layer is silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO₂ x N y ) or aluminum oxide (Al X O y It may include various types of organic / inorganic insulating materials, including ) etc.

[0233] In one embodiment, the insulating layer may include a single layer (or multiple layers) of encapsulation layer. Additionally, depending on the embodiment, at least one overcoat layer, a filler layer, and / or an upper substrate may be further disposed on top of the insulating layer.

[0234] Additionally, a light conversion layer may be optionally provided on the light-emitting unit (EMU) of each pixel (PXL). The light conversion layer may include a color conversion layer (or wavelength conversion layer) and / or a color filter layer corresponding to a predetermined color. The light conversion layer may be formed directly on the first and second contact electrodes (CNE1, CNE2) and / or the third insulating layer (INS3) of each pixel (PXL), or may be formed on an insulating layer covering the first and second contact electrodes (CNE1, CNE2) and / or the third insulating layer (INS3), and the type, structure, location, and method of forming the light conversion layer are not particularly limited.

[0235] For example, in each pixel area (PXA), a light conversion layer may be optionally further provided on top of the display layer (DPL), including light conversion particles (e.g., quantum dots of a predetermined color) for converting the color (or wavelength) of light emitted from light-emitting elements (LD), light scattering particles for increasing the utilization rate of light emitted from the light-emitting elements (LD), and / or a color filter material of a predetermined color.

[0237] FIGS. 9 to 15 are plan views illustrating a pixel (PXL) according to an embodiment of the present invention. For example, FIGS. 9 to 14 illustrate different modified embodiments of the embodiment of FIG. 6a regarding the shape and / or size of the first and second electrodes (ELT1, ELT2). FIG. 15 illustrates a modified embodiment of the embodiment of FIG. 6a regarding the configuration of the light-emitting unit (EMU), and for example, illustrates an example of a pixel (PXL) including a light-emitting unit (EMU) with a series / parallel structure as in the embodiment of FIG. 5. In describing the embodiments of FIGS. 9 to 15, the same reference numerals are assigned to configurations identical or similar to at least one previously described embodiment (for example, the embodiment of FIG. 6a), and a detailed description thereof is omitted.

[0238] Referring to FIGS. 9 and 10, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at an interval that increases non-linearly and / or continuously at the outer edge (OEA) of the light-emitting region (EA). For example, the first electrode (ELT1) and the second electrode (ELT2) may be formed such that each face facing each other at the outer edge (OEA) of the light-emitting region (EA) has a concave curved shape as in FIG. 9 or a convex curved shape as in FIG. 10. Additionally, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at an interval that increases progressively as they move away from the center (CEA).

[0239] Referring to FIGS. 11 and 12, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at a distance that gradually increases as they move away from the central point (CP) in the central part (CEA) of the light-emitting region (EA). For example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at a minimum distance from the central point (CP), and spaced apart from each other at a distance that gradually increases as they move away from the central point (CP). As an example, the first electrode (ELT1) and the second electrode (ELT2) may be formed such that each face facing each other in the light-emitting region (EA) has a diagonal shape with a constant slope centered on the central point (CP) as in FIG. 11, or a curved shape with a constant curvature centered on the central point (CP) as in FIG. 12. In addition, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at intervals that increase continuously as they move away from the central point (CP).

[0240] In another embodiment, the first electrode (ELT1) and / or the second electrode (ELT2) may be formed such that each face facing each other in the light-emitting region (EA) has at least one inflection point.

[0241] Referring to FIG. 13, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at an interval that varies discontinuously at the outer edge (OEA) of the light-emitting region (EA). For example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other at an interval that gradually increases as they move away from the center (CEA), with each of their facing surfaces at the outer edge (OEA) of the light-emitting region (EA) having a stepped shape.

[0242] Referring to FIG. 14, the light-emitting region (EA) may further include an unaligned region (NALA) located between the outer edge (OEA) and the non-light-emitting region (NEA). For example, the light-emitting region (EA) may include a first unaligned region (NALA1) located between the first outer edge (OEA1) and the non-light-emitting region (NEA), and a second unaligned region (NALA2) located between the second outer edge (OEA2) and the non-light-emitting region (NEA). The unaligned region (NALA) may be the outermost region of the light-emitting region (EA) in the second direction (DR2). For example, the unaligned region (NALA) may be the upper and lower regions of the light-emitting region (EA) and may be in contact with the non-light-emitting region (NEA).

[0243] The first electrode (ELT1) and the second electrode (ELT2) may be formed such that light-emitting elements (LDs) are not aligned and / or connected between them in the non-aligned region (NALA). For example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other in the non-aligned region (NALA) with a relatively large gap compared to the central region (CEA) and the outer region (OEA), and may be spaced apart from each other with a gap so large that it is difficult for light-emitting elements (LDs) to be aligned and / or connected between them. As an example, the first electrode (ELT1) and the second electrode (ELT2) may be spaced apart from each other in the non-aligned region (NALA) with a gap so large that it is difficult for light-emitting elements (LDs) to be properly aligned and / or connected between them, by each having a reduced width and / or a curved structure.

[0244] Referring to FIG. 15, the pixel (PXL) may include first to fourth electrodes (ELT1 to ELT4) spaced apart from each other in a light-emitting region (EA). For example, the first to fourth electrodes (ELT1 to ELT4) may be spaced apart from each other by a predetermined distance along a first direction (DR1) in the light-emitting region (EA).

[0245] The first electrode (ELT1) and the second electrode (ELT2) are arranged adjacent to each other in pairs and can receive different alignment signals during the alignment step of the light-emitting elements (LD). Accordingly, at least one first light-emitting element (LD1) (for example, a plurality of first light-emitting elements (LD1)) can be arranged and / or aligned between the first electrode (ELT1) and the second electrode (ELT2).

[0246] The first electrode (ELT1) and the second electrode (ELT2) are spaced apart from each other by a first gap (d1) in the central part (CEA) of the light-emitting region (EA), and are spaced apart from each other by a gap larger than the first gap (d1) in the outer part (OEA) of the light-emitting region (EA), with the gap gradually increasing as it moves away from the central part (CEA). Accordingly, the first light-emitting elements (LD1) are prevented from being clustered in the outer part (OEA) of the light-emitting region (EA) between the first electrode (ELT1) and the second electrode (ELT2), and the utilization rate and alignment characteristics of the first light-emitting elements (LD1) can be improved.

[0247] The third electrode (ELT3) and the fourth electrode (ELT4) are arranged adjacent to each other in pairs and can receive different alignment signals during the alignment step of the light-emitting elements (LD). Accordingly, at least one second light-emitting element (LD2) (for example, a plurality of second light-emitting elements (LD2)) can be arranged and / or aligned between the third electrode (ELT3) and the fourth electrode (ELT4).

[0248] The third electrode (ELT3) and the fourth electrode (ELT4) are spaced apart from each other by a second gap (d2) in the central part (CEA) of the light-emitting region (EA), and are spaced apart from each other by a gap larger than the second gap (d2) in the outer part (OEA) of the light-emitting region (EA), with the gap gradually increasing as it moves away from the central part (CEA). Accordingly, the second light-emitting elements (LD2) are prevented from being clustered in the outer part (OEA) of the light-emitting region (EA) between the third electrode (ELT3) and the fourth electrode (ELT4), and the utilization rate and alignment characteristics of the second light-emitting elements (LD2) can be improved.

[0249] In one embodiment, the first gap (d1) and the second gap (d2) may be the same as each other. In this case, the strength of the electric field formed between the first electrode (ELT1) and the second electrode (ELT2), and between the third electrode (ELT3) and the fourth electrode (ELT4), is equalized, thereby allowing the light-emitting elements (LD) to be more uniformly aligned in the light-emitting region (EA).

[0250] However, the present invention is not limited thereto. For example, in other embodiments, the first interval (d1) and the second interval (d2) may be set differently from each other to control the alignment and distribution characteristics of the light-emitting elements (LDs) in a desired form.

[0251] Each of the first to fourth electrodes (ELT1 to ELT4) may or may not overlap with the bank (BNK), and the size, shape, and / or position of each of the first to fourth electrodes (ELT1 to ELT4) may vary depending on the design conditions of the pixel (PXL), etc. For example, the first electrode (ELT1) may not overlap with the bank (BNK) in the first direction (DR1) as shown in FIG. 6a to 14, or may overlap with the bank (BNK) in the first direction (DR1) as shown in FIG. 15.

[0252] Additionally, the pixel (PXL) may further include first to third contact electrodes (CNE1 to CNE3) for stably connecting the first and second light-emitting elements (LD1, LD2) between the first to fourth electrodes (ELT1 to ELT4).

[0253] The first contact electrode (CNE1) is disposed on the first electrode (ELT1) and the first end (EP1) of the first light-emitting elements (LD1), and can electrically connect the first electrode (ELT1) and the first end (EP1) of the first light-emitting elements (LD1).

[0254] The second contact electrode (CNE2) is disposed on the second electrode (ELT2), the second ends (EP2) of the first light-emitting elements (LD1), the third electrode (ELT3), and the first ends (EP1) of the second light-emitting elements (LD2), and can electrically connect the second electrode (ELT2), the second ends (EP2) of the first light-emitting elements (LD1), the third electrode (ELT3), and the first ends (EP1) of the second light-emitting elements (LD2).

[0255] The third contact electrode (CNE3) is disposed on the second ends (EP2) of the fourth electrode (ELT4) and the second light-emitting elements (LD2), and can electrically connect the second ends (EP2) of the fourth electrode (ELT4) and the second light-emitting elements (LD2).

[0256] Each of the first to third contact electrodes (CNE1 to CNE3) may have a width equal to or different from each of the first to fourth electrodes (ELT1 to ELT4), and the size, shape and / or position of each of the first to third contact electrodes (CNE1 to CNE3) may be varied according to the design conditions of the pixel (PXL), etc. For example, the first contact electrode (CNE1) may have a width greater than the width of the first electrode (ELT1), as shown in FIG. 6a to 14, or a width smaller than the width of the first electrode (ELT1), as shown in FIG. 15.

[0258] According to the pixel (PXL) and the display device (DD) including the same according to various embodiments of the present invention as described above, by gradually widening the gap between the first electrode (ELT1) and the second electrode (ELT2) at the outer edge (OEA) of the light-emitting region (EA), the phenomenon in which light-emitting elements (LDs) are clustered at the outer edge (OEA) of the light-emitting region (EA) due to the ACEO effect is prevented, and the light-emitting elements (LDs) can be more stably aligned between the first electrode (ELT1) and the second electrode (ELT2). Accordingly, the utilization rate and alignment characteristics of the light-emitting elements (LDs) can be improved, and the light-emitting characteristics and brightness of the pixel (PXL) can be improved.

[0260] Although the technical concept of the present invention has been specifically described according to the aforementioned embodiments, it should be noted that the embodiments are for illustrative purposes only and are not intended to be limiting. Furthermore, those skilled in the art will understand that various modifications are possible within the scope of the technical concept of the present invention.

[0261] The scope of the present invention is not limited to the contents described in the detailed description of the specification, but must be determined by the claims. Furthermore, all modifications or variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0263] BNK: Bank BNP1: Pattern 1 BNP2: 2nd pattern CEA: Central part of the luminescence region CNE1: First contact electrode CNE2: Second contact electrode CNE3: Third contact electrode DA: Indicator area DD: Display device EA: Light-emitting area ELT1: First electrode ELT2: Second electrode ELT3: Third electrode ELT4: Fourth electrode EMU: Light-emitting unit EP1: First end of the light-emitting element EP2: Second end of the light-emitting element LD: Light-emitting element NA: Non-display area NALA: Unaligned area of ​​the light-emitting region NEA: Non-luminous region OEA: Outer edge of the luminous region PXA: Pixel area PXC: Pixel circuit PXL: Pixels

Claims

Claim 1 A pixel comprising: a light-emitting region including a central portion and an outer portion; a non-light-emitting region surrounding the light-emitting region; a first electrode and a second electrode spaced apart from each other in the light-emitting region; and a first light-emitting element aligned between the first electrode and the second electrode, wherein the first electrode and the second electrode are spaced apart from each other at a first interval in the central portion, spaced apart from each other at an interval greater than the first interval in the outer portion, and spaced apart from each other at an interval that gradually increases as they move away from the central portion, and the first light-emitting element includes a plurality of light-emitting elements arranged in the outer portion, wherein in the plurality of light-emitting elements, the width of the portion that does not overlap with the first and second electrodes gradually increases as they move away from the central portion. Claim 2 In claim 1, the first electrode and the second electrode are pixels spaced apart from each other at a linearly increasing interval from the outer edge. Claim 3 In claim 1, the first electrode and the second electrode are pixels spaced apart from each other at intervals that increase non-linearly at the outer edge. Claim 4 In claim 1, the first electrode and the second electrode are pixels spaced apart from each other at intervals that vary discontinuously at the outer edge. Claim 5 In claim 1, the first electrode and the second electrode have shapes that are symmetrical to each other with respect to the first light-emitting element. Claim 6 In claim 1, each of the first electrode and the second electrode has a shape symmetrical with respect to the central portion, a pixel. Claim 7 A pixel according to claim 1, wherein the first electrode and the second electrode have a shape that is symmetrical to each other with respect to the first light-emitting element, and each has a shape that is symmetrical to the top and bottom with respect to the central part. Claim 8 In claim 1, the first electrode and the second electrode each have a diagonal shape, a curved shape, or a stepped shape on each of their respective faces, forming a pixel. Claim 9 In claim 1, the first electrode and the second electrode are spaced apart from each other along a first direction in the light-emitting region, and each extends along a second direction, forming a pixel. Claim 10 In claim 9, the first electrode and the second electrode are spaced apart from each other by a first interval along the first direction in the central portion and spaced apart from each other by a greater interval than the first interval along the first direction in the outer portion, and the distance along the first direction gradually increases as it moves away from the central portion, a pixel. Claim 11 In claim 9, the central portion comprises a region corresponding to the central point of the light-emitting region in the second direction, and a predetermined range of regions extending in both directions from the central point toward the outer portion, a pixel. Claim 12 In claim 11, the first electrode and the second electrode are pixels spaced apart from each other by a uniform distance with the first interval from the central portion. Claim 13 In claim 11, the first electrode and the second electrode are pixels that are spaced apart from each other at intervals that gradually increase as they move away from the central point, even in the central part. Claim 14 In claim 11, the first electrode and the second electrode each have a constant slope or curvature centered on the central point on each of their respective facing surfaces and are spaced apart from each other at a continuously increasing interval. Claim 15 In claim 1, the light-emitting region further includes an unaligned region located between the outer region and the non-light-emitting region, and the first electrode and the second electrode are spaced apart from each other in the unaligned region by a larger distance than the central region and the outer region, and each has a reduced width, a pixel. Claim 16 In claim 1, the first light-emitting element is a pixel electrically connected between the first electrode and the second electrode. Claim 17 A pixel according to claim 16, further comprising: a third electrode and a fourth electrode spaced apart from each other in the light-emitting region and separated from the first electrode and the second electrode; and a second light-emitting element aligned between the third electrode and the fourth electrode. Claim 18 In claim 17, the third electrode and the fourth electrode are spaced apart from each other at a second interval from the central portion, spaced apart from each other at an interval greater than the second interval from the outer portion, and spaced apart from each other at an interval that gradually increases as they move away from the central portion, a pixel. Claim 19 A pixel according to claim 17, further comprising: a first contact electrode electrically connecting the first electrode and the first end of the first light-emitting element; a second contact electrode electrically connecting the second electrode, the second end of the first light-emitting element, the third electrode, and the first end of the second light-emitting element; and a third contact electrode electrically connecting the fourth electrode and the second end of the second light-emitting element. Claim 20 A display device comprising a pixel disposed in a display area, wherein the pixel comprises: a light-emitting area including a central portion and an outer portion; a non-light-emitting area surrounding the light-emitting area; a first electrode and a second electrode disposed spaced apart from each other in the light-emitting area; and a first light-emitting element aligned between the first electrode and the second electrode, wherein the first electrode and the second electrode are spaced apart from each other at a first interval in the central portion, spaced apart from each other at an outer portion with a interval greater than the first interval, and spaced apart from each other at an interval that gradually increases as they move away from the central portion, wherein the first light-emitting element comprises a plurality of light-emitting elements disposed in the outer portion, and wherein the width of the portion that does not overlap with the first and second electrodes among the plurality of light-emitting elements gradually increases as they move away from the central portion.

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