Electronic system including host, memory controller and memory device and operating method thereof

Abstract

The present invention relates to an electronic device, wherein an electronic system for changing a randomly recorded logical block address to an address corresponding to continuous data comprises: a file system comprising a plurality of zones to which logical block addresses corresponding to continuous data are assigned; a memory device comprising a plurality of memory blocks to which the continuous data is programmed; and a memory controller that maps the logical block addresses to physical block addresses corresponding to continuous pages included in each of the plurality of memory blocks so that the continuous data is programmed in the plurality of memory blocks. In the electronic system, the plurality of zones each comprise a plurality of segments, and the file system assigns the logical block addresses corresponding to the continuous data to invalid segments among the plurality of segments.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to an electronic system and a method of operating the same. Background Technology

[0002] A storage device is a device that stores data under the control of a host device, such as a computer, smartphone, or smartpad. Depending on the device used to store data, storage devices include devices that store data on magnetic disks, such as hard disk drives (HDDs), and devices that store data on semiconductor memory, particularly non-volatile memory, such as solid-state drives (SSDs) and memory cards.

[0003] A storage device may include a memory device in which data is stored and a memory controller that stores data in the memory device. The memory device may be classified into volatile memory and non-volatile memory. Here, non-volatile memory includes ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM), flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), etc. The problem to be solved

[0004] An embodiment of the present invention provides an electronic system for changing a randomly recorded logical block address to an address corresponding to continuous data and a method of operating the same. means of solving the problem

[0005] An electronic system according to an embodiment of the present invention comprises: a file system comprising a plurality of zones to which logical block addresses corresponding to continuous data are assigned; a memory device comprising a plurality of memory blocks to which the continuous data is programmed; and a memory controller that maps the logical block addresses to physical block addresses corresponding to continuous pages included in each of the plurality of memory blocks so that the continuous data is programmed in the plurality of memory blocks, wherein the plurality of zones each comprise a plurality of segments, and the file system may assign the logical block addresses corresponding to the continuous data to invalid segments among the plurality of segments.

[0006] A method of operation of an electronic system according to an embodiment of the present invention may include: a file system comprising a plurality of zones each comprising a plurality of segments; a memory device comprising a plurality of memory blocks; and a memory controller controlling the memory device. The method of operation of the electronic system may include: a step of sequentially assigning logical block addresses corresponding to continuous data to the plurality of segments; a step of creating a mapping relationship between the logical block addresses and physical block addresses corresponding to continuous pages included in the plurality of memory blocks; a step of programming the continuous data to the continuous pages according to the mapping relationship; a step of updating the mapping relationship; and a step of assigning the logical block addresses corresponding to the continuous data to invalid segments among the plurality of segments when the mapping relationship is updated. Effects of the invention

[0007] According to the present technology, when there are no free segments in a flash-friendly file system (F2FS) file system, an overwrite operation is performed on an invalid segment, and the logical block address is moved to a single area through garbage collection during the idle period, thereby changing it to an address corresponding to continuous data, which can improve the performance of an electronic system including a host, a memory controller, and a memory device. Brief explanation of the drawing

[0008] Figure 1 is a block diagram illustrating a storage device. Figure 2 is a diagram illustrating the structure of the memory device of Figure 1. Figure 3 is a diagram showing an example of the memory cell array of Figure 2. Figure 4 is a diagram showing map data output and update between a host and a storage device. Figure 5 is a diagram showing the sections of a file system and programmed memory blocks. Figure 6 is a diagram showing a page that is invalidated when a map update occurs. Figure 7 is a diagram showing the update of each section of the file system according to the map update. Figure 8 is a diagram showing that a logical block address is overwritten in an invalidated segment. Figure 9 is a diagram illustrating the program of data after the logical block address has been overwritten. Figure 10 is a diagram showing the process of garbage collection being performed in a file system. Figure 11 is a diagram illustrating the mapping relationships that change after garbage collection is performed on a file system. FIG. 12 is a drawing for explaining the operation of an electronic system according to one embodiment of the present invention. FIG. 13 is a drawing for explaining the operation of an electronic system according to one embodiment of the present invention. FIG. 14 is a drawing for explaining another embodiment of the memory controller of FIG. 1. FIG. 15 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present invention is applied. FIG. 16 is a block diagram exemplarily showing a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present invention is applied. FIG. 17 is a block diagram showing a user system to which a storage device according to an embodiment of the present invention is applied. Specific details for implementing the invention

[0009] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0010] Hereinafter, in order to provide a detailed explanation sufficient for a person skilled in the art to easily implement the technical concept of the present invention, embodiments of the present invention will be described with reference to the attached drawings.

[0012] Figure 1 is a block diagram illustrating a storage device.

[0013] Referring to FIG. 1, the storage device (50) may include a memory device (100) and a memory controller (200).

[0014] The storage device (50) may be a device that stores data under the control of the host (300), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0015] The storage device (50) can be manufactured as any one of various types of storage devices according to the host interface, which is the method of communication with the host (300). For example, the storage device (50) can be configured as any one of various types of storage devices such as an SSD, MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD type secure digital card, USB (universal serial bus) storage device, UFS (universal flash storage) device, PCMCIA (personal computer memory card international association) card type storage device, PCI (peripheral component interconnection) card type storage device, PCI-E (PCI express) card type storage device, CF (compact flash) card, smart media card, memory stick, etc.

[0016] The storage device (50) can be manufactured in any one of various types of package forms. For example, the storage device (50) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0017] A memory device (100) can store data. The memory device (100) operates in response to the control of a memory controller (200). The memory device (100) may include a memory cell array comprising a plurality of memory cells that store data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, and the plurality of memory cells may constitute a plurality of pages. In an embodiment, a page may be a unit that stores data in the memory device (100) or reads data stored in the memory device (100). A memory block may be a unit that erases data.

[0018] In the embodiment, the memory device (100) may be DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. For convenience of explanation, the present specification assumes that the memory device (100) is a NAND flash memory.

[0019] The memory device (100) can be implemented as a two-dimensional array structure or a three-dimensional array structure. Hereinafter, a three-dimensional array structure is described as an example, but the present invention is not limited to a three-dimensional array structure. The present invention can be applied to a flash memory device in which the charge storage layer is composed of a conductive floating gate (FG), as well as to a charge trap flash (CTF) in which the charge storage layer is composed of an insulating film.

[0020] In an embodiment, the memory device (100) may operate in a Single Level Cell (SLC) manner, storing one data bit in one memory cell. Alternatively, the memory device (100) may operate in a manner that stores at least two data bits in one memory cell. For example, the memory device (100) may operate in a Multi Level Cell (MLC) manner, storing two data bits in one memory cell, a Triple Level Cell (TLC) manner, storing three data bits, or a Quadruple Level Cell (QLC) manner, storing four data bits.

[0021] The memory device (100) is configured to receive commands and addresses from the memory controller (200) and to access an area selected by the address among the memory cell array. That is, the memory device (100) can perform an operation corresponding to the command on the area selected by the address. For example, the memory device (100) can perform a write operation (program operation), a read operation, or an erase operation according to the received command. For example, if a program command is received, the memory device (100) will program data in the area selected by the address. If a read command is received, the memory device (100) will read data from the area selected by the address. If an erase command is received, the memory device (100) will erase the data stored in the area selected by the address.

[0022] The memory controller (200) can control the overall operation of the storage device (50).

[0023] When power voltage is applied to the storage device (50), the memory controller (200) can execute firmware. If the memory device (100) is a flash memory device (100), the memory controller (200) can execute firmware such as a Flash Translation Layer (FTL) to control communication between the host (300) and the memory device (100).

[0024] In an embodiment, the memory controller (200) may include firmware (not shown) capable of receiving data and a logical block address (LBA) from a host (300) and converting the logical block address (LBA) into a physical block address (PBA) representing the addresses of memory cells to be stored in the memory device (100). Additionally, the memory controller (200) may store a logical-physical address mapping table in a buffer memory that configures the mapping relationship between the logical block address (LBA) and the physical block address (PBA).

[0025] The memory controller (200) can control the memory device (100) to perform program operations, read operations, or erase operations, etc., according to a request from the host (300). For example, when a program request is received from the host (300), the memory controller (200) can change the program request into a program command and provide the program command, a physical block address (PBA), and data to the memory device (100). When a read request is received from the host (300) along with a logical block address, the memory controller (200) can change the read request into a read command, select a physical block address corresponding to the logical block address, and then provide the read command and the physical block address (PBA) to the memory device (100). When an erase request is received from a host (300) along with a logical block address, the memory controller (200) can change the erase request into an erase command, select a physical block address corresponding to the logical block address, and then provide the erase command and the physical block address (PBA) to the memory device (100).

[0026] In an embodiment, the memory controller (200) can generate program commands, addresses, and data on its own without a request from the host (300) and transmit them to the memory device (100). For example, the memory controller (200) can provide the commands, addresses, and data to the memory device (100) to perform background operations such as program operations for wear leveling and program operations for garbage collection.

[0027] In an embodiment, the memory controller (200) may include a flash conversion layer (210). The flash conversion layer (210) may convert a logical block address (LBA) corresponding to a request received from a host (300) into a physical block address (PBA) and output it to a memory device (100).

[0028] For example, as described above, the flash conversion layer (210) can convert a logical block address (LBA) corresponding to a program request into a physical block address (PBA), convert a logical block address (LBA) corresponding to a read request into a physical block address (PBA), or convert a logical block address (LBA) corresponding to an erase request into a physical block address (PBA). The flash conversion layer (210) outputs the converted physical block address (PBA) to the memory device (100), and the memory device (100) can perform an operation on a page or memory block corresponding to the physical block address (PBA).

[0029] In an embodiment, the memory controller (200) receives consecutive logical block addresses from the file system (310) and can convert the received logical block addresses into physical block addresses. When consecutive physical block addresses are output to the memory device (100), the memory device (100) can perform consecutive operations corresponding to the consecutive physical addresses.

[0030] In an embodiment, the storage device (50) may further include a buffer memory (not shown). The memory controller (200) may control data exchange between the host (300) and the buffer memory (not shown). Alternatively, the memory controller (200) may temporarily store system data for controlling the memory device (100) in the buffer memory. For example, the memory controller (200) may temporarily store data input from the host (300) in the buffer memory and then transfer the data temporarily stored in the buffer memory to the memory device (100).

[0031] In various embodiments, the buffer memory may be used as an operating memory or cache memory of the memory controller (200). The buffer memory may store codes or commands executed by the memory controller (200). Alternatively, the buffer memory may store data processed by the memory controller (200).

[0032] In the embodiment, the buffer memory may be implemented as dynamic random access memory (DRAM) or static random access memory (SRAM), such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), or RDRAM (Rambus Dynamic Random Access Memory).

[0033] In various embodiments, the buffer memory may be connected outside the storage device (50). In this case, volatile memory devices connected outside the storage device (50) may perform the role of the buffer memory.

[0034] In an embodiment, the memory controller (200) can control at least two memory devices. In this case, the memory controller (200) can control the memory devices according to an interleaving method to improve operational performance.

[0035] The host (300) can communicate with the storage device (50) using at least one of various communication methods such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (Multi-Media Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0036] In an embodiment, the host (300) may include a file system (310). The file system (310) may include a plurality of zones to improve the continuous write performance of the storage device (50). The plurality of zones may be composed of non-volatile memory or volatile memory.

[0037] Additionally, multiple zones may each include segments. For example, among the segments, a segment assigned a logical block address may be a valid segment, and a segment not assigned a logical block address may be a free segment. Furthermore, as the mapping relationship is updated, a valid segment may become invalid and turn into an invalid segment.

[0038] If a logical block address can no longer be assigned to a free segment among the segments included in each of the multiple zones, the invalid segment may be reused by performing garbage collection (GC) or by overwriting the invalid segment.

[0039] Consecutive logical block addresses may be assigned to multiple zones. For example, logical block addresses corresponding to consecutive write requests may be assigned sequentially to free segments among the segments included in the multiple zones. That is,

[0040] In an embodiment, when the memory device (100) does not contain bad blocks, failed pages, or invalid pages, the performance of the storage device (50) by the file system (310) can be increased.

[0041] However, if the memory device (100) contains bad blocks, failed, or invalid pages, random writes may be performed instead of sequential writes. For example, if a large amount of overwrite occurs in multiple areas of the file system (310), random writes may be performed on the memory device (100). When random writes are performed, the performance of the storage device (50) may be degraded.

[0042] Accordingly, in the present invention, a method for improving the performance of a storage device (50) is provided when random writing is performed because there is no free segment in the file system (310).

[0044] Figure 2 is a diagram illustrating the structure of the memory device of Figure 1.

[0045] Referring to FIG. 2, the memory device (100) may include a memory cell array (110), peripheral circuits (120), and control logic (130).

[0046] A memory cell array (110) includes a plurality of memory blocks (BLK1 to BLKz). The plurality of memory blocks (BLK1 to BLKz) are connected to a row decoder (121) via row lines (RL). The plurality of memory blocks (BLK1 to BLKz) may be connected to a page buffer group (123) via bit lines (BL1 to BLn). Each of the plurality of memory blocks (BLK1 to BLKz) includes a plurality of memory cells. In an example, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line may be defined as a single page. Thus, a single memory block may include a plurality of pages.

[0047] Row lines (RL) may include at least one source selection line, a plurality of word lines, and at least one drain selection line.

[0048] The memory cells included in the memory cell array (110) can each be configured as a single level cell (SLC) that stores one data bit, a multi level cell (MLC) that stores two data bits, a triple level cell (TLC) that stores three data bits, or a quadruple level cell (QLC) that can store four data bits.

[0049] The peripheral circuit (120) may be configured to perform a program operation, a read operation, or an erase operation on a selected area of ​​the memory cell array (110) under the control of the control logic (130). The peripheral circuit (120) may drive the memory cell array (110). For example, the peripheral circuit (120) may apply various operating voltages to row lines (RL) and bit lines (BL1~BLn) or discharge the applied voltages under the control of the control logic (130).

[0050] The peripheral circuit (120) may include a row decoder (121), a voltage generator (122), a page buffer group (123), a column decoder (124), an input / output circuit (125), and a sensing circuit (126).

[0051] A row decoder (121) is connected to a memory cell array (110) through row lines (RL). The row lines (RL) may include at least one source selection line, a plurality of word lines, and at least one drain selection line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row lines (RL) may further include a pipe selection line.

[0052] The row decoder (121) is configured to decode a row address (RADD) received from the control logic (130). The row decoder (121) selects at least one memory block among the memory blocks (BLK1 to BLKz) according to the decoded address. Additionally, the row decoder (121) can select at least one word line of the selected memory block to apply voltages generated by the voltage generator (122) to at least one word line (WL) according to the decoded address.

[0053] For example, during a program operation, the row decoder (121) will apply a program voltage to the selected word lines and a program pass voltage at a level lower than the program voltage to the unselected word lines. During a program verification operation, the row decoder (121) will apply a verification voltage to the selected word lines and a verification pass voltage higher than the verification voltage to the unselected word lines. During a read operation, the row decoder (121) will apply a read voltage to the selected word lines and a read pass voltage higher than the read voltage to the unselected word lines.

[0054] In an embodiment, the erase operation of the memory device (100) is performed in units of memory blocks. During the erase operation, the row decoder (121) can select one memory block according to the decoded address. During the erase operation, the row decoder (121) can apply a ground voltage to the word lines connected to the selected memory block.

[0055] The voltage generation unit (122) operates in response to the control of the control logic (130). The voltage generation unit (122) is configured to generate multiple voltages using the external power supply voltage supplied to the memory device (100). Specifically, the voltage generation unit (122) can generate various operating voltages (Vop) used for program, read, and erase operations in response to an operation signal (OPSIG). For example, the voltage generation unit (122) can generate a program voltage, a verification voltage, a pass voltage, a read voltage, and an erase voltage, etc., in response to the control of the control logic (130).

[0056] As an example, the voltage generating unit (122) can generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generating unit (122) is used as the operating voltage of the memory device (100).

[0057] As an example, the voltage generating unit (122) can generate multiple voltages using an external power supply voltage or an internal power supply voltage.

[0058] For example, the voltage generation unit (122) includes a plurality of pumping capacitors that receive an internal power supply voltage, and will selectively activate the plurality of pumping capacitors in response to the control of the control logic (130) to generate a plurality of voltages.

[0059] The generated multiple voltages can be supplied to the memory cell array (110) by the row decoder (121).

[0060] The page buffer group (123) includes first to n-th page buffers (PB1 to PBn). The first to n-th page buffers (PB1 to PBn) are each connected to a memory cell array (110) through first to n-th bit lines (BL1 to BLn). The first to n-th page buffers (PB1 to PBn) operate in response to the control of the control logic (130). Specifically, the first to n-th page buffers (PB1 to PBn) can operate in response to page buffer control signals (PBSIGNALS). For example, the first to n-th page buffers (PB1 to PBn) can temporarily store data received through the first to n-th bit lines (BL1 to BLn), or sense the voltage or current of the bit lines (BL1 to BLn) during a read or verification operation.

[0061] Specifically, during a program operation, the first to n-th page buffers (PB1 to PBn) will transmit data (DATA) received through the input / output circuit (125) to the selected memory cells through the first to n-th bit lines (BL1 to BLn) when a program voltage is applied to the selected word line. The memory cells of the selected page are programmed according to the transmitted data (DATA). During a program verification operation, the first to n-th page buffers (PB1 to PBn) read page data by sensing the voltage or current received from the selected memory cells through the first to n-th bit lines (BL1 to BLn).

[0062] When a read operation is performed, the first to n-th page buffers (PB1~PBn) read data (DATA) from the memory cells of the selected page through the first to n-th bit lines (BL1~BLn), and output the read data (DATA) to the input / output circuit (125) under the control of the column decoder (124).

[0063] During an erase operation, the first to n-th page buffers (PB1 to PBn) can float the first to n-th bit lines (BL1 to BLn) or apply an erase voltage.

[0064] The column decoder (124) can transfer data between the input / output circuit (125) and the page buffer group (123) in response to a column address (CADD). For example, the column decoder (124) can exchange data with the first to n page buffers (PB1 to PBn) through data lines (DL) or exchange data with the input / output circuit (125) through column lines (CL).

[0065] The input / output circuit (125) can transmit a command (CMD) and an address (ADDR) received from the memory controller (200 in FIG. 1) described with reference to FIG. 1 to the control logic (130), or exchange data (DATA) with the column decoder (124).

[0066] The sensing circuit (126) can generate a reference current in response to an allow bit signal (VRYBIT) during a read operation or a verify operation, and output a pass signal (PASS) or fail signal (FAIL) by comparing the sensing voltage (VPB) received from the page buffer group (123) with the reference voltage generated by the reference current.

[0067] The control logic (130) can control the peripheral circuit (120) by outputting an operation signal (OPSIG), a row address (RADD), page buffer control signals (PBSIGNALS), and an allow bit (VRYBIT) in response to a command (CMD) and an address (ADDR). For example, the control logic (130) can control the read operation of a selected memory block in response to a sub-block read command and an address. Additionally, the control logic (130) can control the erase operation of a selected sub-block included in the selected memory block in response to a sub-block erase command and an address. Additionally, the control logic (130) can determine whether the verification operation has passed or failed in response to a pass or fail signal (PASS or FAIL).

[0069] Figure 3 is a diagram showing an example of the memory cell array of Figure 2.

[0070] Referring to FIG. 2 and FIG. 3, FIG. 3 is a circuit diagram showing one of the memory blocks (BLKa) among the plurality of memory blocks (BLK1~BLKz) included in the memory cell array (110) of FIG. 2.

[0071] A first select line, word lines, and a second select line may be connected to the memory block (BLKa) and arranged in parallel with each other. For example, the word lines may be arranged in parallel between the first and second select lines. Here, the first select line may be a source select line (SSL) and the second select line may be a drain select line (DSL).

[0072] To explain more specifically, the memory block (BLKa) may include a plurality of strings connected between bit lines (BL1 to BLn) and a source line (SL). Bit lines (BL1 to BLn) may be connected to the strings individually, and the source line (SL) may be connected to the strings in common. Since the strings can be configured identically, the string (ST) connected to the first bit line (BL1) will be explained in detail as an example.

[0073] A string (ST) may include a source select transistor (SST), a plurality of memory cells (F1 to F16), and a drain select transistor (DST) connected in series between a source line (SL) and a first bit line (BL1). A single string (ST) may include at least one source select transistor (SST) and one drain select transistor (DST), and may also include more memory cells (F1 to F16) than the number shown in the drawing.

[0074] The source of the source select transistor (SST) can be connected to the source line (SL), and the drain of the drain select transistor (DST) can be connected to the first bit line (BL1). Memory cells (F1 to F16) can be connected in series between the source select transistor (SST) and the drain select transistor (DST). The gates of the source select transistors included in different strings can be connected to the source select line (SSL), the gates of the drain select transistors can be connected to the drain select line (DSL), and the gates of the memory cells (F1 to F16) can be connected to multiple word lines (WL1 to WL16). Among the memory cells included in different strings, a group of memory cells connected to the same word line can be called a physical page (PPG). Therefore, the memory block (BLKa) may contain as many physical pages as there are word lines (WL1~WL16).

[0075] A single memory cell can store 1 bit of data. This is commonly referred to as a single-level cell (SLC). In this case, a single physical page (PPG) can store one logical page (LPG) of data. One logical page (LPG) of data can contain as many data bits as the number of memory cells contained within that physical page (PPG). Alternatively, a single memory cell can store 2 or more bits of data. This is commonly referred to as a multi-level cell (MLC). In this case, a single physical page (PPG) can store 2 or more logical pages (LPG) of data.

[0076] A memory cell in which 2 bits or more of data are stored in a single memory cell is called a multi-level cell (MLC). However, as the number of bits of data stored in a single memory cell has recently increased, a multi-level cell (MLC) has come to refer to a memory cell in which 2 bits of data are stored. A memory cell in which 3 bits or more of data are stored is called a triple-level cell (TLC), and a memory cell in which 4 bits or more of data are stored is called a quadruple-level cell (QLC). In addition to this, memory cell methods in which data of multiple bits is stored are being developed, and this embodiment can be applied to a memory device (100) in which 2 bits or more of data are stored.

[0077] In another embodiment, the memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. These plurality of memory cells are arranged along the +X direction, the +Y direction, and the +Z direction.

[0079] Figure 4 is a diagram showing map data output and update between a host and a storage device.

[0080] Referring to FIG. 4, the host (300) of FIG. 4 includes a file system (310), and the storage device (50) of FIG. 4 may include a flash conversion layer (210) and a memory device (100).

[0081] The memory device (100) is physically impossible to overwrite. That is, the memory device (100) can program multiple memory cells after performing an erase operation on multiple memory cells during program operation (write after erase).

[0082] Accordingly, due to the non-overwriteable nature of the memory device (100), the memory controller (200 in FIG. 1) controlling the memory device (100) may include a flash conversion layer (210) that maps a logical block address (LBA) and a physical block address (PBA) so that a physical continuous write operation is performed on the memory device (100).

[0083] That is, by the flash conversion layer (210) mapping the physical block address (PBA) corresponding to the logical block address (LBA) to a new physical block address that is not an invalid address, the memory device (100) that cannot be overwritten can perform a continuous write operation.

[0084] In an embodiment, the flash conversion layer (210) forms a mapping relationship between a logical block address (LBA) and a physical block address (PBA) and can output the physical block address (PBA) to a memory device (100).

[0085] Afterward, when map data is updated by wear-leveling or garbage collection (GC), the flash translation layer (210) can update the mapping relationship between the logical block address (LBA) and the physical block address (PBA) based on update information (UPDATE_INF) output from the memory device (100). That is, the flash translation layer (210) can form a new mapping relationship between the logical block address (LBA) and the physical block address (PBA).

[0086] In an embodiment, the file system (310) can improve the performance of the memory device (100). Specifically, the file system (310) can perform an operation to improve the performance of the memory device (100) when the memory device (100) performs a continuous write operation.

[0087] For example, when a host (300) outputs a series of program requests to a storage device (50), the file system (310) can sequentially allocate logical block addresses (LBAs) corresponding to the series of program requests. Specifically, the file system (310) can sequentially allocate consecutive logical block addresses (LBAs) to a plurality of zones and output the consecutive logical block addresses (LBAs) to the storage device (50).

[0088] In an embodiment, the file system (310) can update the logical block addresses (LBAs) itself by sequentially allocating consecutive logical block addresses (LBAs) to a plurality of zones. Additionally, the file system (310) can perform garbage collection (GC) itself, just like the memory device (100). That is, when the logical block address (LBA) of a specific segment among the segments included in a specific zone becomes invalid, garbage collection (GC) can be performed to secure a free segment. This garbage collection (GC) of the file system (310) can be performed during idle time.

[0089] However, since garbage collection (GC) cannot be performed when the file system (310) is in a busy state, the file system (310) can overwrite a new logical block address (LBA) to a segment corresponding to an invalid logical block address (LBA). This is called slack space recycle (SSR).

[0090] That is, in foreground garbage collection rather than background garbage collection, a new logical block address (LBA) can be assigned to an invalidated segment. Here, foreground garbage collection is an operation distinct from background garbage collection, and foreground garbage collection refers to an operation performed after the file system (310) has completed the operation currently being performed. Foreground garbage collection can be performed when background garbage collection cannot be performed.

[0091] Accordingly, after the file system (310) has completed allocating logical block addresses to segments, new logical block addresses can be overwritten to invalidated segments through a foreground garbage collection (foreground GC) operation. That is, foreground garbage collection (foreground GC) is an operation that affects latency, while background garbage collection (background GC) is an operation that does not affect latency because it is performed during the idle period while the file system (310) is operating.

[0092] In the embodiment, when a new logical block address (LBA) is assigned to an invalidated segment, the memory device (100) can perform a random write operation rather than a sequential write operation. That is, because a new logical block address (LBA) is randomly assigned to multiple sections of the file system (310), a random write operation can also be performed on the memory device (100).

[0093] Accordingly, in the present invention, a method is provided in which a file system (310) overwrites a new logical block address (LBA) in a segment corresponding to a logical block address (LBA) that has been invalidated through foreground garbage collection (foreground GC), performs a continuous write operation on a memory device (100), and allocates the logical block addresses (LBAs) allocated to a plurality of zones to one zone.

[0095] Figure 5 is a diagram showing the sections of a file system and programmed memory blocks.

[0096] Referring to FIGS. 4 and FIGS. 5, FIG. 5 illustrates a plurality of zones included in the file system (310 of FIG. 4) of FIG. 4 and a plurality of memory blocks included in the memory device (100 of FIG. 4) of FIG. 4.

[0097] In FIG. 5, a plurality of zones are illustrated as zones 1 to 3 (ZONE1 to ZONE3) and memory blocks are illustrated as memory blocks 1 to 3 (BLK1 to BLK3), but a larger or smaller number of zones may be included in the file system (310 in FIG. 4), and a larger or smaller number of memory blocks may be included in the memory device (100 in FIG. 4). Each of zones 1 to 3 (ZONE1 to ZONE3) may be composed of a plurality of segments.

[0098] Furthermore, the first to third zones (ZONE1~ZONE3) are units where garbage collection (GC) is performed, each zone corresponds to a memory block, and a plurality of segments are units where programs and reads are performed, each segment may correspond to a page included in a memory block.

[0099] Referring to FIG. 5, it is assumed that the logical block addresses (LBAs) output from the host (300 in FIG. 4) are logical block addresses (LBAs) corresponding to consecutive program requests. It is also assumed that consecutive program operations are performed for each file. That is, after the data contained in the first file (FILE1) is consecutively programmed, the data contained in the second file (FILE2) and the data contained in the third file (FILE3) can be consecutively programmed.

[0100] In an embodiment, the file system (310 in FIG. 4) includes first to third zones (ZONE1 to ZONE3), and each zone may be composed of seven segments. A logical block address (LBA) may be assigned to each segment.

[0101] For example, the first to seventh logical block addresses (LBA1~LBA7) corresponding to data included in the first file (FILE1) may be assigned to the first zone (ZONE1), the eighth to fourteenth logical block addresses (LBA8~LBA14) corresponding to data included in the second file (FILE2) may be assigned to the second zone (ZONE2), and the fifteenth to twenty-first logical block addresses (LBA15~LBA21) corresponding to data included in the third file (FILE3) may be assigned to the third zone (ZONE3).

[0102] When logical block addresses (LBAs) corresponding to the data contained in each file are assigned to multiple segments, a continuous program operation, i.e., a continuous write operation, can be performed on the memory blocks contained in the memory device (100 in FIG. 4).

[0103] Specifically, the flash conversion layer (210 in FIG. 4) can assign the first to seventh logical block addresses (LBA1 to LBA7) to consecutive physical block addresses. That is, the flash conversion layer (210 in FIG. 4) can sequentially map the first to seventh logical block addresses (LBA1 to LBA7) to physical block addresses corresponding to pages included in the first memory block (BLK1).

[0104] In the same manner as above, the flash conversion layer (210 in FIG. 4) can sequentially map the 8th to 14th logical block addresses (LBA8~LBA14) to the physical block addresses of pages included in the 2nd memory block (BLK2), and sequentially map the 15th to 21st logical block addresses (LBA15~LBA21) to the physical block addresses of pages included in the 3rd memory block (BLK3).

[0105] Afterwards, when the memory device (100 in FIG. 4) receives physical block addresses from the flash conversion layer (210 in FIG. 4), a continuous program operation can be performed.

[0106] For example, data included in the first file (FILE1) can be sequentially programmed into pages included in the first memory block (BLK1), data included in the second file (FILE2) can be sequentially programmed into pages included in the second memory block (BLK2), and data included in the third file (FILE3) can be sequentially programmed into pages included in the third memory block (BLK3).

[0107] In the embodiment, since logical block addresses (LBAs) are assigned to all segments of each section of the file system (310 in FIG. 4), the method of assigning the next logical block address (LBA) may be problematic. For example, to assign the next logical block address (LBA), the file system (310 in FIG. 4) may perform garbage collection (GC).

[0109] Figure 6 is a diagram showing a page that is invalidated when a map update occurs.

[0110] Referring to FIGS. 5 and FIGS. 6, FIGS. 6 illustrates physical block addresses corresponding to pages 1 through 21 (PAGE1 through PAGE21) included in the first to third memory blocks (BLK1 through BLK3) of FIGS. 5, and logical block addresses corresponding to each of the physical block addresses.

[0111] In FIG. 6, it is assumed that the first memory block (BLK1) includes pages 1 through 7 (PAGE1~PAGE7), the second memory block (BLK2) includes pages 8 through 14 (PAGE8~PAGE14), and the third memory block (BLK3) includes pages 15 through 21 (PAGE15~PAGE21).

[0112] In an embodiment, the first to 21st logical block addresses (LBA1 to LBA21) can be mapped to the first to 21st physical block addresses (PBA1 to PBA21). That is, the first to 21st physical block addresses (PBA1 to PBA21) may each be addresses corresponding to the first to 21st pages (PAGE1 to PAGE21).

[0113] Referring to FIGS. 5 and 6, as logical block addresses (LBA1~LBA7) corresponding to data contained in the first file (FILE1), logical block addresses (LBA8~LBA14) corresponding to data contained in the second file (FILE2), and logical block addresses (LBA15~LBA21) corresponding to data contained in the third file (FILE3) are allocated consecutively by the file system (310 of FIG. 4), consecutive program operations can be performed on pages corresponding to the first to seventh physical block addresses (PBA1~PBA7), eighth to fourteenth physical block addresses (PBA8~PBA14), and fifteenth to twenty-first physical block addresses (PBA15~PBA21).

[0114] Afterwards, map data is updated by wear-leveling or garbage collection (GC), and certain pages among the pages contained in each memory block may be invalidated.

[0115] For example, by wear-leveling or garbage collection (GC), the data of the third page (PAGE3) corresponding to the third physical block address (PBA3), the data of the sixth page (PAGE6) corresponding to the sixth physical block address (PBA6), the data of the ninth page (PAGE9) corresponding to the ninth physical block address (PBA9), the data of the tenth page (PAGE10) corresponding to the tenth physical block address (PBA10), the data of the fifteenth page (PAGE15) corresponding to the fifteenth physical block address (PBA15), the data of the seventeenth page (PAGE17) corresponding to the seventeenth physical block address (PBA17), and the data of the eighteenth page (PAGE18) corresponding to the eighteenth physical block address (PBA18) may be rendered invalid.

[0116] Accordingly, the mapping relationship between the third logical block address (LBA3) and the third physical block address (PBA3), the mapping relationship between the sixth logical block address (LBA6) and the sixth physical block address (PBA6), the mapping relationship between the ninth logical block address (LBA9) and the ninth physical block address (PBA9), the mapping relationship between the tenth logical block address (LBA10) and the tenth physical block address (PBA10), the mapping relationship between the fifteenth logical block address (LBA15) and the fifteenth physical block address (PBA15), the mapping relationship between the seventeenth logical block address (LBA17) and the seventeenth physical block address (PBA17), and the mapping relationship between the eighteenth logical block address (PBA18) and the eighteenth physical block address (PBA18) may be invalidated.

[0117] In the embodiment, if the mapping relationship between the logical block address (LBA) and the physical block address (PBA) is invalidated, the segments included in each section of the file system (310 in FIG. 4) may also be invalidated.

[0118] In the embodiment, the method of assigning logical block addresses (LBAs) to segments in each section before the file system (310 in FIG. 4) performs garbage collection (GC) after each segment has been invalidated may be problematic.

[0120] Figure 7 is a diagram showing the update of each section of the file system according to the map update.

[0121] Referring to FIGS. 6 and FIGS. 7, FIGS. 7 illustrates the process of invalidating the segments of each area included in the file system (310 in FIGS. 4) after the data of the third page (PAGE3) of FIGS. 6, the data of the sixth page (PAGE6), the data of the ninth page (PAGE9), the data of the tenth page (PAGE10), the data of the fifteenth page (PAGE15), the data of the seventeenth page (PAGE17), and the data of the eighteenth page (PAGE18) of FIGS. 6 are invalidated.

[0122] In an embodiment, as map data is updated by wear-leveling or garbage collection (GC), each section of the file system (310 in FIG. 4) can be updated.

[0123] For example, as pages 3, 6, 9, 10, 15, 17, and 18 (PAGE3, PAGE6, PAGE9, PAGE10, PAGE15, PAGE17, PAGE18) of FIG. 6 become invalid, the mapping relationship between the logical block address (LBA) and the physical block address (PBA) corresponding to each page may become invalid.

[0124] In an embodiment, as the mapping relationship between the logical block address (LBA) and the physical block address (PBA) becomes invalid, the third and sixth logical block addresses (LBA3, LBA6) assigned to the first zone (ZONE1), the ninth and tenth logical block addresses (LBA9, LBA10) assigned to the second zone (ZONE2), and the fifteenth, seventeenth, and eighteenth logical block addresses (LBA15, LBA17, LBA18) assigned to the third zone (ZONE3) may become invalid.

[0125] At this time, since logical block addresses (LBA1~LBA21) have been allocated to all segments of each area included in the file system (310 in FIG. 4), there may be no segments to which logical block addresses will be allocated thereafter. Therefore, garbage collection (GC) can be performed on the file system (310 in FIG. 4) during idle time.

[0126] However, since idle time does not always exist, garbage collection (GC) may not be performed on the file system (310 in FIG. 4) for a long time. In this case, since logical block addresses cannot be assigned to the zones of the file system (310 in FIG. 4), new logical block addresses can be assigned to the segments of each zone of the file system (310 in FIG. 4) by slack space recycle (SSR).

[0128] Figure 8 is a diagram showing that a logical block address is overwritten in an invalidated segment.

[0129] Referring to FIGS. 7 and 8, FIG. 8 illustrates the allocation of new logical block addresses after the segments corresponding to the third and sixth logical block addresses (LBA3, LBA6) assigned to the first zone (ZONE1) in FIG. 7, the ninth and tenth logical block addresses (LBA9, LBA10) assigned to the second zone (ZONE2), and the fifteenth, seventeenth, and eighteenth logical block addresses (LBA15, LBA17, LBA18) assigned to the third zone (ZONE3) are respectively invalidated.

[0130] In an embodiment, even though logical block addresses (LBA1 to LBA21) are allocated to all segments of each zone included in the file system (310 in FIG. 4), no idle time occurs, so garbage collection (GC) may not be performed on the file system (310 in FIG. 4). In this case, in the idle state, the file system (310 in FIG. 4) may allocate new logical block addresses to each zone by slack space recycle (SSR) instead of garbage collection (GC).

[0131] In an embodiment, after logical block addresses corresponding to data contained in the third file (FILE3) are assigned to the third zone (ZONE3), logical block addresses corresponding to data contained in the fourth file (FILE4) can be assigned to the file system (310 in FIG. 4).

[0132] At this time, since the file system (310 in FIG. 4) is in a busy state, garbage collection (GC) cannot be performed, so an overwrite operation on a specific segment can be performed by free space recycling (SSR).

[0133] For example, since the segments corresponding to the 3rd and 6th logical block addresses (LBA3, LBA6) assigned to the 1st zone (ZONE1), the segments corresponding to the 9th and 10th logical block addresses (LBA9, LBA10) assigned to the 2nd zone (ZONE2), and the segments corresponding to the 15th, 17th, and 18th logical block addresses (LBA15, LBA17, LBA18) assigned to the 3rd zone (ZONE3) have been invalidated, logical block addresses corresponding to the data contained in the 4th file (FILE4) can be assigned to each invalidated segment.

[0134] However, since the logical block addresses corresponding to the data included in the fourth file (FILE4) are not allocated consecutively in one area, a random write operation may be performed instead of a sequential write operation. The performance of the storage device may be degraded by the random write operation. That is, the performance improvement achieved by the formation of a mapping relationship for consecutive data by the file system (310 in FIG. 4) may be reduced.

[0135] Furthermore, by forming mapping relationships for non-continuous data, additional loss may occur in the formation of the mapping relationships.

[0136] Accordingly, in the present invention, when a logical block address in each section is overwritten by slack space recycle (SSR), a method for programming data and a method for updating mapping data are provided.

[0138] Figure 9 is a diagram illustrating the program of data after the logical block address has been overwritten.

[0139] Referring to FIGS. 6, FIGS. 8, and FIGS. 9, the process of programming the data contained in the fourth file (FILE4) into a memory block contained in a memory device (100 in FIG. 4) is illustrated after the mapping relationship between the logical block address (LBA) and the physical block address (PBA) in FIG. 6 is invalidated, and after logical block addresses corresponding to the data contained in the fourth file (FILE4) are assigned to each segment that was invalidated in FIG. 8.

[0140] In FIG. 9, it is assumed that the memory device (100 in FIG. 4) includes a fourth memory block (BLK4), which is an additional memory block, in addition to the first to third memory blocks (BLK1 to BLK3). It is assumed that the additional memory block is a memory block of an over-provisioning area (OP) that is additionally included in addition to the memory blocks of the user area.

[0141] In an embodiment, even before garbage collection (GC) is performed and segments are secured because there are no remaining segments in the file system (310 in FIG. 4), logical block addresses corresponding to the data contained in the fourth file (FILE4) can be allocated by slack space recycle (SSR). Specifically, logical block addresses corresponding to the data contained in the fourth file (FILE4) can be allocated by overwriting a segment that has been invalidated with a new logical block address.

[0142] When the file system (310 in FIG. 4) overwrites the logical block addresses corresponding to the data contained in the fourth file (FILE4), the flash conversion layer (210 in FIG. 4) can convert the logical block addresses corresponding to the data contained in the fourth file (FILE4) into physical block addresses. At this time, the physical block addresses being converted may be addresses corresponding to the pages contained in the fourth memory block (BLK4).

[0143] Afterwards, when the flash conversion layer (210 in FIG. 4) outputs physical block addresses corresponding to pages included in the fourth memory block (BLK4) to the memory device (100 in FIG. 4), the memory device (100 in FIG. 4) can sequentially program data included in the fourth file (FILE4) into the pages corresponding to the physical block addresses. That is, a sequential write operation can be performed.

[0144] Consequently, since overwriting is possible in the file system (310 in FIG. 4), it is possible to overwrite logical block addresses corresponding to the data contained in the fourth file (FILE4) to the invalidated segments, but since overwriting is not possible in the memory device (100 in FIG. 4), successive write operations can be performed on the pages contained in the fourth memory block (BLK4).

[0145] However, since logical block addresses are not allocated contiguously in the segments of the file system (310 in FIG. 4), operations to allocate logical block addresses contiguously can be performed.

[0147] Figure 10 is a diagram showing the process of garbage collection being performed in a file system.

[0148] Referring to FIGS. 8 and FIGS. 10, FIGS. 10 illustrates the process in which logical block addresses corresponding to the data contained in the fourth file (FILE4) are assigned to each segment that was invalidated in FIGS. 8, and then consecutive logical block addresses are assigned to each segment by garbage collection (GC).

[0149] In an embodiment, when logical block addresses (LBA1 to LBA21) are allocated to all segments of each zone included in the file system (310 in FIG. 4), garbage collection (GC) may be performed on the file system (310 in FIG. 4) during idle time to secure free segments. Here, garbage collection (GC) may also be triggered by internal operations of the host (300 in FIG. 4).

[0150] In an embodiment, as garbage collection (GC) is performed, zones 1 through 3 (ZONE1~ZONE3) can be reset to zones X through Z (ZONE_X~ZONE_Z).

[0151] If Zones 1 through 3 (ZONE1~ZONE3) are configured as Zones X through Z (ZONE_X~ZONE_Z), consecutive logical block addresses may be allocated to Zones X through Z (ZONE_X~ZONE_Z). That is, logical block addresses corresponding to the data contained in the first through fourth files (FILE1~FILE4) may be sequentially allocated again to Zones X through Z (ZONE_X~ZONE_Z). At this time, invalidated segments may not be allocated.

[0152] For example, logical block addresses corresponding to data contained in the first file (FILE1) can be sequentially assigned to each segment of the X-zone (ZONE_X) as X1 to X5 logical block addresses (LBAX1~LBAX5).

[0153] Logical block addresses corresponding to the data contained in the second file (FILE2) can be sequentially assigned to each segment of the X-zone (ZONE_X) as X6 and X7 logical block addresses (LBAX6, LBAX7), and to each segment of the Y-zone (ZONE_Y) as Y1 to Y3 logical block addresses (LBAY1~LBAY3).

[0154] The logical block addresses corresponding to the data contained in the third file (FILE3) can be sequentially assigned to each segment of the Y-zone (ZONE_Y) as Y4 to Y7 logical block addresses (LBAY4~LBAY7).

[0155] The logical block addresses corresponding to the data contained in the fourth file (FILE4) can be assigned to each segment of the Z zone (ZONE_Z) as Z1 to Z7 logical block addresses (LBAZ1~LBAZ7).

[0156] As described above, as garbage collection (GC) is performed on the file system (310 in FIG. 4), logical block addresses corresponding to consecutive data contained in the first to fourth files (FILE1~FILE4) can be sequentially allocated to segments of zone X to zone Z (ZONE_X~ZONE_Z). Accordingly, logical block addresses corresponding to data contained in the fourth file (FILE4) can be allocated to segments of zone Z (ZONE_Z), which is a single zone.

[0157] In an embodiment, as garbage collection (GC) is performed on the file system (310 in FIG. 4), the flash translation layer (210 in FIG. 4) can also update the mapping relationship between the logical block address (LBA) and the physical block address (PBA). Additionally, as the flash translation layer (210 in FIG. 4) updates the mapping relationship, the data of the pages contained in the memory blocks of the memory device (100 in FIG. 4) can also be moved.

[0159] Figure 11 is a diagram illustrating the mapping relationships that change after garbage collection is performed on a file system.

[0160] Referring to FIGS. 10 and FIGS. 11, FIG. 11 illustrates the mapping relationship that changes after garbage collection (GC) is performed on the file system (310 in FIG. 4) in FIG. 10.

[0161] In an embodiment, when update information is received from a file system (310 in FIG. 4) as garbage collection (GC) is performed, the flash conversion layer (210 in FIG. 4) can update the mapping relationship between logical block addresses (LBA) and physical block addresses (PBA).

[0162] In an embodiment, as the flash conversion layer (210 in FIG. 4) updates the mapping relationship, the X1 to X5 logical block addresses (LBAX1 to LBAX5) corresponding to the data contained in the first file (FILE1) can form a mapping relationship with the first to fifth physical block addresses (PBA1 to PBA5) corresponding to the pages contained in the first memory block (BLK1).

[0163] The X6th and X7th logical block addresses (LBAX6, LBAX7) and Y1 to Y3rd logical block addresses (LBAY1~LBAY3) corresponding to the data included in the second file (FILE2) can each form a mapping relationship with the 6th and 7th physical block addresses (PBA6, PBA7) corresponding to the pages included in the first memory block (BLK1) and the 8th to 10th physical block addresses (PBA8~PBA10) corresponding to the pages included in the second memory block (BLK2).

[0164] The Y4 to Y7 logical block addresses (LBAY4~LBAY7) corresponding to the data included in the third file (FILE3) can each form a mapping relationship with the 11 to 14 physical block addresses (PBA11~PBA14) corresponding to the pages included in the second memory block (BLK2).

[0165] As a result, the data contained in the first to third files (FILE1~FILE3) is sequentially programmed into the pages within the first and second memory blocks (BLK1, BLK2), so that the data in the pages within the first and second memory blocks (BLK1, BLK2) can be treated as continuous data.

[0166] Additionally, as the data of the pages included in the first to third memory blocks (BLK1~BLK3) is moved, the third memory block (BLK3) can become a free block (FREE). Afterwards, new data can be programmed into the pages included in the third memory block (BLK3).

[0167] In an embodiment, as the flash conversion layer (210 in FIG. 4) updates the mapping relationship, the Z1 to Z7 logical block addresses (LBAZ1 to LBAZ7) corresponding to the data included in the fourth file (FILE4) can each form a mapping relationship with the physical block addresses corresponding to the pages included in the fourth memory block (BLK4).

[0168] As the Z1 to Z7 logical block addresses (LBAZ1~LBAZ7) form a mapping relationship with the physical block addresses corresponding to the pages included in the fourth memory block (BLK4), only the mapping relationship can be updated without moving the data of the pages included in the fourth memory block (BLK4). That is, by updating only the mapping relationship without moving the data of the pages within the fourth memory block (BLK4), the data of the pages within the fourth memory block (BLK4) can be treated as continuous data.

[0169] Therefore, data programmed into pages within a memory block can be treated as continuous data without data movement.

[0171] FIG. 12 is a drawing for explaining the operation of an electronic system according to one embodiment of the present invention.

[0172] Referring to FIG. 12, in step S1201, the host can allocate logical block addresses corresponding to continuous data for each section. In an embodiment, the host can allocate logical block addresses corresponding to continuous data sequentially for fast access to continuous data.

[0173] Specifically, the file system included in the host includes multiple zones, and each zone may be composed of multiple segments. The host may sequentially assign logical block addresses corresponding to continuous data to multiple segments.

[0174] In step S1203, the memory controller can form a mapping relationship between a logical block address and a physical block address based on a logical block address output from the host. At this time, the logical block address output from the host may be a logical block address corresponding to consecutive data.

[0175] The memory controller can output a physical block address to the memory device after establishing a mapping relationship. The memory device can program continuous data output from the host into a page corresponding to the physical block address output from the memory controller.

[0176] Afterwards, in step S1205, the memory controller can update the mapping relationship. For example, when map data is updated by wear-leveling or garbage collection (GC), the memory controller can update the mapping relationship between the logical block address and the physical block address based on the update information output from the memory device.

[0177] As the mapping relationship is updated, in step S1207, the host may invalidate segments of specific regions among the multiple regions included in the file system. That is, as the map data is updated, the segment to which the corresponding logical block address is assigned may be invalidated based on the newly formed mapping relationship.

[0178] In step S1209, the host may allocate a new logical block address to the invalidated segment. In the embodiment, garbage collection (GC) may not be performed on the file system for a long time. In this case, since free segments are not secured and a new logical block address cannot be allocated, a new logical block address may be overwritten to the invalidated segment by slack space recycle (SSR).

[0179] In step S1211, after performing garbage collection (GC), the host can output a command to the memory controller indicating that the mapping relationship has been updated by the garbage collection (GC).

[0180] Specifically, the host can perform garbage collection (GC) on its own, and the zones within the host can be reset to new zones by garbage collection (GC), excluding invalidated segments. Afterward, the host can output a command to the memory controller indicating that the mapping relationship has been updated by garbage collection (GC).

[0181] In step S1213, the memory controller may form a new mapping relationship between a logical block address and a physical block address based on a command indicating that the mapping relationship received from the host has been updated. In this case, the physical block address may be an address corresponding to a page included in a memory block of an over-provisioning area (OP) that is additionally included in addition to the memory blocks of the user area.

[0182] Therefore, a new logical block address corresponding to continuous data is mapped to a physical block address corresponding to pages within the new memory block, and continuous data can be programmed into the pages within the new memory block.

[0184] FIG. 13 is a drawing for explaining the operation of an electronic system according to one embodiment of the present invention.

[0185] Referring to FIG. 13, in step S1301, the host may enter an idle period. The idle period may be a period during which no operation is performed.

[0186] In step S1303, garbage collection (GC) may be performed on the file system contained in the host. Specifically, garbage collection (GC) may be performed on the file system so that free segments are secured in each zone of the file system. When garbage collection (GC) is performed on the file system, logical block addresses overwritten in segments invalidated by slack space recycle (SSR) may be allocated to segments of one zone.

[0187] In step S1305, the memory controller can update the mapping relationship. Specifically, as garbage collection (GC) is performed on the file system, zones within the file system are reconfigured, and logical block addresses corresponding to contiguous data can be re-assigned sequentially to the segments of the reconfigured zones.

[0188] In step S1307, garbage collection may be performed on the storage device according to the updated mapping relationship. Specifically, as logical block addresses are reallocated to each section of the file system, the memory controller may update the mapping relationship between logical block addresses and physical block addresses. Furthermore, the memory device may move data according to the updated mapping relationship.

[0189] In an embodiment, as logical block addresses overwritten in invalidated segments are assigned to segments of one area, the data corresponding to the logical block addresses assigned to one area can be treated as continuous data by updating only the mapping relationship without moving the data of the memory device.

[0191] FIG. 14 is a drawing for explaining another embodiment of the memory controller of FIG. 1.

[0192] The memory controller (1000) is connected to a host and a memory device. In response to a request from the host, the memory controller (1000) is configured to access the memory device. For example, the memory controller (1000) is configured to control the write, read, erase, and background operations of the memory device. The memory controller (1000) is configured to provide an interface between the memory device and the host. The memory controller (1000) is configured to run firmware for controlling the memory device.

[0193] Referring to FIG. 14, the memory controller (1000) may include a processor (1010), a memory buffer (1020), an error correction unit (ECC; 1030), a host interface (1040), a buffer control circuit (1050), a memory interface (1060), and a bus (1070).

[0194] The bus (1070) can be configured to provide a channel between the components of the memory controller (1000).

[0195] The processor (1010) can control the general operations of the memory controller (1000) and perform logical operations. The processor (1010) can communicate with an external host through the host interface (1040) and with a memory device through the memory interface (1060). Additionally, the processor (1010) can communicate with the memory buffer (1020) through the buffer controller (1050). The processor (1010) can control the operation of the storage device by using the memory buffer (1020) as an operating memory, cache memory, or buffer memory.

[0196] The processor (1010) can perform the function of a flash translation layer (FTL). The processor (1010) can convert a logical block address (LBA) provided by a host into a physical block address (PBA) through the flash translation layer (FTL). The flash translation layer (FTL) can receive a logical block address (LBA) as input using a mapping table and convert it into a physical block address (PBA). There are various address mapping methods of the flash translation layer depending on the mapping unit. Representative address mapping methods include the page mapping method, the block mapping method, and the hybrid mapping method.

[0197] The processor (1010) is configured to render data received from a host. For example, the processor (1010) will render data received from the host using a rendering seed. The rendered data is provided to a memory device as data to be stored and programmed into a memory cell array.

[0198] The processor (1010) can perform rendering and de-rendering by running software or firmware.

[0199] The memory buffer (1020) can be used as the operating memory, cache memory, or buffer memory of the processor (1010). The memory buffer (1020) can store codes and commands executed by the processor (1010). The memory buffer (1020) can store data processed by the processor (1010). The memory buffer (1020) may include Static RAM (SRAM) or Dynamic RAM (DRAM).

[0200] The error correction unit (1030) can perform error correction. The error correction unit (1030) can perform error correction encoding (ECC encoding) based on data to be written to a memory device through the memory interface (1060). The error correction encoded data can be transmitted to a memory device through the memory interface (1060). The error correction unit (1030) can perform error correction decoding (ECC decoding) on ​​data received from a memory device through the memory interface (1060). For example, the error correction unit (1030) can be included in the memory interface (1060) as a component of the memory interface (1060).

[0201] The host interface (1040) is configured to communicate with an external host under the control of the processor (1010). The host interface (1040) may be configured to communicate using at least one of various communication methods such as USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (Multi-Media Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0202] The buffer controller (1050) is configured to control the memory buffer (1020) under the control of the processor (1010).

[0203] The memory interface (1060) is configured to communicate with a memory device under the control of the processor (1010). The memory interface (1060) can communicate commands, addresses, and data with the memory device through a channel.

[0204] For example, the memory controller (1000) may not include a memory buffer (1020) and a buffer controller (1050).

[0205] For example, the processor (1010) can control the operation of the memory controller (1000) using codes. The processor (1010) can load codes from a non-volatile memory device (e.g., Read Only Memory) provided inside the memory controller (1000). As another example, the processor (1010) can load codes from a memory device through a memory interface (1060).

[0206] For example, the bus (1070) of the memory controller (1000) may be divided into a control bus and a data bus. The data bus may be configured to transmit data within the memory controller (1000), and the control bus may be configured to transmit control information, such as commands and addresses, within the memory controller (1000). The data bus and the control bus may be separated from each other and may not interfere with or affect each other. The data bus may be connected to a host interface (1040), a buffer controller (1050), an error correction unit (1030), and a memory interface (1060). The control bus may be connected to a host interface (1040), a processor (1010), a buffer controller (1050), a memory buffer (1020), and a memory interface (1060).

[0208] FIG. 15 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present invention is applied.

[0209] Referring to FIG. 15, the memory card system (2000) includes a memory controller (2100), a memory device (2200), and a connector (2300).

[0210] A memory controller (2100) is connected to a memory device (2200). The memory controller (2100) is configured to access the memory device (2200). For example, the memory controller (2100) is configured to control the read, write, erase, and background operations of the memory device (2200). The memory controller (2100) is configured to provide an interface between the memory device (2200) and a host. The memory controller (2100) is configured to run firmware for controlling the memory device (2200). The memory device (2200) may be implemented in the same way as the memory device (100 of FIG. 1) described with reference to FIG. 1.

[0211] For example, the memory controller (2100) may include components such as RAM (Random Access Memory), a processing unit, a host interface, a memory interface, and an error correction unit.

[0212] The memory controller (2100) can communicate with an external device through a connector (2300). The memory controller (2100) can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller (2100) is configured to communicate with an external device through at least one of various communication standards such as USB (Universal Serial Bus), MMC (Multi-Media Card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. For example, the connector (2300) may be defined by at least one of the various communication standards described above.

[0213] For example, the memory device (2200) can be implemented with various non-volatile memory devices such as EEPROM (Electrically Erasable and Programmable ROM), NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), ReRAM (Resistive RAM), FRAM (Ferroelectric RAM), STT-MRAM (spin transfer torque Magnetic RAM), etc.

[0214] The memory controller (2100) and the memory device (2200) can be integrated into a single semiconductor device to form a memory card. For example, the memory controller (2100) and the memory device (2200) can be integrated into a single semiconductor device to form a memory card such as a PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash card (CF), Smart Media card (SM, SMC), Memory Stick, Multimedia card (MMC, RS-MMC, MMCmicro, eMMC), SD card (SD, miniSD, microSD, SDHC), Universal Flash Storage (UFS), etc.

[0216] FIG. 16 is a block diagram exemplarily showing a Solid State Drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.

[0217] Referring to FIG. 16, the SSD system (3000) includes a host (3100) and an SSD (3200). The SSD (3200) exchanges signals (SIG) with the host (3100) through a signal connector (3001) and receives power (PWR) through a power connector (3002). The SSD (3200) includes an SSD controller (3210), a plurality of flash memories (3221 to 322n), an auxiliary power supply (3230), and a buffer memory (3240).

[0218] In an embodiment, the SSD controller (3210) can perform the function of the memory controller (200 of FIG. 1) described with reference to FIG. 1.

[0219] The SSD controller (3210) can control a plurality of flash memories (3221 to 322n) in response to a signal (SIG) received from the host (3100). For example, the signal (SIG) may be signals based on the interface between the host (3100) and the SSD (3200). For example, the signal (SIG) may be a signal defined by at least one of the interfaces such as USB (Universal Serial Bus), MMC (Multi-Media Card), eMMC (embedded MMC), PCI (peripheral component interconnection), PCI-E (PCI-express), ATA (Advanced Technology Attachment), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc.

[0220] The auxiliary power unit (3230) is connected to the host (3100) via a power connector (3002). The auxiliary power unit (3230) receives power (PWR) from the host (3100) and can charge. The auxiliary power unit (3230) can provide power to the SSD (3200) when power supply from the host (3100) is not smooth. For example, the auxiliary power unit (3230) may be located inside the SSD (3200) or outside the SSD (3200). For example, the auxiliary power unit (3230) may be located on the main board and provide auxiliary power to the SSD (3200).

[0221] The buffer memory (3240) operates as a buffer memory of the SSD (3200). For example, the buffer memory (3240) may temporarily store data received from the host (3100) or data received from a plurality of flash memories (3221 to 322n), or may temporarily store metadata (e.g., mapping tables) of the flash memories (3221 to 322n). The buffer memory (3240) may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc., or non-volatile memory such as FRAM, ReRAM, STT-MRAM, PRAM, etc.

[0223] FIG. 17 is a block diagram showing a user system to which a storage device according to an embodiment of the present invention is applied.

[0224] Referring to FIG. 17, the user system (4000) includes an application processor (4100), a memory module (4200), a network module (4300), a storage module (4400), and a user interface (4500).

[0225] The application processor (4100) can run components included in the user system (4000), an operating system (OS), or user programs, etc. For example, the application processor (4100) may include controllers, interfaces, graphics engines, etc. that control components included in the user system (4000). The application processor (4100) may be provided as a system-on-chip (SoC).

[0226] The memory module (4200) can operate as the main memory, operational memory, buffer memory, or cache memory of the user system (4000). The memory module (4200) may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, LPDDR3 SDRAM, etc. or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, etc. For example, the application processor (4100) and the memory module (4200) may be packaged based on POP (Package on Package) and provided as a single semiconductor package.

[0227] The network module (4300) can communicate with external devices. For example, the network module (4300) can support wireless communication such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile communication), WCDMA (wideband CDMA), CDMA-2000, TDMA (TIME Division Multiple Access), LTE (Long Term Evolution), WiMAX, WLAN, UWB, Bluetooth, Wi-Fi, etc. For example, the network module (4300) can be included in the application processor (4100).

[0228] The storage module (4400) can store data. For example, the storage module (4400) can store data received from the application processor (4100). Alternatively, the storage module (4400) can transfer data stored in the storage module (4400) to the application processor (4100). For example, the storage module (4400) can be implemented as a non-volatile semiconductor memory device such as PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), NAND flash, NOR flash, or a three-dimensional NAND flash. For example, the storage module (4400) can be provided as a removable storage medium such as a memory card or an external drive of the user system (4000).

[0229] For example, the storage module (4400) may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as the memory device described with reference to FIG. 2 and FIG. 3. The storage module (4400) may operate in the same manner as the storage device (50) described with reference to FIG. 1.

[0230] The user interface (4500) may include interfaces for inputting data or commands to the application processor (4100) or outputting data to an external device. For example, the user interface (4500) may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, etc. The user interface (4500) may include user output interfaces such as an LCD (Liquid Crystal Display), OLED (Organic Light Emitting Diode) display, AMOLED (Active Matrix OLED) display, LED, speaker, monitor, etc. Explanation of the symbols

[0231] 50: Storage device 100: Memory device 200: Memory controller 210: Flash conversion layer 300: Host 310: File system

Claims

Claim 1 An electronic system comprising: a file system configured to assign logical block addresses corresponding to continuous data to a plurality of segments included in a plurality of zones; a memory device including a plurality of memory blocks; and a memory controller configured to map the logical block addresses to physical block addresses corresponding to consecutive pages included in each of the plurality of memory blocks so that the continuous data is programmed into consecutive pages included in each of the plurality of memory blocks, wherein the file system is configured to assign new logical block addresses corresponding to the continuous data to invalid segments included in the plurality of zones, and each of the invalid segments is a segment in which a logical block address mapped to a physical block address corresponding to the invalid data has already been assigned. Claim 2 An electronic system according to claim 1, wherein the memory controller is configured to update a mapping relationship between the logical block addresses and the physical block addresses, the updated mapping relationship indicates one or more physical block addresses corresponding to invalid data, and the file system is configured to change one or more segments included in the plurality of zones into the invalid segments based on the updated mapping relationship. Claim 3 An electronic system according to claim 1, wherein when the plurality of segments are all allocated, the file system allocates the new logical block addresses to the invalid segments before garbage collection is performed on the plurality of segments. Claim 4 An electronic system according to claim 1, wherein the file system assigns the new logical block addresses to the invalid segments where the logical block addresses have already been assigned. Claim 5 An electronic system according to claim 1, wherein the memory controller maps the new logical block addresses assigned to the invalid segments to physical block addresses corresponding to consecutive pages within any one of the plurality of memory blocks. Claim 6 In claim 5, an electronic system in which any one of the plurality of memory blocks is one of the memory blocks of the over-provisioning area. Claim 7 In claim 3, when the garbage collection is performed, the file system assigns the new logical block addresses assigned to the invalid segments to the segments of any one of the plurality of zones. Claim 8 In claim 7, the file system is an electronic system that outputs mapping information updated according to the garbage collection to the memory device through the memory controller. Claim 9 An electronic system according to claim 8, wherein the memory controller controls the memory device to move the continuous data based on the updated mapping information. Claim 10 An electronic system according to claim 7, wherein when the garbage collection is performed, the memory controller maps logical block addresses assigned to segments of any one of the plurality of zones to physical block addresses corresponding to pages sequentially programmed in the memory device. Claim 11 A method of operation of an electronic system comprising a file system including a plurality of zones each including a plurality of segments, a memory device including a plurality of memory blocks, and a memory controller for controlling the memory device, the method comprising: a step of sequentially assigning logical block addresses corresponding to continuous data to the plurality of segments; a step of creating a mapping relationship between the logical block addresses and physical block addresses corresponding to continuous pages included in the plurality of memory blocks; a step of programming the continuous data to the continuous pages according to the mapping relationship; a step of updating the mapping relationship; and a step of assigning new logical block addresses corresponding to the continuous data to invalid segments among the plurality of segments when the mapping relationship is updated. Claim 12 A method of operation of an electronic system according to claim 11, wherein when the mapping relationship is updated, the segments among the plurality of segments to which the logical block addresses to which the mapping relationship is updated are invalidated and changed to the invalid segments. Claim 13 A method of operation of an electronic system according to claim 11, characterized in that, in the step of allocating the new logical block addresses corresponding to the continuous data, the new logical block addresses are allocated before garbage collection is performed on the plurality of segments when all of the plurality of segments are allocated. Claim 14 A method of operation of an electronic system according to claim 11, characterized in that, in the step of allocating the new logical block addresses corresponding to the continuous data, the new logical block addresses are overwritten on the invalid segments. Claim 15 A method of operation of an electronic system according to claim 11, further comprising the step of mapping the logical block addresses assigned to the invalid segments to physical block addresses corresponding to consecutive pages within any one of the plurality of memory blocks. Claim 16 In claim 15, a method of operation of an electronic system in which any one of the plurality of memory blocks is any one of the memory blocks of an over-provisioning area. Claim 17 A method of operation of an electronic system according to claim 13, characterized in that, by the garbage collection, the new logical block addresses assigned to the invalid segments are assigned to the segments of any one of the plurality of zones. Claim 18 A method of operation of an electronic system according to claim 17, further comprising the step of outputting mapping information updated according to the garbage collection to the memory device through the memory controller. Claim 19 A method of operation of an electronic system according to claim 18, further comprising the step of moving the continuous data within the plurality of memory blocks based on the updated mapping information. Claim 20 A method of operation of an electronic system according to claim 17, further comprising the step of mapping logical block addresses assigned to segments of any one of the plurality of zones to physical block addresses corresponding to pages sequentially programmed in the memory device when the garbage collection is performed.

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