Display device

Abstract

Embodiments of the present invention relate to a display device and provide a method for efficiently increasing the area of ​​a storage capacitor and utilizing an area overlapping with a contact hole located on an active pattern as the area of ​​a storage capacitor by using an active layer in which a semiconductor layer and a conductive layer are stacked to arrange a storage capacitor and an active pattern placed in a subpixel. In addition, since the position of the contact hole can be easily adjusted, the contact hole is not placed in an area adjacent to the driving transistor, thereby increasing the size of the driving transistor and improving the aperture ratio of the subpixel.

Description

Technology Field

[0001] Embodiments of the present invention relate to a display device. Background Technology

[0002] As the information society develops, various demands for display devices that display images are increasing, and various types of display devices, such as liquid crystal displays and organic light-emitting diode displays, are being utilized.

[0003] Among display devices, organic light-emitting display devices display images using self-emissive organic light-emitting diodes, thereby providing the advantages of fast response speed, excellent contrast ratio, and high color reproduction.

[0004] An organic light-emitting display device may include an organic light-emitting diode disposed in each subpixel and a driving transistor that supplies a driving current to the organic light-emitting diode.

[0005] To improve the driving performance of organic light-emitting diodes placed in subpixels, it is necessary to increase the size of the driving transistors placed in the subpixels. However, there are many difficulties in increasing the size of the driving transistors due to the various wiring and circuit elements placed in the subpixels. The problem to be solved

[0006] Embodiments of the present invention provide a method for increasing the size of a driving transistor that drives an organic light-emitting diode placed in a subpixel and improving the aperture ratio of the subpixel.

[0007] Embodiments of the present invention provide a method for efficiently distributing the area occupied by a storage capacitor placed in a subpixel and increasing the capacity of the storage capacitor. means of solving the problem

[0008] In one aspect, embodiments of the present invention may provide a display device comprising a display panel having a plurality of subpixels arranged therein, wherein each of the plurality of subpixels comprises a light-emitting element, a driving transistor electrically connected to the light-emitting element, a storage capacitor electrically connected to the driving transistor, and a first active pattern electrically connected to the storage capacitor.

[0009] A storage capacitor may include a first capacitor electrode, a second capacitor electrode located on the first capacitor electrode, and a third capacitor electrode located on the second capacitor electrode and having at least a portion located in an area that overlaps with the first capacitor electrode.

[0010] The first active pattern can be electrically connected to the third capacitor electrode through a first contact hole located in an area overlapping with the first capacitor electrode, and is placed on the same layer as the layer on which the second capacitor electrode is placed.

[0011] The first active pattern includes a semiconductor layer and a conductive layer disposed on at least a portion of the semiconductor layer, and at least a portion of the conductive layer can be removed in the first contact hole.

[0012] In the first contact hole, the third capacitor electrode can come into contact with the upper surface of the semiconductor layer and the side surface of the conductive layer included in the first active pattern.

[0013] In another aspect, embodiments of the present invention may provide a display device comprising a display panel having a plurality of subpixels arranged thereon, wherein each of the plurality of subpixels comprises a light-emitting element, a driving transistor electrically connected to the light-emitting element, and a storage capacitor electrically connected to the driving transistor, wherein the storage capacitor comprises a first capacitor electrode, a second capacitor electrode located on the first capacitor electrode and located in a portion of the region overlapping with the first capacitor electrode, and a third capacitor electrode located on the second capacitor electrode, with a portion located in the region overlapping with the second capacitor electrode and the remainder located in the region overlapping with the first capacitor electrode among the regions other than the region overlapping with the second capacitor electrode.

[0014] In another aspect, embodiments of the present invention may provide a display device comprising a substrate, a first capacitor electrode located on the substrate, a second capacitor electrode located on the first capacitor electrode and disposed in a portion of an area overlapping with the first capacitor electrode and electrically connected to the first capacitor electrode, and a third capacitor electrode located on the second capacitor electrode and disposed in an area overlapping with the first capacitor electrode among areas other than the area overlapping with the second capacitor electrode, wherein at least a portion thereof. Effects of the invention

[0015] According to embodiments of the present invention, by ensuring that a contact hole is not placed in an area adjacent to a driving transistor placed in a subpixel, the size of the driving transistor can be increased and the aperture ratio of the subpixel can be improved.

[0016] According to embodiments of the present invention, by utilizing the area overlapping with the contact hole located in the circuit area of ​​a subpixel as the area of ​​the storage capacitor, the area of ​​the storage capacitor can be efficiently increased and the capacity of the storage capacitor can be improved. Brief explanation of the drawing

[0017] FIG. 1 is a schematic diagram showing the configuration included in a display device according to embodiments of the present invention. FIG. 2 is a diagram showing an example of a circuit structure of a subpixel included in a display device according to embodiments of the present invention. FIG. 3 is a diagram showing an example of the arrangement structure of the light-emitting region and circuit region of a subpixel included in a display device according to embodiments of the present invention. FIG. 4 is a drawing showing an example of a specific planar structure of a circuit area of ​​a subpixel included in a display device according to embodiments of the present invention. FIG. 5 is a diagram showing an example of the structure of a storage capacitor located in the circuit area of ​​a subpixel included in a display device according to embodiments of the present invention. FIG. 6 is a diagram showing an example of a cross-sectional structure of the AA' portion in the circuit area of ​​a subpixel included in a display device according to embodiments of the present invention. FIG. 7 is a diagram showing an example of a cross-sectional structure of the BB' portion in the circuit area of ​​a subpixel included in a display device according to embodiments of the present invention. FIG. 8 is a diagram showing an example of a cross-sectional structure of the CC' portion in the circuit area of ​​a subpixel included in a display device according to embodiments of the present invention. FIG. 9 is a diagram showing an example of a cross-sectional structure of the DD' portion in the circuit area of ​​a subpixel included in a display device according to embodiments of the present invention. Specific details for implementing the invention

[0018] Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present invention, if it is determined that a detailed description of related known components or functions may obscure the essence of the present invention, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0019] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the present invention. These terms are used merely to distinguish the components from other components, and the essence, order, sequence, or number of the components are not limited by such terms.

[0020] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0021] In describing the temporal or flow relationships of components, for example, when the temporal or flow-related relationships are described using "after," "following," "next," "before," etc., cases that are not continuous may be included unless "immediately" or "directly" is used.

[0022] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0023] FIG. 1 is a schematic diagram showing the configuration included in a display device (100) according to embodiments of the present invention.

[0024] Referring to FIG. 1, the display device (100) may include a display panel (110), a gate driving circuit (120) for driving the display panel (110), a data driving circuit (130), and a controller (140), etc.

[0025] The display panel (110) may include an active area (AA) in which a plurality of subpixels (SP) are arranged, and a non-active area (NA) located outside the active area (AA).

[0026] A plurality of gate lines (GL) and a plurality of data lines (DL) may be arranged on the display panel (110). A subpixel (SP) may be located in the area where the gate line (GL) and the data line (DL) intersect.

[0027] The gate driving circuit (120) is controlled by the controller (140) and sequentially outputs scan signals to a plurality of gate lines (GL) arranged on the display panel (110) to control the driving timing of a plurality of subpixels (SP).

[0028] The gate driving circuit (120) may include one or more gate driver integrated circuits (GDICs). Depending on the driving method, the gate driving circuit (120) may be located on only one side of the display panel (110) or on both sides.

[0029] Each gate driver integrated circuit (GDIC) may be connected to a bonding pad of a display panel (110) using a Tape Automated Bonding (TAB) method or a Chip On Glass (COG) method. Alternatively, each gate driver integrated circuit (GDIC) may be implemented as a Gate In Panel (GIP) type and placed directly on the display panel (110). Alternatively, each gate driver integrated circuit (GDIC) may be integrated and placed on the display panel (110) depending on the case. Alternatively, each gate driver integrated circuit (GDIC) may be implemented using a Chip On Film (COF) method, which is mounted on a film connected to the display panel (110).

[0030] The data driving circuit (130) receives a data signal from the controller (140) and can convert the data signal into an analog data voltage (Vdata). The data driving circuit (130) outputs the data voltage (Vdata) to each data line (DL) in accordance with the timing at which a scan signal is applied through the gate line (GL), so that each subpixel (SP) expresses brightness according to the data signal.

[0031] The data driving circuit (130) may include one or more source driver integrated circuits (SDIC).

[0032] Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, etc.

[0033] Each source driver integrated circuit (SDIC) may be connected to a bonding pad of a display panel (110) using a tape automatic bonding (TAB) method or a chip on glass (COG) method. Alternatively, each source driver integrated circuit (SDIC) may be placed directly on the display panel (110). Alternatively, each source driver integrated circuit (SDIC) may be integrated and placed on the display panel (110) in some cases. Alternatively, each source driver integrated circuit (SDIC) may be implemented using a chip on film (COF) method. In this case, each source driver integrated circuit (SDIC) may be mounted on a film connected to the display panel (110) and electrically connected to the display panel (110) through wiring on the film.

[0034] The controller (140) supplies various control signals to the gate driving circuit (120) and the data driving circuit (130) and can control the operation of the gate driving circuit (120) and the data driving circuit (130).

[0035] The controller (140) may be mounted on a printed circuit board or a flexible printed circuit. The controller (140) may be electrically connected to a gate driving circuit (120) and a data driving circuit (130) through the printed circuit board or the flexible printed circuit.

[0036] The controller (140) can control the gate driving circuit (120) to output a scan signal according to the timing implemented in each frame. The controller (140) can convert image data received from an external source to a signal format used by the data driving circuit (130) and output the converted data signal to the data driving circuit (130).

[0037] The controller (140) receives various timing signals, including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE: Data Enable), a clock signal (CLK), etc., along with video data from an external source (e.g., a host system).

[0038] The controller (140) can generate various control signals using various timing signals received from the outside and output them to the gate driving circuit (120) and the data driving circuit (130).

[0039] For example, the controller (140) can output various gate control signals (GCS), including a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE), to control the gate driving circuit (120).

[0040] The gate start pulse (GSP) controls the operation start timing of one or more gate driver integrated circuits (GDICs) constituting the gate driving circuit (120). The gate shift clock (GSC) is a clock signal commonly input to one or more gate driver integrated circuits (GDICs) and controls the shift timing of the scan signal. The gate output enable signal (GOE) specifies the timing information of one or more gate driver integrated circuits (GDICs).

[0041] Additionally, the controller (140) can output various data control signals (DCS), including a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE), to control the data driving circuit (130).

[0042] The source start pulse (SSP) controls the data sampling start timing of one or more source driver integrated circuits (SDICs) constituting the data driving circuit (130). The source sampling clock (SSC) is a clock signal that controls the data sampling timing in each source driver integrated circuit (SDIC). The source output enable signal (SOE) controls the output timing of the data driving circuit (130).

[0043] The display device (100) may further include a power management integrated circuit (not shown) that supplies various voltages or currents to a display panel (110), a gate driving circuit (120), a data driving circuit (130), etc., or controls various voltages or currents to be supplied.

[0044] Each subpixel (SP) may be an area defined by the intersection of a gate line (GL) and a data line (DL), and at least one circuit element including a light-emitting element may be disposed therein.

[0045] For example, if the display device (100) is an organic light-emitting display device, an organic light-emitting diode (OLED) and several circuit elements may be arranged in a plurality of subpixels (SP). The display device (100) can control each subpixel (SP) to display brightness corresponding to image data by driving several circuit elements to control the current supplied to the organic light-emitting diode (OLED) arranged in the subpixel (SP).

[0046] FIG. 2 is a diagram showing an example of the circuit structure of a subpixel (SP) included in a display device (100) according to embodiments of the present invention.

[0047] FIG. 2 shows an example of a circuit structure of a subpixel (SP) when the display device (100) is an organic light-emitting display device, but embodiments of the present invention may be applied to other types of display devices.

[0048] Referring to FIG. 2, a light-emitting element (ED) and a driving transistor (DRT) for driving the light-emitting element (ED) may be disposed in a subpixel (SP). In addition, at least one additional circuit element may be disposed in the subpixel (SP) in addition to the light-emitting element (ED) and the driving transistor (DRT).

[0049] For example, as shown in the example in FIG. 2, a switching transistor (SWT), a sensing transistor (SENT), and a storage capacitor (Cstg) may be further placed in the subpixel (SP).

[0050] Accordingly, the example illustrated in FIG. 2 illustrates a 3T1C structure in which three thin-film transistors and one capacitor are disposed in addition to the light-emitting element (ED) in the subpixel (SP), but embodiments of the present invention are not limited thereto. Additionally, the example illustrated in FIG. 2 illustrates a case where all thin-film transistors are N-type, but depending on the case, the thin-film transistors disposed in the subpixel (SP) may be P-type.

[0051] The switching transistor (SWT) can be electrically connected between the data line (DL) and the first node (N1).

[0052] A data voltage (Vdata) can be supplied to a subpixel (SP) through a data line (DL). The first node (N1) may be the gate node of a driving transistor (DRT).

[0053] The switching transistor (SWT) can be controlled by a scan signal supplied to the gate line (GL). The switching transistor (SWT) can control the application of a data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT).

[0054] The driving transistor (DRT) can be electrically connected between the driving voltage line (DVL) and the light-emitting element (ED).

[0055] A first driving voltage (EVDD) can be supplied to a third node (N3) through a driving voltage line (DVL). The first driving voltage (EVDD) may be, for example, a high-potential driving voltage. The third node (N3) may be the drain node or source node of a driving transistor (DRT).

[0056] The driving transistor (DRT) can be controlled by the voltage applied to the first node (N1). Also, the driving transistor (DRT) can control the driving current supplied to the light-emitting element (ED).

[0057] The sensing transistor (SENT) can be electrically connected between the reference voltage line (RVL) and the second node (N2).

[0058] A reference voltage (Vref) can be supplied to the second node (N2) through the reference voltage line (RVL). The second node (N2) may be the source node or the drain node of the driving transistor (DRT).

[0059] The sensing transistor (SENT) can be controlled by a scan signal supplied to the gate line (GL). The gate line (GL) controlling the sensing transistor (SENT) may be the same as or different from the gate line (GL) controlling the switching transistor (SWT).

[0060] The sensing transistor (SENT) can control the application of a reference voltage (Vref) to the second node (N2). Additionally, the sensing transistor (SENT) can, in some cases, control the sensing of the voltage of the second node (N2) through the reference voltage line (RVL).

[0061] A storage capacitor (Cstg) can be electrically connected between a first node (N1) and a second node (N2). The storage capacitor (Cstg) can maintain a data voltage (Vdata) applied to the first node (N1) for one frame.

[0062] The light-emitting element (ED) can be electrically connected between the second node (N2) and the line to which the second driving voltage (EVSS) is supplied. The second driving voltage (EVSS) may be, for example, a low-potential driving voltage.

[0063] When a turn-on level scan signal is applied to the gate line (GL), the switching transistor (SWT) and the sensing transistor (SENT) can be turned on. A data voltage (Vdata) can be applied to the first node (N1), and a reference voltage (Vref) can be applied to the second node (N2).

[0064] The driving current supplied by the driving transistor (DRT) can be determined according to the difference between the voltage of the first node (N1) and the voltage of the second node (N2).

[0065] The light-emitting element (ED) can display brightness according to the driving current supplied through the driving transistor (DRT).

[0066] In order to improve the brightness of the subpixel (SP), it may be very important to increase the area of ​​the light-emitting region through which light emitted from the light-emitting element (ED) in the subpixel (SP) is emitted outward. In the case of a display device (100) having a back-emitting structure in which light emitted from the light-emitting element (ED) is emitted to the back surface of the substrate, the light-emitting region may be placed in an area other than the circuit region where the circuit element is placed, so it is necessary to efficiently arrange the circuit region to increase the light-emitting region.

[0067] FIG. 3 is a diagram showing an example of the arrangement structure of the light-emitting region and circuit region of a subpixel (SP) included in a display device (100) according to embodiments of the present invention.

[0068] Referring to FIG. 3, an example of a structure in which four adjacent subpixels (SP) are arranged is shown. For example, each of the four subpixels (SP) can represent a different color, and the four subpixels (SP) can form a single pixel.

[0069] A data line (DL) that supplies a data voltage (Vdata) to each of the four subpixels (SP) can be electrically connected to each of the four subpixels (SP).

[0070] A first driving voltage (EVDD) supplied through a driving voltage line (DVL) can be supplied to two or more subpixels (SP). For example, the first driving voltage (EVDD) can be supplied to a subpixel (SP) through a driving voltage line connection pattern (DVL_CP) that is electrically connected to the driving voltage line (DVL).

[0071] The reference voltage (Vref) supplied through the reference voltage line (RVL) can be supplied to two or more subpixels (SP). For example, the reference voltage (Vref) can be supplied to the subpixels (SP) through a reference voltage line connection pattern (RVL_CP) that is electrically connected to the reference voltage line (RVL).

[0072] A gate line (GL) that controls the driving timing of four subpixels (SP) can be positioned to intersect with a data line (DL). The gate line (GL) can be electrically connected to a switching transistor (SWT) and a sensing transistor (SENT) positioned in each of the four subpixels (SP).

[0073] In addition to the light-emitting region where light emitted from the light-emitting element (ED) in the four subpixels (SP) is emitted outward, there may be a circuit region where circuit elements such as thin-film transistors are placed.

[0074] A switching transistor (SWT) and a sensing transistor (SENT) may be placed in the circuit area located in the subpixel (SP). Additionally, a driving transistor (DRT) and a storage capacitor (Cstg) may be placed in the circuit area of ​​the subpixel (SP).

[0075] The luminous efficiency exhibited by the subpixel (SP) can be improved depending on the performance of the driving transistor (DRT) and the storage capacitor (Cstg) placed in the circuit area of ​​the subpixel (SP).

[0076] A display device (100) according to embodiments of the present invention provides a method to improve the aperture ratio of a subpixel (SP) and improve the luminous efficiency of a light-emitting element (ED) placed in a subpixel (SP) by a structure in which a driving transistor (DRT) and a storage capacitor (Cstg) are efficiently arranged in the circuit area of ​​a subpixel (SP).

[0077] FIG. 4 is a drawing showing an example of a specific planar structure of a circuit area of ​​a subpixel (SP) included in a display device (100) according to embodiments of the present invention.

[0078] Referring to FIG. 4, circuit elements and wiring placed in a subpixel (SP) can be placed using two or more metal layers. For example, circuit elements and wiring placed in a subpixel (SP) can be placed using a first metal layer (M1), an active layer (ACT), a second metal layer (M2), and a third metal layer (M3).

[0079] The first metal layer (M1) may, for example, be the metal layer closest to the substrate among the metal layers disposed on the substrate. Alternatively, the first metal layer (M1) may be a metal layer closer to the substrate than the active layer (ACT), the second metal layer (M2), and the third metal layer (M3).

[0080] For example, a driving voltage line (DVL), a data line (DL), and a reference voltage line (RVL) can be arranged using the first metal layer (M1). Additionally, a storage capacitor (Cstg) can be arranged using the first metal layer (M1).

[0081] Additionally, depending on the case, a repair pattern (RP) can be placed using the first metal layer (M1).

[0082] The repair pattern (RP) can be used, for example, during the repair process of the gate line (GL) using the driving voltage line connection pattern (DVL_CP) when a disconnection defect occurs in the gate line (GL).

[0083] If a disconnection failure occurs in the gate line (GL), the pixel containing the point where the gate line (GL) is disconnected can be darkened. Additionally, the driving voltage line (DVL) can be cut, and the cut driving voltage line (DVL) and the gate line (GL) can be welded. By welding the repair pattern (RP) and the driving voltage line connection pattern (DVL_CP), the scan signal supplied to the gate line (GL) can be transmitted through the cut driving voltage line (DVL), the driving voltage line connection pattern (DVL_CP), and the repair pattern (RP).

[0084] The active layer (ACT) can be located on the first metal layer (M1).

[0085] For example, the channel regions of a switching transistor (SWT), a sensing transistor (SENT), and a driving transistor (DRT) can be arranged using the active layer (ACT). Additionally, the source electrode and drain electrode of a thin-film transistor can be arranged using the active layer (ACT).

[0086] In addition, wiring or an active pattern (AP) that is electrically connected to a thin-film transistor can be arranged using the active layer (ACT).

[0087] For example, a reference voltage line connection pattern (RVL_CP) that electrically connects the reference voltage line (RVL) and the sensing transistor (SENT) using the active layer (ACT) can be placed.

[0088] Since the reference voltage line connection pattern (RVL_CP) is placed using the active layer (ACT), the reference voltage line connection pattern (RVL_CP) and the sensing transistor (SENT) can be directly connected. Therefore, a contact hole for electrical connection between the reference voltage line connection pattern (RVL_CP) and the sensing transistor (SENT) may not be required. Consequently, the number of contact holes placed in the subpixel (SP) can be reduced.

[0089] As another example, a first active pattern (AP1) may be arranged to electrically connect the switching transistor (SWT) and the storage capacitor (Cstg) using an active layer (ACT). In some cases, the first active pattern (AP1) may be considered to include at least a portion of the active layer (ACT) constituting the switching transistor (SWT).

[0090] As another example, a second active pattern (AP2) may be arranged to electrically connect the sensing transistor (SENT) and the storage capacitor (Cstg) using an active layer (ACT). In some cases, the second active pattern (AP2) may be viewed as including a part of the active layer (ACT) constituting the sensing transistor (SENT).

[0091] Additionally, a storage capacitor (Cstg) can be placed using the active layer (ACT). In this way, a reference voltage line connection pattern (RVL_CP), a first active pattern (AP1), a second active pattern (AP2), and a storage capacitor (Cstg) can be placed using the active layer (ACT). The reference voltage line connection pattern (RVL_CP), the second active pattern (AP2), and the storage capacitor (Cstg) can be placed as a single unit. A structure can be formed in which the reference voltage line connection pattern (RVL_CP), a sensing transistor (SENT), and a driving transistor (DRT) are connected using the active layer (ACT). Accordingly, the contact hole for electrical connection between the voltage line and the thin-film transistor can be reduced, and the circuit structure of the subpixel (SP) can be configured.

[0092] The active layer (ACT) can be made of a semiconductor material, for example. In this case, wiring using the active layer (ACT) can be arranged by a conductorization process.

[0093] The active layer (ACT) may, as another example, have a structure in which a metal material is stacked on a semiconductor material. Furthermore, the semiconductor material and the metal material included in the active layer (ACT) may be in direct contact. In such cases, the metal material of the active layer (ACT) may be removed from the channel region and placed in a part that constitutes wiring, etc.

[0094] The second metal layer (M2) can be located on the active layer (ACT).

[0095] For example, a gate line (GL) can be placed using the second metal layer (M2). Additionally, a driving voltage line connection pattern (DVL_CP) can be placed using the second metal layer (M2).

[0096] In addition, the gate electrode of the driving transistor (DRT) can be placed using the second metal layer (M2). A storage capacitor (Cstg) can be placed using the second metal layer (M2).

[0097] Additionally, depending on the case, an electrode connection pattern (CE_CP) that electrically connects the first metal layer (M1) and the active layer (ACT) may be arranged using the second metal layer (M2).

[0098] The third metal layer (M3) may be located on the second metal layer (M2).

[0099] For example, a pixel electrode (PXL) can be disposed using a third metal layer (M3). The pixel electrode (PXL) may be the anode electrode of a light-emitting element (ED) disposed in a subpixel (SP).

[0100] In the subpixel (SP), various types of contact holes may be arranged to electrically connect metal layers placed on different layers to each other.

[0101] For example, a plurality of contact holes (CHa) may be located in a subpixel (SP) that penetrate at least one insulating layer located between a first metal layer (M1) and a second metal layer (M2).

[0102] In addition, a plurality of contact holes (CHb) may be located in the subpixel (SP) by penetrating at least one insulating layer located between the active layer (ACT) and the second metal layer (M2).

[0103] In addition, a plurality of contact holes (CHc) may be located in the subpixel (SP) by penetrating at least one insulating layer located between the second metal layer (M2) and the third metal layer (M3).

[0104] A display device (100) according to embodiments of the present invention can minimize the number of wiring and contact holes placed in a subpixel (SP) to improve the aperture ratio of the subpixel (SP).

[0105] For example, since the switching transistor (SWT) and the sensing transistor (SENT) are driven by a single gate line (GL), the number of gate lines (GL) placed in the subpixel (SP) can be reduced.

[0106] In addition, since only the first contact hole (CH1) for connecting the switching transistor (SWT) and the storage capacitor (Cstg) and the second contact hole (CH2) for connecting the sensing transistor (SENT) and the storage capacitor (Cstg) are provided, the number of contact holes provided in the subpixel (SP) can be reduced.

[0107] In addition, since the third contact hole (CH3) for electrical connection with the pixel electrode (PXL) is located in an area overlapping with the second contact hole (CH2), the overall area where the contact holes are placed can be reduced.

[0108] In addition, the storage capacitor (Cstg) placed in the subpixel (SP) can be placed using three or more layers. Therefore, the area occupied by the storage capacitor (Cstg) in the subpixel (SP) can be efficiently placed, and the capacity of the storage capacitor (Cstg) can be increased.

[0109] FIG. 5 is a diagram showing an example of the structure of a storage capacitor (Cstg) located in the circuit area of ​​a subpixel (SP) included in a display device (100) according to embodiments of the present invention.

[0110] Referring to FIG. 5, the storage capacitor (Cstg) placed in the subpixel (SP) may include a first capacitor electrode (CE1), a second capacitor electrode (CE2), and a third capacitor electrode (CE3).

[0111] The first capacitor electrode (CE1) can be arranged using the first metal layer (M1).

[0112] A portion of the first capacitor electrode (CE1) may overlap with the driving transistor (DRT). A portion of the first capacitor electrode (CE1) may overlap with the first active pattern (AP1).

[0113] The second capacitor electrode (CE2) can be arranged using the active layer (ACT).

[0114] The second capacitor electrode (CE2) may be located on the first capacitor electrode (CE1). The second capacitor electrode (CE2) may be located in a portion of the area that overlaps with the first capacitor electrode (CE1).

[0115] The second capacitor electrode (CE2) can be electrically connected to the driving transistor (DRT). The second capacitor electrode (CE2) can be integrated with the active layer (ACT) constituting the driving transistor (DRT).

[0116] The second capacitor electrode (CE2) can be electrically connected to the second active pattern (AP2). The second capacitor electrode (CE2) can be integral with the second active pattern (AP2).

[0117] The second capacitor electrode (CE2) can be electrically connected to the first capacitor electrode (CE1) by an electrode connection pattern (CE_CP). The electrode connection pattern (CE_CP) can be arranged using a second metal layer (M2).

[0118] The third capacitor electrode (CE3) can be placed using the second metal layer (M2).

[0119] The third capacitor electrode (CE3) can be located on the second capacitor electrode (CE2).

[0120] The third capacitor electrode (CE3) may be located in at least a portion of the area overlapping with the first capacitor electrode (CE1). The third capacitor electrode (CE3) may be located in at least a portion of the area overlapping with the second capacitor electrode (CE2).

[0121] A portion of the third capacitor electrode (CE3) may overlap with the first capacitor electrode (CE1) in an area other than the area overlapping with the second capacitor electrode (CE2).

[0122] The third capacitor electrode (CE3) can be electrically connected to the gate electrode of the driving transistor (DRT). The third capacitor electrode (CE3) can be integral with the gate electrode of the driving transistor (DRT).

[0123] The third capacitor electrode (CE3) can be electrically connected to the first active pattern (AP1).

[0124] The third capacitor electrode (CE3) can be electrically connected to the first active pattern (AP1) through the first contact hole (CH1). The first contact hole (CH1) can be located in an area other than the region where the gate electrode of the third capacitor electrode (CE3) and the driving transistor (DRT) are connected.

[0125] For example, a third capacitor electrode (CE3) may be located between the first contact hole (CH1) and the driving transistor (DRT).

[0126] Since contact holes are not located in the area adjacent to the driving transistor (DRT), the size of the driving transistor (DRT) can be easily increased.

[0127] In addition, the third capacitor electrode (CE3) forms the storage capacitor (Cstg) with the second capacitor electrode (CE2), and the first capacitor electrode (CE1) forms the storage capacitor (Cstg) in an area that does not overlap with the second capacitor electrode (CE2), so the capacity of the storage capacitor (Cstg) can be increased.

[0128] In addition, the pixel electrode (PXL) can be electrically connected to the first capacitor electrode (CE1) and the second capacitor electrode (CE2) through the electrode connection pattern (CE_CP).

[0129] The pixel electrode (PXL) can be positioned using the third metal layer (M3) and can be located on the third capacitor electrode (CE3).

[0130] Therefore, the third capacitor electrode (CE3) can form the pixel electrode (PXL) and the storage capacitor (Cstg).

[0131] By using multiple layers to arrange the storage capacitor (Cstg), the area where the storage capacitor (Cstg) is arranged can be efficiently configured, and the capacity of the storage capacitor (Cstg) can be increased.

[0132] In addition, the area of ​​the storage capacitor (Cstg) can be maximized by positioning the first capacitor electrode (CE1) below the contact hole (CHb) which is positioned through the insulating layer located between the active layer (ACT) and the second metal layer (M2), such as the first contact hole (CH1).

[0133] For example, by using an active layer (ACT) in which a semiconductor material and a metal material are stacked, a first active pattern (AP1) can be arranged so that the area overlapping with the first contact hole (CH1) can be used as the area of ​​the storage capacitor (Cstg).

[0134] In addition, the metal material included in the active layer (ACT) may not be placed in the channel region of the thin-film transistor placed in the subpixel (SP).

[0135] FIG. 6 is a diagram showing an example of a cross-sectional structure of the AA' portion in the circuit area of ​​a subpixel (SP) included in a display device (100) according to embodiments of the present invention.

[0136] Referring to FIG. 6, an example of the cross-sectional structure of a driving transistor (DRT) placed in a subpixel (SP) is shown.

[0137] A first capacitor electrode (CE1) can be disposed on a substrate (SUB) using a first metal layer (M1).

[0138] A buffer layer (BUF) can be placed on the first capacitor electrode (CE1).

[0139] The active layer (ACT) can be placed on the buffer layer (BUF).

[0140] The active layer (ACT) may include, for example, a semiconductor layer (SEMI) and a conductive layer (COND) disposed on the semiconductor layer (SEMI). The conductive layer (COND) may be disposed on at least a portion of the semiconductor layer (SEMI) of the active layer (ACT).

[0141] The material constituting the semiconductor layer (SEMI) included in the active layer (ACT) may, for example, be an oxide semiconductor. The semiconductor layer (SEMI) may be an oxide of a metal such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc. Alternatively, the semiconductor layer (SEMI) may be composed of a combination of a metal such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), titanium (Ti), etc., and their oxides. Furthermore, the semiconductor layer (SEMI) may be a semiconductor material other than an oxide semiconductor, but the embodiments of the present invention are not limited thereto.

[0142] The conductive layer (COND) included in the active layer (ACT) may include, for example, any one of a metal or an alloy thereof such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), and titanium (Ti), but embodiments of the present invention are not limited thereto.

[0143] In the process of placing the active layer (ACT), for example, a conductive layer (COND) may not be placed in the channel region of the driving transistor (DRT) by a halftone exposure process.

[0144] Only the semiconductor layer (SEMI) included in the active layer (ACT) can be placed in the channel region of the driving transistor (DRT).

[0145] In the regions corresponding to the source and drain electrodes of the driving transistor (DRT), a semiconductor layer (SEMI) and a conductive layer (COND) included in the active layer (ACT) can be arranged in a stacked structure.

[0146] A gate insulation layer (GI) can be placed on the active layer (ACT).

[0147] The gate electrode of the driving transistor (DRT) can be placed on the gate insulating layer (GI).

[0148] The gate electrode of the driving transistor (DRT) may be made of a second metal layer (M2) and may be integrated with the third capacitor electrode (CE3).

[0149] A contact hole may not be located in the area adjacent to the driving transistor (DRT).

[0150] Therefore, the size of the driving transistor (DRT) can be increased. Additionally, the area adjacent to the driving transistor (DRT) can be used as the area for the storage capacitor (Cstg).

[0151] FIG. 7 is a diagram showing an example of a cross-sectional structure of the BB' portion in the circuit area of ​​a subpixel (SP) included in a display device (100) according to embodiments of the present invention.

[0152] Referring to FIG. 7, the first capacitor electrode (CE1) may be located in the region where the third capacitor electrode (CE3) and the gate electrode of the driving transistor (DRT) are connected.

[0153] The second capacitor electrode (CE2) may be located in a portion of the first capacitor electrode (CE1).

[0154] The third capacitor electrode (CE3) can be located on the second capacitor electrode (CE2).

[0155] A portion of the third capacitor electrode (CE3) is located in an area overlapping with the second capacitor electrode (CE2), and can form a storage capacitor (Cstg) with the second capacitor electrode (CE2).

[0156] Another part of the third capacitor electrode (CE3) may be located in an area overlapping with the first capacitor electrode (CE1) in an area where the second capacitor electrode (CE2) is not placed. Thus, another part of the third capacitor electrode (CE3) may form a storage capacitor (Cstg) with the first capacitor electrode (CE1).

[0157] By increasing the size of the driving transistor (DRT) and allowing the storage capacitor (Cstg) to be placed in the area where the driving transistor (DRT) and the third capacitor electrode (CE3) are connected, the capacity of the storage capacitor (Cstg) can be further increased.

[0158] In addition, by allowing the area where the third capacitor electrode (CE3) and the first active pattern (AP1) are connected to be used as an area of ​​the storage capacitor (Cstg), the capacity of the storage capacitor (Cstg) can be efficiently increased.

[0159] FIG. 8 is a diagram showing an example of a cross-sectional structure of the CC' portion in the circuit area of ​​a subpixel (SP) included in a display device (100) according to embodiments of the present invention.

[0160] Referring to FIG. 8, a buffer layer (BUF) may be disposed on the first capacitor electrode (CE1). A first active pattern (AP1) may be disposed on the buffer layer (BUF).

[0161] The first active pattern (AP1) may include a semiconductor layer (SEMI).

[0162] The first active pattern (AP1) may include a conductive layer (COND) disposed in a portion of the semiconductor layer (SEMI).

[0163] The conductive layer (COND) included in the first active pattern (AP1) may be removed in at least a portion of the area corresponding to the first contact hole (CH1). A portion of the conductive layer (COND) included in the first active pattern (AP1) may be removed through a process of placing the first contact hole (CH1).

[0164] For example, an active layer (ACT) in which a semiconductor layer (SEMI) and a conductive layer (COND) are stacked can be placed on a buffer layer (BUF). A gate insulating layer (GI) can be placed on the active layer (ACT).

[0165] A process of etching the gate insulating layer (GI) may be performed to place the first contact hole (CH1). The process of etching the gate insulating layer (GI) may be a dry etching process, but is not limited thereto.

[0166] In the process of etching the gate insulating layer (GI), the conductive layer (COND) disposed on the semiconductor layer (SEMI) of the active layer (ACT) can be removed. And, in the process of etching the gate insulating layer (GI), the semiconductor layer (SEMI) of the active layer (ACT) may remain without being removed.

[0167] Since the semiconductor layer (SEMI) of the active layer (ACT) remains, it is possible to prevent damage to the buffer layer (BUF) located below the active layer (ACT) during the etching process of the gate insulation layer (GI).

[0168] Therefore, the third capacitor electrode (CE3) placed on the gate insulation layer (GI) can be prevented from penetrating below the buffer layer (BUF), so that the first capacitor electrode (CE1) can be placed below the first contact hole (CH1).

[0169] The conductive layer (COND) included in the active layer (ACT) may remain in an area other than the first contact hole (CH1). Additionally, the conductive layer (COND) may be positioned along the outer edge of the first contact hole (CH1). Furthermore, the conductive layer (COND) may protrude toward the first contact hole (CH1) from beneath the gate insulating layer (GI).

[0170] Through the aforementioned process, a first active pattern (ACT1) can be disposed having a conductive layer (COND) disposed on a semiconductor layer (SEMI) and a portion of the semiconductor layer (SEMI).

[0171] The second metal layer (M2) constituting the third capacitor electrode (CE3) can be placed in the gate insulation layer (GI) and the first contact hole (CH1).

[0172] The third capacitor electrode (CE3) may, for example, contact the upper surface of the semiconductor layer (SEMI) included in the first active pattern (AP1) at the first contact hole (CH1). The third capacitor electrode (CE3) may, for example, contact the side surface of the conductive layer (COND) included in the first active pattern (AP1) at the first contact hole (CH1). Additionally, depending on the case, the third capacitor electrode (CE3) may contact the upper surface of the conductive layer (COND) included in the first active pattern (AP1) at the first contact hole (CH1).

[0173] Since the third capacitor electrode (CE3) is in contact with the conductive layer (COND) of the first active pattern (AP1), the third capacitor electrode (CE3) and the first active pattern (AP1) can be electrically connected.

[0174] Therefore, the third capacitor electrode (CE3) and the switching transistor (SWT) can be electrically connected. The data voltage (Vdata) supplied through the data line (DL) and the switching transistor (SWT) can be applied to the gate electrode of the third capacitor electrode (CE3) and the driving transistor (DRT).

[0175] A first capacitor electrode (CE1) may be located below the first contact hole (CH1).

[0176] The third capacitor electrode (CE3) can be configured with the first capacitor electrode (CE1) and the storage capacitor (Cstg) in the area where the first contact hole (CH1) is placed for electrical connection with the first active pattern (AP1).

[0177] Embodiments of the present invention can efficiently increase the area where a storage capacitor (Cstg) can be placed in a subpixel (SP) and improve the capacity of the storage capacitor (Cstg).

[0178] In addition, embodiments of the present invention can prevent the area of ​​the storage capacitor (Cstg) from being reduced due to the contact hole by minimizing the area occupied by the contact hole in the subpixel (SP).

[0179] FIG. 9 is a diagram showing an example of a cross-sectional structure of the DD' portion in the circuit area of ​​a subpixel (SP) included in a display device (100) according to embodiments of the present invention.

[0180] Referring to FIG. 9, the first capacitor electrode (CE1) and the second capacitor electrode (CE2) can be electrically connected through the second contact hole (CH2).

[0181] The second contact hole (CH2) may be located on an area overlapping with the first capacitor electrode (CE1).

[0182] The second contact hole (CH2) may be located on the side of the storage capacitor (Cstg) where the first contact hole (CH1) is located. The second capacitor electrode (CE2) constituting the storage capacitor (Cstg) may be located between the second contact hole (CH2) and the driving transistor (DRT).

[0183] The second contact hole (CH2) may include a contact hole (CHa) disposed through at least one insulating layer located between the first metal layer (M1) and the second metal layer (M2). Additionally, the second contact hole (CH2) may include a contact hole (CHb) disposed through at least one insulating layer located between the active layer (ACT) and the second metal layer (M2).

[0184] For example, a buffer layer (BUF) may be placed on the first capacitor electrode (CE1).

[0185] An active layer (ACT) may be disposed in a portion of the buffer layer (BUF). The active layer (ACT) may include a semiconductor layer (SEMI) and a conductive layer (COND) disposed on the semiconductor layer (SEMI).

[0186] A portion of the buffer layer (BUF) and the gate insulation layer (GI) disposed on the first capacitor electrode (CE1) can be removed by an etching process. Additionally, a portion of the gate insulation layer (GI) disposed on the active layer (ACT) can be removed by an etching process.

[0187] A portion of the gate insulation layer (GI) disposed on the active layer (ACT) is removed, and a portion of the conductive layer (COND) included in the active layer (ACT) may be removed.

[0188] An active layer (ACT) from which a portion of the conductive layer (COND) disposed on the semiconductor layer (SEMI) has been removed can become a second active pattern (AP2).

[0189] A portion of the conductive layer (COND) included in the second active pattern (AP2) may protrude toward the outside of the gate insulating layer (GI).

[0190] An electrode connection pattern (CE_CP) placed in the second contact hole (CH2) can come into contact with the upper surface of the first capacitor electrode (CE1). Additionally, the electrode connection pattern (CE_CP) can come into contact with the upper surface of the semiconductor layer (SEMI) and the side surface of the conductive layer (COND) included in the second active pattern (AP2).

[0191] Since the electrode connection pattern (CE_CP) contacts the conductive layer (COND) included in the second active pattern (AP2), the second active pattern (AP2) and the first capacitor electrode (CE1) can be electrically connected. Also, since the second active pattern (AP2) is integral with the second capacitor electrode (CE2), the second capacitor electrode (CE2) and the first capacitor electrode (CE1) can be electrically connected.

[0192] Additionally, a third contact hole (CH3) may be placed in an area that overlaps with at least a portion of the second contact hole (CH2).

[0193] The third contact hole (CH3) may, for example, be a contact hole (CHc) disposed penetrating at least one insulating layer located between the second metal layer (M2) and the third metal layer (M3). The third contact hole (CH3) may be disposed in a protective layer (PAS) and an overcoat layer (OC) disposed on the second metal layer (M2).

[0194] Through the third contact hole (CH3), the pixel electrode (PXL) and the electrode connection pattern (CE_CP) can be electrically connected.

[0195] Accordingly, the pixel electrode (PXL) can be electrically connected to the storage capacitor (Cstg), sensing transistor (SENT), and driving transistor (DRT) placed in the subpixel (SP) through the third contact hole (CH3).

[0196] By minimizing the number of contact holes placed in the subpixel (SP), the area of ​​the storage capacitor (Cstg) is prevented from being reduced, and the aperture ratio of the subpixel (SP) can be improved.

[0197] According to the embodiments of the present invention described above, by arranging the storage capacitor (Cstg) placed in the subpixel (SP) using three or more layers, the area of ​​the storage capacitor (Cstg) can be efficiently arranged and the capacity of the storage capacitor (Cstg) can be increased.

[0198] In addition, by utilizing an active layer (ACT) in which a semiconductor layer (SEMI) and a conductive layer (COND) are stacked, and placing an active pattern (AP) that is placed on a subpixel (SP), the area overlapping with the contact hole placed on the active pattern (AP) can be utilized as the area of ​​a storage capacitor (Cstg).

[0199] In addition, since the area overlapping with the contact hole can be used as the area of ​​the storage capacitor (Cstg), the position of the contact hole can be easily adjusted so that the contact hole is not located in an area adjacent to the driving transistor (DRT).

[0200] Therefore, the size of the driving transistor (DRT) placed in the subpixel (SP) and the capacity of the storage capacitor (Cstg) can be efficiently increased, and the aperture ratio of the subpixel (SP) can be improved.

[0201] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Furthermore, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and thus the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0202] 100: Display device 110: Display panel 120: Gate driving circuit 130: Data driving circuit 140: Controller

Claims

Claim 1 A display device comprising a display panel having a plurality of subpixels arranged thereon, wherein each of the plurality of subpixels comprises: a light-emitting element; a driving transistor electrically connected to the light-emitting element; a storage capacitor electrically connected to the driving transistor; and a first active pattern electrically connected to the storage capacitor, wherein the storage capacitor comprises: a first capacitor electrode; a second capacitor electrode located on the first capacitor electrode; and a third capacitor electrode located on the second capacitor electrode, wherein at least a portion thereof is located in an area overlapping with the first capacitor electrode, and the first active pattern is arranged on the same layer as the layer on which the second capacitor electrode is arranged and is electrically connected to the third capacitor electrode through a first contact hole located in an area overlapping with the first capacitor electrode. Claim 2 A display device according to claim 1, wherein the first active pattern comprises a semiconductor layer and a conductive layer disposed in at least a portion of the semiconductor layer, and at least a portion of the conductive layer is removed in the first contact hole. Claim 3 In paragraph 2, the display device wherein the third capacitor electrode in the first contact hole contacts the upper surface of the semiconductor layer included in the first active pattern and the side surface of the conductive layer. Claim 4 A display device according to claim 1, wherein a portion of the third capacitor electrode is located in the region overlapping with the first capacitor electrode among the regions other than the region overlapping with the second capacitor electrode. Claim 5 In claim 1, the third capacitor electrode is a display device connected to the gate electrode of the driving transistor. Claim 6 In claim 5, the display device wherein the first contact hole is located in an area other than the region where the third capacitor electrode and the gate electrode of the driving transistor are connected. Claim 7 In claim 1, the second capacitor electrode comprises a semiconductor layer and a conductive layer disposed over the entire area of ​​the semiconductor layer, forming a display device. Claim 8 In claim 1, the first capacitor electrode is a display device electrically connected to the second capacitor electrode. Claim 9 A display device according to claim 1, wherein each of the plurality of subpixels comprises: a second active pattern disposed on the same layer as the layer on which the second capacitor electrode is disposed and connected to the second capacitor electrode; and an electrode connection pattern disposed on the same layer as the layer on which the third capacitor electrode is disposed and electrically connected to the first capacitor electrode and the second active pattern through a second contact hole located in an area overlapping with the first capacitor electrode. Claim 10 A display device according to claim 9, wherein the second active pattern comprises a semiconductor layer and a conductive layer disposed in at least a portion of the semiconductor layer, and at least a portion of the conductive layer is removed in the second contact hole. Claim 11 In claim 10, the electrode connection pattern in the second contact hole contacts the upper surface of the semiconductor layer included in the second active pattern and the side surface of the conductive layer in a display device. Claim 12 In claim 9, the electrode connection pattern is a display device electrically connected to the light-emitting element through a third contact hole that overlaps with at least a portion of the second contact hole. Claim 13 In claim 9, the second capacitor electrode is a display device located between the second contact hole and the driving transistor. Claim 14 A display device comprising a display panel having a plurality of subpixels arranged thereon, wherein each of the plurality of subpixels includes: a light-emitting element; a driving transistor electrically connected to the light-emitting element; and a storage capacitor electrically connected to the driving transistor, wherein the storage capacitor includes: a first capacitor electrode; a second capacitor electrode located on the first capacitor electrode and located in a portion of an area overlapping with the first capacitor electrode; and a third capacitor electrode located on the second capacitor electrode, wherein a portion thereof is located in an area overlapping with the second capacitor electrode and the remainder thereof is located in an area overlapping with the first capacitor electrode among areas other than the area overlapping with the second capacitor electrode, and includes at least one contact hole located in an area overlapping with the first capacitor electrode and an area overlapping with the third capacitor electrode, and an active pattern arranged in an area including an area overlapping with the at least one contact hole, arranged in the same layer as the layer on which the second capacitor electrode is arranged. Claim 15 delete Claim 16 In claim 14, the second capacitor electrode is a display device located between the at least one contact hole and the driving transistor. Claim 17 delete Claim 18 In claim 14, the active pattern comprises a semiconductor layer disposed entirely in the at least one contact hole and a conductive layer disposed along the outer edge of the at least one contact hole on the semiconductor layer, forming a display device. Claim 19 A display device comprising: a substrate; a first capacitor electrode located on the substrate; a second capacitor electrode located on the first capacitor electrode and disposed in a portion of an area overlapping with the first capacitor electrode and electrically connected to the first capacitor electrode; and a third capacitor electrode located on the second capacitor electrode, wherein at least a portion thereof is disposed in an area overlapping with the first capacitor electrode among areas other than the area overlapping with the second capacitor electrode, and comprises at least one contact hole located in an area overlapping with the first capacitor electrode and an area overlapping with the third capacitor electrode, and comprises an active pattern disposed in the same layer as the layer on which the second capacitor electrode is disposed and disposed in an area including an area overlapping with the at least one contact hole, wherein the active pattern comprises a semiconductor layer and a conductive layer disposed in at least a portion of the semiconductor layer, and at least a portion of the conductive layer is removed at the at least one contact hole. Claim 20 delete

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