High Density Capacitor And Manufacturing Method Therefor

Abstract

A high-density capacitor and a method for manufacturing the same are disclosed. According to one aspect of the present disclosure, a high-density capacitor is provided, comprising a MOS capacitor, wherein the MOS capacitor comprises a silicon layer having a dopant concentration of at least 1 × 10²⁰ cm⁻³; a first dielectric layer formed on top of the silicon layer; and a first metal layer formed on top of the first dielectric layer.

Description

Technology Field

[0001] The present disclosure relates to a high-density capacitor and a method for manufacturing the same. More specifically, it relates to a high-density on-chip capacitor using a silicon photonics chip manufacturing process and a method for manufacturing the same. Background Technology

[0002] The following description merely provides background information related to the present embodiment and does not constitute prior art.

[0003] Silicon photonics technology is a technology that integrates various photonic devices into a single chip using commercial CMOS (complementary metal-oxide-semiconductor) semiconductor processes. By mass-producing devices for optical communication, silicon photonics technology enables the reduction of costs, miniaturization, and increased capacity of optical communication modules. In particular, silicon photonics optical transmitters and silicon photonics optical receivers are being considered as key components to cope with the exponentially increasing data center traffic and communication traffic.

[0004] In order for these silicon photonics devices to achieve electrical DC coupling or electrical AC coupling with the outside of the chip, high-density on-chip capacitors with high capacitance per unit area are required.

[0005] One of the metal-insulator-metal capacitor (MIM) structures for increasing the integration density of conventional on-chip capacitors is disclosed in US2009 / 0200638 A1, which utilizes a high-k material with a high dielectric constant as the dielectric material or minimizes the distance between metal layers. Such a structure has a distance between metal layers of tens of nanometers. However, capacitors with a distance between metal layers of tens of nanometers require high-end semiconductor processes, making them difficult to apply to silicon photonic devices.

[0006] In contrast, there is a method for manufacturing MIM capacitors with a metal layer spacing of 1 micrometer. Such MIM capacitors can be manufactured using the production process of silicon photonic devices, but a large area is required to achieve capacitance at the picoFrad level.

[0007] Another on-chip capacitor is the one disclosed in US2010 / 0226166 A1, which utilizes the MOS structure of a metal-oxide-semiconductor field effect transistor (MOSFET) device. However, MOS capacitors are difficult to implement in the manufacturing process of silicon photonic devices.

[0008] Accordingly, an on-chip capacitor is required that utilizes the production process of silicon photonics devices but has high capacitance per unit area. The problem to be solved

[0009] One objective of the present disclosure is to provide an on-chip capacitor with high capacitance per unit area.

[0010] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0011] According to one aspect of the present disclosure, a MOS capacitor is included, wherein the MOS capacitor has a dopant concentration of at least 1×10 20 cm -3 A high-density capacitor is provided, comprising: a silicon layer; a first dielectric layer formed on top of the silicon layer; and a first metal layer formed on top of the first dielectric layer.

[0012] According to another aspect of the present disclosure, a method for manufacturing a high-density capacitor comprises, wherein the high-density capacitor includes a MOS capacitor, and the method for manufacturing the MOS capacitor comprises a silicon layer of at least 1×10 20 cm -3 A manufacturing method is provided that includes the process of doping to have a dopant concentration, forming a first dielectric layer on the upper layer of a silicon layer, and forming a first metal layer on the upper layer of the first dielectric layer. Effects of the invention

[0013] According to an embodiment of the present disclosure, an on-chip capacitor with high capacitance per unit area can be provided by including a MOS capacitor comprising silicon doped at a high concentration.

[0014] The effects of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art from the description below. Brief explanation of the drawing

[0015] FIG. 1 is a cross-sectional view illustrating a MOS capacitor according to one embodiment of the present disclosure. FIG. 2 is a cross-sectional view illustrating a high-density capacitor according to one embodiment of the present disclosure. FIG. 3 is a cross-sectional view illustrating a silicon photonics chip according to one embodiment of the present disclosure. FIG. 4a is a graph showing the S11 parameters of a silicon optical modulator according to one embodiment of the present disclosure. FIG. 4b is a graph showing the S21 parameters of a silicon optical modulator according to one embodiment of the present disclosure. Specific details for implementing the invention

[0016] Some embodiments of the present disclosure are described in detail below with reference to exemplary drawings. It should be noted that in assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions could obscure the essence of the present disclosure, such detailed description is omitted.

[0017] In describing the components of the embodiments according to the present disclosure, symbols such as first, second, i), ii), a), b), etc., may be used. These symbols are intended only to distinguish the components from other components, and the essence, order, or sequence of the components is not limited by the symbols. When a part in the specification is described as 'comprising' or 'having' a component, this means that, unless explicitly stated otherwise, it does not exclude other components but may include additional components.

[0018] The detailed description set forth below, together with the accompanying drawings, is intended to describe exemplary embodiments of the present disclosure and is not intended to represent the only embodiment in which the present disclosure may be practiced.

[0019] In this specification, when a part such as a layer, film, region, or plate is described as being above or on top of another part, this includes not only cases where it is directly above the other part but also cases where the other part is located in between. Conversely, when a part is described as being directly above, it means that no other part is located in between. Furthermore, when a part is described as being above or below another part, it refers to being located above or below in the direction indicated in the drawing, and does not necessarily refer to being above or below in a direction perpendicular to the ground.

[0020] FIG. 1 is a cross-sectional view illustrating a MOS capacitor according to one embodiment of the present disclosure.

[0021] Referring to FIG. 1, a MOS capacitor (metal-oxide-semiconductor capacitor, 10) includes a silicon layer (100), a first dielectric layer (110), and a first metal layer (120).

[0022] The silicon layer (100) comprises doped silicon. To operate as a capacitor, the silicon layer (100) must have low resistance. The silicon layer (100) may comprise a high concentration of dopant to have low resistance. That is, the silicon layer (100) may comprise silicon doped to a high concentration. According to one embodiment of the present disclosure, the doping concentration of the silicon layer (100) is 1×10 20 cm -3 It may be. According to another embodiment, the doping concentration of the silicon layer (100) is 1×10 20 cm -3 It can be higher.

[0023] A first dielectric layer (110) is formed on the upper layer of a silicon layer (100). The first dielectric layer (110) comprises a dielectric material. The first dielectric layer (110) may comprise an oxide. For example, the first dielectric layer (110) may comprise silicon oxide (SiO2).

[0024] The first dielectric layer (110) may have a predetermined thickness. The thickness of the first dielectric layer (110) may be, for example, 500 nm to 800 nm.

[0025] The first metal layer (120) is formed on the upper layer of the silicon layer (100) and the first dielectric layer (110). That is, the first dielectric layer (110) is formed between the first metal layer (120) and the silicon layer (100). The first metal layer (120) includes a metal having conductivity. The metal included in the first metal layer (120) may have low resistance.

[0026] The silicon layer (100) and the first metal layer (120) may have the same area. Alternatively, the area of ​​the silicon layer (100) and the area of ​​the first metal layer (120) may be different. The silicon layer (100) and the first metal layer (120) may be formed to be parallel. The silicon layer (100) and the first metal layer (120) may each be connected to a different power source. Alternatively, the first metal layer (120) may be connected to a power source, and the silicon layer (100) may be grounded.

[0027] Due to the first dielectric layer (110) existing between the silicon layer (100) and the first metal layer (120), no current flows between the silicon layer (100) and the first metal layer (120). That is, electric charge is accumulated in the silicon layer (100) and the first metal layer (120), and can function as a capacitor.

[0028] Capacitance of MOS capacitor (10) ) is equal to mathematical formula 1.

[0029]

[0030] Here, is relative permittivity, vacuum permittivity, is the area of ​​the MOS capacitor (10), is the distance between the silicon layer (100) and the first metal layer (120), that is, the thickness of the first dielectric layer (110).

[0031] FIG. 2 is a cross-sectional view illustrating a high-density capacitor according to one embodiment of the present disclosure.

[0032] Referring to FIG. 2, the high-density capacitor (30) may include a MOS capacitor (10) and a MIM capacitor (metal-insulator-metal capacitor, 20).

[0033] The MOS capacitor (10) includes a silicon layer (100), a first dielectric layer (110), and a first metal layer (120). The MOS capacitor (10) is the same MOS capacitor as shown in FIG. 1.

[0034] The MIM capacitor (20) includes a first metal layer (120), a second dielectric layer (200), and a second metal layer (210).

[0035] The first metal layer (120) is formed on the upper layer of the first dielectric layer (110). That is, the first dielectric layer (110) is formed between the first metal layer (120) and the silicon layer (100). The first metal layer (120) includes a conductive metal. The metal included in the first metal layer (120) may be a metal with low resistance.

[0036] According to one embodiment of the present disclosure, the first metal layer of the MIM capacitor (20) may be the same metal layer as the first metal layer of the MOS capacitor (10).

[0037] A second dielectric layer (200) is formed on the upper layer of the first metal layer (120). The second dielectric layer (200) includes a dielectric material. The second dielectric layer (200) may include an oxide. For example, the second dielectric layer (200) may include silicon dioxide (SiO2). As another example, the second dielectric layer (200) may include the same material as the first dielectric layer (110). In other words, the first dielectric layer (110) and the second dielectric layer (200) may have the same composition.

[0038] The second dielectric layer (200) may have a predetermined thickness. The thickness of the second dielectric layer (200) may be, for example, 1 μm to 1.5 μm.

[0039] The second metal layer (210) is formed on the upper layer of the second dielectric layer (200). That is, the second dielectric layer (200) is formed between the first metal layer (120) and the second metal layer (210). The second metal layer (210) includes a conductive metal. The metal included in the second metal layer (210) may be a metal with low resistance. The metal included in the second metal layer (210) may be the same material as the metal included in the first metal layer (120). In other words, the first metal layer (120) and the second metal layer (210) may differ only in shape and position.

[0040] The first metal layer (120) and the second metal layer (210) may have the same area. Alternatively, the areas of the first metal layer (120) and the second metal layer (210) may differ from each other. The first metal layer (120) and the second metal layer (210) may each be connected to different power sources. Alternatively, the first metal layer (120) may be connected to a power source, and the second metal layer (210) may be grounded.

[0041] Capacitance of MIM capacitor (20) ) is equal to mathematical formula 2.

[0042]

[0043] Here, is relative permittivity, vacuum permittivity, is the area of ​​the MIM capacitor (20), This refers to the distance between the first metal layer (120) and the second metal layer (210), that is, the thickness of the second dielectric layer (200).

[0044] According to one embodiment of the present disclosure, the first dielectric layer (110) and the second dielectric layer (200) may be composed of the same material. That is, the relative permittivity of the MIM capacitor (20) and the MOS capacitor (10) may be the same.

[0045] The areas of the MIM capacitor (20) and the MOS capacitor (10) may be the same. For example, the MOS capacitor (10) and the MIM capacitor (20) may be formed in an area allocated for capacitors in a silicon photonics chip. In this case, the capacitance of the high-density capacitor (30) including the MIM capacitor (20) and the MOS capacitor (10) ) is equal to mathematical formula 3.

[0046]

[0047] According to one embodiment of the present disclosure, silver It can be about twice that. For example, is 500 nm, and The capacitance can be 1.0 μm. In this case, the capacitance of the high-density capacitor (30) can be about three times the capacitance of the MIM capacitor (20).

[0048] That is, by using a high-density capacitor (30) according to one embodiment of the present disclosure, the capacitance per area can be increased by about 3 times compared to a MIM capacitor (20).

[0049] FIG. 3 is a cross-sectional view illustrating a silicon photonics chip according to one embodiment of the present disclosure. The silicon photonics chip illustrated in FIG. 3 utilizes the high-density capacitor (30) of FIG. 2 as a bypass capacitor.

[0050] Referring to FIG. 3, a silicon photonics chip (40) may include a substrate (300), a buried oxide layer (310), a high-density capacitor (30), a first metal layer (120), a second metal layer (210), and a silicon optical modulator (320).

[0051] The substrate (300) includes a semiconductor material. The semiconductor material may be at least one of silicon (Si), sapphire, gallium nitride (GaN), and gallium oxide (Ga2O3), but is not necessarily limited to these and may be various materials.

[0052] The substrate (300) may have a single crystal structure. Here, a single crystal structure refers to a structure in which the entire object is a single crystal, that is, a structure in which it is a single grain. In a single crystal structure, the crystallographic direction and structure are identical at any point on the object.

[0053] The substrate (300) may be composed of a material with high purity. For example, it may be made of silicon with 11N (eleven-nine) purity. 11N means a purity of 99.999999999%.

[0054] The substrate (300) may include a dopant. The dopant may be at least one element selected from boron (B), aluminum (Al), gallium (Ga), phosphorus (P), and arsenic (As).

[0055] A buried oxide layer (310) is formed on the upper layer of the substrate (300). The buried oxide layer (310) contains oxide. The buried oxide layer (310) may contain silicon oxide. By the buried oxide layer (310), the substrate (300) and the high-density capacitor (30), and the substrate (300) and the silicon optical modulator (320) are electrically insulated.

[0056] The high-density capacitor (30) and the silicon optical modulator (320) may be formed on the upper layer of the buried oxide layer (310). The high-density capacitor (30) and the silicon optical modulator (320) may be formed spaced apart from each other. In other words, the high-density capacitor (30) and the silicon optical modulator (320) may not be in contact.

[0057] The first metal layer (120) can be formed on the upper layer of the silicon optical modulator (320).

[0058] The silicon optical modulator (320) may be connected to the first metal layer (120). The silicon optical modulator (320) may be connected to the first metal layer (120) using a conductor. That is, the silicon optical modulator (320) and the first metal layer (120) may be electrically connected.

[0059] The first metal layer (120) and the second metal layer (210) may be connected. The first metal layer (120) and the second metal layer (210) may be connected using a conductor. In other words, the first metal layer (120) and the second metal layer (210) may be electrically connected.

[0060] The first metal layer (120) and the second metal layer (210) may be discontinuous layers. That is, the first metal layer (120) and the second metal layer (210) may each include a plurality of separated regions.

[0061] Among the components illustrated in FIG. 3, the high-density capacitor (30), the first metal layer (120), the second metal layer (210), and the silicon optical modulator (320) may be formed by being embedded in the first dielectric layer (110). That is, the high-density capacitor (30), the first metal layer (120), the second metal layer (210), and the silicon optical modulator (320) may be formed inside the first dielectric layer (110). Here, the second dielectric layer (200) included in the high-density capacitor (30) may be a part of the first dielectric layer (110).

[0062] Figures 4a and 4b are graphs showing the S parameters of a silicon optical modulator.

[0063] FIG. 4a is a graph showing the S11 parameters of a silicon optical modulator according to one embodiment of the present disclosure.

[0064] FIG. 4b is a graph showing the S21 parameters of a silicon optical modulator according to one embodiment of the present disclosure.

[0065] Figures 4a and 4b are graphs showing the S11 and S21 parameters when power is supplied to a silicon optical modulator using wire bonding with a wire bonding inductance of 400 pH.

[0066] Referring to FIGS. 4a and 4b, a silicon photonics chip without a high-density capacitor (30) has a silicon photomodulator with an S11 parameter exceeding 10 dB (400). Additionally, the bandwidth is approximately 25 GHz when the S21 parameter is 6 dB (410).

[0067] However, the silicon photomodulator (320) of the silicon photonics chip (40) including the high-density capacitor (30) has a maximum value of S11 parameter of 10 dB or less (420), and the bandwidth when the S21 parameter is 6 dB is about 35 GHz (430). That is, in the case of the silicon photonics chip (40) including the high-density capacitor (30), the reflection property and transmission property of the silicon photomodulator (320) are improved.

[0068] In the case of a silicon photonics chip (40) according to one embodiment of the present disclosure, the distance between metal layers is about 1 μm to 1.5 μm, and the distance between the silicon layer (100) and the metal layer (120) is about 500 nm to 800 nm, and is manufactured using a silicon photonics process. A high-density capacitor (30) according to one embodiment of the present disclosure can provide a MOS capacitor (10) having a capacitance per area that is twice that of a MIM capacitor (20) by using a silicon phononics process.

[0069] At least some of the components described in the exemplary embodiments of the present disclosure may be implemented as hardware elements including at least one of a Digital Signal Processor (DSP), a processor, a controller, an Application-Specific IC (ASIC), a programmable logic device (such as an FPGA), or other electronic devices, or a combination thereof. Additionally, at least some of the functions or processes described in the exemplary embodiments may be implemented in software, and the software may be stored on a recording medium. At least some of the components, functions, and processes described in the exemplary embodiments of the present disclosure may be implemented as a combination of hardware and software.

[0070] The method according to exemplary embodiments of the present disclosure may be written as a program executable on a computer and may also be implemented on various recording media such as magnetic storage media, optical reading media, and digital storage media.

[0071] Implementations of the various technologies described herein may be implemented as digital electronic circuits, or as computer hardware, firmware, software, or combinations thereof. Implementations may be implemented as computer program products, i.e., computer programs tangibly embodied in information carriers, such as machine-readable storage devices (computer-readable media) or radio signals, for processing by the operation of data processing devices, e.g., programmable processors, computers, or multiple computers, or for controlling such operation. Computer programs such as the computer program(s) described above may be written in any form of programming language, including compiled or interpreted languages, and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. Computer programs may be deployed to be processed on one computer or multiple computers at one site, or distributed across multiple sites and interconnected by a communication network.

[0072] Processors suitable for processing computer programs include, for example, both general-purpose and special-purpose microprocessors, and any one or more processors of any type of digital computer. Generally, the processor will receive instructions and data from read-only memory or random access memory, or both. The elements of the computer may include at least one processor that executes instructions and one or more memory devices that store instructions and data. Generally, the computer may include one or more mass storage devices that store data, for example, magnetic, magneto-optical disks, or optical disks, or may be combined to receive data from these, transmit data to these, or both. Information carriers suitable for embodying computer program instructions and data include, for example, semiconductor memory devices, magnetic media such as hard disks, floppy disks, and magnetic tapes; optical media such as CD-ROMs (Compact Disk Read Only Memory) and DVDs (Digital Video Disks); magneto-optical media such as floptical disks; ROMs (Read Only Memory); RAMs (Random Access Memory); flash memory; EPROMs (Erasable Programmable ROM); EEPROMs (Electrically Erasable Programmable ROM); etc. Processors and memory may be supplemented by or included in special-purpose logic circuit organizations.

[0073] The processor may execute an operating system and software applications executed on said operating system. Additionally, the processor device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, the processor device may be described as being used as a single unit; however, those skilled in the art will understand that the processor device may include multiple processing elements and / or multiple types of processing elements. For example, the processor device may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are also possible.

[0074] Additionally, non-transitory computer-readable media may be any available medium accessible by a computer and may include both computer storage media and transmission media.

[0075] Although this specification contains details of a number of specific embodiments, they should not be understood as limiting the scope of any invention or claimables, but rather as descriptions of features that may be characteristic of a specific embodiment of a specific invention. Specific features described in this specification in the context of individual embodiments may be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any appropriate sub-combination. Furthermore, while features may operate in a specific combination and be described as initially claimed, one or more features from the claimed combination may be excluded from the combination in some cases, and the claimed combination may be changed to a sub-combination or a variation of the sub-combination.

[0076] Likewise, although operations are depicted in the drawings in a specific order, this should not be understood as requiring that such operations be performed in that specific or sequential order depicted to obtain a desirable result, or that all depicted operations must be performed. In certain cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of the various device components of the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and devices can generally be integrated together into a single software product or packaged into multiple software products.

[0077] Meanwhile, the embodiments of the present invention disclosed in this specification and drawings are merely specific examples provided to aid understanding and are not intended to limit the scope of the present invention. It is obvious to those skilled in the art that other variations based on the technical concept of the present invention are possible in addition to the embodiments disclosed herein.

[0078] The scope of protection of this embodiment shall be interpreted by the claims below, and all technical ideas within an equivalent scope shall be interpreted as being included within the scope of rights of this embodiment. Explanation of the symbols

[0079] 10: MOS capacitor 100: Silicon layer 110: First dielectric layer 120: First metallic layer 20: MIM capacitor 200: Second dielectric layer 210: Second metal layer

Claims

Claim 1 A structure comprising a MOS (metal-oxide-semiconductor) capacitor and a MIM (metal insulator metal) capacitor stacked vertically, wherein the MOS capacitor and the MIM capacitor are formed on the upper surface of a silicon photonics chip, and the MOS capacitor has a dopant concentration of at least 1×10 20 cm -3 A high-density capacitor comprising: a silicon layer; a first dielectric layer formed on top of the silicon layer; and a first metal layer formed on top of the first dielectric layer, wherein the MIM capacitor comprises: the first metal layer; a second dielectric layer formed on top of the first metal layer; and a second metal layer formed on top of the second dielectric layer, and wherein the silicon photonics chip comprises: a buried oxide layer formed on the lower layer of the silicon; and a semiconductor substrate formed on the lower layer of the buried oxide layer. Claim 2 delete Claim 3 delete Claim 4 A high-density capacitor according to claim 1, wherein the first dielectric layer and the second dielectric layer comprise the same dielectric. Claim 5 In claim 1, the high-density capacitors, wherein the areas of the MOS capacitor and the MIM capacitor are the same. Claim 6 A high-density capacitor according to claim 1, wherein the thickness of the first dielectric layer is at least 500 nm. Claim 7 A high-density capacitor according to claim 1, wherein the thickness of the second dielectric layer is at least 1000 nm. Claim 8 A method for manufacturing a high-density capacitor comprising a structure in which a MOS capacitor and a MIM capacitor are stacked vertically, wherein the MOS capacitor and the MIM capacitor are formed on top of a silicon photonics chip, and the silicon layer is at least 1×10 20 cm -3 A manufacturing method comprising the steps of doping to have a dopant concentration, forming a first dielectric layer on the upper surface of the silicon layer, forming a first metal layer on the upper surface of the first dielectric layer, forming a second dielectric layer on the upper surface of the first metal layer, and forming a second metal layer on the upper surface of the second dielectric layer, wherein the MOS capacitor and the MIM capacitor share the same region of the first metal layer. Claim 9 delete Claim 10 delete Claim 11 A manufacturing method according to claim 8, wherein the first dielectric layer and the second dielectric layer comprise the same dielectric. Claim 12 In claim 8, a manufacturing method for forming the MOS capacitor and the MIM capacitor such that the MOS capacitor and the MIM capacitor have the same area. Claim 13 A manufacturing method according to claim 8 for forming the first dielectric layer having a thickness of at least 500 nm. Claim 14 A manufacturing method according to claim 8 for forming the second dielectric layer having a thickness of at least 1000 nm.

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