Shared memory sub-system and operation method thereof between heterogeneous devices based on single-port memory

Abstract

The present invention may provide a shared memory subsystem in a system for transmitting and receiving data between heterogeneous devices with different functions using a single-port shared memory, comprising: a data writing device configured to receive large volume data from the outside and perform a write operation on the single-port shared memory; and a data reading device configured to perform a read operation on data written on the single-port shared memory, wherein the data writing device includes a master memory subsystem having master access rights to the shared memory, and the data reading device includes a slave memory subsystem that accesses the shared memory under the control of the master memory subsystem.

Description

Technology Field

[0001] The present invention relates to a memory subsystem architecture, and more specifically, to a shared memory subsystem and a method of operation thereof that enables a single-port DRAM to be utilized as a shared buffer in a manner similar to non-volatile storage between heterogeneous devices with different functions. Furthermore, the present invention relates to a shared memory subsystem and a method of operation thereof that controls high-speed data transmission and reception in a zero-copy manner without physical copying of data. Background Technology

[0003] Recently, there has been a surge in demand for high-speed data transmission between heterogeneous devices performing different functions, such as CPUs, GPUs, and NPUs, for AI computation and large-scale data processing. Existing data sharing technologies between heterogeneous devices primarily include Compute Express Link (CXL), SATA-based storage sharing, and explicit copy-based methods. However, while CXL interface-based sharing supports high-speed memory sharing, it requires the separate design of a dedicated controller for implementation. Furthermore, because it mandates the use of the expensive PCIe standard at the physical layer, it presents problems such as very high system implementation costs and manufacturing complexity. Additionally, SATA protocol-based storage sharing methods, such as SSDs and HDDs, can store large amounts of data but are significantly slower than DRAM and suffer from high interface latency, making them unsuitable for real-time data processing. Furthermore, the copy-based approach, in which each device possesses independent local DRAM and explicitly copies data between the two memories whenever data is exchanged, has limitations. It not only leads to the waste of memory resources due to the redundant storage of identical data but also severely degrades the overall system throughput due to unnecessary computational overhead incurred during the copying process. Prior art literature

[0005] Republic of Korea Registered Patent No. 10-2572143 The problem to be solved

[0006] The present invention aims to solve the problems of the aforementioned prior art by providing a memory subsystem structure that enables efficient data sharing between heterogeneous devices using an inexpensive single-port DRAM without expensive dual-port memory or a complex CXL controller.

[0007] In addition, the present invention aims to simplify data transmission and reception protocols and drastically reduce transmission delay time by establishing a zero-copy environment that eliminates the explicit data copying process between heterogeneous devices.

[0008] In addition, the present invention aims to provide a system and method for dynamically allocating memory areas in an interleaving manner by directly controlling a MUX (Multiplexer) and a command line (CMD Line) on the master side to prevent single-port memory access conflicts between a master device (Write-only) providing data and a slave device (Read-only) consuming data. means of solving the problem

[0010] According to one embodiment of the present invention, a shared memory subsystem may be provided, wherein the system for transmitting and receiving data between heterogeneous devices with different functions using a single-port shared memory comprises: a data writing device configured to receive large volume data from the outside and perform a write operation on the single-port shared memory; and a data reading device configured to perform a read operation on data written on the single-port shared memory, wherein the data writing device includes a master memory subsystem having master access rights to the shared memory, and the data reading device includes a slave memory subsystem that accesses the shared memory under the control of the master memory subsystem.

[0011] In addition, the master memory subsystem can apply a selection signal to a multiplexer (MUX) connected so that the command line (CMD Line) of the master memory subsystem and the command line of the slave memory subsystem are multiplexed, thereby exclusively switching the physical access paths of both devices to the single-port shared memory.

[0012] In addition, the master memory subsystem can suppress signal reflection on a single shared bus by dynamically controlling the impedance value of a termination resistor provided in each physical layer (PHY) of the data writing device and the data reading device according to the switching state of the multiplexer.

[0013] In addition, the master memory subsystem and the slave memory subsystem each have an asynchronous interface bridge including asynchronous first-in, first-out (Async FIFO) logic for signal matching between different clock domains, and can exchange command line and status register signals with each other through the asynchronous interface bridge.

[0014] In addition, the single-port shared memory is logically divided into a first zone (Zone A) and a second zone (Zone B) according to the address space, and the master memory subsystem can determine in real time whether an overflow occurs by monitoring a threshold for the capacity of the first zone where data received from the data writing device is written.

[0015] In addition, the master memory subsystem can perform interleaving access control by controlling the multiplexer to acquire command line control of the slave memory subsystem when an overflow occurs as a result of the determination and the read for the second zone is not completed, and by forcing the first zone write operation of the data write device and the second zone read operation of the data read device to be performed alternately.

[0016] In addition, the master memory subsystem can control the write operation to be performed continuously by moving the write address of the data write device to the address of the second area, which has become valid after the read operation is completed, when the write to the first area is 100% complete.

[0017] In addition, the master memory subsystem may perform delay calibration training to pre-correct signal delay values ​​according to physical wiring length for the physical layer (SPHY) of the slave memory subsystem in order to ensure timing precision during the interleaving access control. Effects of the invention

[0019] According to the present invention, by using an inexpensive single-port memory instead of an expensive and difficult-to-supply dual-port memory or a complex CXL interface, there is an economic effect of significantly reducing chip production costs and package (PKG) costs.

[0020] In addition, according to the present invention, by adopting a single-path 'zero-copy' method without a data copying process between local DRAMs, the protocol can be simplified and the real-time performance (low latency) of data processing can be maximized.

[0021] In addition, according to the present invention, access conflicts that may occur in a single-port memory are completely resolved through a structure in which the master memory subsystem directly controls the command line (CMD Line) of the slave, and signal integrity between heterogeneous devices with different frequencies is ensured through Async FIFO-based bridge and dynamic termination resistor (ODT) control.

[0022] The effects of the present invention are not limited to those mentioned above, and other unmentioned technical effects will be clearly understood by a person skilled in the art from the description below. Brief explanation of the drawing

[0024] FIG. 1 is a configuration diagram of a package (PKG) of a single-port memory-based shared memory system according to one embodiment of the present invention. FIG. 2 is an internal block diagram of a master memory subsystem (MMSS) and a slave memory subsystem (SMSS) according to one embodiment of the present invention. FIG. 3 is a diagram of an asynchronous interface (Async FIFO) bridge structure for clock domain matching between heterogeneous devices according to an embodiment of the present invention. FIG. 4 is a flowchart of the write operation of the first shared memory area (Area A) of a master memory subsystem according to one embodiment of the present invention. FIG. 5 is a flowchart of the read operation of a shared memory first area (Area A) of a slave memory subsystem according to one embodiment of the present invention. FIG. 6 is an overall flowchart of an interleaving control operation to prepare for an overflow of shared memory according to an embodiment of the present invention. Figure 7 is a flowchart of the operation when the slave memory subsystem in Figure 6 has completed reading the second zone (Zone B). FIG. 8 is a flowchart of MUX control and interleaving operations when the slave memory subsystem in FIG. 6 has not completed reading the second zone (Zone B). Specific details for implementing the invention

[0025] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement the invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the embodiments of the present invention in the drawings, parts unrelated to the explanation have been omitted.

[0026] The terms used in this specification are used merely to describe specific embodiments and are not intended to limit the invention. Singular expressions may include plural expressions unless the context clearly indicates otherwise.

[0027] In this specification, terms such as “comprising,” “having,” or “having” are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0028] Furthermore, the components shown in the embodiments of the present invention are illustrated independently to represent different characteristic functions and do not imply that each component consists of separate hardware or a single software unit. That is, for convenience of explanation, each component is described as a separate component, and at least two of the components may be combined to form a single component, or a single component may be divided into multiple components to perform a function. Such integrated and separated embodiments of each component are also included within the scope of the present invention as long as they do not deviate from the essence of the invention.

[0029] Hereinafter, a preferred embodiment according to the present invention will be described with reference to the attached drawings.

[0031] FIG. 1 is an overall configuration diagram of a package (PKG) of a single-port memory-based shared memory subsystem according to one embodiment of the present invention.

[0032] Referring to FIG. 1, a system (100) according to the present invention may be configured to include a data writing device (110) and a data reading device (120) that perform different functions and are mounted within a semiconductor package (PKG) substrate, and a single port (1-Port) shared memory (200, DRAM) located outside the package and shared by the two devices.

[0033] In the present invention, a data writing device (110, Device 1) may be defined as a device that receives large amounts of data from an external interface (USB, PCIe, MIPI, etc.) and performs a write operation on the single-port shared memory (200). Additionally, the data writing device (110) is equipped with a master memory subsystem (111, MMSS) having access control master authority over the shared memory (200). Examples of such a data writing device (110) may include an ISP (Image Signal Processor) that receives raw data from a camera sensor, a sensor hub, and a baseband modem that receives external network packets.

[0034] On the other hand, the data reading device (120, Device 2) can be defined as a device that performs a read operation on data recorded in the single-port shared memory (200), and, for example, may be a device that performs high-speed computation and processing. The data reading device (120) is equipped with a slave memory subsystem (121, SMSS) having slave authority to perform memory access under the control of a master. Examples of the data reading device (120) may include an NPU (Neural Network Processing Unit) that performs deep learning computations based on the read data, an AI accelerator, a main AP, etc.

[0036] FIG. 2 is an internal block diagram of a master memory subsystem (111) and a slave memory subsystem (121) according to an embodiment of the present invention. Referring to FIG. 2, the master memory subsystem (111) includes a master memory controller (MMC), a multiplexer (MUX), and a master physical layer (MPHY), and the slave memory subsystem (121) may include a slave memory controller (SMC) and a slave physical layer (SPHY).

[0037] In the present invention, since a single-port shared memory (200) is used instead of a high-cost dual-port memory, arbitration logic is essential to prevent physical collisions between the two devices. To this end, the command line (CMD LINE) connected to the shared memory (200) can be multiplexed through a MUX inside the master memory subsystem (111) to connect the command line of the master memory controller (MMC) and the command line of the slave memory controller (SMC) to the master physical layer (MPHY).

[0038] Additionally, the master memory controller (MMC) can apply a select signal to this MUX to exclusively control and switch which device transmits a command to the shared memory (200), and the master memory controller (MMC) can be configured to directly control the command line of the slave physical layer (SPHY) through the select signal of the MUX.

[0039] In addition, to resolve signal reflection and noise issues that may occur when data lines are connected in a shared bus structure, the Master Memory Controller (MMC) can ensure signal integrity by controlling the dynamic termination (ODT) impedance values ​​of the master physical layer (MPHY) and slave physical layer (SPHY) in real time according to the selection state of the MUX.

[0041] FIG. 3 is a structural diagram of an asynchronous interface bridge (112, 122) for clock domain matching between heterogeneous devices according to one embodiment of the present invention.

[0042] Referring to FIG. 3, for stable state exchange between a data writing device (110) and a data reading device (120), which are heterogeneous devices performing different functions, the master memory subsystem (111) and the slave memory subsystem (121) may each include an asynchronous interface bridge (112, 122) internally. Here, the heterogeneous devices, the data writing device (110) and the data reading device (120), may have different or the same operating frequencies (clocks).

[0043] The above asynchronous interface bridge (112, 122) can be implemented with Async FIFO (Asynchronous First-In, First-Out) based logic, through which command line (CMD LINE), protocol, and status register signals between the two systems can be safely transmitted asynchronously across different clock domain boundaries.

[0045] FIGS. 4 and FIGS. 5 are flowcharts of normal write and read operations for a logical partitioned area (Area A) of a shared memory according to an embodiment of the present invention.

[0046] In the present invention, the single port shared memory (200) can be logically divided into a first area (Area A) and a second area (B) on an address map to prevent data corruption and to perform ping-pong buffering.

[0047] First, referring to FIG. 4, the core (Device 1 Core) of the data writing device (110) requests the master memory subsystem (111) to write to area A (S410). The master memory subsystem (111) can continuously monitor and check the threshold of the capacity of area A where the received data is to be written (S420). At this time, if the threshold is not exceeded and area A is in a normal state and is valid, the master memory subsystem (111) can perform a write operation on area A of the shared memory (200) (S430).

[0048] Referring to FIG. 5, the core (Device 2 Core) of the data reading device (120) requests the slave memory subsystem (121) to read area A (S510). The slave memory subsystem (121) checks with the master memory subsystem (111) whether the data in area A is fully written and valid (Valid status) (S520). When the slave memory subsystem (121) receives an area A Valid signal from the master memory subsystem (111), it can start a data read operation in area A of the shared memory (200) (S530).

[0050] FIG. 6 is a flowchart of the overall interleaving control operation in preparation for an overflow of shared memory according to one embodiment of the present invention.

[0051] Referring to FIG. 6, when the core of the data writing device (110) requests the master memory subsystem (111) to write area A (S601), the master memory subsystem (111) checks with the slave memory subsystem (121) whether the read for area A is complete (S602).

[0052] If area A is in a usable state, the master memory subsystem (111) internally checks whether the capacity of area A is below a threshold (i.e., whether an overflow occurs) (S603). If it is below the threshold, it performs a normal write to area A (S604). However, if it is determined that the threshold of area A will be exceeded (overflow) due to a large amount of external data inflow (NO in S603), the master memory subsystem (111) requests the slave memory subsystem (121) to check whether the read of the next buffer, area B, is completed (S605).

[0053] If reading of section B is completed (YES in S605), naturally move to the address of section B and perform write to the data (S606).

[0054] If the reading of area B is not yet completed (NO of S605), the master memory subsystem (111) forcibly requests the slave memory subsystem (121) to perform the reading of area B (S607).

[0055] At this time, the slave memory subsystem (121) transfers control of its command line (CMD LINE) to the master memory subsystem (111), and the MUX inside the master memory subsystem (111) controls the B section address command to be directly transmitted to the shared memory (200) (S608).

[0056] Through this, the master memory subsystem (111) performs an interleaving operation in which it controls the data writing device (110) to write the remaining data in area A almost simultaneously with the data reading device (120) to read the data in area B (S609).

[0057] When 100% of writing is completed in area A, the master memory subsystem (111) moves to the address of area B, which has been emptied after reading is completed, and continues writing (S610).

[0059] Figures 7 and 8 are flowcharts showing the overflow branching situation of Figure 6 in more detail.

[0060] First, FIG. 7 shows the detailed operation when the slave memory subsystem has completed reading area B (the S605 YES branch of FIG. 6). In response to the data writing device (110) core's request to write area A (S710), if the master memory subsystem (111) determines that the threshold for area A will be exceeded, it requests and confirms with the slave memory subsystem (121) whether the data reading device (120) has completed reading area B (S720). If it is confirmed that area B has been read and is a valid empty space, writing to area B is performed (S730).

[0061] FIG. 8 shows the detailed operation of MUX control and interleaving when the slave memory subsystem has not completed reading area B (branch S605 NO of FIG. 6). In response to a request to write area A (S810) of the data writing device (110) core, if the master memory subsystem (111) determines that the threshold of area A has been exceeded (overflow imminent) and that the reading of area B is incomplete, the slave memory subsystem (121) transmits a command line to the master memory subsystem (111), and the master memory subsystem (111) directly controls the multiplexer (MUX) (S820).

[0062] To achieve such physical line hijacking and control, during the initialization process, the master memory subsystem (111) can pre-perform delay calibration training for the physical layer (SPHY) of the slave memory subsystem (121) to pre-correct signal delay values ​​caused by differences in physical wiring lengths. Subsequently, in accordance with the calibrated timing, the master memory subsystem (111) performs interleaving that alternates between writing to area A and reading to area B at ultra-high speed even in a single-port environment, and by continuing to write to the address of area B when area A is 100% written, bottleneck-free zero-copy data processing can be completed (S830). For example, the above delay calibration training can be performed by the master memory subsystem (111) transmitting a preset test pattern via a path through the slave physical layer (SPHY) during initial booting, measuring the round-trip delay of the response signal, and storing the measured delay value in an internal correction register.

[0064] Although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above. It is understood that various modifications can be made by those skilled in the art without departing from the essence of the invention as claimed in the claims, and such modifications should not be understood individually from the technical spirit or perspective of the present invention.

[0066] The present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0068] 100: Shared memory subsystem between heterogeneous devices 110: Data writing device (1st device) 111: Master Memory Subsystem (MMSS) 112: The 1st Asynchronous Interface Bridge 120: Data reading device (second device) 121: Slave Memory Subsystem (SMSS) 122: The Second Asynchronous Interface Bridge 200: Single Port Shared Memory (DRAM)

Claims

Claim 1 A shared memory subsystem comprising: a data writing device configured to receive large volume data from an external source and perform a write operation on the single-port shared memory; and a data reading device configured to perform a read operation on data written on the single-port shared memory, wherein the data writing device includes a master memory subsystem having master access rights to the shared memory, and the data reading device includes a slave memory subsystem that accesses the shared memory under the control of the master memory subsystem. Claim 2 A shared memory subsystem according to claim 1, wherein the master memory subsystem applies a selection signal to a multiplexer (MUX) connected such that the command line (CMD Line) of the master memory subsystem and the command line of the slave memory subsystem are multiplexed, thereby exclusively switching the physical access paths of both devices to the single-port shared memory. Claim 3 In paragraph 2, the shared memory subsystem is such that the master memory subsystem dynamically controls the impedance value of a termination resistor provided in each physical layer (PHY) of the data write device and the data read device according to the switching state of the multiplexer to suppress signal reflection on a single shared bus. Claim 4 A shared memory subsystem according to claim 1, wherein the master memory subsystem and the slave memory subsystem each have an asynchronous interface bridge including asynchronous FIFO logic for signal matching between different clock domains, and exchange command line and status register signals with each other through the asynchronous interface bridge. Claim 5 A shared memory subsystem according to paragraph 2, wherein the single port shared memory is logically divided into a first zone (Zone A) and a second zone (Zone B) according to an address space, and the master memory subsystem monitors a threshold for the capacity of the first zone where data received from the data writing device is written to determine in real time whether an overflow has occurred. Claim 6 A shared memory subsystem according to claim 5, wherein the master memory subsystem, when an overflow occurs as a result of the determination and the read for the second zone is not completed, controls the multiplexer to acquire command line control of the slave memory subsystem and performs interleaving access control that forces the first zone write operation of the data write device and the second zone read operation of the data read device to be performed alternately. Claim 7 A shared memory subsystem according to claim 6, wherein the master memory subsystem controls the write address of the data write device to move to the address of the second area, which has become valid after the read operation is completed, so as to continuously perform write operations when the write to the first area is 100% completed. Claim 8 A shared memory subsystem according to claim 6, wherein the master memory subsystem performs delay calibration training to pre-correct signal delay values ​​according to physical wiring length for the physical layer (SPHY) of the slave memory subsystem in order to secure timing precision during the interleaving access control.

Images