Display device and manufacturing method thereof

Abstract

A method for manufacturing a polycrystalline silicon layer according to one embodiment comprises the steps of: forming a first amorphous silicon layer on a substrate; doping the first amorphous silicon layer with N-type impurities; forming a second amorphous silicon layer on the first amorphous silicon layer; doping the second amorphous silicon layer with P-type impurities to form an amorphous silicon layer; cleaning the amorphous silicon layer; and irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer.

Description

Technology Field

[0001] The present disclosure relates to a method for manufacturing a polycrystalline silicon layer, a display device comprising a polycrystalline silicon layer manufactured thereby, and a method for manufacturing the same. More specifically, it relates to a method for manufacturing a polycrystalline silicon layer having excellent device characteristics and reduced defects, a display device comprising a polycrystalline silicon layer manufactured thereby, and a method for manufacturing the same. Background Technology

[0002] Among display devices, flat panel display devices are gaining attention due to their ability to be lightweight and thin. Among flat panel display devices, light-emitting display devices are self-emissive display devices that display images using light-emitting diodes and do not require a separate light source. Furthermore, light-emitting display devices are attracting attention as next-generation display devices because they possess low power consumption, high brightness, and high response speed.

[0003] The above-described electroluminescent display device includes a light-emitting diode and a plurality of pixels comprising a plurality of transistors and at least one capacitor as a circuit for driving the light-emitting diode.

[0004] Polycrystalline silicon thin-film transistors with excellent electron mobility can be used as thin-film transistors in such circuits. Polycrystalline silicon thin-film transistors have higher electron mobility and superior stability against light irradiation compared to amorphous silicon thin-film transistors. Therefore, polycrystalline silicon thin-film transistors may be suitable for use as the active layer of driving transistors and / or switching transistors in light-emitting display devices.

[0005] Since the characteristics of such polycrystalline silicon layers determine the characteristics of transistors and display devices containing them, manufacturing polycrystalline silicon layers with excellent characteristics and few surface defects to improve device characteristics is an important task in the display field. The problem to be solved

[0006] The embodiments are intended to provide a method for manufacturing a polycrystalline silicon layer capable of obtaining excellent device characteristics while simultaneously reducing circular stains, a display device comprising a polycrystalline silicon layer manufactured thereby, and a method for manufacturing the same. means of solving the problem

[0007] A method for manufacturing a polycrystalline silicon layer according to one embodiment of the present invention comprises the steps of: forming a first amorphous silicon layer on a substrate; doping the first amorphous silicon layer with N-type impurities; forming a second amorphous silicon layer on the first amorphous silicon layer; doping the second amorphous silicon layer with P-type impurities to form an amorphous silicon layer; cleaning the amorphous silicon layer; and irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer.

[0008] The step of cleaning the amorphous silicon layer may include cleaning the amorphous silicon layer with hydrofluoric acid and rinsing the amorphous silicon layer with deionized water.

[0009] The thickness of the first amorphous silicon layer may be 150 Å or more and 250 Å or less.

[0010] The thickness of the second amorphous silicon layer may be 150 Å or more and 250 Å or less.

[0011] The doping of the above N-type impurities can be carried out with an acceleration voltage greater than 0 and less than or equal to 20 keV and a dose amount greater than or equal to 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm².

[0012] The doping of the above-mentioned P-type impurities can be carried out with an acceleration voltage greater than 0 and less than or equal to 20 keV and a dose amount greater than or equal to 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm².

[0013] After the step of cleaning the amorphous silicon layer with hydrofluoric acid, the contact angle with water measured on the surface of the amorphous silicon layer may be less than 20 degrees.

[0014] A display device according to one embodiment of the present invention comprises a substrate, a thin-film transistor disposed on the substrate, and a display element disposed on the thin-film transistor, wherein the thin-film transistor comprises an active pattern disposed on the substrate and including a source region, a drain region, and a channel region located between the source region and the drain region, a gate insulating film disposed on the active pattern, and a gate electrode disposed on the gate insulating film corresponding to the channel region, and wherein the channel region comprises N-type impurities and P-type impurities.

[0015] The concentration of the P-type impurity may be higher as it approaches the gate insulating film in the channel region.

[0016] The concentration of the N-type impurity may be higher as it moves further away from the gate insulating film in the channel region.

[0017] The above-mentioned P-type impurity may be either boron (B) or fluorine (F).

[0018] The above N-type impurity may be phosphorus (P).

[0019] The thickness of the above active pattern may be 300 Å or more and 500 Å or less.

[0020] The concentration of the P-type impurity within the above channel region may be 1e14 atoms / cm² or more and 1e16 atoms / cm² or less.

[0021] The concentration of the N-type impurity within the above channel region may be 1e14 atoms / cm² or more and 1e16 atoms / cm² or less.

[0022] Within the channel region, the concentration of the P-type impurity and the concentration of the N-type impurity may be substantially the same.

[0023] The thin-film transistor may further include a source electrode and a drain electrode disposed on the gate electrode and electrically connected to the source region and the drain region, respectively.

[0024] The above display element may include a first electrode electrically connected to the thin-film transistor, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer.

[0025] A method for manufacturing a display device according to an embodiment of the present invention comprises the steps of: forming a first amorphous silicon layer on a substrate; doping the first amorphous silicon layer with N-type impurities; forming a second amorphous silicon layer on the first amorphous silicon layer; doping the second amorphous silicon layer with P-type impurities to form an amorphous silicon layer; cleaning the amorphous silicon layer; irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer; etching the polycrystalline silicon layer to form a polycrystalline silicon pattern; forming a gate insulating film on the polycrystalline silicon pattern; forming a gate electrode on the gate insulating film; partially implanting ions into the polycrystalline silicon pattern to form an active pattern including a source region, a drain region, and a channel region; and forming a display element on the gate electrode.

[0026] The step of cleaning the amorphous silicon layer may include cleaning the amorphous silicon layer with hydrofluoric acid and rinsing the amorphous silicon layer with deionized water.

[0027] The doping of the above N-type impurities can be carried out with an acceleration voltage greater than 0 and less than or equal to 20 keV and a dose amount greater than or equal to 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm².

[0028] The doping of the above-mentioned P-type impurities can be carried out with an acceleration voltage greater than 0 and less than or equal to 20 keV and a dose amount greater than or equal to 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm².

[0029] After the step of cleaning the amorphous silicon layer with hydrofluoric acid, the contact angle with water measured on the surface of the amorphous silicon layer may be less than 20 degrees.

[0030] The step of partially implanting ions into the polycrystalline silicon pattern above may involve implanting ions only into the portions corresponding to the source region and drain region using the gate electrode as a mask.

[0031] The method may further include the step of forming a source electrode and a drain electrode on the gate electrode, each electrically connected to the source region and the drain region, respectively.

[0032] The step of forming the above-mentioned display element may include the step of forming a first electrode electrically connected to the active pattern on the gate electrode, the step of forming a light-emitting layer on the first electrode, and the step of forming a second electrode on the light-emitting layer. Effects of the invention

[0033] According to the embodiments, excellent device characteristics can be obtained by reducing protrusions on the surface of the polycrystalline silicon layer, and at the same time, a polycrystalline silicon layer with reduced circular stains and a display device including the same can be obtained. Brief explanation of the drawing

[0034] FIG. 1 is a flowchart illustrating a method for manufacturing a polycrystalline silicon layer according to one embodiment of the present invention. FIGS. 2 to 8 are drawings illustrating a method for manufacturing a polycrystalline silicon layer according to an embodiment of the present invention. FIGS. 9 to 12 are cross-sectional views illustrating a method for manufacturing a thin-film transistor substrate according to one embodiment of the present invention. FIG. 13 is an equivalent circuit diagram of a pixel of a display device according to one embodiment of the present invention. FIG. 14 is a cross-sectional view showing a display device according to one embodiment of the present invention. Figure 15 is a graph showing the results of measuring the contact angle with water before crystallization of the amorphous silicon layer in the examples and comparative examples. Figures 16a and 16b are photographs showing the surface of a polycrystalline silicon layer observed under a microscope in the examples and comparative examples. Figure 17 is a graph showing the number of defects in the examples and comparative examples. Specific details for implementing the invention

[0035] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0036] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0037] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0038] Furthermore, when a part such as a layer, membrane, region, or plate is said to be "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when a part is said to be "directly above" another part, it means that there is no other part in between. Also, being "on" or "on" a reference part means being located above or below the reference part, and does not necessarily mean being located "on" or "on" in the direction opposite to gravity.

[0039] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0040] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0041] Hereinafter, a method for manufacturing a polycrystalline silicon layer according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8.

[0042] FIG. 1 is a flowchart illustrating a method for manufacturing a polycrystalline silicon layer according to an embodiment of the present invention. FIGS. 2 to 8 are drawings illustrating a method for manufacturing a polycrystalline silicon layer according to an embodiment of the present invention.

[0043] Referring to FIGS. 1 and 2, a first amorphous silicon layer (132a) can be formed on a substrate (110) (S100).

[0044] The substrate (110) may be an insulating substrate including glass, quartz, ceramic, etc. In one embodiment, the substrate (110) may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. The substrate (110) may include a flexible material that can be bent or folded, and may be a single layer or a multilayer. The substrate (110) may further include a barrier layer (not shown) having a single layer or a multilayer structure, and the barrier layer may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitrate (SiOxNy), for example.

[0045] A buffer layer (120) may be formed on the substrate (110). The buffer layer (120) provides a flat surface on the upper surface of the substrate (110) and can prevent impurities from penetrating through the substrate (110). In the drawing, the buffer layer (120) is shown as a single layer, but it may be multilayer depending on the embodiment. The buffer layer (120) may be formed by including an organic insulating material or an inorganic insulating material. For example, the buffer layer (120) may be silicon oxide (SiO₂). x ), silicon nitride (SiN x ), and silicon nitrate (SiO₂ x N y It may include inorganic insulating materials such as ).

[0046] A first amorphous silicon layer (132a) may be formed on the buffer layer (120). The first amorphous silicon layer (132a) may be formed by methods such as low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, or vacuum deposition. At this time, the first amorphous silicon layer (132a) may be formed with a thickness of 150 Å to 250 Å.

[0047] Referring to FIGS. 1 and FIGS. 3, N-type impurities (D1) can be doped into the first amorphous silicon layer (132a) (S200).

[0048] Various methods can be applied for doping N-type impurities (D1), but ion implantation may be used as one embodiment. When ion implantation is used, N-type impurities (D1) in an ionic state are accelerated and implanted into the first amorphous silicon layer (132a). In this embodiment, the acceleration voltage for accelerating N-type impurities (D1) may be greater than 0 keV and less than or equal to 20 keV. In addition, the dose amount of N-type impurities (D1) may be greater than 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm².

[0049] The N-type impurity (D1) can be selected from phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). Preferably, the N-type impurity (D1) can be phosphorus (P).

[0050] Referring to FIGS. 1 and FIGS. 4, a second amorphous silicon layer (132b) can be formed on a first amorphous silicon layer (132a) (S300).

[0051] A second amorphous silicon layer (132b) is formed on the first amorphous silicon layer (132a). The second amorphous silicon layer (132b) can be formed by methods such as low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, or vacuum deposition, in the same way as the first amorphous silicon layer (132a). At this time, the second amorphous silicon layer (132a) can be formed with a thickness of 150 Å to 250 Å.

[0052] The second amorphous silicon layer (132b) is formed from the same material by the same method as the first amorphous silicon layer (132a), for example, and after being formed as shown in FIG. 4, it can be formed as a single layer with substantially indistinct boundaries.

[0053] Referring to FIGS. 1 and FIGS. 5, a second amorphous silicon layer (132b) can be doped with a P-type impurity (D2) (S400).

[0054] Various methods can be applied for doping the P-type impurity (D2), but in one embodiment, ion implantation may be used. When using ion implantation, the P-type impurity (D2) in an ionic state is accelerated and implanted into the second amorphous silicon layer (132b). In this embodiment, the acceleration voltage for accelerating the P-type impurity (D2) may be greater than 0 keV and less than or equal to 20 keV. In addition, the dose amount of the P-type impurity (D2) may be greater than 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm². If it is less than 1e14 atoms / cm², the surface of the amorphous silicon layer (132) cannot be sufficiently hydrophilized, and if it is greater than 1e16 atoms / cm², it is undesirable as it may affect the device characteristics of the transistor manufactured using it.

[0055] The P-type impurity (D2) can be selected from boron (B), aluminum (Al), gallium (Ga), and indium (In). Preferably, the P-type impurity (D2) can be boron (B).

[0056] The amorphous silicon layer (132) can be completed by doping with P-type impurities (D2). The amorphous silicon layer (132) in a state where P-type impurities (D2) are doped on the upper surface can have a hydrophilic surface. In particular, because P-type impurities (D2) are doped so that P-type impurities (D2) are present near the surface of the amorphous silicon layer (132), the surface of the amorphous silicon layer (132) maintains hydrophilicity even after cleaning with the hydrofluoric acid (210) described later, thus preventing circular stains from occurring during the subsequent cleaning and rinsing process.

[0057] In addition, since the P-type impurity (D2) is doped in this manner, and the N-type impurity (D1) is also included in the amorphous silicon layer (132) through the film formation and doping process of the first amorphous silicon layer (132a) performed earlier, even if the polycrystalline silicon layer manufactured according to this embodiment is applied to a transistor device, it may not affect the characteristics of the device.

[0058] In particular, in this case, since the first amorphous silicon layer (132a) and the second amorphous silicon layer (132b) are each separated for film formation and doping, only P-type impurities (D2) can be made to exist near the surface of the amorphous silicon layer (132). If N-type impurities (D1) doped to maintain device characteristics are located near the surface of the amorphous silicon layer (132), the phenomenon of water droplet formation after cleaning, which can cause circular stains, may increase. However, as in the present embodiment, by forming the first amorphous silicon layer (132a) and doping it with N-type impurities, and then separately forming the second amorphous silicon layer (132b) and doping it with P-type impurities, it is possible to prevent N-type impurities from existing near the surface of the amorphous silicon layer (132).

[0059] Referring to FIGS. 1 and FIGS. 6, the surface of the amorphous silicon layer (132) can be cleaned with hydrofluoric acid (210) (S500).

[0060] A natural oxide film may exist on the amorphous silicon layer (132) when the upper portion of the amorphous silicon layer (132) is exposed to air. If the natural oxide film remains on the amorphous silicon layer (132), it is necessary to remove it because, during the crystallization step, a protrusion of relatively large thickness may be formed on the surface of the polycrystalline silicon layer by the natural oxide film.

[0061] To this end, the amorphous silicon layer (132) can be cleaned using hydrofluoric acid (210). Hydrofluoric acid (210) may be an aqueous solution in which hydrogen fluoride (HF) is dissolved. For example, hydrofluoric acid (210) may contain about 0.5% hydrogen fluoride. By cleaning the amorphous silicon layer (132) with hydrofluoric acid (210), the natural oxide film formed on the amorphous silicon layer (132) can be removed.

[0062] In one embodiment, the amorphous silicon layer (132) may be cleaned with hydrofluoric acid (210) for about 40 seconds to about 70 seconds. If the amorphous silicon layer (132) is cleaned for less than about 40 seconds, the natural oxide film (NOL) formed on the amorphous silicon layer (132) may not be sufficiently removed. Also, if the amorphous silicon layer (132) is cleaned for longer than about 70 seconds, the amorphous silicon layer (132) may be affected by the hydrofluoric acid (210).

[0063] As such, the surface cleaned by hydrofluoric acid (210) generally has hydrophobic characteristics. On a hydrophobic surface, water droplets with cohesive force form relatively easily, and in the part where the water droplets form, they are oxidized by O2 or -OH groups during the rinsing process described later, and after crystallization, a mark in the form of a circular stain remains. Such circular stains (water marks) can cause pixel defects when applied to a display device. However, in one embodiment of the present invention, as in step S500 above, P-type impurities (D2) are doped so that P-type impurities (D2) exist near the surface of the amorphous silicon layer (132), so the surface maintains hydrophilic characteristics even after cleaning with hydrofluoric acid (210). In this state, if the contact angle of the surface with water is measured, it may be less than 20 degrees. That is, as the contact angle increases, water droplets are more likely to form on the surface, which can remain as circular stains in subsequent processes. However, in this embodiment, due to the doping of P-type impurities (D2), the surface becomes hydrophilic even after cleaning with hydrofluoric acid (210), so the contact angle with water can be less than 20 degrees. Therefore, the occurrence of circular stains can be prevented.

[0064] Referring to FIGS. 1 and FIGS. 7, the surface of the amorphous silicon layer (132) can be rinsed with deionized water (220) (S600).

[0065] The amorphous silicon layer (132) can be rinsed using deionized water (220). For example, the deionized water (220) can be supplied to the amorphous silicon layer (132) through the spray (230) while moving the substrate (110) under the fixed spray (230). The amorphous silicon layer (132) can be rinsed with deionized water (220) to remove the hydrofluoric acid (210) remaining on the amorphous silicon layer (132).

[0066] In particular, in one embodiment of the present invention, even when the amorphous silicon layer (132) is rinsed using deionized water without added hydrogen, circular defects caused by oxygen after the crystallization step can be prevented. That is, because P-type impurities (D2) are present near the surface of the amorphous silicon layer (132), the surface maintains its hydrophilic characteristics even after cleaning with hydrofluoric acid (210), and thus water droplets do not form on the surface. Therefore, even if oxygen remains in the deionized water, it does not oxidize and remain in the form of circular stains, so the occurrence of circular defects itself can be prevented. Furthermore, more preferably, the amorphous silicon layer (132) can be rinsed using deionized water (220) to which hydrogen has been added at a hydrogen concentration of about 1.0 ppm. By doing so, the visibility of circular defects can be prevented more reliably.

[0067] Referring to FIGS. 1 and FIGS. 8, a polycrystalline silicon layer (134) can be formed by irradiating an amorphous silicon layer (132) with a laser beam (240) (S700).

[0068] A polycrystalline silicon layer (134) can be formed by irradiating a laser beam (240) onto an amorphous silicon layer (132). A laser (250) can irradiate the amorphous silicon layer (132) by intermittently generating a laser beam (240). For example, the laser (250) may be an excimer laser that generates a short wavelength, high power, and high efficiency laser beam (240). The excimer laser may include, for example, an inert gas, an inert gas halide, a mercury halide, an inert gas oxide compound, and a polyatomic excimer. For example, the inert gas may be Ar2, Kr2, Xe2, etc., the inert gas halide may be ArF, ArCl, KrF, KrCl, XeF, XeCl, etc., the mercury halide may be HgCl, HgBr, HgI, etc., the inert gas oxide compound may be ArO, KrO, XeO, etc., and the polyatomic excimer may be Kr2F, Xe2F, etc.

[0069] While moving the substrate (110), a laser beam (240) from the laser (250) is irradiated onto the amorphous silicon layer (132) to crystallize the amorphous silicon layer (132) into a polycrystalline silicon layer (134). The laser (250) irradiates the amorphous silicon layer (132) with a force of approximately 450 mJ / cm² 2 Up to about 500 mJ / cm² 2 A laser beam (240) having an energy density can be irradiated. In one embodiment, the width (WB) of the laser beam (240) is about 480 μm, and the scan pitch in the first direction (D1) of the laser beam (240) may be about 9 μm to about 30 μm. For example, when the scan pitch is about 24 μm, the laser beam (240) may be irradiated about 24 times on a predetermined area of ​​the amorphous silicon layer (132). As shown in FIG. 8, the area where the crystallization process is performed using the laser beam (240) can be converted from the amorphous silicon layer (132) into a polycrystalline silicon layer (134).

[0070] Although the doping process, cleaning process, rinsing process, and crystallization process for forming a polycrystalline silicon layer (134) have been described above, it may be possible to add processes for forming a polycrystalline silicon layer (134) in addition to the above processes or to omit some of the above processes. In addition, it may be possible to perform the above processes multiple times. For example, the crystallization process may be performed two or more times.

[0071] Hereinafter, a thin film transistor substrate according to one embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 9 to 12.

[0072] FIGS. 9 to 12 are cross-sectional views illustrating a method for manufacturing a thin-film transistor substrate according to an embodiment of the present invention. Hereinafter, in describing the method for manufacturing a thin-film transistor substrate according to an embodiment of the present invention, a detailed description of parts that overlap with the method for manufacturing a polycrystalline silicon layer according to an embodiment of the present invention is omitted.

[0073] Referring to FIG. 9, a polycrystalline silicon layer (134) formed on a substrate (110) and a buffer layer (120) can be etched to form a polycrystalline silicon pattern (136). The polycrystalline silicon layer (134) can be manufactured by the method for manufacturing a polycrystalline silicon layer (134) according to an embodiment of the present invention described above. Accordingly, the polycrystalline silicon layer (134) includes N-type impurities (D1) and P-type impurities (D2). At this time, the P-type impurities (D2) may be contained near the surface of the polycrystalline silicon layer (134), and the N-type impurities (D1) may be contained near the bottom, that is, adjacent to the buffer layer (120). The boundaries between them do not exist clearly and may exist throughout the entire thickness direction region of the polycrystalline silicon layer (134), but the concentration of P-type impurities (D2) decreases as they move further away from the surface of the polycrystalline silicon layer (134), and the concentration of N-type impurities (D1) decreases as they get closer to the surface of the polycrystalline silicon layer (134). Within the polycrystalline silicon layer (134), the concentration of P-type impurities (D2) is 1e14 atoms / cm² or more and 1e16 atoms / cm² or less, and the concentration of N-type impurities (D1) is 1e14 atoms / cm² or more and 1e16 atoms / cm² or less.

[0074] The polycrystalline silicon layer (134) can be etched by photolithography. For example, a photoresist pattern can be formed on the polycrystalline silicon layer (134) using an exposure process and a development process, and the polycrystalline silicon layer (134) can be etched using the photoresist pattern as an etching barrier.

[0075] Referring to FIG. 10, a gate insulating film (140) and a gate electrode (GE) can be formed on a polycrystalline silicon pattern (136). The gate insulating film (140) can be placed on a buffer layer (120) to cover the polycrystalline silicon pattern (136). The gate insulating film (140) can insulate the gate electrode (GE) from the polycrystalline silicon pattern (136). For example, the gate insulating film (140) can be formed of silicon oxide, silicon nitride, etc.

[0076] The gate electrode (GE) can overlap with the polycrystalline silicon pattern (136). The gate electrode (GE) may comprise gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or an alloy thereof, and may have a single layer or a multilayer structure comprising different metal layers. For example, the gate electrode (GE) may comprise a triple layer of molybdenum / aluminum / molybdenum, a copper / titanium double layer, etc.

[0077] For example, a photoresist pattern can be formed overlapping a first metal layer and a polycrystalline silicon pattern (136) on a gate insulating film (140). Then, a gate electrode (GE) can be formed by etching the first metal layer using the photoresist pattern.

[0078] Referring to FIG. 11, an active pattern (AP) including a source region (SR), a channel region (CR), and a drain region (DR) can be formed by partially implanting ions into a polycrystalline silicon pattern (136).

[0079] The ion implantation process can be performed using the gate electrode (GE) as a mask. That is, in the polycrystalline silicon pattern (136), the portion overlapping with the gate electrode (GE) remains undoped with ions to form a channel region (CR), and the remaining portion is partially doped to form a source region (SR) and a drain region (DR). The ions may be N-type impurities or P-type impurities.

[0080] In this ion implantation process, the portion of the polycrystalline silicon pattern (136) that overlaps with the gate electrode (GE) remains undoped with ions and becomes the channel region (CR). However, as previously explained, since the polycrystalline silicon pattern (136) already contains N-type impurities (D1) and P-type impurities (D2), the channel region (CR) also contains N-type impurities (D1) and P-type impurities (D2). That is, the concentration of P-type impurities (D2) contained in the channel region (CR) increases as it approaches the gate insulating film (140), and the concentration of N-type impurities (D1) increases as it moves away from the gate insulating film (140). Within the channel region (CR), the concentration of P-type impurities (D2) is 1e14 atoms / cm² or more and 1e16 atoms / cm² or less, and the concentration of N-type impurities (D1) is 1e14 atoms / cm² or more and 1e16 atoms / cm² or less. The concentration of P-type impurities (D2) and N-type impurities (D1) within the channel region (CR) can be substantially the same. Thus, even if P-type impurities (D2) are present near the upper surface of the polycrystalline silicon layer (134) to prevent the occurrence of circular stains on the surface of the polycrystalline silicon layer (134), N-type impurities (D1) of substantially the same concentration are present within the channel region (CR), so the characteristics of the device in the transistor may not be affected.

[0081] Meanwhile, the additionally ion-doped portion of the polycrystalline silicon pattern (136) has increased conductivity and possesses the properties of a conductor, thereby becoming a source region (SR) and a drain region (DR). A channel region (CR) can be formed between the source region (SR) and the drain region (DR).

[0082] The thickness of the obtained active pattern may be 300 Å or more and 500 Å or less.

[0083] Referring to FIG. 12, an interlayer insulating film (150), a source electrode (SE), and a drain electrode (DE) can be formed on the gate electrode (GE).

[0084] An interlayer insulating film (150) can be placed on a gate insulating film (140) to cover a gate electrode (GE). The interlayer insulating film (150) can insulate a source electrode (SE) and a drain electrode (DE) from the gate electrode (GE).

[0085] The interlayer insulating film (150) may include an inorganic insulating layer, an organic insulating layer, or a combination thereof. For example, the interlayer insulating film (150) may include silicon oxide, silicon nitride, silicon carbide, or a combination thereof, and may also include insulating metal oxides such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. When the interlayer insulating film (150) includes an organic insulating layer, it may include polyimide, polyamide, acrylic resin, phenolic resin, benzocyclobutene (BCB), etc.

[0086] Next, the interlayer insulating film (150) and the gate insulating film (140) can be partially etched to form through holes that expose the source region (SR) and the drain region (DR), respectively.

[0087] Next, a source electrode (SE) and a drain electrode (DE) can be formed on the interlayer insulating film (150) and electrically connected to the source region (SR) and drain region (DR) of the active pattern (AP), respectively. That is, a second metal layer can be formed on the interlayer insulating film (150) and patterned to form a source electrode (SE) that contacts the source region (SR) through a through hole and a drain electrode (DR) that contacts the drain region (DR). For example, the source electrode (SE) and the drain electrode (DR) each include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or an alloy thereof, and may have a single layer or a multilayer structure including different metal layers. For example, the source electrode (SE) and the drain electrode (DR) may each include a triple layer of molybdenum / aluminum / molybdenum, a double layer of copper / titanium, etc.

[0088] According to one embodiment of the present invention, when forming an amorphous silicon layer prior to a crystallization process, a separation deposition process is performed in which a first amorphous silicon layer containing N-type impurities is formed, and then a second amorphous silicon layer containing P-type impurities is formed. This prevents circular stains that may occur during subsequent cleaning processes using hydrofluoric acid and rinsing processes using deionized water, without affecting device characteristics. Accordingly, a thin-film transistor with improved characteristics such as threshold voltage dispersion and hysteresis can be formed.

[0089] Hereinafter, a display device according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. 13 and 14.

[0090] FIG. 13 is an equivalent circuit diagram of a pixel of a display device according to one embodiment of the present invention, and FIG. 14 is a cross-sectional view showing a display device according to one embodiment of the present invention.

[0091] Referring to FIG. 13, a display device according to one embodiment of the present invention may include signal lines (GL, DL, PL) and a plurality of pixels (PX) connected thereto and arranged in the form of a substantial matrix.

[0092] Signal lines (GL, DL, PL) may include gate lines (GL) transmitting a gate signal (or scan signal), data lines (DL) transmitting a data voltage, and driving voltage lines (PL) transmitting a driving voltage (ELVDD). The gate lines (GL) may extend in a substantial row direction. The data lines (DL) and driving voltage lines (PL) may intersect the gate lines (GL) and extend in a substantial column direction. Each pixel (PX) may include a driving transistor (TR1), a switching transistor (TR2), a storage capacitor (CST), and a light emitting diode (LED).

[0093] The driving transistor (TR1) may include a control terminal, an input terminal, and an output terminal. The control terminal may be connected to a switching transistor (TR2). The input terminal may be connected to a driving voltage line (PL). The output terminal may be connected to an organic light-emitting diode (OLED). The driving transistor (TR1) can transmit an output current (Id), the magnitude of which varies depending on the voltage applied between the control terminal and the output terminal, to the light-emitting diode (LED).

[0094] The switching transistor (TR2) may include a control terminal, an input terminal, and an output terminal. The control terminal may be connected to a gate line (GL). The input terminal may be connected to a data line (DL). The output terminal may be connected to a driving transistor (TR1). The switching transistor (TR2) can transmit a data voltage applied to the data line (DL) to the driving transistor (TR1) in response to a gate signal applied to the gate line (GL).

[0095] A storage capacitor (CST) can be connected between the control terminal and the input terminal of the driving transistor (TR1). The storage capacitor (CST) charges the data voltage applied to the control terminal of the driving transistor (TR1) and can maintain it even after the switching transistor (TR2) is turned off.

[0096] The light-emitting diode (LED) may include an anode connected to the output terminal of the driving transistor (TR1) and a cathode connected to the common voltage (ELVSS). The light-emitting diode (LED) can display an image by emitting light at different brightness levels depending on the output current (Id) of the driving transistor (TR1).

[0097] In one embodiment of the present invention, each pixel (PX) is described as comprising two thin-film transistors (TR1, TR2) and one capacitor (CST), but the present invention is not limited thereto. In another embodiment, each pixel (PX) may comprise three or more thin-film transistors or two or more capacitors.

[0098] Referring to FIG. 14, a display device (100) according to one embodiment of the present invention may include a substrate (110), a thin-film transistor disposed on the substrate (110), and a display element disposed on the thin-film transistor. In one embodiment, the display device (100) may include a light-emitting diode (LED), for example, an organic light-emitting diode, as the display element. However, the present invention is not limited thereto, and in other embodiments, the display device (100) may include various other display elements.

[0099] The thin-film transistor (TR1) and light-emitting diode (LED) illustrated in FIG. 14 may correspond to the driving transistor (TR1) and light-emitting diode (LED) illustrated in FIG. 13, respectively. Meanwhile, a display device (100) according to one embodiment of the present invention may include a thin-film transistor substrate (TR) according to one embodiment of the present invention illustrated in FIG. 12. In addition, although the thin-film transistor (TR1) in one embodiment of the present invention is described as including polycrystalline silicon, it is not necessarily limited thereto, and other transistors included in the pixel (PX) may be formed to have an active layer including other materials such as amorphous silicon or oxide semiconductor.

[0100] In one embodiment, the driving thin-film transistor (TR1) shown in FIG. 13 may be formed to have an active layer including polycrystalline silicon, while the switching thin-film transistor (TR2 in FIG. 13) may be formed to have an active layer including an oxide semiconductor. At this time, the oxide semiconductor is a single metal oxide such as indium oxide (In), tin oxide (Sn), or zinc oxide (Zn); a binary metal oxide such as In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, or In-Ga oxide; an In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, or In-Dy-Zn oxide. It may include at least one of ternary metal oxides such as In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, or In-Lu-Zn ​​oxide, and quaternary metal oxides such as In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn oxide, or In-Hf-Al-Zn oxide. For example, the oxide semiconductor may be an IGZO (In-Ga-Zn-O) semiconductor containing metals such as indium (In) and gallium (Ga) in ZnO. However, it is not necessarily limited thereto and can be modified in various ways according to other embodiments.

[0101] When the active layer of a thin-film transistor includes an oxide semiconductor, it has a low off-current and is capable of low-frequency driving. Therefore, by configuring one of the thin-film transistors (TR1, TR2) to include an oxide semiconductor layer, the power consumption of the display device (100) can be reduced.

[0102] A light-emitting diode (LED) may include a first electrode (E1), a light-emitting layer (180), and a second electrode (E2) that are sequentially stacked. The light-emitting diode (LED) can emit light based on a driving current delivered from a thin-film transistor (TR1) to display an image.

[0103] To form a light-emitting diode (LED), a planarization film (or protective film) (160) may first be formed on a source electrode (SE) and a drain electrode (DE). The planarization film (160) may be placed on an interlayer insulating film (150) to cover the source electrode (SE) and the drain electrode (DE). The planarization film (160) may insulate the first electrode (E1) from the source electrode (SE) and the drain electrode (DE).

[0104] The planarization film (160) may include an organic insulating layer, an inorganic insulating layer, or a combination thereof. For example, the planarization film (160) may have a single layer or multilayer structure of silicon nitride or silicon oxide. When the planarization film (160) includes an organic insulating layer, it may include polyimide, acrylic resin, phenolic resin, benzocyclobutene (BCB), polyamide, etc.

[0105] Next, the flattening film (160) can be patterned to form a contact hole that exposes the drain electrode (DE), and a first electrode (E1) electrically connected to the drain electrode (DE) can be formed on the flattening film (160). For example, a third metal layer can be formed on the flattening film (160) and patterned to form a first electrode (E1) that contacts the drain electrode (DE) through the contact hole.

[0106] The first electrode (E1) may be a pixel electrode of the display device. Depending on the light emission type, the first electrode (E1) may be formed as a transmissive electrode or as a reflective electrode. When the first electrode (E1) is formed as a transmissive electrode, the first electrode (E1) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium oxide (In2O3), zinc oxide (ZnO), tin oxide (SnO2), etc. When the first electrode (E1) is formed as a reflective electrode, the first electrode (E1) may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), etc., and may have a stacked structure with the material used in the transmissive electrode.

[0107] A pixel defining film (170) can be formed on the planarization film (160). The pixel defining film (170) may have an opening that exposes at least a portion of the first electrode (E1). For example, the pixel defining film (170) may include an organic insulating material.

[0108] A light-emitting layer (180) can be formed on the first electrode (E1). The light-emitting layer (180) can be formed on the upper surface of the first electrode (E1) exposed by the opening of the pixel defining film (170). For example, the light-emitting layer (180) can be formed by methods such as screen printing, inkjet printing, or deposition.

[0109] The light-emitting layer (180) may include a low-molecular-weight organic compound or a high-molecular-weight organic compound. For example, the organic light-emitting layer (180) may include copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, etc. as the low-molecular-weight organic compound. Additionally, the light-emitting layer (180) may include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, and polyfluorene, etc. as the high-molecular-weight organic compound.

[0110] In one embodiment, the light-emitting layer (180) may emit red light, green light, or blue light. In another embodiment, when the light-emitting layer (180) emits white light, the light-emitting layer (180) may include a multilayer structure including a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, or a single layer structure including a red light-emitting material, a green light-emitting material, and a blue light-emitting material.

[0111] In one embodiment, a hole injection layer and / or a hole transport layer may be further formed between the first electrode (E1) and the light-emitting layer (180), or an electron transport layer and / or an electron injection layer may be further formed on the light-emitting layer (180).

[0112] A second electrode (E2) may be formed on the light-emitting layer (180). The second electrode (E2) may be a common electrode of the display device. Depending on the light-emitting type of the display device, the second electrode (E2) may be formed as a transparent electrode or as a reflective electrode. For example, when the second electrode (E2) is formed as a transparent electrode, the second electrode (E2) may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a combination thereof.

[0113] The display device (100) and transistor substrate (TR) formed in this manner can improve device characteristics by including a polycrystalline silicon layer manufactured according to one embodiment of the present invention, and a detailed description thereof will be given later with reference to FIG. 15, FIG. 16a, FIG. 16b and FIG. 17.

[0114] FIG. 15 is a graph showing the results of measuring the contact angle with water before crystallization of the amorphous silicon layer in the examples and comparative examples, FIG. 16a and FIG. 16b are photographs showing the surface of the polycrystalline silicon layer observed under a microscope in the examples and comparative examples, and FIG. 17 is a graph showing the number of defects in the examples and comparative examples.

[0115] The six samples shown on the horizontal axis in Fig. 15 are as follows.

[0116] Reference Example: Untreated amorphous silicon layer

[0117] Comparative Example 1: Sample in which the surface of an amorphous silicon layer was cleaned with hydrofluoric acid for 60 seconds

[0118] Example 1: A sample in which 1e14 atoms / cm² of phosphorus (P) was doped into a first amorphous silicon layer and 1e14 atoms / cm² of boron (B) was doped into a second amorphous silicon layer, and then washed with hydrofluoric acid for 60 seconds.

[0119] Comparative Example 2: A sample in which 1e12 atoms / cm² of phosphorus (P) is doped into a first amorphous silicon layer and 1e12 atoms / cm² of boron (B) is doped into a second amorphous silicon layer, and then washed with hydrofluoric acid for 60 seconds.

[0120] Example 2: A sample in which 1e14 atoms / cm² of phosphorus (P) was doped into a first amorphous silicon layer and 1e14 atoms / cm² of fluorine (F) was doped into a second amorphous silicon layer, and then washed with hydrofluoric acid for 60 seconds.

[0121] Comparative Example 3: A sample in which 1e12 atoms / cm² of phosphorus (P) is doped into a first amorphous silicon layer and 1e12 atoms / cm² of fluorine (F) is doped into a second amorphous silicon layer, and then washed with hydrofluoric acid for 60 seconds.

[0122] The results of measuring the contact angle with water on the surface of each sample are shown in FIG. 15. As shown in FIG. 15, in the case of Comparative Example 1, which was cleaned only with hydrofluoric acid, it was found that the contact angle was very large because the surface had hydrophobic characteristics. On the other hand, in the case of Examples 1 and 2, in which the surface was doped with P-type impurities at a concentration of 1 e14 atoms / cm² or more, it was confirmed that the contact angle was significantly lower. In addition, in the case of Comparative Examples 2 and 3, in which the concentration of P-type impurities did not reach 1 e14 atoms / cm² even after doping, it was confirmed that the contact angle remained high.

[0123] Next, device characteristics of a display device including a polycrystalline silicon layer obtained from Comparative Example 1 and Example 1 were measured. The measured values ​​are as follows.

[0125] Threshold voltage [V] Dr_range[V] Mobility [cm 2 / Vs] Hysteria[V] Comparative Example 1 -3.46 -3.30 64.32 0.182 Example 1 -3.26 -3.36 64.66 0.161

[0126] As shown in Table 1, the median threshold voltage (Vth) of Comparative Example 1 is -3.46, and the median threshold voltage (Vth) of Example 1 is -3.26, confirming that although additional doping was performed as in Example 1, the device characteristics were maintained at the same level. In addition, regarding the driving range (DR), mobility, and hysteresis (delta Vth), which is defined as the difference in threshold voltage (Vth), it was confirmed that Example 1, which was additionally doped, maintained the same level compared to Comparative Example 1, which was not doped.

[0127] Next, the results of observing the surface of the polycrystalline silicon layer obtained from Comparative Example 1 and Example 1 under a microscope are shown in FIGS. 16a, 16b, and 17.

[0128] As shown in FIG. 16a, circular stains occurred on the surface of the polycrystalline silicon layer of Comparative Example 1, whereas as shown in FIG. 16b, circular stains did not occur on the surface of the polycrystalline silicon layer of Example 1.

[0129] The total number of defects and the number of circular stains for samples of the same size were determined and are shown in FIG. 17. As shown in FIG. 17, compared to Comparative Example 1, the total number of defects in Example 1 was significantly reduced. In particular, regarding circular stains, 19 were observed in Comparative Example 1, whereas none were found in Example 1, confirming that it is significantly superior in reducing circular stains. That is, since a cleaning process using hydrofluoric acid was performed in Comparative Example 1 as well, protrusions on the surface of the polycrystalline silicon layer can be reduced, and thus fundamentally excellent device characteristics can be obtained. Furthermore, in the case of Example 1, excellent device characteristics can be maintained by retaining the advantages of such a cleaning process using hydrofluoric acid, while simultaneously significantly reducing circular stains on the surface.

[0130] In conclusion, it was confirmed that, according to one embodiment of the present invention, the polycrystalline silicon layer can prevent the occurrence of circular stains, in particular, without degrading device characteristics, thereby preventing pixel defects caused by circular stains.

[0131] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0132] 110: Substrate 120: Buffer layer 132: Amorphous silicon layer 132a: First amorphous silicon layer 132b: Second amorphous silicon layer D1: N-type impurity D2: P-type impurity 134: Polycrystalline silicon layer AP: Active pattern GE: Gate electrode SE: Source electrode DE: Drain electrode E1: First electrode 180: Organic light-emitting layer E2: Second electrode

Claims

Claim 1 A method for manufacturing a polycrystalline silicon layer comprising: forming a first amorphous silicon layer on a substrate; doping the first amorphous silicon layer with N-type impurities; forming a second amorphous silicon layer on the first amorphous silicon layer; doping the second amorphous silicon layer with P-type impurities to form an amorphous silicon layer; cleaning the amorphous silicon layer; and irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer, wherein the doping of the N-type impurities and the doping of the P-type impurities are carried out with substantially the same dose amount. Claim 2 A method for manufacturing a polycrystalline silicon layer according to claim 1, wherein the step of cleaning the amorphous silicon layer comprises: cleaning the amorphous silicon layer with hydrofluoric acid; and rinsing the amorphous silicon layer with deionized water. Claim 3 A method for manufacturing a polycrystalline silicon layer according to claim 1, wherein the thickness of the first amorphous silicon layer is 150 Å or more and 250 Å or less. Claim 4 A method for manufacturing a polycrystalline silicon layer according to claim 1, wherein the thickness of the second amorphous silicon layer is 150 Å or more and 250 Å or less. Claim 5 A method for manufacturing a polycrystalline silicon layer according to claim 1, wherein the doping of the N-type impurity is carried out at an acceleration voltage greater than 0 and less than or equal to 20 keV and a dose amount greater than or equal to 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm². Claim 6 A method for manufacturing a polycrystalline silicon layer according to claim 1, wherein the doping of the P-type impurity is carried out at an acceleration voltage greater than 0 and less than or equal to 20 keV and a dose amount greater than or equal to 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm². Claim 7 A method for manufacturing a polycrystalline silicon layer having a contact angle with water of less than 20 degrees measured on the surface of the amorphous silicon layer after the step of cleaning the amorphous silicon layer with hydrofluoric acid in paragraph 2. Claim 8 A display device comprising: a substrate; a thin-film transistor disposed on the substrate; and a display element disposed on the thin-film transistor, wherein the thin-film transistor comprises: an active pattern disposed on the substrate and including a source region, a drain region, and a channel region located between the source region and the drain region; a gate insulating film disposed on the active pattern; and a gate electrode disposed on the gate insulating film corresponding to the channel region, wherein the channel region comprises N-type impurities and P-type impurities, wherein the concentration of the P-type impurities is greater as it approaches the gate insulating film in the channel region, and wherein the concentration of the P-type impurities and the concentration of the N-type impurities within the channel region are substantially the same. Claim 9 delete Claim 10 A display device according to claim 8, wherein the concentration of N-type impurities is greater as it moves away from the gate insulating film in the channel region. Claim 11 A display device according to claim 8, wherein the P-type impurity is either boron (B) or fluorine (F). Claim 12 In paragraph 8, the N-type impurity is phosphorus (P), a display device. Claim 13 A display device according to claim 8, wherein the thickness of the active pattern is 300 Å or more and 500 Å or less. Claim 14 A display device according to claim 8, wherein the concentration of the P-type impurity in the channel region is 1e14 atoms / cm² or more and 1e16 atoms / cm² or less. Claim 15 A display device according to claim 8, wherein the concentration of the N-type impurity within the channel region is 1e14 atoms / cm² or more and 1e16 atoms / cm² or less. Claim 16 delete Claim 17 A display device according to claim 8, wherein the thin-film transistor further comprises a source electrode and a drain electrode disposed on the gate electrode and electrically connected to the source region and the drain region, respectively. Claim 18 In claim 8, the display element comprises: a first electrode electrically connected to the thin-film transistor; a light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer, a display device. Claim 19 A method for manufacturing a display device comprising the steps of: forming a first amorphous silicon layer on a substrate; doping the first amorphous silicon layer with N-type impurities; forming a second amorphous silicon layer on the first amorphous silicon layer; doping the second amorphous silicon layer with P-type impurities to form an amorphous silicon layer; cleaning the amorphous silicon layer; irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer; etching the polycrystalline silicon layer to form a polycrystalline silicon pattern; forming a gate insulating film on the polycrystalline silicon pattern; forming a gate electrode on the gate insulating film; partially implanting ions into the polycrystalline silicon pattern to form an active pattern including a source region, a drain region, and a channel region; and forming a display element on the gate electrode, wherein the doping of the N-type impurities and the doping of the P-type impurities are carried out with substantially the same dose amount. Claim 20 A method for manufacturing a display device according to claim 19, wherein the step of cleaning the amorphous silicon layer comprises: cleaning the amorphous silicon layer with hydrofluoric acid; and rinsing the amorphous silicon layer with deionized water. Claim 21 A method for manufacturing a display device according to claim 19, wherein the doping of the N-type impurity is carried out at an acceleration voltage greater than 0 and less than or equal to 20 keV and a dose amount greater than or equal to 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm². Claim 22 A method for manufacturing a display device according to claim 19, wherein the doping of the P-type impurity is carried out at an acceleration voltage greater than 0 and less than or equal to 20 keV and a dose amount greater than or equal to 1e14 atoms / cm² and less than or equal to 1e16 atoms / cm². Claim 23 A method for manufacturing a display device according to claim 19, wherein the contact angle with water measured on the surface of the amorphous silicon layer is less than 20 degrees after the step of cleaning the amorphous silicon layer with hydrofluoric acid. Claim 24 In claim 19, the step of partially implanting ions into the polycrystalline silicon pattern is a method for manufacturing a display device in which ions are implanted only into the portions corresponding to the source region and drain region using the gate electrode as a mask. Claim 25 A method for manufacturing a display device according to claim 19, further comprising the step of forming a source electrode and a drain electrode on the gate electrode that are electrically connected to the source region and the drain region, respectively. Claim 26 A method for manufacturing a display device according to claim 19, wherein the step of forming the display element comprises: forming a first electrode electrically connected to the active pattern on the gate electrode; forming a light-emitting layer on the first electrode; and forming a second electrode on the light-emitting layer.

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