Transmitter for transmitting duo binary signal

Abstract

A transmitter according to the present invention is a transmitter that generates a duobinary signal corresponding to Level 0, Level 1, or Level 2 according to first data and second data, and comprises: a pull-up driving circuit including a plurality of pull-up resistors selectively connected between a first power source and a transmitting node according to first data or second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively connected between a transmitting node and a second power source according to first data or second data, wherein at least one of the plurality of pull-up resistors is connected between the first power source and the transmitting node when at least one of the first data and the second data is activated, or at least one of the plurality of pull-down resistors is connected between the second power source and the transmitting node when at least one of the first data and the second data is activated.

Description

Technology Field

[0001] The present invention relates to a transmitter that transmits a duobinary signal. Background Technology

[0002] Figure 1 is a circuit diagram showing a conventional transmitter (1).

[0003] A conventional transmitter (1) includes a pull-up drive circuit (10) and a pull-down drive circuit (20).

[0004] The pull-up drive circuit (10) is connected between the first power supply (VDD) and the transmitting node (Nt), and the pull-down drive circuit (20) is connected between the transmitting node (Nt) and the second power supply (GND).

[0005] The pull-up driving circuit (10) includes a PMOS transistor (MP1) and a pull-up resistor (RU1) sequentially connected between the first power supply (VDD) and the transmitting node (Nt).

[0006] The first data (D1) is input to the gate of the PMOS transistor (MP1).

[0007] The pull-up driving circuit (10) further includes a PMOS transistor (MP2) and a pull-up resistor (RU2) sequentially connected between the first power supply (VDD) and the transmitting node (Nt).

[0008] The second data (D2) is input to the gate of the PMOS transistor (MP2).

[0009] The pull-down driving circuit (20) includes a pull-down resistor (RD1) and an NMOS transistor (MN1) sequentially connected between the transmitting node (Nt) and the second power supply (GND).

[0010] The first data (D1) is input to the gate of the NMOS transistor (MN1).

[0011] The pull-down driving circuit (20) further includes a pull-down resistor (RD2) and an NMOS transistor (MN2) sequentially connected between the transmitting node (Nt) and the second power supply (GND).

[0012] The second data (D2) is input to the gate of the NMOS transistor (MN2).

[0013] A channel (3) having the form of a microstrip or the like is located between the transmitting node (Nt) and the receiving node (Nr).

[0014] The receiver (2) includes a termination resistor (Rt) connected between the first power source (VDD) and the receiving node (Nr).

[0015] In FIG. 1, when both the first data (D1) and the second data (D2) are at a low level, it corresponds to level 2 of the duobinary signal; when the first data (D1) is at a high level and the second data (D2) is at a low level, it corresponds to level 1 of the duobinary signal; and when both the first data (D1) and the second data (D2) are at a high level, it corresponds to level 0 of the duobinary signal.

[0016] For example, according to the GDDR standard, the termination resistor (Rt) is set to 60 ohms, and according to the conventional duo-binary transmitter specifications, the size of the pull-up resistors (RU1, RU2) is set to 120 ohms so that the total size of the pull-up resistor is 60 ohms, and the size of the pull-down resistors (RD1, RD2) is assumed to be 80 ohms so that the total size of the pull-down resistor is 40 ohms.

[0017] The received voltage (Vr) of the receiving node (Nr) is calculated through DC analysis as follows.

[0018] At level 2, the receiving voltage (Vr) of the receiving node (Nr) is the power supply voltage (VDD), at level 1, the receiving voltage (Vr) is 2 / 3 of the power supply voltage (VDD), and at level 0, the receiving voltage (Vr) is 4 / 7 of the power supply voltage (VDD).

[0019] The interval between level 2 and level 1 is 7 / 21 VDD, and the interval between level 1 and level 0 is 2 / 21 VDD, so the interval between levels is not constant.

[0020] As such, conventional transmitters have a problem in which significant bit errors occur during reception because the intervals between the levels of the duobinary signal are not constant. Prior art literature

[0021] KR 10-2020-0041424 AUS 2020 / 0007362 A1 The problem to be solved

[0022] This technology provides a transmitter that reduces the occurrence of errors by maintaining a constant spacing between adjacent levels when transmitting duobinary signals. means of solving the problem

[0023] A transmitter according to one embodiment of the present invention is a transmitter that generates a duobinary signal corresponding to level 0, level 1, or level 2 according to first data and second data, and comprises: a pull-up driving circuit including a plurality of pull-up resistors selectively connected between a first power source and a transmitting node according to first data or second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively connected between a transmitting node and a second power source according to first data or second data, wherein at least one of the plurality of pull-up resistors is connected between the first power source and the transmitting node when at least one of the first data and the second data is activated, or at least one of the plurality of pull-down resistors is connected between the second power source and the transmitting node when at least one of the first data and the second data is activated. Effects of the invention

[0024] This technology can reduce the occurrence of errors when transmitting duobinary signals by maintaining a constant interval between adjacent levels. Brief explanation of the drawing

[0025] FIG. 1 is a circuit diagram showing a transmitter according to the prior art. FIG. 2 is a circuit diagram showing a transmitter according to one embodiment of the present invention. FIG. 3 is a circuit diagram showing a transmitter according to another embodiment of the present invention. Specific details for implementing the invention

[0026] Embodiments of the present invention are disclosed below with reference to the attached drawings.

[0027] FIG. 2 is a circuit diagram showing a transmitter (100) according to one embodiment of the present invention.

[0028] The transmitter (100) according to the present embodiment includes a pull-up driving circuit (110) and a pull-down driving circuit (120).

[0029] The pull-up drive circuit (110) is connected between the first power supply (VDD) and the transmitting node (Nt), and the pull-down drive circuit (120) is connected between the transmitting node (Nt) and the second power supply (GND).

[0030] The pull-up driving circuit (110) includes a first PMOS transistor (MP1) and a second PMOS transistor (MP2) to which a first data (D1) is input to the gate and the source is connected to a first power supply (VDD), and includes a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4) to which a second data (D2) is input to the gate and the source is connected to a first power supply (VDD).

[0031] The pull-up driving circuit (110) includes a first pull-up resistor (RU1) connected between the drain of the first PMOS transistor (MP1) and the transmitting node (Nt), a second pull-up resistor (RU2) connected between the drain of the second PMOS transistor (MP2) and the third PMOS transistor (MP3) and the transmitting node (Nt), and a third pull-up resistor (RU3) connected between the drain of the fourth PMOS transistor (MP4) and the transmitting node (Nt).

[0032] The pull-down driving circuit (120) includes a first pull-down resistor (RD1) and a second pull-down resistor (RD2), one end of which is connected to a transmitting node (Nt).

[0033] The pull-down driving circuit (120) includes a first NMOS transistor (MN1) connected between the other end of the first pull-down resistor (RD1) and the second power supply (GND), with the first data (D1) input to the gate.

[0034] The pull-down driving circuit (120) includes a second NMOS transistor (MN2) connected between the other end of the second pull-down resistor (RD2) and the second power supply (GND), with the second data (D2) input to the gate.

[0035] A channel (3) having the form of a microstrip or the like is located between the transmitting node (Nt) and the receiving node (Nr).

[0036] The receiver (2) includes a termination resistor (Rt) connected between the first power source (VDD) and the receiving node (Nr).

[0037] In FIG. 2, when both the first data (D1) and the second data (D2) are at a low level, it corresponds to level 2 of the duobinary signal; when one of the first data (D1) and the second data (D2) is at a low level and the other is at a high level, it corresponds to level 1 of the duobinary signal; and when both the first data (D1) and the second data (D2) are at a high level, it corresponds to level 0 of the duobinary signal.

[0038] In this embodiment, the termination resistance (Rt) is assumed to be 60 ohms.

[0039] In this embodiment, the first pull-up resistor (RU1) and the third pull-up resistor (RU3) have the same size, and the first pull-down resistor (RD1) and the second pull-down resistor (RD2) have the same size.

[0040] In addition, the sizes of the first pull-up resistor (RU1) and the second pull-up resistor (RU2) are set differently.

[0041] In this embodiment, unlike conventional methods, a second pull-up resistor (RU2) connected between the first power supply (VDD) and the transmitting node (Nt) at level 1 is additionally provided to allow the spacing between levels to be adjusted to a constant level.

[0042] In this embodiment, in order to make the total pull-up resistor size 60 ohms, the size of the first pull-up resistor (RU1) and the third pull-up resistor (RU3) is assumed to be 240 ohms, and the size of the second pull-up resistor (RU2) is assumed to be 120 ohms.

[0043] In addition, to make the total pull-up resistor size 40 ohms, the size of the first pull-down resistor (RD1) and the second pull-down resistor (RD2) is assumed to be 80 ohms.

[0044] The received voltage (Vr) of the receiving node (Nr) is calculated through DC analysis as follows.

[0045] In this embodiment, the receiving voltage (Vr) of the receiving node (Nr) at level 2 is the power supply voltage (VDD), the receiving voltage (Vr) at level 1 is 7 / 10 VDD, and the receiving voltage (Vr) at level 0 is 4 / 10 VDD.

[0046] At this time, the interval between level 2 and level 1 and the interval between level 1 and level 0 is constant at 3 / 10 VDD.

[0047] In this way, the present invention can set the interval between level 2 and level 1 of the duobinary signal and the interval between level 1 and level 0 to be the same by simply modifying the configuration of the pull-up driving circuit (110).

[0048] FIG. 3 is a circuit diagram showing a transmitter (200) according to another embodiment of the present invention.

[0049] The transmitter (200) includes a pull-up drive circuit (210) and a pull-down drive circuit (220).

[0050] The pull-up drive circuit (210) is connected between the first power supply (VDD) and the transmitting node (Nt), and the pull-down drive circuit (220) is connected between the transmitting node (Nt) and the second power supply (GND).

[0051] The pull-up driving circuit (210) includes a first pull-up resistor (RU1) and a second pull-up resistor (RU2), one end of which is connected to a transmitting node (Nt).

[0052] The pull-up driving circuit (210) includes a first PMOS transistor (MP1) whose drain is connected to the other end of the first pull-up resistor (RU1), whose source is connected to the first power supply (VDD), and whose gate is input to the first data (D1).

[0053] The pull-up driving circuit (210) includes a second PMOS transistor (MP2) whose drain is connected to the other end of the second pull-up resistor (RU2), whose source is connected to the first power supply (VDD), and whose gate is input to the second data (D2).

[0054] The pull-down driving circuit (220) includes a first pull-down resistor (RD1), a second pull-down resistor (RD2), and a third pull-down resistor (RD3), each having one end connected to a transmitting node (Nt).

[0055] The pull-down driving circuit (220) includes a first NMOS transistor (MN1) whose drain is connected to the other end of the first pull-down resistor (RD1), whose source is connected to a second power source, and to which a first data (D1) is applied to its gate.

[0056] The pull-down driving circuit (220) includes a second NMOS transistor (MN2) whose drain is connected to the other end of the second pull-down resistor (RD2), whose source is connected to the second power supply, and to which the first data (D1) is applied to the gate.

[0057] The pull-down driving circuit (220) includes a third NMOS transistor (MN3) whose drain is connected to the other end of the second pull-down resistor (RD2), whose source is connected to the second power supply, and to which the second data (D2) is applied to the gate.

[0058] The pull-down driving circuit (220) includes a fourth NMOS transistor (MN4) whose drain is connected to the other end of the third pull-down resistor (RD3), whose source is connected to a second power source, and to which a second data (D2) is applied to its gate.

[0059] A channel (3) having the form of a microstrip or the like is located between the transmitting node (Nt) and the receiving node (Nr).

[0060] The receiver (4) includes a termination resistor (Rt) connected between the second power source (GND) and the receiving node (Nr).

[0061] In FIG. 3, when both the first data (D1) and the second data (D2) are at a low level, it corresponds to level 2 of the duobinary signal; when one of the first data (D1) and the second data (D2) is at a high level and the other is at a low level, it corresponds to level 1 of the duobinary signal; and when both the first data (D1) and the second data (D2) are at a high level, it corresponds to level 0 of the duobinary signal.

[0062] In the embodiment of FIG. 3, the termination resistance (Rt) is assumed to be 60 ohms.

[0063] In the embodiment of FIG. 3, the first pull-up resistor (RU1) and the second pull-up resistor (RU2) have the same size, and the first pull-down resistor (RD1) and the third pull-down resistor (RD3) have the same size.

[0064] In addition, the sizes of the first pull-down resistor (RD1) and the second pull-down resistor (RD2) are set differently.

[0065] Unlike the conventional embodiment of FIG. 3, a second pull-down resistor (RD2) connected between the second power supply (GND) and the transmitting node (Nt) at level 1 is additionally provided to allow the spacing between levels to be adjusted to a constant level.

[0066] In the embodiment of FIG. 3, in order to make the total pull-up resistor size 40 ohms, the sizes of the first pull-up resistor (RU1) and the second pull-up resistor (RU2) are assumed to be 80 ohms.

[0067] In addition, to make the total pull-down resistor size 60 ohms, the size of the first pull-down resistor (RD1) and the third pull-down resistor (RD3) is assumed to be 240 ohms, and the size of the second pull-down resistor (RD2) is assumed to be 120 ohms.

[0068] The received voltage (Vr) of the receiving node (Nr) is calculated through DC analysis as follows.

[0069] In the embodiment of FIG. 3, the receiving voltage (Vr) of the receiving node (Nr) at level 2 is 6 / 10 VDD, the receiving voltage (Vr) at level 1 is 3 / 10 VDD, and the receiving voltage (Vr) at level 0 is 0 VDD.

[0070] At this time, the interval between level 2 and level 1 and the interval between level 1 and level 0 is constant at 3 / 10 VDD.

[0071] In this way, the present invention can set the interval between level 2 and level 1 of the duobinary signal and the interval between level 1 and level 0 to be the same by simply modifying the configuration of the pull-down driving circuit (220).

[0072] Through this, the quality of the transmitted duobinary signal can be improved in the present invention.

[0073] The scope of the present invention is not limited to the disclosure above. The scope of the present invention should be interpreted based on the scope literally described in the claims and their equivalents. Explanation of the symbols

[0074] 1, 100, 200: Transmitter 2, 4: Receiver Channel 3: Channel 10, 110, 210: Pull-up driver circuit 20, 120, 220: Pull-down drive circuit

Claims

Claim 1 delete Claim 2 A transmitter that generates a duobinary signal corresponding to Level 0, Level 1, or Level 2 according to first data and second data, comprising: a pull-up driving circuit including a plurality of pull-up resistors selectively connected between a first power source and a transmitting node according to the first data or the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively connected between the transmitting node and a second power source according to the first data or the second data, wherein the pull-up driving circuit includes a first pull-up resistor connected between the first power source and the transmitting node according to the first data; a second pull-up resistor connected between the first power source and the transmitting node according to the first data or the second data; and a third pull-up resistor connected between the first power source and the transmitting node according to the second data. Claim 3 A transmitter according to claim 2, wherein the pull-up driving circuit further comprises: a transistor connecting the first pull-up resistor between the first power source and the transmitting node according to the first data; a transistor connecting the second pull-up resistor between the first power source and the transmitting node according to the first data; a transistor connecting the second pull-up resistor between the first power source and the transmitting node according to the second data; and a transistor connecting the third pull-up resistor between the first power source and the transmitting node according to the second data. Claim 4 A transmitter according to claim 2, wherein the pull-down driving circuit comprises: a first pull-down resistor connected between the transmitting node and the second power source according to the first data; and a second pull-down resistor connected between the transmitting node and the second power source according to the second data. Claim 5 A transmitter according to claim 4, wherein the pull-down driving circuit further comprises: a transistor connecting the first pull-down resistor between the second power source and the transmitting node according to the first data; and a transistor connecting the second pull-down resistor between the second power source and the transmitting node according to the second data. Claim 6 A transmitter that generates a duobinary signal corresponding to Level 0, Level 1, or Level 2 according to first data and second data, comprising: a pull-up driving circuit including a plurality of pull-up resistors selectively connected between a first power source and a transmitting node according to the first data or the second data; and a pull-down driving circuit including a plurality of pull-down resistors selectively connected between the transmitting node and a second power source according to the first data or the second data, wherein the pull-down driving circuit includes a first pull-down resistor connected between the second power source and the transmitting node according to the first data; a second pull-down resistor connected between the second power source and the transmitting node according to the first data or the second data; and a third pull-down resistor connected between the second power source and the transmitting node according to the second data. Claim 7 A transmitter according to claim 6, wherein the pull-down driving circuit further comprises: a transistor connecting the first pull-down resistor between the second power source and the transmitting node according to the first data; a transistor connecting the second pull-down resistor between the second power source and the transmitting node according to the first data; a transistor connecting the second pull-down resistor between the second power source and the transmitting node according to the second data; and a transistor connecting the third pull-down resistor between the second power source and the transmitting node according to the second data. Claim 8 A transmitter according to claim 6, wherein the pull-up driving circuit comprises: a first pull-up resistor connected between the transmitting node and the first power source according to the first data; and a second pull-up resistor connected between the transmitting node and the first power source according to the second data. Claim 9 A transmitter according to claim 8, wherein the pull-up driving circuit further comprises: a transistor connecting the first pull-up resistor between the first power source and the transmitting node according to the first data; and a transistor connecting the second pull-up resistor between the first power source and the transmitting node according to the second data.

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