Overlay Design for Electron Beam and Scatter Measurement Overlays

Abstract

Combined electron beam overlay and scattering measurement overlay targets include first and second periodic structures having gratings. The gratings in the second periodic structure may be located below the gratings of the first periodic structure or between the gratings of the first periodic structure. These overlay targets can be used in semiconductor manufacturing.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This disclosure is based on and claims priority to U.S. Provisional Application No. 63 / 215,551 filed on June 28, 2021, the full text of which is incorporated herein by reference.

[0003] Technology field

[0004] The present disclosure relates to overlay measurement in a semiconductor device. Background Technology

[0005] The evolution of the semiconductor manufacturing industry is increasing the demand for yield management, and in particular, for metrology and inspection systems. While critical dimension (CD) continues to shrink, the industry requires time reduction to achieve high-yield, high-value-added production. Minimizing the total time required from the detection of yield issues to their resolution determines the return on investment for semiconductor manufacturers.

[0006] Manufacturing semiconductor devices, such as logic devices and memory devices, typically involves processing a semiconductor wafer using many manufacturing processes to form various features and multiple levels of the semiconductor device. For example, lithography is a semiconductor manufacturing process that involves transferring a pattern from a reticle onto a photoresist arranged on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical-mechanical polishing (CMP), etching, deposition, and ion implantation. Multiple semiconductor devices may be manufactured arranged on a single semiconductor wafer and separated into individual semiconductor devices.

[0007] The relative positions of structures within a semiconductor device are called overlays (OVL). Measuring the overlay error between consecutive patterned layers on a wafer is a process control technique used in the manufacture of integrated circuits. Overlay accuracy generally concerns determining how accurately a first patterned layer is aligned with respect to a second patterned layer placed above or below it, and determining how accurately the first pattern is aligned with respect to a second pattern placed on the same layer.

[0008] Metrology processes are used at various stages during the semiconductor manufacturing process to monitor and control one or more semiconductor layer processes. Overlay measurements generally specify how accurately a first patterned layer is aligned with respect to a second patterned layer placed above or below it, or how accurately a first pattern is aligned with respect to a second pattern placed on the same layer. Overlay error is one of the characteristics that is monitored and controlled. Overlay error is typically determined using an overlay target having structures formed on one or more layers of a workpiece (e.g., a semiconductor wafer). If two layers or patterns are properly formed, structures on one layer or pattern tend to be aligned with structures on the other layer or pattern. If two layers or patterns are not properly formed, structures on one layer or pattern tend to be offset or misaligned with respect to structures on the other layer or pattern. Overlay error is misalignment between any patterns used at different stages of the semiconductor manufacturing process.

[0009] Overlay metrology targets are printed to measure alignment between two or more layers. Structures on the wafer can take the form of grids, and these grids can be periodic. If two layers or patterns are properly formed, a structure on one layer or pattern can be aligned with respect to a structure on another layer or pattern.

[0010] Various technologies and processes for overlay measurement are being developed and adopted with varying degrees of success. Overlay measurement has become a technique that helps enable lithographic patterning. Overlay measurement is performed by various algorithms that extract an overlay term from the asymmetry of the target. Overlay measurement targets are designed so that the overlay can induce an asymmetric signature from the reflected signal.

[0011] Current optical overlay measurement methods rely on two main techniques: imaging and scattermechanics. Scattering overlay measurements and imaging-based overlay measurements use different target designs due to their different measurement methods. In imaging, the positions of periodic targets are measured within the field of view of an optical system, and the overlay is inferred from the positions of targets printed on different layers. Scattering infers the relative displacement of the layers by utilizing the interference between electromagnetic (EM) waves scattered by periodic overlay marks (targets with periodic structures) printed on different layers. In both cases, control over the amplitude and phase of the diffraction order of the scattered electromagnetic waves can affect the accuracy and precision of the overlay measurement.

[0012] When overlay error is observed, overlay measurements can be used to apply corrections and keep the overlay error within desired limits. For example, overlay measurements can be fed to an analysis routine that calculates scanner corrections, as well as other statistics that may be used by an operator to better align the lithography tools used in the process. In typical manufacturing operations, the semiconductor manufacturing process is executed in batches called lots. A lot, or wafer lot, is defined as a quantity of wafers processed together as a single group. Conventional overlay monitoring and control techniques generally take a single set of scanner corrections and apply the same set to all wafers within the same lot.

[0013] However, as semiconductor devices become more complex, improved target designs and measurement methods are required.

[0014] Embodiments of the present disclosure provide a target. The target may include a first periodic structure formed on a first layer of a semiconductor device. Each of a plurality of grids in the first periodic structure may have a first width along a first axis and a first height along a second axis. The first periodic structure may have a first pitch. The target may further include a second periodic structure formed on a second layer of a semiconductor device. Each of a plurality of grids in the second periodic structure may have a second width along a first axis and a second height along a second axis. The second width may be narrower than the first width. The second periodic structure may have a second pitch that is smaller than the first pitch. The grids of the first periodic structure may be positioned to overlap with the grids of the second periodic structure. The first periodic structure and the second periodic structure may provide electron beam overlay measurements and scattering measurement overlay measurements.

[0015] According to an embodiment of the present disclosure, the first height may be longer than the second height. The second periodic structure may be composed of two arrays. The grids of the first periodic structure may extend along a second axis across each of the arrays of the second periodic structure.

[0016] According to an embodiment of the present disclosure, the second periodic structure may extend beyond the first periodic structure along the first axis.

[0017] According to an embodiment of the present disclosure, a first periodic structure and a second periodic structure may be in a first array. The target may further include a second array of the first periodic structure and the second periodic structure. The second periodic structure in the second array may extend beyond the first periodic structure in a direction along a second axis from the second periodic structure of the first array.

[0018] According to an embodiment of the present disclosure, the target may further include a third array of a first periodic structure and a third array and a fourth array of a second periodic structure. The first height may be longer than the second height, and the grids of the first periodic structure in the third array may extend along a second axis across the third array and the fourth array of the second periodic structure.

[0019] According to an embodiment of the present disclosure, four arrays of a first periodic structure and a second periodic structure may be arranged such that two of the four arrays are oriented perpendicularly to the other two of the four arrays. The second periodic structure may extend beyond the first periodic structure along a second axis. Each of the grids in the first periodic structures may define a gap along the second axis. The second periodic structure may be exposed through the gap, and the first periodic structure extends beyond the second periodic structure along the second axis.

[0020] Another embodiment of the present disclosure may provide a target. The target may include a first periodic structure formed on a first layer of a semiconductor device. Each of a plurality of grids in the first periodic structure may have a first width along a first axis and a first height along a second axis, and the first periodic structure has a first pitch. The target may further include a second periodic structure formed on a second layer of a semiconductor device. Each of a plurality of grids in the second periodic structure may have a second width and a second height. The second width may be the same as the first width. The second periodic structure may have a second pitch equal to the first pitch, and the grids of the first periodic structure are disposed between the grids of the second periodic structure. The first periodic structure and the second periodic structure may provide electron beam overlay measurements and scattering measurement overlay measurements.

[0021] According to an embodiment of the present disclosure, four arrays of a first periodic structure and a second periodic structure may be arranged such that two of the four arrays are oriented perpendicularly to the other two of the four arrays.

[0022] According to an embodiment of the present disclosure, a second periodic structure may extend beyond a first periodic structure along a second axis on one side of each of the arrays, and a first periodic structure may extend beyond a second periodic structure along a second axis on the opposite side of each of the arrays.

[0023] According to an embodiment of the present disclosure, each of the grids in the first periodic structures may define a gap along a second axis. The second periodic structure may extend beyond the first periodic structure in the gap along the second axis in each of the arrays.

[0024] Another embodiment of the present disclosure provides a method. The method may include the step of providing a target. The target may include a first periodic structure formed on a first layer of a semiconductor device. Each of a plurality of grids in the first periodic structure may have a first width along a first axis and a first height along a second axis, and the first periodic structure may have a first pitch. The target may also include a second periodic structure formed on a second layer of a semiconductor device. Each of a plurality of grids in the second periodic structure may have a second width and a second height.

[0025] The present method may further include the step of performing electron beam overlay measurements and scattering measurement overlay measurements on a target using at least one semiconductor metrology tool.

[0026] According to an embodiment of the present disclosure, the second width may be narrower than the first width. The second periodic structure may have a second pitch smaller than the first pitch, and the grids of the first periodic structure are positioned on the grids of the second periodic structure.

[0027] According to an embodiment of the present disclosure, the first height may be longer than the second height. The second periodic structure may be composed of two arrays, and the grids of the first periodic structure may extend along the second axis across each of the arrays of the second periodic structure.

[0028] According to an embodiment of the present disclosure, a first periodic structure and a second periodic structure may be in a first array. The target may further include a second array of the first periodic structure and the second periodic structure. The second periodic structure in the second array may extend beyond the first periodic structure in a direction along a second axis from the second periodic structure of the first array.

[0029] According to an embodiment of the present disclosure, the second periodic structure may extend beyond the first periodic structure along the first axis and the second axis.

[0030] According to an embodiment of the present disclosure, four arrays of a first periodic structure and a second periodic structure may be arranged such that two of the four arrays are oriented perpendicularly to the other two of the four arrays.

[0031] According to an embodiment of the present disclosure, a second periodic structure may extend beyond a first periodic structure along a second axis on one side of each of the arrays, and a first periodic structure may extend beyond a second periodic structure along a second axis on the opposite side of each of the arrays.

[0032] According to an embodiment of the present disclosure, each of the grids in the first periodic structures may define a gap along a second axis, and the first periodic structure may extend beyond the second periodic structure along the second axis in each of the arrays.

[0033] According to an embodiment of the present disclosure, the second width may be the same as the first width, and the second periodic structure may have a second pitch that is the same as the first pitch. The grids of the first periodic structure may be located between the grids of the second periodic structure.

[0034] According to an embodiment of the present disclosure, four arrays of a first periodic structure and a second periodic structure may be arranged such that two of the four arrays are oriented perpendicularly to the other two of the four arrays.

[0035] According to an embodiment of the present disclosure, a second periodic structure may extend beyond a first periodic structure along a second axis on one side of each of the arrays, and a first periodic structure may extend beyond a second periodic structure along a second axis on the opposite side of each of the arrays.

[0036] According to an embodiment of the present disclosure, each of the grids in the first periodic structures may define a gap along a second axis, and the second periodic structure may extend beyond the second periodic structure in the gap along the second axis in each of the arrays.

[0037] Another embodiment of the present disclosure provides a semiconductor measurement tool. The semiconductor measurement tool may be configured to perform an overlay measurement on any one of the targets of the present disclosure. Brief explanation of the drawing

[0038] For a more full understanding of the nature and purpose of the present disclosure, the following specific details taken in connection with the accompanying drawings should be referenced, in which: FIG. 1 is an exemplary scattering measurement overlay target; FIG. 2 shows a combined electron beam overlay and a scattering measurement overlay target; FIG. 3 shows another combined electron beam overlay and scattering measurement overlay target; FIG. 4 shows another combined electron beam overlay and scattering measurement overlay target; FIG. 5 shows another combined electron beam overlay and scattering measurement overlay target; FIG. 6 shows another combined electron beam overlay and scattering measurement overlay target; FIG. 7 is a combined electron beam overlay and scattering measurement overlay target having a region of interest in the center; FIG. 8 is a combined electron beam overlay and scattering measurement overlay target having a region of interest in the center; FIG. 9 is a flowchart of a method according to the present disclosure; and FIG. 10 is an illustration of a system according to the present disclosure. Specific details for implementing the invention

[0039] While the claimed subject matter will be described in terms of specific embodiments, other embodiments are also within the scope of this disclosure, including embodiments that do not provide all of the advantages and features set forth herein. Various structural, logical, process steps, and electronic modifications may be made without departing from the scope of this disclosure. Accordingly, the scope of this disclosure is defined only by reference to the appended claims.

[0040] Generally, an overlay error between two process layers or a shift between two sets of structures on the same layer can be determined using overlay targets, for this purpose the target structures are designed to have a known relationship between their symmetry characteristics, and a discrepancy from such symmetry corresponds to an overlay error in the targets. As used herein, a layer may refer to any suitable material, such as a semiconductor or photoresist layer, that is created and patterned for the manufacture of a wafer device or a test structure. The following target examples are presented as having structures on two (or more) layers for overlay measurement, but each target may include two (or more) sets of structures on the same layer to determine a shift error between such sets of structures. Additionally, embodiments of the present disclosure may be applied to any type of periodic targets, and such targets may be formed as an inactive region (e.g., a scribe line) or an active region (e.g., part of the device portion of the die) of a die on a production wafer. The techniques described in this specification may also be applied to targets to determine other types of characteristics, such as critical dimension (CD), CD uniformity (CDU), edge placement error (EPE), pattern fidelity, etc.

[0041] Overlay targets typically occupy expensive locations on integrated circuits. Semiconductor manufacturers generally seek to reduce the measurement time and wafer area required for these overlay targets. Wafer space can be saved, measurement times can be faster, and the results of the two technologies can be compared by combining imaging-based and scattering-based targets. Accordingly, including two targets within an integrated circuit area and measuring both overlay targets simultaneously will provide advantages to the semiconductor manufacturing process.

[0042] The embodiments disclosed herein combine electron beam overlay (eOVL) and scatterometry overlay (SCOL). Currently, scanning electron microscopy (SEM) technology is used as a ruler for optical measurement. The embodiments disclosed herein provide solutions utilizing novel target designs for electron beam overlay for combination with optical measurement. Target prototypes can also combine optical image-based overlay (IBO) and diffraction-based overlay (DBO) targets (as illustrated in FIG. 5) with electron beam overlay specialized targets. Alternating the combined targets enables denser sampling, which can increase model accuracy, because the number of measurement samples on the wafer increases while maintaining the same wafer real estate. The combined targets provide a 2x increased number of targets for both technologies, utilizing 100% of the real estate available for overlay measurement.

[0043] The target designs disclosed herein can reduce measurement move acquisition measurement (MAM) time and improve measurement accuracy because regions of interest (ROIs) can contain both X information content and Y information content within a small field of view (FOV). For example, in a single ROI, one grid may be for information in the X direction and another grid may be for information in the Y direction. Since all information is contained within a single target, there may be no need to move to two different targets. Accordingly, the disclosed targets increase information content per area.

[0044] Measurements can be applied to the rough and fine pitches of different target archetypes. Target layer materials may differ between line and spatial features. Inverse combination use cases allow the use of current optical targets with denser sampling of electron beam overlay targets. A combined design of a 4-cell scattering overlay and an electron beam overlay can also be used.

[0045] The embodiments disclosed herein may enable scatter measurement target axis separation by including two cells per direction, as in a standard 4-cell design, and bars extending in both directions for each layer per cell. This may provide physical separation between layers of different alignment methods. The placement of regions of interest on such a target type may be separated for each layer. This is because multiple regions of interest used per direction target a bar-over-bar and bar-over-trench architecture having induced overlays. This may be used for a scatter measurement target (f0) that is measurable regardless of its shift coverage (e.g., FIGS. 1 to 3). Bidirectional application may also be possible within the same target having axially extended bars (e.g., FIGS. 4 to 8).

[0046] Arbitrary design image-based or diffraction-based overlays can align the electron beam overlay target, the center of the electron beam overlay, and the optical target. This can eliminate process variation effects and placement error effects, and improve the ability to correct modeled terms. Due to design rules, the electron beam overlay target can be placed as close as possible to the optical target. To process very small semiconductor structures, special illumination conditions (e.g., annular, structured, etc.) may be used during the lithography step. These illumination conditions can be optimized for a specific process step and may be favorable only for specific pattern shapes (e.g., diagonal). The pattern shapes allowed for a specific process step may be defined by so-called "design rules." Patterns that violate design rules (e.g., standard target design) may experience processing problems. It may be desirable to design targets that adhere to design rules for actual device patterns.

[0047] Additional segments may be added to the optical target to fill the space occupied by the placement of electron beam overlay targets or the extension of bars, which can enable more information content.

[0048] FIG. 1 is an exemplary scattering measurement overlay target. The overlay target includes a first periodic structure (101) and a second periodic structure (102). These are shown in different shades for convenience of illustration. The first periodic structure (101) is formed on a first layer of a semiconductor device and has a first pitch along an axis, and the second periodic structure (102) is formed on a second layer of a semiconductor device and has a second pitch different from the first pitch along the corresponding axis. Dummy structures may be used to fill empty areas (e.g., white areas in FIG. 1) of the target (100) (or other targets of the present disclosure) or to gradually change between large and small structures without interfering with the target design. In FIG. 1, "previous" refers to the first layer and "current" refers to the second layer. "CD" refers to a critical dimension corresponding to the width of the first periodic structure (101) and the width of the second periodic structure (102). "Pitch" describes the distance between two adjacent structures in the first periodic structure (101) and the second periodic structure (102). When properly illuminated, the first and second periodic structures (101, 102) form a pattern together. The layers may be adjacent to each other or separated by other layers. The first periodic structure (101) and the second periodic structure (102) are illustrated transparently for convenience of illustration.

[0049] For each of the drawings of FIG. 1, corresponding side cross-sectional views of the first periodic structure (101) and the second periodic structure (102) within separate layers (e.g., the first layer and the second layer) are shown.

[0050] FIG. 2 is a combined electron beam overlay and scattering measurement overlay target (200). The target (200) may be a combined electron beam overlay and scattering measurement overlay target in one direction. For example, scattering measurement uses regions where layers of gratings overlap, while electron beam overlay uses regions where layers of gratings are separated. The target (200) includes a first periodic structure (101) formed on a first layer of a semiconductor device. Each of the plurality of gratings in the first periodic structure (101) has a first width along a first axis (e.g., X) and a first height along a second axis (e.g., Y). The first width may be between 1 μm and 100 μm. The first height may be between 10 μm and 100 μm. The first width and the first height may be larger or smaller than the above ranges depending on the specific application. The first periodic structure (101) has a first pitch. The first pitch may be between 200 nm and 1000 nm. The first pitch may also be smaller or larger than the above ranges depending on the specific application.

[0051] A second periodic structure (102) is formed on a second layer of a semiconductor device. Each of the plurality of grids in the second periodic structure (102) has a second width along a first axis (e.g., X) and a second height along a second axis (e.g., Y). The second width of the second periodic structure (102) is narrower than the first width of the first periodic structure (101). The second width may be between 1 μm and 100 μm. The second height may be between 10 μm and 100 μm. The first width and the first height may be larger or smaller than the above ranges depending on the specific application. The second periodic structure (102) has a second pitch that is less than the first pitch of the first periodic structure (101). The second pitch may be between 200 nm and 1000 nm. The second pitch may also be smaller or larger than the above ranges depending on the specific application. The grids of the first periodic structure (101) are positioned on the grids of the second periodic structure (102).

[0052] The first and second periodic structures (101, 102) are overlaid on each other and formed as arrays of mutually parallel lines on the first and second layers of the semiconductor device. The lines are aligned along an axis such as the Y-axis. The size, dimensions, and angles of the structures in the fine segmented portions may vary depending on the semiconductor manufacturer, technology node, and processing stage. Note that the structures may operate in sizes ranging from a few nanometers to a few micrometers. In the case of diagonal structures, 15° to 30° may be typical, but other angles are also possible.

[0053] The target (200) may have overall side lengths between 10 μm and 100 μm. For example, the overall side lengths may be 40 μm or less. Generally, the size of the target (200) may vary depending on the selected optical wavelength and beam size. A larger target may make measurement easier but may occupy more area on the semiconductor wafer. Reducing the size of the target (100) may reduce production costs and increase available space on the wafer. The specific balance of physical properties and costs for selecting the target size may vary depending on the design rules of the process for a specific layer and / or product. The target (200) may have a rectangular shape.

[0054] In the embodiment of FIG. 2, the first height of the first periodic structure (101) is longer than the second height of the second periodic structure (102). The second periodic structure (102) is arranged in two arrays (201, 202). The grids of the first periodic structure (101) extend along the second axis across each of the arrays (201, 202) of the second periodic structure (102).

[0055] The first periodic structure (101) may have a first height between 10 μm and 100 μm. The difference between the first height and the second height bay depends on design rules for specific uses.

[0056] The target (200) may have an unpatterned area (203) within the second layer of the semiconductor device between the ends of the two arrays (201, 202).

[0057] The first periodic structure (101) extending across the unpatterned area (203) within the second layer can enable easy detection of the ends of the second periodic structure (102). This can also enable detection of the symmetry center of the target (200).

[0058] The first and second layers of FIG. 2 or other embodiments described herein may be adjacent to each other, but not necessarily, and may be separated by a height of 100 nm to more than 10 μm. The upper layer, illustrated herein as a first layer having a first periodic structure (101), transmits photons at least partially. Although embodiments disclosed herein illustrate the first periodic structure (101) arranged on top of a second periodic structure (102), it is also understood that targets may be formed such that the second periodic structure (102) is arranged on top of the first periodic structure (101). The pitch of the first periodic structure (101) and the second periodic structure may be on the order of wavelengths of an optical system so as to be measurable by an optical system. Thus, the pitch may range from 400 nm to 1000 nm or more, depending on the specific optical system. The design of the target also varies depending on the details of the wafer processing, which determine the acceptable distance, pitch, height, etc.

[0059] FIG. 3 is another combined electron beam overlay and scattering measurement overlay target (300). The target (300) may be a combined electron beam overlay and scattering measurement overlay target in one direction perpendicular to the direction shown in FIG. 2. In the target (300), the lattices of the second periodic structure (102) extend beyond the first periodic structure (101). Both the first periodic structure and the second periodic structure are arranged into two arrays (301, 302).

[0060] The first periodic structure (101) and the second periodic structure (102) include extension portions that extend approximately 500 nm to 2000 nm in opposite directions along the corresponding axis beyond the other periodic structure. The extension portions of the second periodic structure may enable easy optical detection of the ends of the first periodic structure (101) and the second periodic structure (102), and accordingly their respective centers of symmetry. The size and structure of the target (300) may be similar to the target (200) described above.

[0061] FIG. 4 is another combined electron beam overlay and scattering measurement overlay target (400). The target (400) may be an electron beam overlay and scattering measurement overlay target combined in two vertical directions. The second periodic structure (102) consists of four arrays (401-404).

[0062] As with targets (200 and 300), the grids of the second periodic structure (102) extend beyond the first periodic structure (101) in arrays (401-404). As with target (200), target (400) may have an unpatterned area (203) within the second layer of the semiconductor device between the ends of the two arrays (201, 202). Accordingly, the second periodic structure (102) extends beyond the first periodic structure (101) along a second axis perpendicular to the first axis.

[0063] The first height of the first periodic structure (101) between the third array and the fourth array (403, 404) is longer than the second height of the second periodic structures (102) in the third array and the fourth array (403, 404). The grids of the first periodic structure (101) in the third array (403) extend along the second axis across the third and fourth arrays (403, 404) of the second periodic structure (102). The size and structure of the target (400) may be similar to the target (200) described above.

[0064] The target (400) also includes regions of interest (103) (represented by hollow black rectangles). The regions of interest (103) may be related to the setup of the image processing algorithm and the type of image processing algorithm used. Segments of the grid in the outer bars may be removed due to higher sensitivity to aberrations for parallel segmented parts. Placement of regions of interest on fine segmented parts can improve aberration accuracy within a single bar by excluding extreme segments.

[0065] FIG. 5 is another combined electron beam overlay and scattering measurement overlay target (500). The target (500) may be a combined electron beam overlay and scattering measurement overlay target. There are four arrays (501-504) of first and second periodic structures (101, 102). Two arrays (501 and 503) are oriented perpendicularly to the other two arrays (502, 504).

[0066] The second periodic structure (102) extends beyond the first periodic structure (102) along a second axis perpendicular to the first axis. Accordingly, the outer edges of the arrays (501-504) are the grids of the second periodic structure (102). The first periodic structure (101) extends beyond the second periodic structure (102) on the opposite side of the arrays (501-504) where the outer edges may not be.

[0067] The target (500) also includes regions of interest (103). The size and structure of the target (500) may be similar to the target (200) described above.

[0068] FIG. 6 is another combined electron beam overlay and scattering measurement overlay target (600). The target (600) may be a combined electron beam overlay and scattering measurement overlay target. There are four arrays (601-604) of first and second periodic structures (101, 102). Two arrays (601 and 603) are oriented perpendicularly to the other two arrays (602, 604).

[0069] Each grid in the first periodic structures (101) defines a gap (104) along the axes. The second periodic structure (102) is exposed through the gaps (104). The first periodic structure (101) extends beyond the second periodic structure (102) along the axes.

[0070] The target (600) also includes regions of interest (103). The size and structure of the target (600) may be similar to the target (200) described above.

[0071] FIG. 7 is a combined electron beam overlay and scattering measurement overlay target (700) having a region of interest in the center. The target (700) may be a combined electron beam overlay and scattering measurement overlay target. The target (700) includes a first periodic structure (101) formed on a first layer of a semiconductor device. Each of the grids in the first periodic structure (101) has a first width along a first axis (e.g., X or Y) and a first height along a second axis perpendicular to the first axis. The first periodic structure (101) has a first pitch.

[0072] A second periodic structure (102) is formed on a second layer of a semiconductor device. Each of the grids in the second periodic structure (102) has a second width and a second height. The second width may be the same as the first width. The second height may be the same as the first height. The second periodic structure (102) may have a second pitch that may be the same as the first pitch.

[0073] The second periodic structure (102) may include two grids within the width of one grid of the first periodic structure (101). There may be a gap between these two grids. If a gap is included between the grids, compatibility with the wafer process parameters of the target may be improved. For example, if the current processing step requires gaps in the device structures, it may be advantageous to create targets that mimic these gaps.

[0074] The grids of the second periodic structure (102) are placed between the grids of the first periodic structure (101).

[0075] There are four arrays (701-704) of first and second periodic structures (101, 102). Two arrays (701 and 703) are oriented perpendicularly to the other two arrays (702, 704).

[0076] The second periodic structure (102) extends beyond the first periodic structure (101) along the axis of each of the arrays (701-704). The first periodic structure (101) extends beyond the second periodic structure (102) along the axis on the opposite side of each of the arrays.

[0077] The target (700) also includes regions of interest (103). The size and structure of the target (700) may be similar to the target (200) described above.

[0078] FIG. 8 is a combined electron beam overlay and scattering measurement overlay target (800) having a region of interest in the center. The target (800) may be a combined electron beam overlay and scattering measurement overlay target. The target (800) has arrays (801-804). A first periodic structure (101) defines a gap (104) along the axis of each of the arrays (801-804). A second periodic structure (102) extends along the axis beyond the first periodic structure (101) into the gap (104).

[0079] The target (800) also includes regions of interest (103). The size and structure of the target (800) may be similar to the target (200) described above.

[0080] FIG. 9 is a flowchart of the method (900). In the method, a target is provided (901). The target may be one of the targets disclosed herein. An overlay measurement is performed using a semiconductor metrology tool (902). The semiconductor metrology tool may be a conventional tool using existing processing algorithms or an electron beam tool using different measurement techniques. For example, a single beam spot may be applied to a grating. A single reflectance value is collected for each grating. Each cell will contain an induced offset for calculating the overlay. At least four cells having different induced offsets may be used. This method may be propagated until "n" cells have occurred. The beam spots may be scanned to average the spot position accuracy.

[0081] FIG. 10 is an illustration of a system (1000). The system (1000) includes a chuck (1002) configured to hold a wafer (1001). The wafer (1001) includes one or more overlay targets as described in the embodiments herein.

[0082] The system (1000) includes an imaging optical system (1003) configured to measure an overlay target on a chuck (1002). The imaging optical system (1003) may include a light source oriented to direct radiation onto a specific location on a wafer (1001), and one or more detectors oriented to detect an optical signal from the wafer (1001). The light source within the optical system (1003) may generate an illumination beam directed toward the wafer (1001). The imaging optical system (1003) may also include various lenses, optical components, other steering devices, or other beam transfer devices. The illumination beam may be an optical beam or an electron beam.

[0083] The imaging optical system (1003) can be used for acquisition so that the imaging optical system (1003) becomes part of the acquisition system for scattering measurement.

[0084] The system (1000) includes a scattering measurement system (1004) configured to measure an overlay target on a chuck (1002). The scattering measurement system (1004) may be configured to measure the same overlay target as the imaging optical system (1003).

[0085] The scattering measurement system (1004) may include a light source oriented to direct radiation onto a specific location on the wafer (1001), and one or more detectors oriented to detect a scattering measurement signal scattered by the wafer (1001). The light source within the scattering measurement system (1004) may generate a light beam directed toward the wafer (1001). The scattering measurement system (1004) may also include various lenses or optical components. The scattering measurement system (1004) may use information from the imaging optical system (1003) or the imaging optical system (1003) during the scattering measurement sequence.

[0086] Measurement of the wafer (1001) by the imaging optical system (1003) and the scattering measurement system (1004) can be performed while the wafer (1001) is held on the chuck (1002). Accordingly, the wafer (1001) may not move between the measurement by the imaging optical system (1003) and the measurement by the scattering measurement system (1004). For example, the vacuum around the wafer (1001) is not broken between the measurement by the imaging optical system (1003) and the measurement by the scattering measurement system (1004). For example, one of the measurements by the imaging optical system (1003) and the measurement by the scattering measurement system (1004) occurs after the other. As another example, the measurement by the imaging optical system (1003) and the measurement by the scattering measurement system (1004) occur at least partially simultaneously or at the same time.

[0087] Although disclosed as a single system (1000), the imaging optical system (1003) and the scattering measurement system (1004) may be two separate systems. Each of the systems may have a separate chuck.

[0088] The processor (1005) communicates electronically with the electronic data storage unit (1006), the imaging optical system (1003), and the scattering measurement system (1004). The processor (1005) may include a microprocessor, a microcontroller, or other components. The processor (1005) may receive output from the imaging optical system (1003) and the scattering measurement system (1004).

[0089] The system (1000) may include an imaging optical system acquisition module (1007) configured to acquire an overlay target on the chuck (1002) using an imaging optical system (1003). The optical system acquisition module (1007) forms an acquired image that can be used by the imaging optical system (1003) or the scattering measurement system (1004). Although illustrated as separate units, the imaging optical system acquisition module (1007) may be part of the imaging optical system (1003). The imaging optical system acquisition module (1007) may also be part of the processor (1005).

[0090] The processor (1005) and the electronic data storage unit (1006) may be part of the system (1000) or another device. In an example, the processor (1005) and the electronic data storage unit (1006) may be part of a standalone control unit or within a centralized quality control unit. Multiple processors (1005) or electronic data storage units (1006) may be used. In an embodiment, the processor (1005) may be placed within the system (1000).

[0091] The processor (1005) may be implemented by any combination of hardware, software, and firmware. Additionally, the functions of the processor as described herein may be performed by a single unit or distributed among different components, each of which may be implemented by any combination of hardware, software, and firmware. Program code or instructions for the processor (1005) to implement various methods and functions may be stored in readable storage media, such as memory within an electronic data storage unit (1006) or other memory.

[0092] The processor (1005) may be coupled to the components of the system (1000) in any suitable manner so that the processor (1005) can receive an output (e.g., through one or more transmission media including wired and / or wireless transmission media). The processor (1005) may be configured to perform a number of functions using the output.

[0093] The processor (1005), other system(s), or other subsystem(s) described herein may be part of various systems, including personal computer systems, image computers, mainframe computer systems, workstations, network appliances, internet appliances, or other devices. The subsystem(s) or system(s) may also include any suitable processor known in the art, such as a parallel processor. Additionally, the subsystem(s) or system(s) may include a platform having high-speed processing and software, as either a standalone or networked tool.

[0094] If the system comprises more than one subsystem, the different subsystems may be combined with each other so that images, data, information, commands, etc., can be transmitted between the subsystems. For example, one subsystem may be combined to additional subsystem(s) by any suitable transmission medium, which may include any suitable wired and / or wireless transmission medium known in the art. Two or more of such subsystems may also be effectively combined by a shared computer-readable storage medium (not shown).

[0095] The processor (1005) may be configured to perform a number of functions using the output of the imaging optical system (1003) and the scattering measurement system (1004), or other outputs. For example, the processor (1005) may be configured to send measurement results of the wafer (1001). In another example, the processor (1005) may determine electron beam overlay and / or scattering measurement overlay errors within the target. In another example, the processor (1005) may be configured to send outputs to the electronic data storage unit (1006), or another storage medium, respectively. The processor (1005) may also be configured as described herein.

[0096] The processor (1005) may be configured according to any one of the embodiments described herein. The processor (1005) may also be configured to perform other functions or additional steps using the output of the measurement system (1000) or using images or data from other sources.

[0097] In another embodiment, the processor (1005) may be communicably coupled to any of the various components or subsystems of the system (1000) in any manner known in the art. Furthermore, the processor (1005) may be configured to receive and / or obtain data or information from other systems (e.g., inspection results from an inspection system, such as a review tool, a remote database containing design data, etc.) by means of a transmission medium that may include wired and / or wireless portions. In this way, the transmission medium may serve as a data link between the processor (1005) and other subsystems of the system (1000) or systems outside the system (1000).

[0098] In some embodiments, various steps, functions, and / or operations of the system (1000) and methods disclosed herein are performed by one or more of electronic circuits, logic gates, multiplexers, programmable logic elements, ASICs, analog or digital controllers / switches, microcontrollers, or computing systems. Program instructions implementing methods such as those described herein may be transmitted via a carrier medium or stored on a carrier medium. The carrier medium may include a storage medium such as read-only memory, random access memory, magnetic or optical disk, non-volatile memory, solid-state memory, magnetic tape, etc. The carrier medium may include a transmission medium such as a wire, cable, or wireless transmission link. For example, the various steps described throughout this disclosure may be performed by a single processor (1005) (or computer system), or alternatively, by a plurality of processors (1005) (or a plurality of computer systems). Furthermore, different subsystems of the system (1000) may include one or more computing or logic systems. Accordingly, the foregoing description should be interpreted merely as an example, not as a limitation to the present disclosure.

[0099] Additional embodiments relate to a non-transient computer-readable medium that stores program instructions executable on a processor for inspecting a wafer, as disclosed herein. In particular, a processor, such as a processor (1005), may be coupled to a non-transient computer-readable medium containing executable processor instructions and to memory within an electronic data storage medium, such as an electronic data storage unit (1006). A computer implementation method may include any step(s) of any method(s) described herein. For example, the processor (1005) may be programmed to perform some or all of the steps of FIG. 9. The memory within the electronic data storage unit (1006) may be a storage medium such as a magnetic or optical disk, a magnetic tape, or any other suitable non-transient computer-readable medium known in the art.

[0100] Program instructions may be implemented in any various ways, particularly including procedure-based techniques, component-based techniques, and / or object-oriented techniques. For example, program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Class (MFC), Streaming SIMD Extension (SSE), or other technologies or methods, as required.

[0101] In other embodiments, the design method of the targets disclosed herein may be used. The method may be performed using a processor as described herein. The grids of the first and second periodic structures of the targets disclosed herein may be optimized.

[0102] Although specific configurations have been presented in the embodiments exemplified herein, variations including all or part of the features of these embodiments are also possible.

[0103] Although the present disclosure has been described with respect to one or more specific embodiments, it will be understood that other embodiments of the present disclosure may be practiced without departing from the scope of the present disclosure. Accordingly, the present disclosure is considered to be limited only by the appended claims and a reasonable interpretation thereof.

Claims

Claim 1 As a target, a first periodic structure formed on a first layer of a semiconductor device - each of a plurality of grids in the first periodic structure has a first width along a first axis and a first height along a second axis, and the first periodic structure has a first pitch -; A second periodic structure formed on a second layer of the semiconductor device - each of a plurality of grids in the second periodic structure has a second width along the first axis and a second height along the second axis, the second width is narrower than the first width, the second periodic structure has a second pitch smaller than the first pitch, the grids of the first periodic structure are positioned to overlap with the grids of the second periodic structure, the second periodic structure extends beyond the first periodic structure along the first axis, and the first periodic structure and the second periodic structure are in a first array - ; a second array of the first periodic structure and the second periodic structure - the second periodic structure in the second array extends beyond the first periodic structure in a direction along the second axis from the second periodic structure of the first array - ; A target comprising a third array of the first periodic structure, and a third array and a fourth array of the second periodic structure— wherein the first height is longer than the second height, and the lattices of the first periodic structure in the third array extend along the second axis across the third array and the fourth array of the second periodic structure— wherein the first periodic structure and the second periodic structure provide electron beam overlay measurements and scattering measurement overlay measurements. Claim 2 A target according to claim 1, wherein the second periodic structure is composed of two arrays, and the grids of the first periodic structure extend along the second axis across each of the arrays of the second periodic structure. Claim 3 A target according to claim 1, wherein four arrays of the first periodic structure and the second periodic structure are arranged such that two of the four arrays are oriented perpendicularly to the other two of the four arrays. Claim 4 In paragraph 3, the target, wherein the second periodic structure extends beyond the first periodic structure along the second axis. Claim 5 In paragraph 3, each of the grids in the first periodic structure defines a gap along the second axis, the second periodic structure is exposed through the gap, and the first periodic structure extends beyond the second periodic structure along the second axis, a target. Claim 6 A target comprising: a first periodic structure formed on a first layer of a semiconductor device, wherein each of a plurality of grids in the first periodic structure has a first width along a first axis and a first height along a second axis, and the first periodic structure has a first pitch; and a second periodic structure formed on a second layer of the semiconductor device, wherein each of a plurality of grids in the second periodic structure has a second width and a second height, wherein the second width is equal to the first width, and the second periodic structure has a second pitch equal to the first pitch, and the grids of the first periodic structure are disposed between the grids of the second periodic structure; wherein the first periodic structure and the second periodic structure provide electron beam overlay measurement and scattering measurement overlay measurement. Claim 7 A target according to claim 6, wherein four arrays of the first periodic structure and the second periodic structure are arranged such that two of the four arrays are oriented perpendicularly to the other two of the four arrays. Claim 8 A target according to claim 7, wherein the second periodic structure extends beyond the first periodic structure along the second axis on one side of each of the arrays, and the first periodic structure extends beyond the second periodic structure along the second axis on the opposite side of each of the arrays. Claim 9 A target according to claim 7, wherein each of the grids in the first periodic structure defines a gap along the second axis, and the second periodic structure extends beyond the first periodic structure in the gap along the second axis in each of the arrays. Claim 10 A method comprising the step of providing a target, wherein the target comprises: a first periodic structure formed on a first layer of a semiconductor device, wherein each of a plurality of grids in the first periodic structure has a first width along a first axis and a first height along a second axis, and the first periodic structure has a first pitch; and a second periodic structure formed on a second layer of the semiconductor device, wherein each of a plurality of grids in the second periodic structure has a second width and a second height, wherein the second width is equal to the first width, and the second periodic structure has a second pitch equal to the first pitch, and the grids of the first periodic structure are positioned between the grids of the second periodic structure; and the step of performing electron beam overlay measurements and scattering measurement overlay measurements on the target using at least one semiconductor measurement tool. Claim 11 A method according to claim 10, wherein four arrays of the first periodic structure and the second periodic structure are arranged such that two of the four arrays are oriented perpendicularly to the other two of the four arrays, and then: the second periodic structure extends beyond the first periodic structure along the second axis on one side of each of the arrays, and the first periodic structure extends beyond the second periodic structure along the second axis on the opposite side of each of the arrays; and each of the grids in the first periodic structure defines a gap along the second axis, and the second periodic structure extends beyond the first periodic structure in the gap along the second axis on each of the arrays. Claim 12 A semiconductor measurement tool configured to perform the overlay measurement on the target of the method of claim 10. Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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