Display apparatus

Abstract

A display device according to one example of the present invention comprises: a substrate having a light-blocking film disposed thereon; a buffer layer located on the substrate; a thin-film transistor located on the buffer layer and including a gate electrode, a source electrode, and a drain electrode; an interlayer insulating film and a planarization film located on the gate electrode; a plurality of contact holes penetrating the interlayer insulating film and the planarization film, each exposing a portion of the drain electrode, a portion of the gate electrode, and a portion of the buffer layer, respectively; a first pixel electrode located on the planarization film and electrically connected to the drain electrode through at least one contact hole among the plurality of contact holes; and a second pixel electrode located on the planarization film and connected to the gate electrode through at least one contact hole among the plurality of contact holes, wherein the second pixel electrode overlaps with the light-blocking layer with the buffer layer in between through a contact hole that exposes a portion of the buffer layer among the plurality of contact holes.

Description

Technology Field

[0001] This specification relates to a display device capable of improving the aperture ratio. Background Technology

[0002] Display devices are applied to various electronic devices such as TVs, mobile phones, laptops, and tablets. To this end, research is continuously being conducted to develop thinner, lighter, and lower power consumption display devices.

[0003] Examples of display devices include Liquid Crystal Display (LCD), Plasma Display Panel (PDP), Field Emission Display (FED), Electro-Wetting Display (EWD), and Organic Light Emitting Display (OLED).

[0004] Among these, an organic light-emitting display (OLED) includes a plurality of pixel regions arranged in a display area where an image is displayed, and a plurality of organic light-emitting elements corresponding to the plurality of pixel regions. Since organic light-emitting elements are self-emissive devices that emit light on their own, the organic light-emitting display has the advantages of faster response speed compared to liquid crystal displays, higher luminous efficiency, brightness, and viewing angle, as well as superior contrast ratio and color reproduction rate.

[0005] An organic light-emitting display device includes a light-emitting section and a circuit section for driving the light-emitting section. The circuit section includes thin-film transistors and storage capacitors. In the case of such an organic light-emitting display device using a bottom emission method, where light generated from the light-emitting layer is emitted in the opposite direction of the substrate—that is, toward the back of the substrate—light cannot be emitted to the outside in the area where the circuit section is located. Consequently, the aperture ratio is reduced by the amount of the area where the circuit section is located. The problem to be solved

[0006] The problem to be solved according to one embodiment of the present specification is to provide a display device capable of improving the aperture ratio by increasing the area of ​​the light-emitting region in an organic light-emitting display device.

[0007] In addition, the invention according to the embodiments of this specification aims to increase the lifespan of an organic light-emitting diode by increasing the area of ​​the light-emitting region and reducing the current consumption required to achieve the same brightness in individual pixels.

[0008] In addition, the invention is intended to provide a display device capable of increasing the total capacitance of the storage capacitor while increasing the area of ​​the light-emitting region by reducing the area occupied by the storage capacitor.

[0009] In addition, the purpose is to increase the capacitance of the storage capacitor by improving the structure of the dielectric constituting the storage capacitor.

[0010] In addition, it aims to prevent disconnection of the pixel electrode caused by undercuts occurring between the insulating films.

[0011] The problems solved according to one embodiment of this specification are not limited to the purposes mentioned above, and other unmentioned purposes and advantages of the present invention may be understood from the following description and will be more clearly understood by the embodiments of this specification. Furthermore, it will be readily apparent that the purposes and advantages of this specification can be realized by the means and combinations thereof set forth in the claims. means of solving the problem

[0012] A display device according to one embodiment of the present specification comprises: a substrate having a light-blocking film disposed thereon; a buffer layer located on the substrate; a thin-film transistor located on the buffer layer and including a gate electrode, a source electrode, and a drain electrode; an interlayer insulating film and a planarization film located on the gate electrode; a plurality of contact holes penetrating the interlayer insulating film and the planarization film, each exposing a portion of the drain electrode, a portion of the gate electrode, and a portion of the buffer layer, respectively; a first pixel electrode located on the planarization film and electrically connected to the drain electrode through at least one contact hole among the plurality of contact holes; and a second pixel electrode located on the planarization film and connected to the gate electrode through at least one contact hole among the plurality of contact holes, wherein the second pixel electrode overlaps with the light-blocking layer with the buffer layer in between through a contact hole among the plurality of contact holes that exposes a portion of the buffer layer.

[0013] A display device according to another embodiment of the present specification comprises: a first light-blocking film and a second light-blocking film disposed on a substrate; a thin-film transistor located on the buffer layer and comprising a gate electrode, a source electrode, and a drain electrode; an interlayer insulating film and a planarization film located on the gate electrode; a plurality of contact holes penetrating the interlayer insulating film and the planarization film, each exposing a portion of the drain electrode and the buffer layer; and a first pixel electrode located on the planarization film and electrically connected to the drain electrode and the first light-blocking layer through at least one contact hole among the plurality of contact holes, wherein the first pixel electrode overlaps with the second light-blocking layer with the buffer layer in between through a contact hole among the plurality of contact holes that exposes a portion of the buffer layer. Effects of the invention

[0014] According to one embodiment of the present specification, by forming the pixel electrode by separating it into a first pixel electrode and a second pixel electrode and using the second pixel electrode as a storage upper electrode, the area occupied by the storage capacitor in the circuit part can be reduced.

[0015] In addition, by separating the light-blocking layer into a first light-blocking layer and a second light-blocking layer, and forming a capacitor contact hole on the separated second light-blocking layer to utilize the pixel electrode as the upper storage electrode, the area occupied by the storage capacitor in the circuit part can be reduced.

[0016] Accordingly, by reducing the area occupied by the storage capacitor and increasing the area of ​​the light-emitting region, it is possible to improve the aperture ratio.

[0017] In addition, it offers the advantage of increasing the capacitance of the storage capacitor by reducing the thickness of the dielectric constituting the storage capacitor while reducing the area occupied by the storage capacitor.

[0018] In addition, it offers the advantage of improving the reliability of the display device by increasing the area of ​​the light-emitting region to reduce the current consumption required to achieve the same brightness in individual pixels, thereby increasing the lifespan of the organic light-emitting diode.

[0019] In addition, by covering the exposed side portions of the interlayer insulating film and buffer layer at the capacitor contact hole where the storage capacitor is placed with a flattening film to a predetermined thickness to create a smooth surface, it is possible to prevent the occurrence of disconnection of the pixel electrode.

[0020] The effects of this specification are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0021] FIGS. 1a and FIGS. 1b are drawings illustrated to explain a display device according to a first embodiment of the present specification. FIGS. 2a and FIGS. 2b are drawings shown to explain a display device according to a second embodiment of the present specification. FIGS. 3 to 13 are cross-sectional views shown to explain a method for manufacturing a display device according to a second embodiment of the present specification. FIGS. 14a and FIGS. 14b are drawings shown to explain a display device according to a third embodiment of the present specification. FIGS. 15 to 26 are cross-sectional views shown to explain a method for manufacturing a display device according to a third embodiment of the present specification. Specific details for implementing the invention

[0022] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is defined only by the scope of the claims.

[0023] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary and are not limited to the depicted items. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0024] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0025] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0026] In the case of an explanation of a temporal relationship, for example, when a temporal sequence is explained using 'after', 'following', 'next', 'before', etc., it may include cases where the sequence is not continuous unless 'immediately' or 'directly' is used.

[0027] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0028] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0029] Hereinafter, a display device according to each embodiment of the present invention will be described with reference to the attached drawings.

[0030] FIGS. 1a and 1b are drawings illustrating a display device according to a first embodiment of the present specification. FIG. 1a is a plan view of a display device according to a first embodiment of the present specification. FIG. 1b is a cross-sectional view taken along the directions I-I', II-II', III-III', IV-IV', VV', and VI-VI' of FIG. 1a.

[0031] Referring to FIG. 1a and FIG. 1b, a display device (10) according to the first embodiment of the present specification includes a light-emitting region (192) in which an organic light-emitting element that emits light is disposed, and a circuit portion equipped with driving circuit elements for supplying driving current to the organic light-emitting element. The light-emitting region (192) and the driving circuit elements are disposed in a display region in which a plurality of subpixels are arranged in a matrix form to display an image.

[0032] The driving circuit elements include a thin-film transistor (T) and a storage capacitor (Cst). The driving circuit elements constituting the circuit are placed in the remaining area excluding the light-emitting region (194). The thin-film transistor (T) includes a gate electrode (164), a source electrode (166), a drain electrode (168), and an active layer (125).

[0033] The gate electrode (164) is positioned overlapping the channel region (CH) of the active layer (125). A gate insulating film (130) is disposed between the gate electrode (164) and the channel region (CH) of the active layer (125). The gate electrode (164) can be configured with a stacked structure of a first gate metal (161) and a second gate metal (163). The source electrode (166), drain electrode (168), and pad electrode (174) are made of the same material as the gate electrode (164) and can be located on the same plane.

[0034] The active layer (125) has a source region (SA) and a drain region (DA) facing each other with the channel region (CH) in between. The channel region (CH) is arranged to overlap with the gate electrode (164) with the gate insulating film (130) in between.

[0035] The source electrode (166) is electrically connected to the source region (SA) of the active layer (125), and the drain electrode (168) is electrically connected to the drain region (DA) of the active layer (125). The drain electrode (168) is electrically connected to the first electrode (186) by contacting it through a pixel contact hole (184) formed through the planarization film (182) and the interlayer insulating film (176). Additionally, the drain electrode (168) can be electrically connected to the light blocking layer (105) through a light-blocking contact hole (154) that penetrates the first buffer layer (120) and the second buffer layer (122).

[0036] A light-blocking layer (105) is formed between the active layer (125) and the substrate (100). The light-blocking layer (105) is formed at a position that overlaps with the active layer (125), and is formed to overlap with at least the channel region (CH) of the active layer (125). The surface of the light-blocking layer (105) is partially exposed through a light-blocking contact hole (154) so ​​that it can be electrically connected to the active layer (125) through a drain electrode (168).

[0037] The light-blocking layer (105) may be formed in a structure in which a first metal layer (102) and a second metal layer (104) are laminated. The storage lower electrode (110) and the wiring electrode (115) may be formed on the same plane as the light-blocking layer (105) and of the same material. Here, the wiring electrode (115) includes one of a driving power supply line (VDD), a data line (DL), and a reference power supply line (Vref). When viewed from a plane, the wiring electrode (115) is arranged in a first direction (X) of the substrate (100), for example, in a horizontal line.

[0038] A buffer layer (120, 122) is disposed on a light-blocking layer (105), a storage lower electrode (110), and a wiring electrode (115). The buffer layer (120, 122) can be formed as a double-layer structure of a first buffer layer (120) and a second buffer layer (122).

[0039] A storage capacitor (Cst) can be configured by overlapping a storage lower electrode (110) and a storage upper electrode (125a) with a first buffer layer (120) and a second buffer layer (122) in between. That is, a multilayer structure in which the first buffer layer (120) and the second buffer layer (122) are stacked between the storage lower electrode (110) and the storage upper electrode (172) is arranged as a dielectric. At this time, the storage upper electrode (125a) is made of the same material as the active layer (125) and is arranged in the form of a plate on the same plane.

[0040] The first buffer layer (120) is formed of silicon nitride (SiNx) of a first thickness, and the second buffer layer (122) is formed of silicon oxide (SiOx) of a second thickness thicker than the first buffer layer (120). For example, the first buffer layer (120) is formed with a first thickness of 1000 Å to 1500 Å, and the second buffer layer (122) is formed with a second thickness of 2700 Å to 3300 Å. Accordingly, the dielectric in the storage capacitor (Cst) has a thickness of at least 3000 Å.

[0041] As the dielectric constant of the first buffer layer (120) is approximately 6.9 and the dielectric constant of the second buffer layer (122) is approximately 3.9, the capacitance value of the storage capacitor (Cst) has a value of 0.0011 * constant. The capacitance of the storage capacitor (Cst) decreases inversely proportional to the thickness of the dielectric, and increases as the thickness of the dielectric decreases. One method to increase the capacitance of the storage capacitor (Cst) is to shorten the distance between the storage lower electrode (110) and the storage upper electrode (172). However, in the first embodiment of the present specification, since the dielectric has a thickness of at least 3000 Å, there is a limit to reducing the distance between the storage lower electrode (110) and the storage upper electrode (172). In addition, if the area occupied by the storage capacitor (Cst) is increased to improve capacitance, the aperture ratio may decrease as the area of ​​the light-emitting region (192) is reduced.

[0042] The pad electrode (174) serves to supply a driving signal to each of the gate electrode (164), the data line (DL), the driving power supply line (VDD), and the reference power supply line (Vref). Corresponding to the driving power supply line (VDD), the data line (DL), and the reference power supply line (Vref) arranged in the first direction (X), which is a horizontal line, scan lines (SCAN1, SCAN2) are arranged in the second direction (Y), which is a vertical line.

[0043] An interlayer insulating film (176) and a planarization film (182) are disposed on a substrate (100) on which a gate electrode (164), a source electrode (166), a drain electrode (168), and a storage top electrode (125a) are formed. A color filter (180) is disposed on the interlayer insulating film (176). The color filter (180) may be one of red (R), green (G), and blue (B). The planarization film (182) further includes a pixel contact hole (184) that exposes a portion of the surface of the drain electrode (168).

[0044] A first electrode (186) is disposed on a planarization film (182) and a pixel contact hole (184) and connected to a drain electrode (168). The first electrode (186) is disposed to overlap with a driving circuit element including a light-emitting region (192) formed by a bank hole (194) provided in a bank (190), a thin-film transistor (T), and a storage capacitor (Cst). The width (EAW1) of the light-emitting region (192) can be defined by the size of the bank hole (194). The first electrode (186) may also be referred to as an anode electrode or a pixel electrode.

[0045] The organic light-emitting layer (198) is connected to the first electrode (186) and extends to the upper surface of the bank (190). The organic light-emitting layer (198) is composed of a stacked structure of a hole transport layer (HTL), a light-emitting layer (EML), and an electron transport layer (ETL). The organic light-emitting layer (198) is made of an organic material that emits white light, and can display a color through a color filter (180).

[0046] A second electrode (199) is disposed on the organic light-emitting layer (198). Accordingly, an organic light-emitting device (OLED) is formed, consisting of the first electrode (186), the organic light-emitting layer (198), and the second electrode (199). The second electrode (199) may also be referred to as a common electrode or a cathode electrode.

[0047] As described above, there is a limit to improving the capacitance of the storage capacitor (Cst) by introducing a structure in which the first buffer layer (120) and the second buffer layer (122) are stacked as a double layer with a dielectric. In addition, in order to improve the aperture ratio by increasing the area of ​​the light-emitting region within a limited space, the area occupied by the storage capacitor (Cst) must be reduced.

[0048] Accordingly, in another embodiment of this specification, a display device structure and a method for manufacturing the same are described, which can increase the capacitance of a storage capacitor while reducing the area occupied by the circuit portion within the limited space of the display device, and increase the area of ​​the light-emitting region by the size of the reduced area of ​​the circuit portion to improve the aperture ratio. The description will be explained below with reference to the drawings.

[0049] FIGS. 2a and 2b are drawings illustrating a display device according to a second embodiment of the present specification. FIG. 2a is a plan view of a display device according to a second embodiment. FIG. 2b is a cross-sectional view taken along the directions I-I', II-II', III-III', IV-IV', and VV' of FIG. 2a.

[0050] Referring to FIG. 2a and FIG. 2b, a display device (20) according to a second embodiment of the present specification includes a light-emitting region (272) in which an organic light-emitting element that emits light is disposed, and a circuit section equipped with driving circuit elements for supplying driving current to the organic light-emitting element. The driving circuit elements include thin-film transistors and storage capacitors. The driving circuit elements constituting the circuit section are disposed in the remaining region excluding the light-emitting region (272).

[0051] A thin-film transistor comprises a gate electrode (GE), a source electrode (SE), a drain electrode (DE), and an active layer (220). The gate electrode (GE) may be positioned overlapping the channel region (CH) of the active layer (220). A gate insulating film (230) may be disposed between the gate electrode (GE) and the channel region (CH) of the active layer (220). The gate electrode (GE), source electrode (SE), and drain electrode (DE) may be a single layer or a multilayer composed of any one of the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof.

[0052] The source electrode (SE) is electrically connected to the source region (SA) of the active layer (220), and the drain electrode (DE) is electrically connected to the drain region (DA) of the active layer (220). Additionally, the drain electrode (DE) is electrically connected to the first pixel electrode (260) by contacting it through a pixel contact hole (256) that penetrates the planarization film (245) and the interlayer insulating film (240). Additionally, the drain electrode (DE) may be electrically connected to the light blocking layer (205) through a light-blocking contact hole (222) that penetrates the first buffer layer (212) and the second buffer layer (214). The source electrode (SE) and the drain electrode (DE) are located in the same plane as the gate electrode (GE).

[0053] The active layer (220) has a source region (SA) and a drain region (DA) positioned opposite each other with a channel region (CH) in between. In one example, the active layer (220) may be formed by including at least one of amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the active layer (220) may include at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO).

[0054] A light-blocking layer (205) is formed between the active layer (220) and the substrate (200). The light-blocking layer (205) is formed at a position overlapping with the active layer (220) and is positioned to overlap with at least the channel region (CH) of the active layer (220). A portion of the light-blocking layer (205) can function as a storage lower electrode in the capacitor region (IV-IV'). The light-blocking layer (205) may be formed in a stacked structure of a first metal layer (202) and a second metal layer (204).

[0055] A wiring electrode (210) may be formed of the same material on the same plane as the light-blocking layer (205). The wiring electrode (210) includes a driving power supply line (VDD), a data line (DL), and a reference power supply line (Vref), and is arranged in a first direction (X), for example, a horizontal line. A first buffer layer (212) and a second buffer layer (214) are disposed on the light-blocking layer (205) and the wiring electrode (210). The first buffer layer (212) may be formed of silicon nitride (SiNx) of a first thickness, and the second buffer layer (214) may be made of silicon oxide (SiOx) of a second thickness that is thicker than the first buffer layer (212).

[0056] The storage capacitor is configured such that a light-blocking layer (205) is positioned as a storage lower electrode with the first buffer layer (212) in between, and a second pixel electrode (262) is positioned as a storage upper electrode. The second pixel electrode (262) may be formed on the exposed surface of a capacitor contact hole (258) penetrating the flattening film (245), the interlayer insulating film (240), and the second buffer layer (214), and may be positioned extending to the upper surface of the flattening film (245). In another example, the flattening film (245) may be positioned between the capacitor contact hole (258), the interlayer insulating film (240), and the second buffer layer (214). In other words, the flattening film (245) may be formed to cover the side portions of the interlayer insulating film (240) and the second buffer layer (214) by a predetermined thickness.

[0057] In this way, by forming the second pixel electrode (262) along the exposed surface of the capacitor contact hole (258), the area occupied by the storage capacitor within the circuit can be reduced compared to when the storage upper electrode (125a, see FIG. 1b) is formed in a flat shape on the planarization film to achieve the same capacitance. Furthermore, the width (EAW2) of the light-emitting region can be increased (△EA1) by at least the area of ​​the reduced storage capacitor, thereby increasing the area of ​​the light-emitting region. Additionally, the capacitance can be increased by introducing a single layer of the first buffer layer (220) as a dielectric. A detailed explanation of this will be provided later.

[0058] A pad electrode (PE) is disposed on the same plane as the gate electrode (GE), source electrode (SE), and drain electrode (DE). The pad electrode (PE) serves to supply driving signals to the gate electrode (GE), data line (DL), driving power supply line (VDD), and reference power supply line (Vref), respectively. In the embodiments of this specification, a configuration in which the pad electrode (PE) is connected to the driving power supply line (VDD) is presented as an example, but it is not limited thereto. For example, the pad electrode (PE) may be composed of multiple electrodes connected to the data line (DL) and the reference power supply line (Vref), respectively. A pad cover electrode (263) is disposed on the pad electrode (PE).

[0059] Scan lines (SCAN1, SCAN2) are arranged in a second direction (Y), which is a vertical line, corresponding to a driving power supply line (VDD), a data line (DL), and a reference power supply line (Vref) arranged in a first direction (X), which is a horizontal line. The scan lines (SCAN1, SCAN2) may include a first scan line (SCAN1) that supplies a scan signal for selecting each horizontal line while supplying a data signal on a subpixel, and a second scan line (SCAN2) that supplies a signal for selecting each horizontal line while initializing the data signal supplied on the subpixel. Here, each of the driving power supply line (VDD) and the reference power supply line (Vref) may correspond to two or more vertical lines, namely the scan lines (SCAN1, SCAN2).

[0060] An interlayer insulating film (240) and a planarization film (245) are disposed on a substrate (200) on which a gate electrode (GE), a source electrode (SE), and a drain electrode (DE) are formed. A color filter (242) is disposed on the interlayer insulating film (240). The color filter (242) is disposed at a position that overlaps with the light-emitting region (272). The color filter (242) can display a color assigned to each subpixel. For example, the color filter (242) may be one of red (R), green (G), and blue (B).

[0061] The planarization film (245) is formed to form a flat surface and may be composed of photoacrylic resin, etc. The planarization film (245) includes a pixel contact hole (256) that exposes a portion of the surface of the drain electrode (DE).

[0062] A first pixel electrode (260) is placed on a flattening film (245) and a pixel contact hole (256) and electrically connected to a drain electrode (DE). The first pixel electrode (260) is placed on the flattening film (245) so as to overlap with a driving circuit element including a thin-film transistor and a storage capacitor, and a light-emitting region (272) formed by a bank hole (270) provided in a bank (265).

[0063] The second pixel electrode (262) is in direct contact with the gate electrode (GE) and extends along the exposed surface of the gate contact hole (257) to the upper surface of the flattening film (245), covering the entire exposed surface of the capacitor contact hole (258). Accordingly, the second pixel electrode (262) can be positioned to overlap with the light blocking layer (205), which acts as the lower storage electrode, with the first buffer layer (212) in between, thereby becoming the upper storage electrode. Thus, a storage capacitor can be configured consisting of the light blocking layer (205), the first buffer layer (212), and the second pixel electrode (262). Referring to FIG. 2a, the first pixel electrode (260) and the second pixel electrode (262) can be positioned spaced apart from each other by a predetermined distance when viewed from a plane. The first pixel electrode (260) and the second pixel electrode (262) may include a transparent metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0064] In the second embodiment according to the present specification, the pixel electrode is separated into a first pixel electrode (260) and a second pixel electrode (262), and the first pixel electrode (260) is connected to a light-blocking layer (205) through a pixel contact hole (256) and a light-blocking contact hole (222), and the second pixel electrode (262) is extended to a capacitor contact hole (258) and overlaps with the light-blocking layer (205) to form a storage capacitor. Here, by separating the first pixel electrode (260) and the second pixel electrode (262) and introducing a gate contact hole (257) and a capacitor contact hole (258), different potentials can be applied between the light-blocking layer (205) connected to the first pixel electrode (260) and the light-blocking layer (205) connected to the second pixel electrode (262), thereby forming a storage capacitor.

[0065] Meanwhile, the width (EAW2) of the light-emitting region (272) may be defined by the size of the bank hole (270). According to the second embodiment of the specification, the capacitor contact hole (258) is formed by penetrating the flattening film (245), the interlayer insulating film (240), and the second buffer layer (214), and the second pixel electrode (262) is formed on the exposed surface of the capacitor contact hole (258) to form the storage upper electrode. As such, the area of ​​the storage upper electrode may be formed by extending to the flattening film (245), including the exposed surface of the flattening film (245), the interlayer insulating film (240), and the second buffer layer (214). In this way, by forming the storage upper electrode along the exposed surface of the capacitor contact hole (258), the area occupied by the storage capacitor within the circuit can be reduced. And the width (EAW2) in the light-emitting region is increased by at least the area of ​​the reduced storage capacitor, thereby increasing the area of ​​the light-emitting region. That is, the width (EAW2) of the light-emitting region (272) according to the second embodiment of the present specification is increased by at least the width (EAW1) of the light-emitting region according to the first embodiment and the increased width (△EA1), thereby increasing the area of ​​the entire light-emitting region (272). As the area of ​​the light-emitting region (272) increases, the aperture ratio can be improved.

[0066] The organic light-emitting layer (275) is arranged to extend to the upper surface of the bank (265) while connecting to the first pixel electrode (260) exposed by the bank hole (270). The organic light-emitting layer (275) is made of an organic material that emits white light and may display color by a color filter (242), but is not limited thereto.

[0067] A second electrode (280) is disposed on the organic light-emitting layer (275). Accordingly, an organic light-emitting device (OLED) composed of a first pixel electrode (260), an organic light-emitting layer (275), and a second electrode (280) is formed.

[0068] The method of manufacturing the display device of FIGS. 2a and 2b will be described below with reference to the drawings. FIGS. 3 to 13 are cross-sectional views shown to explain the method of manufacturing a display device according to the second embodiment of the present specification. Here, components identical or similar to FIGS. 2a and 2b will be described briefly.

[0069] Referring to FIG. 3, a light-blocking layer (205) and a wiring electrode (210) are formed on a substrate (200). Specifically, a first metal layer (202) and a second metal layer (204) are formed on the substrate (200). Next, a photolithography process using a mask and an etching process are performed on the first metal layer (202) and the second metal layer (204) to form a light-blocking layer (205) and a wiring electrode (210). Here, it is preferable that the light-blocking layer (205) be formed at a position that overlaps with the active layer of the thin-film transistor to be formed later. The light-blocking layer (205) serves to protect the thin-film transistor from light incident from the outside. In one example, the light-blocking layer (205) can serve as a storage lower electrode in the capacitor region (IV-IV'). The wiring electrode (210) may be any one of the driving power supply line (VDD), the data line (DL), or the reference power supply line (Vref).

[0070] The substrate (200) may be made of a flat insulating material. For example, the substrate (200) may be a transparent substrate. The substrate (200) may be made of a hard material such as glass or reinforced glass, or may be made of a flexible material such as plastic, but is not limited thereto.

[0071] The light-blocking layer (205) and the wiring electrode (210) can be formed using the same material. For example, the first metal layer (202) and the second metal layer (204) may be formed by including any one selected from the group of opaque metal materials such as molybdenum (Mo), aluminum (Al), titanium (Ti), or copper (Cu), or an alloy thereof.

[0072] Referring to FIG. 4, a buffer layer (215) is formed on a substrate (200). The buffer layer (215) can be formed to cover the exposed surface of the light-blocking layer (205) and the wiring electrode (210). The buffer layer (215) serves to insulate the light-blocking layer (205) and the wiring electrode (210) from the upper components to be formed later. Additionally, the buffer layer (215) blocks moisture, oxygen, or impurities from penetrating from the substrate (200) toward the organic light-emitting diode to be formed on top, and protects the thin-film transistor.

[0073] The buffer layer (215) can be formed as a multilayer structure. In one example, the buffer layer (215) may include a first buffer layer (212) and a second buffer layer (214). The first buffer layer (212) and the second buffer layer (214) may be composed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). Here, the first buffer layer (212) may be formed of silicon nitride (SiNx) of a first thickness, and the second buffer layer (214) may be formed of silicon oxide (SiOx) of a second thickness that is thicker than the first buffer layer (220). For example, the first buffer layer (212) may be formed with a first thickness of 1000 Å to 1500 Å, and the second buffer layer (214) may be formed with a second thickness of 2700 Å to 3300 Å.

[0074] Referring to FIG. 5, an active layer (220) is formed on a buffer layer (215). The active layer (220) may be formed by including at least one of amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the active layer (220) may include at least one oxide semiconductor material such as an indium gallium zinc oxide (IGZO) system and an indium zinc oxide (IZO) system. Additionally, the active layer (220) may be formed with other oxide semiconductor materials known in the art. The active layer (220) may be formed at a location that overlaps with the region where a gate electrode is to be formed.

[0075] A gate insulating film (230) is formed on the front surface of a buffer layer (215) including an active layer (220), and a patterning process is performed on the gate insulating film (230) to form a plurality of GI holes (222, 224, 226, 228) within the gate insulating film (230).

[0076] The patterning process can be performed by forming a photoresist pattern (not shown) containing a plurality of open regions on a gate insulating film (230) and removing the gate insulating film (230) exposed by the open regions. Through this patterning process, a plurality of GI holes (222, 224, 226, 228) are formed within the gate insulating film (230).

[0077] A plurality of GI holes (222, 224, 226, 228) may include a light-blocking contact hole (222) formed such that the buffer layer (215) is removed to expose the surface of the light-blocking layer (205). Additionally, a plurality of GI holes (222, 224, 226, 228) may include a source contact hole (224) and a drain contact hole (226) that expose the surface of the active layer (220). Then, the gate insulating film (230) is exposed by removing the photoresist pattern through a strip process.

[0078] Referring to FIG. 6, a gate electrode (GE), a source electrode (SE), a drain electrode (DE), and a pad electrode (PE) are formed on a substrate (200).

[0079] To this end, a gate metal layer (232, 234) is formed on a gate insulating film (230) having a plurality of GI holes (222, 224, 226, 228). The gate metal layer (232, 234) can be formed in a stacked structure of a first gate metal layer (232) and a second gate metal layer (234). In one example, the first gate metal layer (232) and the second gate metal layer (234) may be composed of any one of the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof, but are not limited thereto.

[0080] Next, a gate electrode (GE) is formed by patterning the gate metal layer (232, 234) and the gate insulating film (230) through a photolithography process using a photomask and an etching process. The etching process can be performed using a dry etching method. During the process of forming the gate electrode (GE), a source electrode (SE), a drain electrode (DE), and a pad electrode (PE) can be formed together. Since the source electrode (SE), the drain electrode (DE), and the pad electrode (PE) are formed by patterning the same gate metal layer (232, 234), they can be formed on the same plane as the gate electrode (GE). The drain electrode (DE) can come into contact with the exposed surface of the light-blocking layer (205) while filling the light-blocking contact hole (222).

[0081] Meanwhile, during the process of dry etching to form a gate electrode (GE), conductivity may be achieved on the active layer (220). When the active layer (220) is formed as an oxide semiconductor, the conductivity characteristics vary depending on the oxygen content. For example, if the oxygen content within the oxide semiconductor decreases, the resistance of the oxide semiconductor decreases, and conductivity may be achieved in which the oxide semiconductor acquires conductive properties. Conductivity may be achieved by contacting the exposed surface of the active layer (220) with the etching gas applied in dry etching to reduce the oxygen content within the oxide semiconductor, thereby forming a conductive region.

[0082] The conductive region may include a source region (SA) and a drain region (DA). Additionally, a channel region (CH) may be disposed in the active layer (220) below the gate electrode (GE) where the conductive region is not formed.

[0083] Referring to FIG. 7, an interlayer insulating film (240) is formed on a substrate (200) on which a gate electrode (GE) is formed. The interlayer insulating film (240) is formed with a sufficient thickness to cover the surfaces of the gate electrode (GE), source electrode (SE), drain electrode (DE), and pad electrode (PE). The interlayer insulating film (240) can be formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).

[0084] Next, a color filter (242) is formed on the interlayer insulating film (240). To do this, red (R), green (G), and blue (B) pigments are applied to the interlayer insulating film (240), and a mask process is performed to form a color filter (242) corresponding to the light-emitting region. If the color filter (242) consists of red (R), green (G), and blue (B), the mask process may require three mask processes.

[0085] A planarization film (245) is formed on the interlayer insulating film (240) on which the color filter (242) is disposed. The planarization film (245) can be formed to have a sufficient thickness to flatten the surface on the substrate (200) while serving to protect the lower components. The planarization film (245) may include an organic insulating material having photo-like properties. In one example, the planarization film (245) may include a photoacrylic material.

[0086] Next, a photoresist pattern (247) is formed including a plurality of open regions (a) that selectively expose the surface of the planarization film (245). The plurality of open regions (a) are positioned to overlap with the region where the drain electrode (DE), the gate electrode (GE), and the storage capacitor are to be formed. The photoresist pattern (247) can be formed using a positive type resist material.

[0087] Referring to FIG. 8, a first patterning process is performed using a photoresist pattern (247) on a planarization film (245). The first patterning process can be performed using a dry etching method. Then, the planarization film (245) exposed by a plurality of open regions (a) of the photoresist pattern (247) is etched to form a plurality of upper contact holes (250, 252, 254) within the planarization film (245). The plurality of upper contact holes (250, 252, 254) may include a first upper contact hole (250) that overlaps at a location where a gate electrode (GE) is placed, a second upper contact hole (252) that overlaps at a location where a drain electrode (DE) is placed, and a third upper contact hole (254) that overlaps at a location where a light-blocking layer (205), which serves as a storage lower electrode in the capacitor region (IV-IV'), is placed.

[0088] The surface of the interlayer insulating film (240) below the flattening film (245) can be exposed by a plurality of upper contact holes (250, 252, 254).

[0089] In the first patterning process, the planarization film (245) is processed using a dry etching method with a photoresist pattern (247), thereby allowing the multiple upper contact holes (250, 252, 254) to have fine line widths, compared to a method of directly performing exposure and development processes on the planarization film (245) to perform patterning. Then, a stripping process is performed to remove the photoresist pattern (247).

[0090] Referring to FIG. 9, a second patterning process is performed on a planarized film (245) having a plurality of upper contact holes (250, 252, 254) formed therein. The second patterning process can be performed using a wet etching method. In one example, the wet etching method can be performed using a buffered oxide etchant (BOE) solution mixed with an ammonium fluoride (NH4F) solution and a hydrogen fluoride (HF) solution.

[0091] When a second patterning process using a wet etching method is performed, the interlayer insulating film (240) with the surface exposed is removed, and a first lower contact hole (251), a second lower contact hole (253), and a third lower contact hole (255) can be formed. Accordingly, a gate contact hole (257), a pixel contact hole (256), and a capacitor contact hole (258) can be formed within the planarization film (245) and the interlayer insulating film (240). Here, the gate contact hole (257) is composed of a first lower contact hole (251) and a first upper contact hole (250), the pixel contact hole (256) is composed of a second lower contact hole (253) and a second upper contact hole (252), and the capacitor contact hole (258) can be composed of a third lower contact hole (255) and a third upper contact hole (254).

[0092] The BOE solution can selectively etch silicon oxide. Accordingly, the capacitor contact hole (258) formed in the capacitor region (IV-IV') can have the second buffer layer (214) made of silicon oxide removed, thereby exposing the surface of the first buffer layer (212). The first buffer layer (212) is composed of a material having a different etching selectivity ratio from that of the second buffer layer (214), for example, silicon nitride. Accordingly, it can serve as an etching stop layer to prevent excessive etching into the underlying film during the second patterning process.

[0093] Meanwhile, due to the isotropic etching characteristics of wet etching, the first lower contact hole (251), the second lower contact hole (253), and the third lower contact hole (255) formed within the interlayer insulating film (240) can be formed with a relatively wider width than the first upper contact hole (250), the second upper contact hole (252), and the third upper contact hole (254). Accordingly, an undercut (UC) may occur between the planarization film (245) and the interlayer insulating film (240). An undercut can be understood as a phenomenon in which the interlayer insulating film (240) is additionally removed inwardly from the end portion of the planarization film (245). If a subsequent process is carried out while an undercut (UC) has occurred, problems such as a disconnection may occur in the subsequent process.

[0094] Accordingly, as illustrated in FIG. 10, an ashing process is performed to remove a portion of the thickness of the planarization film (245). The ashing process can be performed using a dry etching method with oxygen (O2) plasma. By performing the ashing process, the planarization film (245) can be removed from the portion that protrudes beyond the side portion of the interlayer insulating film (245) and forms an undercut (UC), thereby aligning it with one side portion of the interlayer insulating film (240). Accordingly, the pixel contact hole (256) and the gate contact hole (257) can be formed so that the end portions of the planarization film (245) and the interlayer insulating film (240) are aligned in a line. Additionally, the capacitor contact hole (258) can be formed so that the end portions of the planarization film (245), the interlayer insulating film (240), and the second buffer layer (214) are aligned in a line.

[0095] Referring to FIG. 11, a first pixel electrode (260) and a second pixel electrode (262) are formed on a flattening film (245) having a pixel contact hole (256), a gate contact hole (257), and a capacitor contact hole (258).

[0096] The first pixel electrode (260) can be electrically connected to the gate electrode (GE) through the drain electrode (DE) exposed in the pixel contact hole (256). The second pixel electrode (262) can be connected by direct contact with the gate electrode (GE) exposed by the gate contact hole (257). The second pixel electrode (262) can be formed to directly contact the gate electrode (GE) and extend along the exposed surface of the gate contact hole (257) to the upper surface of the flattening film (245) to cover the entire exposed surface of the capacitor contact hole (258). Accordingly, the second pixel electrode (262) can be positioned to overlap with the light blocking layer (205), which acts as the lower storage electrode, with the first buffer layer (212) in between, thereby becoming the upper storage electrode. Thus, a storage capacitor composed of the light blocking layer (205), the first buffer layer (212), and the second pixel electrode (262) can be formed.

[0097] A storage capacitor according to the first embodiment of the present specification introduces a double layer of a first buffer layer (120) and a second buffer layer (122) as dielectrics. The first buffer layer (120) is made of silicon nitride, and the second buffer layer (122) is made of silicon oxide. The dielectric constant of silicon nitride is about 6.9, while the dielectric constant of silicon oxide is about 3.9. In addition, the first buffer layer (120) is formed to have a first thickness of 1000 Å to 1500 Å, and the second buffer layer (12) is formed to have a second thickness of 2700 Å to 3300 Å. Accordingly, the capacitor capacitance of the storage capacitor (Cst) according to the first embodiment has a constant value of 0.0011.

[0098] Accordingly, the dielectric of the storage capacitor according to the second embodiment of the present specification is composed of a single layer of the first buffer layer (212) containing silicon nitride. Since the dielectric constant of silicon nitride is approximately 6.9, the capacitance value of the storage capacitor (Cst) has a value of 0.0069 * constant. Accordingly, the capacitor capacity of the storage capacitor according to the second embodiment, in which a single layer of the first buffer layer (220) is introduced as a dielectric, can be secured at a capacitor capacity that is approximately 6 times greater than that of the storage capacitor (Cst) according to the first embodiment. In other words, by introducing a single layer of the first buffer layer (220) as a dielectric, the light emission of the light-emitting element can be maintained for a relatively longer period than when a double layer of the first buffer layer and the second buffer layer is introduced.

[0099] Additionally, as illustrated in FIG. 1a and FIG. 1b, the storage capacitor according to the first embodiment of the present specification uses the same material as the active layer (125) as the storage upper electrode (125a). Accordingly, since the storage upper electrode (125a) is formed on the same plane as the active layer (125), the area occupied by the storage capacitor in the circuit must be secured.

[0100] In this regard, according to the second embodiment of the present specification, the capacitor contact hole (258) is formed by penetrating the flattening film (245), the interlayer insulating film (240), and the second buffer layer (214), and the second pixel electrode (262) is formed on the exposed surface of the capacitor contact hole (258) to form the storage upper electrode. As such, the area of ​​the storage upper electrode can be formed by extending to the flattening film (245), including the exposed surface of the flattening film (245), the interlayer insulating film (240), and the second buffer layer (214). In this way, by forming the storage upper electrode along the exposed surface of the capacitor contact hole (258), the area occupied by the storage capacitor within the circuit can be reduced compared to when the storage upper electrode (125a, see FIG. 1b) is formed in a flat shape on the flattening film to achieve the same capacitance. And the width of the light-emitting region can be increased by at least the area of ​​the reduced storage capacitor, thereby increasing the area of ​​the light-emitting region.

[0101] As the area of ​​the light-emitting region increases, the current consumption required to achieve the same brightness in individual pixels can be reduced, thereby increasing the lifespan of the organic light-emitting diode and improving the reliability of the display device.

[0102] The first pixel electrode (260) and the second pixel electrode (262) can be formed using the same material. For example, the first pixel electrode (260) and the second pixel electrode (262) may be composed of a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The first pixel electrode (260) may also be referred to as an anode electrode. Here, during the process of forming the first pixel electrode (260) or the second pixel electrode (262), a pad cover electrode (263) may be formed to cover the exposed surface of the pad electrode (PE) and prevent corrosion of the pad electrode (PE).

[0103] Referring to FIG. 12, a bank (265) having a bank hole (270) is formed on a flattening film (245) on which a first pixel electrode (260) and a second pixel electrode (262) are formed. The bank (265) can be formed to cover the remaining portion while exposing a portion of the first pixel electrode (260) through the bank hole (270).

[0104] To this end, an insulating film is formed on the planarization film (245), and a patterning process is performed on the insulating film to form bank holes (265). The bank (265) separates each sub-pixel by defining a boundary region that defines the light-emitting region of the area where the pixel is to be formed. The bank (265) can be formed using an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), or an organic insulating material such as polyimide. The bank (265) can be formed in an area excluding the pad region (I-I') that exposes the pad electrode (PE) covered by the pad cover electrode (263).

[0105] Referring to FIG. 13, an organic light-emitting layer (275) and a second electrode (280) are formed on a light-emitting region defined by a bank (265). Accordingly, an organic light-emitting device (OLED) composed of a first pixel electrode (260), an organic light-emitting layer (275), and a second electrode (280) can be formed. The organic light-emitting layer (275) and the second electrode (280) can be formed in the remaining region excluding the pad region (I-I').

[0106] The organic light-emitting layer (275) is formed to be directly connected to the first pixel electrode (260) exposed by the bank hole (270). In one example, the organic light-emitting layer (275) may be formed to extend along the exposed surface of the first pixel electrode (260) to the upper surface of the bank (265). In one example, the organic light-emitting layer (275) is made of an organic material that emits white light and may display a color by means of a color filter (242).

[0107] The second electrode (280) can be formed to cover the entire exposed surface of the organic light-emitting layer (275). The second electrode (280) can be formed as a common electrode that applies voltage by making common contact with adjacent pixels on the display area. The second electrode (280) may also be referred to as a cathode electrode. In one example, the second electrode (280) may be composed of a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). Alternatively, the second electrode (280) may be formed of a semi-transparent metal material composed of molybdenum (Mo), tungsten (W), silver (Ag), or aluminum (Al) and an alloy containing at least one of these.

[0108] A display device according to the second embodiment of the present specification forms a pixel electrode by separating it into a first pixel electrode and a second pixel electrode. The first pixel electrode is connected to a light-emitting part while electrically connecting the gate electrode and the light-blocking film, and the second pixel electrode is used as a storage upper electrode while directly connecting the gate electrode through a gate contact hole. This allows the area occupied by the storage capacitor in the circuit to be reduced, thereby increasing the area of ​​the light-emitting region. Additionally, the capacitance of the storage capacitor can be increased by applying a configuration that reduces the dielectric thickness.

[0109] FIGS. 14a and FIGS. 14b are drawings illustrating a display device according to a third embodiment of the present specification. FIG. 14a is a plan view of a display device according to a third embodiment. FIG. 14b is a cross-sectional view taken by cutting along the directions I-I', II-II', III-III', IV-IV', and VV' of FIG. 14a.

[0110] Referring to FIG. 14a and FIG. 14b, a display device (30) according to the third embodiment of the present specification includes a light-emitting region (372) in which an organic light-emitting element that emits light is disposed, and a circuit section equipped with driving circuit elements for supplying a driving current to the organic light-emitting element. The driving circuit elements include a thin-film transistor and a storage capacitor. The driving circuit elements constituting the circuit section are disposed in the remaining region excluding the light-emitting region (372).

[0111] The thin-film transistor includes a gate electrode (GE), a source electrode (SE), a drain electrode (DE), and an active layer (320). The gate electrode (GE) may be positioned overlapping the channel region (CH) of the active layer (320). A gate insulating film (330) is disposed between the gate electrode (GE) and the channel region (CH) of the active layer (320). The gate electrode (GE), the source electrode (SE), and the drain electrode (DE) are made of the same material and are located on the same plane. The source electrode (SE) is electrically connected to the source region (SA) of the active layer (320), and the drain electrode (DE) is electrically connected to the drain region (DA) of the active layer (320). Additionally, the drain electrode (DE) is electrically connected to the first pixel electrode (360) by contacting it through a pixel contact hole (351) that penetrates the planarization film (345) and the interlayer insulating film (340). Additionally, the drain electrode (DE) can be electrically connected to the first light-blocking layer (305) through a light-blocking contact hole (322) that penetrates the buffer layer (315).

[0112] A first light-blocking layer (305) and a second light-blocking layer (311) are located between the active layer (320) and the substrate (300). When viewed from a plane, the first light-blocking layer (305) and the second light-blocking layer (311) are spaced apart from each other by a predetermined distance.

[0113] A wiring electrode (310) may be located on the same plane as the first light-blocking layer (305) and the second light-blocking layer (311). The wiring electrode (310) includes a driving power supply line (VDD) or a data line (DL). Here, the wiring electrode (310) is arranged in a first direction (X) of the substrate (300), for example, in a horizontal line. Corresponding to the driving power supply line (VDD) or data line (DL) arranged in the first direction (X), which is a horizontal line, a scan line (SCAN1) and a reference power supply line (Vref) are arranged in a second direction (Y), which is a vertical line. Here, the driving power supply line (VDD) may correspond to a single scan line (SCAN1).

[0114] An interlayer insulating film (340) and a planarization film (345) are disposed on a substrate (300) on which a gate electrode (GE), a source electrode (SE), and a drain electrode (DE) are formed. A color filter (342) is disposed on the interlayer insulating film (340). The color filter (342) is disposed at a position that overlaps with the light-emitting region (372). The planarization film (345) is formed to form a flat surface and may be composed of photoacrylic resin, etc. The planarization film (345) includes a pixel contact hole (351) that exposes a portion of the surface of the drain electrode (DE) and a capacitor contact hole (355) that exposes a portion of the surface of the second light-blocking layer (311).

[0115] The flattening film (345) can cover the exposed side portions of the interlayer insulating film (340) and the second buffer layer (314) by a predetermined thickness.

[0116] The storage capacitor is configured such that the second light-blocking layer (311) and the first pixel electrode (360) are positioned in an overlapping manner with the first buffer layer (312) in between. The first pixel electrode (360) may be positioned to extend from the exposed surface of the pixel contact hole (351) to the upper surface of the flattening film (345) and to cover the exposed surface of the capacitor contact hole (355) formed on the capacitor region (IV-IV'). The capacitor contact hole (355) may be positioned to penetrate the flattening film (345), the interlayer insulating film (340), and the second buffer layer (314).

[0117] A first pixel electrode (360) is placed on a flattening film (345) and a pixel contact hole (31) and electrically connected to a drain electrode (DE). The first pixel electrode (360) is placed on the flattening film (345) so as to overlap with a driving circuit element including a thin-film transistor and a storage capacitor, and a light-emitting region (372) formed by a bank hole (370) provided in a bank (365).

[0118] The organic light-emitting layer (375) is connected to the first pixel electrode (360) and extends to the upper surface of the bank (365). A second electrode (380) is disposed on the organic light-emitting layer (375). Accordingly, an organic light-emitting device (OLED) composed of the first pixel electrode (360), the organic light-emitting layer (375), and the second electrode (380) is formed.

[0119] Meanwhile, the width (EAW3) of the light-emitting region (372) can be defined by the size of the bank hole (370). According to the third embodiment of the present specification, the capacitor contact hole (355) is formed by penetrating the flattening film (345), the interlayer insulating film (340), and the second buffer layer (314), and the first pixel electrode (360) is formed on the exposed surface of the capacitor contact hole (355) to form the storage upper electrode. As such, the area of ​​the storage upper electrode can be formed by extending to the flattening film (345), including the exposed surface of the flattening film (345), the interlayer insulating film (340), and the second buffer layer (314). In this way, by forming the storage upper electrode along the exposed surface of the capacitor contact hole (355), the area occupied by the storage capacitor within the circuit can be reduced. And the width (EAW3) in the light-emitting region increases by at least the area of ​​the reduced storage capacitor, thereby increasing the area of ​​the light-emitting region. That is, the width (EAW3) of the light-emitting region (372) according to the third embodiment of the present specification increases by at least the width (EAW1) of the light-emitting region according to the first embodiment and the increased width (△EA2), thereby increasing the area of ​​the entire light-emitting region (372). As the area of ​​the light-emitting region (372) increases, the aperture ratio can be improved.

[0120] The method of manufacturing the display device of FIGS. 14a and FIGS. 14b will be described below with reference to the drawings. FIGS. 15 to 26 are cross-sectional views shown to explain the method of manufacturing the display device according to the third embodiment. Here, components identical or similar to FIGS. 14a and FIGS. 14b will be described briefly.

[0121] Referring to FIG. 15, a light-blocking layer (305, 311) and a wiring electrode (310) are formed on a substrate (300). Specifically, a first metal layer (302) and a second metal layer (304) are formed on the substrate (300). Next, a photolithography process using a mask and an etching process are performed on the first metal layer (302) and the second metal layer (304) to form the light-blocking layer (305, 311) and the wiring electrode (310).

[0122] The light-blocking layer (305, 311) can be formed by including a first light-blocking layer (305) and a second light-blocking layer (311). Here, it is preferable that the first light-blocking layer (305) be formed at a position that overlaps with the active layer of the thin-film transistor to be formed later. The first light-blocking layer (305) serves to protect the thin-film transistor from light incident from the outside. The second light-blocking layer (311) can serve as a storage lower electrode in the capacitor region. As shown in FIG. 14a, the first light-blocking layer (305) and the second light-blocking layer (311) can be spaced apart from each other by a predetermined distance.

[0123] The wiring electrode (310) may be any one of a driving power supply line (VDD), a data line (DL), or a reference power supply line (Vref). The first light-blocking layer (305), the second light-blocking layer (311), and the wiring electrode (310) may be formed using the same material.

[0124] Referring to FIG. 16, a buffer layer (315) is formed on a substrate (300). The buffer layer (315) can be formed to cover the exposed surface of the light-blocking layer (305, 311) and the wiring electrode (310). The buffer layer (315) insulates the light-blocking layer (305, 311) and the wiring electrode (310) and acts as a protective film to prevent the penetration of moisture or impurities.

[0125] The buffer layer (315) may be formed as a multilayer structure including a first buffer layer (312) and a second buffer layer (314), but is not limited thereto. In one example, the first buffer layer (312) and the second buffer layer (314) may be composed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The first buffer layer (312) may be formed with a first thickness of 1000 Å to 1500 Å, and the second buffer layer (314) may be formed with a second thickness of 2700 Å to 3300 Å, which is thicker than the first thickness of the first buffer layer (312).

[0126] Referring to FIG. 17, an active layer (320) is formed on a buffer layer (315). Then, a gate insulating film (330) having a plurality of GI holes (322, 324, 326, 328) is formed on the active layer (320).

[0127] The active layer (320) may be formed by including at least one of amorphous silicon, polycrystalline silicon, or oxide semiconductor. For example, the active layer (320) may include at least one of oxide semiconductor materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO). The active layer (320) may be formed at a position that overlaps with the region where a gate electrode is to be formed thereafter. A plurality of GI holes (322, 324, 326, 328) may include a light-blocking contact hole (322) in which the buffer layer (315) is removed to expose the surface of the first light-blocking layer (305). Additionally, a plurality of GI holes (322, 324, 326, 328) may include a source contact hole (324) and a drain contact hole (326) in which the surface of the active layer (320) is exposed.

[0128] Referring to FIG. 18, a gate electrode (GE), a source electrode (SE), a drain electrode (DE), and a pad electrode (PE) are formed on a substrate (300). To do this, a gate metal layer (332, 334) is formed on a gate insulating film (330) having a plurality of GI holes (322, 324, 326, 328), and a patterning process is performed on the gate metal layer (332, 334). The patterning process can be performed using a dry etching method.

[0129] The gate metal layer (332, 334) can be formed in a stacked structure of the first gate metal layer (332) and the second gate metal layer (334). In one example, the first gate metal layer (332) and the second gate metal layer (334) may be composed of any one of the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof.

[0130] The gate electrode (GE), source electrode (SE), drain electrode (DE), and pad electrode (PE) can be formed by patterning the same gate metal layer (332, 334). Accordingly, they can be formed on the same plane. The drain electrode (DE) can come into contact with the exposed surface of the first light-blocking layer (305) while filling the light-blocking contact hole (322). Here, the surface of the second light-blocking layer (310) is covered with a buffer layer (315).

[0131] Meanwhile, during the process of dry etching to form the gate electrode (GE), conductivity may be formed on the active layer (320) to form a conductive region. The conductive region may include a source region (SA) and a drain region (DA). Additionally, a channel region (CH) may be disposed on the active layer (320) below the gate electrode (GE) where the conductive region is not formed.

[0132] Referring to FIG. 19, an interlayer insulating film (340) is formed on a substrate (300) on which a gate electrode (GE) is formed. The interlayer insulating film (340) is formed with a sufficient thickness to cover the surfaces of the gate electrode (GE), source electrode (SE), drain electrode (DE), and pad electrode (PE). The interlayer insulating film (340) can be formed from an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). Next, a color filter (342) is formed on the interlayer insulating film (340). To do this, red (R), green (G), and blue (B) pigments can be applied to the interlayer insulating film (340), and a mask process can be performed to form a color filter (342) corresponding to a light-emitting region.

[0133] A planarization film (345) is subsequently formed on the interlayer insulating film (340). The planarization film (345) can be formed to have a sufficient thickness to planarize the surface of the substrate (300). The planarization film (345) may include an organic insulating material having photo-like properties. In one example, the planarization film (345) may include a photoacrylic material.

[0134] Next, a first patterning process is performed on the planarization film (345) to form a plurality of upper contact holes (346, 348) within the planarization film (345). To do this, a mask having an opening is placed on the upper surface of the planarization film (345) having photo-specific properties, and an exposure process is performed on the planarization film (345) exposed by the opening to modify the exposed portion, and then a development process is performed to remove the modified portion of the planarization film (345) using a developer to form a plurality of upper contact holes (346, 348).

[0135] A plurality of upper contact holes (346, 348) may include a first upper contact hole (346) that overlaps the location where a drain electrode (DE) is placed, and a second upper contact hole (348) that overlaps the location where a second light-blocking layer (311), which serves as a storage lower electrode in the capacitor region (IV-IV'), is placed. The first upper contact hole (346) and the second upper contact hole (348) may each expose the surface of the interlayer insulating film (340).

[0136] Referring to FIG. 20, a second patterning process is performed on a flattening film (345) in which a first upper contact hole (346) and a second upper contact hole (348) are formed to form a first lower contact hole (350) and a second lower contact hole (354) within an interlayer insulating film (340). Accordingly, a pixel contact hole (351) and a capacitor contact hole (355) may be formed within the flattening film (45) and the interlayer insulating film (340). Here, the pixel contact hole (351) may be composed of a first lower contact hole (350) and a first upper contact hole (346), and the capacitor contact hole (355) may be composed of a second lower contact hole (354) and a second upper contact hole (348). The second lower contact hole (354) of the capacitor contact hole (355) can expose the surface of the first buffer layer (312) by removing the second buffer layer (314).

[0137] To this end, first, a dry etching method is performed on the first upper contact hole (346) and the second upper contact hole (348) to etch the interlayer insulating film (340). During the dry etching process, in the region (IV-IV') where the storage capacitor is to be formed, the interlayer insulating film (340) is completely etched, and the second buffer layer (314) can be additionally etched to a predetermined depth from the surface. Accordingly, in the region (IV-IV') where the storage capacitor is to be formed, the second buffer layer (314) can remain on the first buffer layer (312) by a predetermined thickness.

[0138] Next, a process is performed to remove the second buffer layer (314) remaining on the first buffer layer (312) in the region (IV-IV') where the storage capacitor is to be formed. The process for removing the remaining second buffer layer (314) can be performed using a wet etching method. In one example, the wet etching method can be performed using a buffered oxide etchant (BOE) solution mixed with an ammonium fluoride (NH4F) solution and a hydrogen fluoride (HF) solution. By using the BOE solution, the remaining second buffer layer (314) made of silicon oxide in the storage capacitor region (IV-IV') can be removed, and the surface of the first buffer layer (312) can be exposed. Since the first buffer layer (312) is composed of silicon nitride, it can act as an etching stop layer without being etched by the BOE solution.

[0139] Meanwhile, due to the isotropic characteristics of wet etching, the first lower contact hole (350) and the second lower contact hole (354) formed within the interlayer insulating film (340) are formed to have a wider width than the first upper contact hole (346) and the second upper contact hole (348), so that an undercut (UC) may occur between the flattening film (345) and the interlayer insulating film (340).

[0140] Referring to FIG. 21, a reflow process is performed on the planarization film (345). The reflow process involves applying heat to the planarization film (345) to make it fluid, and the fluid planarization film (345) can cover the exposed side portions of the interlayer insulating film (340) and the second buffer layer (314) by a predetermined thickness. Accordingly, the exposed surface of the pixel contact hole (351) and capacitor contact hole (355) can have a smooth surface with the undercut (UC, see FIG. 20) removed. Meanwhile, during the process of performing the reflow process, the width of the pixel contact hole (351) and capacitor contact hole (355) can be reduced by the thickness of the reflow. Then, a curing process is performed to cure the reflowed planarization film (345).

[0141] As described above, during the process of performing wet etching to remove the second buffer layer (314) remaining on the first buffer layer (312) in the storage capacitor region (IV-IV'), an undercut (UC) may occur between the planarization film (345) and the interlayer insulating film (340). If a subsequent first electrode is formed while the undercut (UC) is present, problems such as a disconnection may occur.

[0142] FIG. 22 illustrates an example of a disconnection phenomenon caused by an undercut. Referring to FIG. 22, an undercut (UC) can be understood as a phenomenon in which an interlayer insulating film (PAS) is additionally removed below the shape of a planarization film (OC). In other words, the undercut (UC) can be formed by removing the interlayer insulating film (PAS) in an inward direction from the end of the planarization film (OC), rather than the interlayer insulating film (PAS) being removed vertically aligned with the end of the planarization film (OC).

[0143] In this way, when a pixel electrode (PXL) is formed in a state where an undercut (UC) occurs, the pixel electrode (PXL) is disconnected at the undercut (UC) portion between the end of the planarization film (OC) and the interlayer insulating film (PAS), and thus is not electrically connected to the drain electrode (DE). Consequently, this can act as a defect in the device that is not electrically connected to the light blocking layer (LSD) on the substrate (SUB). Here, the part not described in FIG. 22 is the buffer layer (BUF).

[0144] In this regard, in the third embodiment of the present specification, as illustrated in FIG. 21, a reflow process is performed on the planarization film (345) to cover the side portions of the interlayer insulating film (240) and the buffer layer (314) with the planarization film (345), thereby preventing a break in the line caused by an undercut between the planarization film (345), the interlayer insulating film (340), and the buffer layer (314). Additionally, during the process of performing the reflow process on the planarization film (345), the width of the pixel contact hole (351) and the capacitor contact hole (355) can be reduced by the thickness of the reflow. As such, as the size of the pixel contact hole (351) and the capacitor contact hole (355) is reduced, the area occupied by the contact holes in the circuit can be reduced. The area of ​​the light-emitting region (372) can be secured to the extent that the area occupied by the contact holes in the circuit is reduced.

[0145] Referring to FIG. 23, a first pixel electrode (360) is formed on a flattening film (345) in which a pixel contact hole (351) and a capacitor contact hole (355) are formed.

[0146] The first pixel electrode (360) can be electrically connected to the gate electrode (GE) through the drain electrode (DE) exposed in the pixel contact hole (351). The first pixel electrode (360) may also be referred to as an anode electrode. Here, during the process of forming the first pixel electrode (360), the exposed surface of the pad electrode (PE) can be covered with the same material as the first pixel electrode (360) to form a pad cover electrode (362).

[0147] Referring to FIG. 24, a bank (365) having a bank hole (370) is formed on a flattening film (345) on which a first pixel electrode (360) is formed. The bank (365) can be formed to cover the remaining portion while exposing a portion of the first pixel electrode (360) through the bank hole (370). Here, in the capacitor region (IV-IV'), the second light-blocking layer (311) and the first pixel electrode (360) are positioned overlappingly with the first buffer layer (312) in between to form a storage capacitor.

[0148] The bank (365) separates each subpixel into a boundary area that defines the light-emitting area (372, see FIG. 14a) of the area where the pixel is to be formed. The bank (365) may be formed in an area excluding the pad area (I-I') that exposes the pad electrode (PE) covered by the pad cover electrode (362).

[0149] Next, an organic light-emitting layer (375) and a second electrode (380) are formed on the light-emitting region (372) defined by the bank (365). Accordingly, an organic light-emitting device (OLED) composed of a first pixel electrode (360), an organic light-emitting layer (375), and a second electrode (380) can be formed. The organic light-emitting layer (375) and the second electrode (380) can be formed in the remaining region excluding the pad region (I-I').

[0150] The organic light-emitting layer (375) is formed to be directly connected to the first pixel electrode (360) exposed by the bank hole (370). In one example, the organic light-emitting layer (375) may be formed to extend along the exposed surface of the first pixel electrode (360) to the upper surface of the bank (365). In one example, the organic light-emitting layer (375) is made of an organic material that emits white light and may display a color by means of a color filter (342).

[0151] Although not shown in the drawing, the organic light-emitting layer (375) may include a stacked structure of a hole transport layer (HTL), a light-emitting layer (EML), and an electron transport layer (ETL). The organic light-emitting layer (375) may also be configured to include a hole blocking layer (HBL), a hole injection layer (HIL), an electron blocking layer (EBL), and an electron injection layer (EIL) together with the hole transport layer (HTL), the light-emitting layer (EML), and the electron transport layer (ETL).

[0152] The second electrode (380) can be formed to cover the entire exposed surface of the organic light-emitting layer (375). The second electrode (380) can be formed as a common electrode that applies voltage by making common contact with adjacent pixels on the display area. The second electrode (380) may also be referred to as a cathode electrode.

[0153] Meanwhile, in the third embodiment of this specification, a method of performing direct exposure and development processes on a planarization film (345) and a reflow process was described for the purpose of explaining a preferred embodiment, but it is not limited thereto. For example, a method of forming a photoresist pattern including an open region on a planarization film as described in the second embodiment of this specification and forming a plurality of contact holes using an etching method utilizing the photoresist pattern may be used. In addition, a method of performing direct exposure and development processes on a planarization film and a reflow process to form a plurality of contact holes as described in the second embodiment of this specification may also be applied.

[0154] A display device according to the third embodiment of the present specification can reduce the area occupied by the storage capacitor within the circuit by forming a light-blocking layer by separating it into a first light-blocking layer and a second light-blocking layer, applying the second light-blocking layer as a storage lower electrode, forming a capacitor contact hole overlapping with the second light-blocking layer, and then placing a first pixel electrode as a storage upper electrode on the exposed surface of the capacitor contact hole. By reducing the area occupied by the storage capacitor within the circuit, the area in the light-emitting region can be increased, thereby improving the aperture ratio. Explanation of the symbols

[0155] 100, 200, 300: Substrate 105, 205, 305, 311: Light-blocking layer 215, 315: Buffer layer 220, 320: Active layer 230, 330: Gate insulating film GE: Gate electrode SE: Source electrode DE: Drain electrode 240, 340: Interlayer insulation film 242, 342: Color filter 245, 345: Planarization film 260: First pixel electrode 262: Second pixel electrode 360: First electrode 275, 375: Organic light-emitting layer 280, 380: Second electrode

Claims

Claim 1 A display device comprising: a substrate having a light-blocking layer disposed thereon; a buffer layer located on the substrate; a thin-film transistor located on the buffer layer and including a gate electrode, a source electrode, and a drain electrode; an interlayer insulating film and a planarization film located on the gate electrode; a plurality of contact holes penetrating the interlayer insulating film and the planarization film, each exposing a portion of the drain electrode, a portion of the gate electrode, and a portion of the buffer layer, respectively; a first pixel electrode located on the planarization film and electrically connected to the drain electrode through at least one contact hole among the plurality of contact holes; and a second pixel electrode located on the planarization film and connected to the gate electrode through at least one contact hole among the plurality of contact holes, wherein the second pixel electrode overlaps the light-blocking layer and the substrate in a vertical direction with the buffer layer in between through a contact hole that exposes a portion of the buffer layer among the plurality of contact holes. Claim 2 A display device according to claim 1, wherein the buffer layer comprises a first buffer layer having a first dielectric constant of a first thickness; and a second buffer layer located on the first buffer layer, wherein the second thickness of the second buffer layer is thicker than the first thickness of the first buffer layer, and the second dielectric constant of the second buffer layer is lower than the first dielectric constant of the first buffer layer. Claim 3 A display device according to paragraph 2, wherein the plurality of contact holes include a drain contact hole exposing a portion of the drain electrode and a gate contact hole exposing a portion of the gate electrode; and a capacitor contact hole penetrating the planarization film, the interlayer insulating film and the second buffer layer to expose a portion of the surface of the first buffer layer. Claim 4 A display device according to paragraph 3, wherein the second pixel electrode is formed along the exposed surface of the gate contact hole and connected to the exposed gate electrode, and is formed along the exposed surface of the capacitor contact hole and overlaps with the light blocking layer with the first buffer layer in between to form a storage capacitor. Claim 5 A display device according to claim 1, wherein the first pixel electrode and the second pixel electrode are positioned spaced apart from each other when viewed from a plane. Claim 6 A display device according to paragraph 3, wherein the planarization film is located between the capacitor contact hole, the interlayer insulating film, and the second buffer layer. Claim 7 A display device comprising: a first light-blocking layer and a second light-blocking layer disposed on a substrate; a buffer layer located on the first light-blocking layer and the second light-blocking layer; a thin-film transistor located on the buffer layer and including a gate electrode, a source electrode, and a drain electrode; an interlayer insulating film and a planarization film located on the gate electrode; a plurality of contact holes penetrating the interlayer insulating film and the planarization film, each exposing a portion of the drain electrode and the buffer layer, respectively; and a first pixel electrode located on the planarization film and electrically connected to the drain electrode and the first light-blocking layer through at least one contact hole among the plurality of contact holes, wherein the first pixel electrode overlaps the second light-blocking layer and the substrate in a vertical direction with the buffer layer in between through a contact hole that exposes a portion of the buffer layer among the plurality of contact holes. Claim 8 In claim 7, the first light-blocking layer and the second light-blocking layer are positioned spaced apart from each other when viewed in a planar view. Claim 9 A display device according to claim 7, wherein the buffer layer comprises a first buffer layer having a first dielectric constant of a first thickness; and a second buffer layer located on the first buffer layer, wherein the second thickness of the second buffer layer is thicker than the first thickness of the first buffer layer, and the second dielectric constant of the second buffer layer is lower than the first dielectric constant of the first buffer layer. Claim 10 A display device according to claim 9, wherein the plurality of contact holes include a drain contact hole that exposes a portion of a drain electrode, and a capacitor contact hole that penetrates the planarization film, the interlayer insulating film and the second buffer layer to expose a portion of the surface of the first buffer layer. Claim 11 A display device according to claim 10, wherein the planarization film is located between the capacitor contact hole, the interlayer insulating film, and the second buffer layer. Claim 12 A display device according to claim 10, wherein the planarization film covers an exposed side portion of the interlayer insulating film at the drain contact hole while exposing a portion of the drain electrode, and the first pixel electrode extends along the exposed surface of the planarization film and connects with the exposed drain electrode. Claim 13 A display device according to claim 10, wherein the planarization film covers the exposed side portion of the interlayer insulating film and the second buffer layer at the capacitor contact hole while exposing a portion of the surface of the first buffer layer, and the first pixel electrode extends along the exposed surface of the planarization film and is positioned to overlap with the second light-blocking layer with the first buffer layer in between to form a storage capacitor.

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