Display device

Abstract

The display device includes a substrate comprising a display area in which a plurality of pixels are arranged, a hole area located inside the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane, a printed circuit board placed in the pad area on the substrate, a first hole crack detection wiring placed in the peripheral area on the substrate and extending to the bending area and the pad area, a second hole crack detection wiring placed in the peripheral area on the substrate and extending to the bending area and the pad area and electrically connected to the first hole crack detection wiring, a first transistor in which a gate electrode is connected to a first signal wiring to receive a first signal, a first electrode is connected to the printed circuit board, and a second electrode is connected to the first hole crack detection wiring, and a second transistor in which a gate electrode is connected to a second signal wiring to receive a second signal, a first electrode is connected to a high voltage wiring that applies a high voltage, and a second electrode is connected to the first hole crack detection wiring.

Description

Technology Field

[0001] The present invention relates to a display device. More specifically, the present invention relates to a display device that provides visual information. Background Technology

[0002] As information technology develops, the importance of display devices, which serve as a medium of connection between users and information, is being highlighted. For example, the use of display devices such as liquid crystal display devices (LCDs), organic light emitting display devices (OLEDs), plasma display devices (PDPs), and quantum dot display devices is increasing.

[0003] Meanwhile, if the display device is subjected to impact, cracks may occur in the substrate or the layers laminated on the substrate. Over time, these cracks may grow larger or spread to other layers or areas, potentially causing defects in the display device. For example, signal wiring, such as data or gate wiring, may be severed or experience increased resistance due to the cracks, and moisture may penetrate into the interior of the display device through the cracks, leading to reduced device reliability. Consequently, various problems may arise, such as the pixels of the display device failing to emit light or emitting light incorrectly. The problem to be solved

[0004] The objective of the present invention is to provide a display device capable of inspecting a crack in a hole formed in a hole area.

[0005] However, the purpose of the present invention is not limited to such purposes, and may be expanded in various ways without departing from the spirit and scope of the present invention. means of solving the problem

[0006] To achieve the aforementioned objective of the present invention, a display device according to one embodiment of the present invention may include a substrate comprising a display area in which a plurality of pixels are arranged, a hole area located inside the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane, a printed circuit board placed in the pad area on the substrate, a first hole crack detection wiring placed in the peripheral area on the substrate and extending to the bending area and the pad area, a second hole crack detection wiring placed in the peripheral area on the substrate and extending to the bending area and the pad area and electrically connected to the first hole crack detection wiring, a first transistor in which a gate electrode is connected to a first signal wiring to receive a first signal, a first electrode is connected to the printed circuit board, and a second electrode is connected to the first hole crack detection wiring, and a second transistor in which a gate electrode is connected to a second signal wiring to receive a second signal, a first electrode is connected to a high voltage wiring that applies a high voltage, and a second electrode is connected to the first hole crack detection wiring.

[0007] In one embodiment, when the display device is driven in normal mode, a first signal having a low level is applied to the gate electrode of the first transistor through the first signal wiring so that the first transistor is turned on, and a second signal having a high level is applied to the gate electrode of the second transistor through the second signal wiring so that the second transistor is turned off.

[0008] In one embodiment, the first electrode of the first transistor is connected to the ground of the printed circuit board, and when the display device is driven in the normal mode, a ground voltage can be applied to the first hole crack detection wiring and the second hole crack detection wiring through the printed circuit board.

[0009] In one embodiment, when the display device is driven in the normal mode, a low voltage may be applied to the first hole crack detection wiring and the second hole crack detection wiring through the printed circuit board.

[0010] In one embodiment, when the display device is driven in the normal mode, the first hole crack detection wiring and the second hole crack detection wiring may be in a floating state.

[0011] In one embodiment, when the display device is driven in a test mode, a first signal having a high level is applied to the gate electrode of the first transistor through the first signal wiring so that the first transistor is turned off, and a second signal having a low level is applied to the gate electrode of the second transistor through the second signal wiring so that the second transistor is turned on.

[0012] In one embodiment, when the display device is driven in the inspection mode, the high voltage may be applied to the first hole crack detection wiring and the second hole crack detection wiring through the high voltage wiring.

[0013] In one embodiment, the display device further includes a driving chip disposed in the pad area on the substrate, and the driving chip can provide the first signal to the first signal wiring connected thereto and provide the high voltage to the high voltage wiring through the printed circuit board.

[0014] In one embodiment, the display device may further include first connection lines disposed in the pad area on the substrate and providing a data signal to the pixels through the driving chip, and second connection lines disposed in the pad area on the substrate and providing a driving voltage to the pixels through the printed circuit board.

[0015] In one embodiment, the first hole crack detection wiring located in the pad area may be positioned between the first connecting wiring and the second connecting wiring on a plane.

[0016] In one embodiment, the display device may further include a sensing wire adjacent to the hole area, which is disposed in the display area on the substrate and is separated into one end and the other end to surround the periphery of the hole area.

[0017] In one embodiment, one end of the sensing wiring may be electrically connected to the first hole crack sensing wiring, and the other end of the sensing wiring may be electrically connected to the second hole crack sensing wiring.

[0018] In one embodiment, the display device may further include a semiconductor device comprising an active layer disposed in a display area on the substrate, a gate electrode overlapping with a channel area of ​​the active layer, a source electrode connected to a source area of ​​the active layer, and a drain electrode connected to a drain area of ​​the active layer, a touch sensing structure disposed on the semiconductor device and connected to the semiconductor device, a sensing connection pattern disposed on the connecting electrode, and a sensing electrode pattern disposed on the sensing connection pattern.

[0019] In one embodiment, the first hole crack detection wiring and the second hole crack detection wiring each may include a first conductive pattern disposed in the pad area on the substrate, a bridge pattern disposed in the bending area on the substrate and extending to a part of the peripheral area and a part of the pad area and connected to the first conductive pattern, and a second conductive pattern disposed in the peripheral area on the substrate and connected to the bridge pattern.

[0020] In one embodiment, the first conductive pattern may be disposed on the same layer as the source electrode and the drain electrode, the bridge pattern may be disposed on the same layer as the connecting electrode, and the second conductive pattern may be disposed on the same layer as the sensing electrode pattern.

[0021] To achieve the aforementioned objective of the present invention, a display device according to another embodiment of the present invention may include a substrate comprising a display area in which a plurality of pixels are arranged, a hole area located inside the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane, a driving chip disposed in the pad area on the substrate, a first hole crack detection wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area and directly connected to the driving chip, and a second hole crack detection wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area and electrically connected to the first hole crack detection wiring.

[0022] In one embodiment, when the display device is driven in normal mode, a low voltage may be applied to the first hole crack detection wiring and the second hole crack detection wiring through the driving chip.

[0023] In one embodiment, when the display device is driven in normal mode, the first hole crack detection wiring and the second hole crack detection wiring may be connected to the ground of the driving chip or be in a floating state.

[0024] In one embodiment, when the display device is driven in inspection mode, a high voltage may be applied to the first hole crack detection wiring and the second hole crack detection wiring through the driving chip.

[0025] To achieve the aforementioned objective of the present invention, a display device according to another embodiment of the present invention may include a substrate comprising a display area in which a plurality of pixels are arranged, a hole area located inside the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane, a first hole crack detection wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area, a second hole crack detection wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area and electrically connected to the first hole crack detection wiring, and a transistor in which a gate electrode is connected to a signal wiring to receive a signal, the first electrode is connected to a high voltage wiring that applies a high voltage, and the second electrode is connected to the first hole crack detection wiring.

[0026] In one embodiment, when the display device is driven in normal mode, a signal having a high level is applied to the gate electrode of the transistor through the signal wiring so that the transistor can be turned off.

[0027] In one embodiment, when the display device is driven in the normal mode, the first hole crack detection wiring and the second hole crack detection wiring may be in a floating state.

[0028] In one embodiment, when the display device is driven in a test mode, a signal having a low level is applied to the gate electrode of the transistor through the signal wiring so that the transistor can be turned on.

[0029] In one embodiment, when the display device is driven in the inspection mode, the high voltage may be applied to the first hole crack detection wiring and the second hole crack detection wiring through the high voltage wiring.

[0030] In one embodiment, the display device further comprises a driving chip disposed in the pad area on the substrate and a printed circuit board disposed in the pad area on the substrate, wherein the driving chip is connected to the signal wiring to provide the signal to the signal wiring and can provide the high voltage to the high voltage wiring through the printed circuit board. Effects of the invention

[0031] In a display device according to one embodiment of the present invention, when the display device is operated in a normal mode, which is a mode generally used by a user, a low voltage is applied to the first hole crack detection wiring and the second hole crack detection wiring, and when the display device is operated in an inspection mode for inspecting a crack in a hole formed in a hole area, a high voltage may be applied to the first hole crack detection wiring and the second hole crack detection wiring. Accordingly, corrosion of the first and second hole crack detection wirings for inspecting a crack in a hole formed in a hole area of ​​the display device, which may occur when operated for a long time in a high temperature and high humidity environment and a general user environment, can be improved. In addition, corrosion of driving signal wirings located adjacent to the first and second hole crack detection wirings caused by this can be improved.

[0032] However, the effects of the present invention are not limited to the above effects, and may be extended in various ways without departing from the spirit and scope of the present invention. Brief explanation of the drawing

[0033] FIG. 1 is a plan view showing a display device according to one embodiment of the present invention. Figure 2 is a drawing showing the bent shape of the display device of Figure 1. Figure 3 is a plan view showing an enlarged view of area "A" in Figure 1. FIG. 4 is a cross-sectional view showing a part of the display area of ​​the display device of FIG. 1. Figure 5 is a cross-sectional view taken along the lines II' and II-II' of Figure 1. FIG. 6 is a plan view for explaining a touch sensing structure included in the display device of FIG. 5. Figures 7 and 8 are schematic diagrams illustrating the circuit structure for explaining the normal mode and test mode of the display device of Figure 1. FIG. 9 is a diagram showing a circuit structure for explaining the normal mode and inspection mode of a display device according to another embodiment of the present invention. FIG. 10 is a diagram roughly showing a circuit structure for explaining the normal mode and inspection mode of a display device according to another embodiment of the present invention. Specific details for implementing the invention

[0034] Hereinafter, a display device according to embodiments of the present invention will be described in more detail with reference to the attached drawings. Identical components in the drawings will be referred to by the same reference numerals, and redundant descriptions of identical components will be omitted.

[0035] FIG. 1 is a plan view showing a display device according to an embodiment of the present invention. FIG. 2 is a drawing showing the shape of the display device of FIG. 1 bent. FIG. 3 is a plan view showing an enlarged view of the "A" area of ​​FIG. 1. For example, FIG. 3 is a plan view showing an enlarged view of the right portion of the pad area (PDA) of the display device (100) of FIG. 1.

[0036] Referring to FIGS. 1, 2 and 3, a display device (100) according to one embodiment of the present invention may include a substrate (110), a plurality of pixels (PX), a first sensing wire (M1), a second sensing wire (M2), a third sensing wire (M3), a driving chip (IC), and a printed circuit board (FPC).

[0037] The substrate (110) may include a display area (DA), a hole area (HA), a peripheral area (PA), a bending area (BA), and a pad area (PDA). The peripheral area (PA) may surround at least a portion of the display area (DA). For example, the peripheral area (PA) may surround the entire display area (DA). The display area (DA) may be an area that displays an image by generating light or controlling the transmittance of light provided from an external light source. The peripheral area (PA) may be an area that does not display an image.

[0038] A plurality of pixels (PX), each comprising a semiconductor element and a light-emitting element, may be disposed in a display area (DA) on a substrate (110). The plurality of pixels (PX) may generate light according to a driving signal. The plurality of pixels (PX) may be arranged along a first direction (DR1) and a second direction (DR2) that intersects the first direction (DR1). Here, the second direction (DR2) may be a direction substantially orthogonal to the first direction (DR1).

[0039] In the display area (DA) on the substrate (110), wirings (LN) connected to a plurality of pixels (PX) may be further disposed. For example, the wirings (LN) may include data wiring, gate wiring, power wiring, etc.

[0040] As illustrated in FIG. 2, the bending area (BA) may extend from one side of the peripheral area (PA) and may be bent downward. That is, when the bending area (BA) is bent with the first direction (DR1) as an axis, a pad area (PDA) may be located on the bottom surface of the display device (100). The pad area (PDA) may extend from the bending area (BA) and be located below the display area (DA) or the peripheral area (PA). As illustrated in FIG. 1, when the display device (100) is unfolded, the bending area (BA) may be located between the display area (DA) and the pad area (PDA).

[0041] First connection lines (CL1) may be disposed in the pad area (PDA) on the substrate (110). The first connection lines (CL1) may provide a data signal to data lines disposed in the display area (DA) through a driving chip (IC). The data lines may transmit the data signal to a plurality of pixels (PX).

[0042] A second connection wire (CL2) may be disposed in a pad area (PDA) on the substrate (110). The second connection wire (CL2) may provide a driving voltage to power wires disposed in a display area (DA) via a printed circuit board (FPC). The power wires may transmit the driving voltage to a plurality of pixels (PX).

[0043] Dummy patterns (DP1, DP2) may be placed in the pad area (PDA) on the substrate (110). The dummy patterns (DP1, DP2) may be placed spaced apart from each other in a first direction (DR1). Each of the dummy patterns (DP1, DP2) may extend in a second direction (DR2) orthogonal to the first direction (DR1). The dummy patterns (DP1, DP2) may be placed on a plane between a first connecting wire (CL1) and a second connecting wire (CL2).

[0044] A hole area (HA) may be located within a display area (DA). A hole may be formed in the hole area (HA). The hole may penetrate the substrate (110). In one embodiment, a functional module may be disposed on the lower part of the substrate (110) corresponding to the hole. The functional module may receive external light passing through the hole or transmit signals such as infrared, ultrasound, etc.

[0045] For example, the functional module may include a camera module for capturing (or recognizing) an image of an object located on the front of the display device (100), a face recognition sensor module for detecting a user's face, a pupil recognition sensor module for detecting a user's pupil, an accelerometer and a geomagnetic sensor module for determining the movement of the display device (100), a proximity sensor module and an infrared sensor module for detecting proximity to the front of the display device (100), an illuminance sensor module for measuring the degree of external brightness, etc.

[0046] In one embodiment, the hole region (HA) may have a circular shape in a planar shape. However, the present invention is not limited thereto, and the hole region (HA) may have a polygonal shape in a planar shape, an elliptical shape, etc. Additionally, FIG. 1 illustrates a single hole region (HA) with a hole formed inside located within a display region (DA), but the present invention is not limited thereto. For example, a plurality of hole regions with holes formed inside each may be located within the display region (DA).

[0047] A third sensing wire (M3) adjacent to a hole area (HA) may be disposed in a display area (DA) on the substrate (110). The third sensing wire (M3) may be disposed adjacent to the hole area (HA) in a shape that surrounds the periphery of the hole area (HA) by being separated into one end and the other end. The third sensing wire (M3) may be a wire for inspecting cracks in the hole formed in the hole area (HA).

[0048] A first sensing wire (M1) and a second sensing wire (M2) may be disposed in the peripheral area (PA), bending area (BA), and pad area (PDA) on the substrate (110). The first sensing wire (M1) may include a first-1 hole crack sensing wire (HCD1-1) and a second-1 hole crack sensing wire (HCD2-1). One end of the first-1 hole crack sensing wire (HCD1-1) may be electrically connected to a printed circuit board (FPC), and the other end of the first-1 hole crack sensing wire (HCD1-1) may be electrically connected to one end of the third sensing wire (M3). One end of the second-1 hole crack sensing wire (HCD2-1) may be electrically connected to wires (LN), and the other end of the second-1 hole crack sensing wire (HCD2-1) may be electrically connected to the other end of the third sensing wire (M3).

[0049] The 1-1 hole crack detection wiring (HCD1-1) and the 2-1 hole crack detection wiring (HCD2-1) may be located in the surrounding areas (PA) on the lower, left, and upper sides centered on the display area (DA). The 1-1 hole crack detection wiring (HCD1-1) and the 2-1 hole crack detection wiring (HCD2-1) may extend parallel to each other along the edges of the display area (DA).

[0050] The second detection wiring (M2) may include a first-2 hole crack detection wiring (HCD1-2) and a second-2 hole crack detection wiring (HCD2-2). One end of the first-2 hole crack detection wiring (HCD1-2) may be electrically connected to a printed circuit board (FPC), and the other end of the first-2 hole crack detection wiring (HCD1-2) may be electrically connected to one end of the third detection wiring (M3). One end of the second-2 hole crack detection wiring (HCD2-2) may be electrically connected to the wirings (LN), and the other end of the second-2 hole crack detection wiring (HCD2-2) may be electrically connected to the other end of the third detection wiring (M3).

[0051] The first-2 hole crack detection wiring (HCD1-2) and the second-2 hole crack detection wiring (HCD2-2) may be located in the surrounding areas (PA) on the lower, right, and upper sides centered on the display area (DA). The first-2 hole crack detection wiring (HCD1-2) and the second-2 hole crack detection wiring (HCD2-2) may extend parallel to each other along the edges of the display area (DA).

[0052] The display device (100) can be operated in a normal mode, which is a mode generally used by the user, or in an inspection mode for inspecting cracks in the holes formed in the hole area (HA). When the display device (100) is operated in the normal mode, the driving chip (IC) can output the data signal. When the display device (100) is operated in the inspection mode, the driving chip (IC) can provide voltage (e.g., high voltage) to the printed circuit board (FPC). In this case, the driving chip (IC) may not output the data signal.

[0053] When the display device (100) is driven in the inspection mode, a voltage (e.g., high voltage) may be applied to the first-1 hole crack detection wiring (HCD1-1) and the first-2 hole crack detection wiring (HCD1-2) through a printed circuit board (FPC). The voltage may be applied to the wirings (LN) placed in the display area (DA) through the third detection wiring (M3), the second-1 hole crack detection wiring (HCD2-1), and the second-2 hole crack detection wiring (HCD2-2).

[0054] When the display device (100) is driven in the inspection mode, if no crack occurs in the hole formed in the hole area (HA), the magnitude of the voltage passing through the third detection wiring (M3) may be constant.

[0055] When the display device (100) is driven in the inspection mode, if a crack occurs in the hole formed in the hole area (HA), the magnitude of the voltage passing through the third detection wiring (M3) may be reduced. In this case, the display area (DA) may display a bright vertical stripe pattern. Through this, the crack in the hole formed in the hole area (HA) can be detected.

[0056] In one embodiment, the first-2 hole crack detection wiring (HCD1-2) may be positioned on a plane between the first connection wiring (CL1) which provides the data signal to the data wirings and the second connection wiring (CL2) which provides the driving voltage to the power wirings. That is, the first-2 hole crack detection wiring (HCD1-2) may be adjacent to the second connection wiring (CL2). In other words, the first-2 hole crack detection wiring (HCD1-2) may be positioned between dummy patterns (DP1, DP2) on a plane. However, although the first-2 hole crack detection wiring (HCD1-2) is described as an example in FIG. 3, the present invention is not limited thereto. For example, the first-1 hole crack detection wiring (HCD1-1) may also be positioned between the first connection wiring that provides the data signal to the data wirings on a plane and is positioned in the pad area (PDA), and the second connection wiring that provides the driving voltage to the power wirings and is positioned in the pad area (PDA).

[0057] A printed circuit board (FPC) may be placed in a pad area (PDA) on a substrate (110). Specifically, a portion of the printed circuit board (FPC) may overlap with the pad area (PDA). One end of the printed circuit board (FPC) may be electrically connected to pads placed in the pad area (PDA) on the substrate (110), and the other end of the printed circuit board (FPC) may be electrically connected to an external device. That is, electrical signals, voltages, etc. generated from the external device may be provided to a driving chip (IC) and a plurality of pixels (PX) through the printed circuit board (FPC).

[0058] A driving chip (IC) may be placed on a pad area (PDA) on a substrate (110). The driving chip (IC) may convert a digital data signal among electrical signals into an analog data signal and provide it to a plurality of pixels (PX). For example, the driving chip (IC) may be a data driver. In addition, the driving chip (IC) may provide voltage (e.g., high voltage) to a printed circuit board (FPC).

[0059] However, although FIG. 1 is illustrated as having a chip-on-plastic (COP) or chip-on-glass (COG) structure in which a driving chip (IC) is directly placed on a substrate (110), the present invention is not limited thereto. For example, the driving chip (IC) may have a chip-on-film (COF) structure in which it is directly placed on a flexible film. In this case, a printed circuit board (FPC) may be electrically connected to the flexible film.

[0060] FIG. 4 is a cross-sectional view showing a part of the display area of ​​the display device of FIG. 1.

[0061] Referring to FIG. 4, a display device (100) according to one embodiment of the present invention may include a substrate (110), a display layer (200), a thin film encapsulation structure (300), a touch sensing structure (400), a polarizing member (POL), and a cover window (CW).

[0062] The substrate (110) may include a transparent or opaque material. The substrate (110) may be made of a transparent resin substrate. For example, the transparent resin substrate that can be used as the substrate (110) may be a polyimide substrate. In this case, the polyimide substrate may include a first polyimide layer, a barrier film layer, a second polyimide layer, etc.

[0063] A display layer (200) may be disposed on a substrate (110). The display layer (200) may include a semiconductor element, an insulating layer, a light-emitting element, etc. A detailed description of the components of the display layer (200) will be provided later.

[0064] A thin film encapsulation structure (300) may be disposed on the display layer (200). The thin film encapsulation structure (300) may cover the display layer (200). The thin film encapsulation structure (300) may prevent the display layer (200) from being damaged by moisture, oxygen, etc. A detailed description of the components of the thin film encapsulation structure (300) will be provided later.

[0065] A touch sensing structure (400) may be placed on a thin film encapsulation structure (300). The touch sensing structure (400) can acquire coordinate information based on external input. For example, the touch sensing structure (400) can detect external input using a mutual capping method or a self-capping method. A detailed description of the components of the touch sensing structure (400) will be provided later.

[0066] A polarizing member (POL) may be disposed on the touch sensing structure (400). The polarizing member (POL) may block external light incident on the display device (100) from the outside.

[0067] A cover window (CW) may be disposed on a polarizing member (POL). For example, the cover window (CW) may be formed using reinforced glass, reinforced plastic, etc.

[0068] FIG. 5 is a cross-sectional view taken along the lines II' and II-II' of FIG. 1. FIG. 6 is a plan view illustrating a touch sensing structure included in the display device of FIG. 5.

[0069] Referring to FIGS. 5 and 6, a display device (100) according to one embodiment of the present invention may include a substrate (110), a gate insulating layer (120), a first interlayer insulating layer (130a), a second interlayer insulating layer (130b), a semiconductor device (150), a first planarization layer (140a), a second planarization layer (140b), a connecting electrode (CE), a pixel defining film (160), a light-emitting element (170), a thin film encapsulation structure (300), a touch sensing structure (400), and a first-1 hole crack detection wiring (HCD1-1).

[0070] Here, the semiconductor device (150) may include an active layer (ACT), a first gate electrode (GE1), a second gate electrode (GE2), a source electrode (SE), and a drain electrode (DE), and the light-emitting device (170) may include a lower electrode (171), a light-emitting layer (172), and an upper electrode (173). The thin film encapsulation structure (300) may include a first inorganic thin film encapsulation layer (181), an organic thin film encapsulation layer (182), and a second inorganic thin film encapsulation layer (183), and the touch sensing structure (400) may include a sensing connection pattern (220), a first sensing electrode pattern (240a), a second sensing electrode pattern (240b), and a connection portion (241). The first-1 hole crack detection wiring (HCD1-1) may include a first conductive pattern (135), a bridge pattern (155), and a second conductive pattern (245).

[0071] As described above, the display device (100) may include a display area (DA), a hole area (HA), a peripheral area (PA), a bending area (BA), and a pad area (PDA). As the display device (100) includes a display area (DA), a hole area (HA), a peripheral area (PA), a bending area (BA), and a pad area (PDA), the substrate (110) may also include a display area (DA), a hole area (HA), a peripheral area (PA), a bending area (BA), and a pad area (PDA).

[0072] A buffer layer may be disposed on the substrate (110). The buffer layer can prevent metal atoms or impurities from the substrate (110) from diffusing into an upper structure (e.g., a semiconductor device (150), a light-emitting device (170), etc.) and can control the rate of heat transfer during the crystallization process for forming an active layer (ACT) to obtain a substantially uniform active layer (ACT). Additionally, if the surface of the substrate (110) is not uniform, the buffer layer can serve to improve the flatness of the surface of the substrate (110). For example, the buffer layer may include an organic insulating material or an inorganic insulating material.

[0073] An active layer (ACT) may be disposed on a display area (DA) on a substrate (110). The active layer (ACT) may include a metal oxide semiconductor, an inorganic semiconductor (e.g., amorphous silicon, polysilicon), or an organic semiconductor. The active layer (ACT) may include a source region, a drain region, and a channel region located between the source region and the drain region.

[0074] A gate insulating layer (120) may be disposed on a display area (DA), a peripheral area (PA), and a pad area (PDA) on a substrate (110). The gate insulating layer (120) may have an opening that exposes the upper surface of the substrate (110) located in a bending area (BA). The gate insulating layer (120) covers the active layer (ACT) on the substrate (110) and may be disposed along the profile of the active layer (ACT) with a uniform thickness. Optionally, the gate insulating layer (120) may sufficiently cover the active layer (ACT) on the substrate (110) and may have a substantially flat top surface without creating a step around the active layer (ACT). The gate insulating layer (120) may include silicon compounds, metal oxides, etc. For example, the gate insulating layer (120) may be silicon oxide (SiO₂). x ), silicon nitride (SiN x ), silicon carbide (SiC x ), silicon oxynitride (SiO₂ x N y ), silicon oxycarbide (SiO₂ x C y It may include ) etc. These can be used alone or in combination with each other.

[0075] A first gate electrode (GE1) may be disposed in a display area (DA) on the gate insulating layer (120). The first gate electrode (GE1) may overlap with the channel area of ​​the active layer (ACT). For example, the first gate electrode (GE1) may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0076] A first interlayer insulating layer (130a) may be disposed on the display area (DA), peripheral area (PA), and pad area (PDA) on the gate insulating layer (120). The first interlayer insulating layer (130a) may have an opening that exposes the upper surface of the substrate (110) located in the bending area (BA). The first interlayer insulating layer (130a) may cover the first gate electrode (GE1) and may be disposed with a uniform thickness. Optionally, the first interlayer insulating layer (130a) may have a substantially flat upper surface on the gate insulating layer (120) without creating a step around the first gate electrode (GE1). For example, the first interlayer insulating layer (130a) may include a silicon compound, a metal oxide, etc.

[0077] A second gate electrode (GE2) may be disposed in a display area (DA) on the first interlayer insulating layer (130a). That is, the second gate electrode (GE2) may overlap with the first gate electrode (GE1). For example, the second gate electrode (GE2) may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0078] A second gate electrode (GE2) may be disposed in a display area (DA) on the first interlayer insulating layer (130a). That is, the second gate electrode (GE2) may overlap with the first gate electrode (GE1). For example, the second gate electrode (GE2) may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0079] A second interlayer insulating layer (130b) may be disposed on the display area (DA), peripheral area (PA), and pad area (PDA) on the first interlayer insulating layer (130a). The second interlayer insulating layer (130b) may have an opening that exposes the upper surface of the substrate (110) located in the bending area (BA). The second interlayer insulating layer (130b) may cover the second gate electrode (GE2) and may be disposed with a uniform thickness. Optionally, the second interlayer insulating layer (130b) may have a substantially flat upper surface on the first interlayer insulating layer (130a) without creating a step around the second gate electrode (GE2). For example, the second interlayer insulating layer (130b) may include a silicon compound, a metal oxide, etc.

[0080] A source electrode (SE) and a drain electrode (DE) may be disposed in a display area (DA) on the second interlayer insulating layer (130b). The source electrode (SE) may be connected to the source area of ​​the active layer (ACT) through a contact hole formed by removing a first portion of the gate insulating layer (120), the first interlayer insulating layer (130a), and the second interlayer insulating layer (130b), and the drain electrode (DE) may be connected to the drain area of ​​the active layer (ACT) through a contact hole formed by removing a second portion of the gate insulating layer (120), the first interlayer insulating layer (130a), and the second interlayer insulating layer (130b). For example, the source electrode (SE) and the drain electrode (DE) may each include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0081] A first conductive pattern (135) may be disposed on a pad region (PDA) on the second interlayer insulating layer (130b). For example, the first conductive pattern (135) may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In one embodiment, the first conductive pattern (135) may be disposed on the same layer as the source electrode (SE) and the drain electrode (DE). That is, the first conductive pattern (135) may include the same material as the source electrode (SE) and the drain electrode (DE). In another embodiment, the first conductive pattern (135) may be disposed on the same layer as the first gate electrode (GE1) or the second gate electrode (GE2).

[0082] A first flattening layer (140a) may be disposed on the display area (DA), peripheral area (PA), and pad area (PDA) on the second interlayer insulating layer (130b). The first flattening layer (140a) may have an opening that exposes the upper surface of the substrate (110) located in the bending area (BA). For example, the first flattening layer (140a) may be disposed with a relatively thick thickness to sufficiently cover the source electrode (SE), drain electrode (DE), and first conductive pattern (135) on the second interlayer insulating layer (130b), and in this case, the first flattening layer (140a) may have a substantially flat upper surface, and a flattening process may be added to the first flattening layer (140a) to realize such a flat upper surface of the first flattening layer (140a). The first flattening layer (140a) may have a first contact hole that exposes the upper surface of the drain electrode (DE) in the display area (DA) and a second contact hole that exposes the upper surface of the first conductive pattern (135) in the pad area (PDA).

[0083] The first flattening layer (140a) may include an organic insulating material or an inorganic insulating material. In one embodiment, the first flattening layer (140a) may include an organic insulating material. For example, the first flattening layer (140a) may include a photoresist, a polyacryl-based resin, a polyimide-based resin, a polyamide-based resin, a siloxane-based resin, an acrylic-based resin, an epoxy-based resin, etc. These may be used alone or in combination with each other.

[0084] An organic layer (145) may be disposed in a bending region (BA) on a substrate (110). The organic layer (145) may fill the openings of each of the gate insulating layer (120), the first interlayer insulating layer (130a), the second interlayer insulating layer (130b), and the first planarization layer (140a). The organic layer (145) may relieve stress in the bending region (BA). For example, the organic layer (145) may include photoresist, polyacrylic resin, polyimide resin, polyamide resin, siloxane resin, acrylic resin, epoxy resin, etc. These may be used alone or in combination with each other.

[0085] A connecting electrode (CE) may be disposed in a display area (DA) on the first flattening layer (140a). The connecting electrode (CE) may be connected to a drain electrode (DE) through the first contact hole of the first flattening layer (140a). For example, the connecting electrode (CE) may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0086] A bridge pattern (155) may be disposed in a bending region (BA) on the organic layer (145). The bridge pattern (155) may extend into a portion of the peripheral region (PA) and a portion of the pad region (PDA). The bridge pattern (155) may be connected to the first conductive pattern (135) through the second contact hole of the first planarization layer (140a). For example, the bridge pattern (155) may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. In one embodiment, the bridge pattern (155) may be disposed on the same layer as the connecting electrode (CE). That is, the bridge pattern (155) may include the same material as the connecting electrode (CE).

[0087] A second flattening layer (140b) may be disposed in a display area (DA) on the first flattening layer (140a). That is, the second flattening layer (140b) may not be disposed in the surrounding area (PA) and pad area (PDA). For example, the second flattening layer (140b) may be disposed with a relatively thick thickness to sufficiently cover the connecting electrode (CE) on the first flattening layer (140a), in which case the second flattening layer (140b) may have a substantially flat upper surface, and a flattening process may be added to the second flattening layer (140b) to realize such a flat upper surface of the second flattening layer (140b). Additionally, the second flattening layer (140b) may have a contact hole that exposes the upper surface of the connecting electrode (CE). For example, the second flattening layer (140b) may include an organic insulating material or an inorganic insulating material.

[0088] A lower electrode (171) may be disposed in a display area (DA) on the second planarization layer (140b). The lower electrode (171) may be connected to a connecting electrode (CE) through the contact hole of the second planarization layer (140b). Thus, the lower electrode (171) may be electrically connected to the semiconductor device (150). For example, the lower electrode (171) may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0089] A pixel defining film (160) may be disposed on a display area (DA) on the second flattening layer (140b). The pixel defining film (160) may cover both sides of the lower electrode (171) and may have an opening that exposes the upper surface of the lower electrode (171). For example, the pixel defining film (160) may include an organic insulating material or an inorganic insulating material. In one embodiment, the pixel defining film (160) may include an organic insulating material.

[0090] A light-emitting layer (172) may be disposed on a display area (DA) on a lower electrode (171). That is, the light-emitting layer (172) may be disposed on the lower electrode (171) exposed by the opening of the pixel defining film (160). The light-emitting layer (172) may be formed using at least one of light-emitting materials capable of emitting red light, green light, blue light, etc., depending on the type of subpixel. Optionally, the light-emitting layer (172) may emit white light overall by stacking a plurality of light-emitting materials capable of generating other colors of light, such as red light, green light, and blue light.

[0091] An upper electrode (173) may be disposed on a display area (DA) on the pixel defining film (160) and the light-emitting layer (172). For example, the upper electrode (173) may include a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0092] Accordingly, a light-emitting element (170) comprising a lower electrode (171), a light-emitting layer (172), and an upper electrode (173) can be placed in a display area (DA) on a substrate (110).

[0093] A first inorganic thin film encapsulation layer (181) may be disposed on a display area (DA) on an upper electrode (173). The first inorganic thin film encapsulation layer (181) covers the upper electrode (173) and may be disposed along the profile of the upper electrode (173) with a uniform thickness. The first inorganic thin film encapsulation layer (181) can prevent the light-emitting element (170) from deteriorating due to the penetration of moisture, oxygen, etc. Additionally, the first inorganic thin film encapsulation layer (181) can also perform the function of protecting the light-emitting element (170) from external shocks. For example, the first inorganic thin film encapsulation layer (181) may include a flexible inorganic insulating material.

[0094] An organic thin film encapsulation layer (182) may be disposed on the first inorganic thin film encapsulation layer (181). The organic thin film encapsulation layer (182) can improve the flatness of the display device (100) and can protect the light-emitting element (170) together with the first inorganic thin film encapsulation layer (181). For example, the organic thin film encapsulation layer (182) may include a flexible organic material.

[0095] A second inorganic thin film encapsulation layer (183) may be disposed on an organic thin film encapsulation layer (182). The second inorganic thin film encapsulation layer (183) covers the organic thin film encapsulation layer (182) and may be disposed along the profile of the organic thin film encapsulation layer (182) with a uniform thickness. Together with the first inorganic thin film encapsulation layer (181), the second inorganic thin film encapsulation layer (183) can prevent the light-emitting element (170) from deteriorating due to the penetration of moisture, oxygen, etc. Additionally, together with the first inorganic thin film encapsulation layer (181) and the organic thin film encapsulation layer (182), the second inorganic thin film encapsulation layer (183) can also perform the function of protecting the light-emitting element (170) from external shocks. For example, the second inorganic thin film encapsulation layer (183) may include a flexible inorganic insulating material.

[0096] Optionally, the thin film encapsulation structure (300) may have a 5-layer structure stacked with 3 inorganic thin film encapsulation layers and 2 organic thin film encapsulation layers, or a 7-layer structure stacked with 4 inorganic thin film encapsulation layers and 3 organic thin film encapsulation layers.

[0097] A lower touch insulating layer (210) may be disposed on a display area (DA) on the second inorganic thin film encapsulation layer (183). The lower touch insulating layer (210) may extend to a peripheral area (PA), a bending area (BA), and a pad area (PDA). For example, the lower touch insulating layer (210) may include an inorganic insulating material or an organic insulating material. Optionally, the lower touch insulating layer (210) may have a multilayer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses or include different materials.

[0098] A sensing connection pattern (220) may be disposed on a display area (DA) on a lower touch insulating layer (210). As illustrated in FIG. 6, the sensing connection pattern (220) may electrically connect a first sensing electrode pattern (240a) and a second sensing electrode pattern (240b) through contact holes. For example, the sensing connection pattern (220) and the first and second sensing electrode patterns (240a, 240b) may comprise the same material. Optionally, the sensing connection pattern (220) may comprise a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0099] An interlayer touch insulating layer (230) may be disposed on the display area (DA), peripheral area (PA), bending area (BA), and pad area (PDA) on the lower touch insulating layer (210). The interlayer touch insulating layer (230) may sufficiently cover the sensing connection pattern (220). For example, the interlayer touch insulating layer (230) may include an organic insulating material or an inorganic insulating material. Optionally, the interlayer touch insulating layer (230) may have a multilayer structure including a plurality of insulating layers. For example, the insulating layers may have different thicknesses or include different materials.

[0100] A first sensing electrode pattern (240a), a second sensing electrode pattern (240b), and a connection part (241) may be disposed on a display area (DA) on an interlayer touch insulating layer (230). Additionally, as shown in FIG. 6, a third sensing electrode pattern (242) may be disposed on a display area (DA) on an interlayer touch insulating layer (230), and the third sensing electrode pattern (242) may be disposed on the same layer as the connection part (241). In one embodiment, each of the first sensing electrode pattern (240a), the second sensing electrode pattern (240b), the third sensing electrode pattern (242), and the connecting portion (241) may include carbon nanotubes (CNT), transparent conductive oxide, indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), graphene, silver nanowires (Ag nanowire AgNW), copper (Cu), chromium (Cr), titanium (Ti), aluminum (Al), etc. These may be used alone or in combination with each other. For example, each of the first sensing electrode pattern (240a), the second sensing electrode pattern (240b), the third sensing electrode pattern (242), and the connecting portion (241) may have a multilayer structure including Ti / Al / Ti.

[0101] For example, the first sensing electrode pattern (240a) and the second sensing electrode pattern (240b) may include an electrode pattern array arranged spaced apart from each other in the second direction (D2). Additionally, the third sensing electrode pattern (242) may include an electrode pattern array that extends in the second direction (D2) and is arranged spaced apart from each other in the first direction (D1).

[0102] A second conductive pattern (245) may be disposed in a peripheral region (PA) on the interlayer touch insulating layer (230). The second conductive pattern (245) may be connected to a bridge pattern (155) through a contact hole formed by removing a portion of the lower touch insulating layer (210) and the interlayer touch insulating layer (230). In one embodiment, the second conductive pattern (245) may be disposed on the same layer as the first sensing electrode pattern (240a), the second sensing electrode pattern (240b), the third sensing electrode pattern (242), and the connecting portion (241). That is, the second conductive pattern (245) may include the same material as the first sensing electrode pattern (240a), the second sensing electrode pattern (240b), the third sensing electrode pattern (242), and the connecting portion (241). In another embodiment, the second conductive pattern (245) may be placed on the same layer as the sensing connection pattern (220).

[0103] Accordingly, a first-1 hole crack detection wiring (HCD1-1) comprising a first conduction pattern (135), a bridge pattern (155), and a second conduction pattern (245) may be placed in a peripheral area (PA), a bending area (BA), and a pad area (PDA) on a substrate (110). However, although the first-1 hole crack detection wiring (HCD1-1) is described as an example in FIG. 5, the present invention is not limited thereto. For example, the first-2 hole crack detection wiring (HCD1-2), the second-1 hole crack detection wiring (HCD2-1), and the second-2 hole crack detection wiring (HCD2-2) shown in FIG. 1 may each include the same components as the first-1 hole crack detection wiring (HCD1-1).

[0104] A protective layer (250) may be disposed on a display area (DA) on an interlayer touch insulating layer (230), a first sensing electrode pattern (240a), a second sensing electrode pattern (240b), and a connection part (241). The protective layer (250) may sufficiently cover the first sensing electrode pattern (240a), the second sensing electrode pattern (240b), and the connection part (241).

[0105] The touch insulation structure (400) of the present invention is not limited to the structure shown in FIGS. 5 and 6 and may have various known structures. For example, in other embodiments, the lower touch insulation layer (210) may be omitted. Additionally, the first and second sensing electrode patterns (240a, 240b) and the third sensing electrode pattern (242) may be disposed on different layers, so that the first and second sensing electrode patterns (240a, 240b) may have a continuous structure without a sensing connection pattern (220).

[0106] Additionally, although the display device (100) of the present invention is described as being limited to an organic light-emitting display device, the configuration of the present invention is not limited thereto. In other embodiments, the display device (100) may include a liquid crystal display device (LCD), a field emission display device (FED), a plasma display device (PDP), an electrophoretic image display device (EPD), an inorganic light-emitting display device (ILED), or a quantum dot display device.

[0107] Figures 7 and 8 are schematic diagrams illustrating the circuit structure for explaining the normal mode and test mode of the display device of Figure 1.

[0108] Referring to FIGS. 1, 7 and 8, a display device (100) according to one embodiment of the present invention may include a substrate (110), a plurality of pixels (PX), a first sensing wire (M1), a second sensing wire (M2), a third sensing wire (M3), a driving chip (IC), and a printed circuit board (FPC).

[0109] Here, the first detection wiring (M1) may include a first-1 hole crack detection wiring (HCD1-1) and a second-1 hole crack detection wiring (HCD2-1), and the second detection wiring (M2) may include a first-2 hole crack detection wiring (HCD1-2) and a second-2 hole crack detection wiring (HCD2-2). The first-1 hole crack detection wiring (HCD1-1) and the first-2 hole crack detection wiring (HCD1-2) are defined as the first hole crack detection wiring (HCD1), and the second-1 hole crack detection wiring (HCD2-1) and the second-2 hole crack detection wiring (HCD2-2) are defined as the second hole crack detection wiring (HCD2).

[0110] A display device (100) according to one embodiment of the present invention may further include a first bending crack detection wiring (BCD1), a second bending crack detection wiring (BCD2), a module crack detection wiring (MCD), a first signal wiring (CL1), a second signal wiring (CL2), a high voltage wiring (VGHL), a first transistor (T1), and a second transistor (T2).

[0111] The first bending crack detection wiring (BCD1) and the second bending crack detection wiring (BCD2) can detect cracks occurring in the bending area (e.g., the bending area (BA) in FIG. 1). The module crack detection wiring (MCD) can detect cracks occurring in the outermost area of ​​the display device (100).

[0112] The second hole crack detection wiring (HCD2) can be electrically connected to the first hole crack detection wiring (HCD1). The first bending crack detection wiring (BCD1) can be connected to the module crack detection wiring (MCD). The second bending crack detection wiring (BCD2) can be provided integrally with the first crack detection wiring (BCD1). The module crack detection wiring (MCD) can be connected to the first hole crack detection wiring (HCD1). The high voltage wiring (VGHL) can be connected to a driver chip (IC) and a printed circuit board (FPC). The driver chip (IC) can provide high voltage to the high voltage wiring (VGHL) through the printed circuit board (FPC).

[0113] The first signal wiring (SL1) can be connected to a driver chip (IC). Specifically, the first signal wiring (SL1) can be connected to a driver dummy pad (IC-DP) included in the driver chip (IC). The driver chip (IC) can provide a first signal to the first signal wiring (SL1).

[0114] The first transistor (T1) may include a first electrode, a second electrode, and a gate electrode. The first electrode of the first transistor (T1) may be connected to a printed circuit board (FPC). In one embodiment, the first electrode of the first transistor (T1) may be connected to ground of the printed circuit board (FPC) (see FIG. 7). In another embodiment, the first electrode of the first transistor (T1) may be connected to ground wiring placed in a display area (DA) (see FIG. 8). The second electrode of the first transistor (T1) may be connected to the second electrode of the second transistor (T2). The gate electrode of the first transistor (T1) may be connected to a first signal wiring (SL1). A first signal may be applied to the gate electrode of the first transistor (T1) through the first signal wiring (SL1).

[0115] The second transistor (T2) may include a first electrode, a second electrode, and a gate electrode. The first electrode of the second transistor (T2) may be connected to a high voltage wiring (VGHL). The second electrode of the second transistor (T2) may be connected to the first electrode of the first transistor (T1). The gate electrode of the second transistor (T2) may be connected to a second signal wiring (SL2). A second signal may be applied to the gate electrode of the second transistor (T2) through the second signal wiring (SL2).

[0116] The display device (100) can be operated in a normal mode, which is a mode generally used by the user, or in an inspection mode for inspecting cracks in the hole formed in the hole area (HA). Below, the normal mode or the inspection mode will be described.

[0117] When the display device (100) is driven in the normal mode, the first transistor (T1) may be turned on by a first signal provided through the first signal wiring (SL1), and the second transistor (T2) may be turned off by a second signal provided through the second signal wiring (SL2). At this time, the first signal may have a low level, and the second signal may have a high level. Accordingly, when the display device (100) is driven in the normal mode, a ground voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) through a printed circuit board (FPC). Optionally, when the display device (100) is driven in the normal mode, the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) may be in a floating state. Optionally, when the display device (100) is driven in the normal mode, a low voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) through a printed circuit board (FPC).

[0118] When the display device (100) is driven in the inspection mode, the first transistor (T1) can be turned off by a first signal provided through the first signal wiring (SL1), and the second transistor (T2) can be turned on by a second signal provided through the second signal wiring (SL2). At this time, the first signal may have a high level, and the second signal may have a low level. Accordingly, when the display device (100) is driven in the inspection mode, a high voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) through the high voltage wiring (VGHL).

[0119] When the display device (100) is operated in normal mode, which is a mode generally used by the user, a high voltage may be applied to the first and second hole crack detection wires (HCD1, HCD2). In this case, in a high temperature and high humidity environment and a general user environment, iodine from the polarizing member (e.g., the polarizing member (POL) of FIG. 4) may leach into the first and second hole crack detection wires (HCD1, HCD2), causing corrosion of the first and second hole crack detection wires (HCD1, HCD2). Additionally, due to the corrosion of the first and second hole crack detection wires (HCD1, HCD2), corrosion may occur in the driving signal wires located adjacent to the first and second hole crack detection wires (HCD1, HCD2).

[0120] In a display device (100) according to one embodiment of the present invention, when the display device (100) is driven in the normal mode, a low voltage is applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2), and when the display device (100) is driven in the inspection mode, a high voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2). Accordingly, corrosion of the first and second hole crack detection wirings (HCD1, HCD2) that inspect the cracks in the holes formed in the hole area (HA) of the display device (100), which may occur when driven for a long time in a high temperature and high humidity environment and a general user environment, can be improved. In addition, corrosion of the driving signal wires located adjacent to the first and second hole crack detection wires (HCD1, HCD2), which occurs due to corrosion of the first and second hole crack detection wires (HCD1, HCD2), can be improved.

[0121] FIG. 9 is a diagram showing a circuit structure for explaining the normal mode and inspection mode of a display device according to another embodiment of the present invention.

[0122] Referring to FIGS. 1 and FIGS. 9, a display device (100) according to another embodiment of the present invention may include a substrate (110), a plurality of pixels (PX), a first sensing wire (M1), a second sensing wire (M2), a third sensing wire (M3), a driving chip (IC), and a printed circuit board (FPC). Hereinafter, descriptions that overlap with those of the display device (100) described with reference to FIGS. 1, FIGS. 7, and FIGS. 8 will be omitted.

[0123] A display device (100) according to another embodiment of the present invention may further include a first bending crack detection wiring (BCD1), a second bending crack detection wiring (BCD2), a module crack detection wiring (MCD), and a high voltage wiring (VGHL).

[0124] The second hole crack detection wiring (HCD2) can be electrically connected to the first hole crack detection wiring (HCD1). The first bending crack detection wiring (BCD1) can be connected to the high voltage wiring (VGHL). The second bending crack detection wiring (BCD2) can be provided integrally with the first bending crack detection wiring (BCD1). The module crack detection wiring (MCD) can be connected to the high voltage wiring (VGHL). The high voltage wiring (VGHL) can be connected to a driver chip (IC) and a printed circuit board (FPC). The driver chip (IC) can provide high voltage to the high voltage wiring (VGHL) through the printed circuit board (FPC).

[0125] The first hole crack detection wiring (HCD1) may be directly connected to the driver chip (IC). Specifically, the first hole crack detection wiring (HCD1) may be directly connected to a driver dummy pad (IC-DP) included in the driver chip (IC). In one embodiment, the driver chip (IC) may provide a voltage (e.g., low voltage, high voltage, etc.) to the first hole crack detection wiring (HCD1). In another embodiment, the driver chip (IC) and the driver dummy pattern (IC-DP) may not be electrically connected. In this case, the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) may be in a floating state. In another embodiment, the first hole crack detection wiring (HCD1) may be connected to the ground of the driver chip (IC).

[0126] The above display device can be operated in a normal mode, which is a mode generally used by the user, or in an inspection mode for inspecting cracks in the hole formed in the hole area (HA). Below, the normal mode or the inspection mode will be described.

[0127] When the display device is driven in the normal mode, a low voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) through a driving chip (IC). Optionally, when the display device is driven in the normal mode, the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) may be in a floating state. Optionally, when the display device is driven in the normal mode, the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) may be connected to the ground of the driving chip (IC). In this case, a ground voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) through the driving chip (IC).

[0128] When the above display device is driven in the inspection mode, high voltage can be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) through a driving chip (IC).

[0129] Accordingly, when the display device is driven in the normal mode, a low voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2), and when the display device is driven in the inspection mode, a high voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2).

[0130] FIG. 10 is a diagram roughly showing a circuit structure for explaining the normal mode and inspection mode of a display device according to another embodiment of the present invention.

[0131] Referring to FIGS. 1 and FIGS. 10, a display device (100) according to another embodiment of the present invention may include a substrate (110), a plurality of pixels (PX), a first sensing wire (M1), a second sensing wire (M2), a third sensing wire (M3), a driving chip (IC), and a printed circuit board (FPC). Hereinafter, descriptions that overlap with those of the display device (100) described with reference to FIGS. 1, FIGS. 7, and FIGS. 8 will be omitted.

[0132] A display device (100) according to another embodiment of the present invention may further include a first bending crack detection wiring (BCD1), a second bending crack detection wiring (BCD2), a module crack detection wiring (MCD), a high voltage wiring (VGHL), a third transistor (T3), and a third signal wiring (SL3).

[0133] The second hole crack detection wiring (HCD2) can be electrically connected to the first hole crack detection wiring (HCD1). The first bending crack detection wiring (BCD1) can be connected to the high voltage wiring (VGHL). The second bending crack detection wiring (BCD2) can be provided integrally with the first bending crack detection wiring (BCD1). The module crack detection wiring (MCD) can be connected to the high voltage wiring (VGHL). The high voltage wiring (VGHL) can be connected to a driver chip (IC) and a printed circuit board (FPC). The driver chip (IC) can provide high voltage to the high voltage wiring (VGHL) through the printed circuit board (FPC).

[0134] The third signal wiring (SL3) can be connected to a driver chip (IC). Specifically, the third signal wiring (SL3) can be connected to a driver dummy pad (IC-DP) included in the driver chip (IC). The driver chip (IC) can provide a third signal to the third signal wiring (SL1).

[0135] The third transistor (T3) may include a first electrode, a second electrode, and a gate electrode. The first electrode of the third transistor (T3) may be connected to a high voltage wiring (VGHL). The second electrode of the third transistor (T3) may be connected to a first hole crack detection wiring (HCD1). The gate electrode of the third transistor (T3) may be connected to a third signal wiring (CL3). The third signal may be applied to the gate electrode of the third transistor (T3) through the third signal wiring (SL3).

[0136] The above display device can be operated in a normal mode, which is a mode generally used by the user, or in an inspection mode for inspecting cracks in the hole formed in the hole area (HA). Below, the normal mode or the inspection mode will be described.

[0137] When the display device is driven in the normal mode, the third transistor (T3) can be turned off by a third signal provided through the third signal wiring (SL3). At this time, the third signal may have a high level. Accordingly, when the display device is driven in the normal mode, the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) may be in a floating state.

[0138] When the display device is driven in the inspection mode, the third transistor (T3) can be turned on by a third signal provided through the third signal wiring (SL3). At this time, the third signal may have a low level. Accordingly, when the display device is driven in the inspection mode, a high voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) through the high voltage wiring (VGHL).

[0139] Accordingly, when the display device is driven in the normal mode, the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2) may be in a floating state, and when the display device is driven in the inspection mode, a high voltage may be applied to the first hole crack detection wiring (HCD1) and the second hole crack detection wiring (HCD2).

[0140] Although the foregoing description refers to exemplary embodiments of the present invention, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as set forth in the following claims. Industrial applicability

[0141] The present invention can be applied to various display devices that may be equipped with a display device. For example, the present invention can be applied to high-resolution smartphones, mobile phones, smartpads, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, laptops, etc. Explanation of the symbols

[0142] 100: Display device DA: Display area HA: Hole area PA: Surrounding area BA: Bending area PDA: Pad area IC: Driver chip FPC: Printed circuit board M1, M2, M3: First to third sensing wires HCD1-1, HCD1-2: 1-1 and 1-2 hole crack detection wiring HCD2-1, HCD2-2: 2-1 and 2-2 hole crack detection wiring BCD1, BCD2: 1st and 2nd bending crack detection wires MCD: Module Crack Detection Wiring SL1, SL2, SL3: First to third signal wires T1, T2, T3: First to third transistors

Claims

Claim 1 A display device comprising: a substrate including a display area in which a plurality of pixels are arranged, a hole area located inside the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane; a printed circuit board disposed in the pad area on the substrate; a first hole crack detection wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area; a second hole crack detection wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area, and electrically connected to the first hole crack detection wiring; a first transistor having a gate electrode connected to a first signal wiring to receive a first signal, a first electrode connected to the printed circuit board, and a second electrode connected to the first hole crack detection wiring; and a second transistor having a gate electrode connected to a second signal wiring to receive a second signal, a first electrode connected to a high voltage wiring that applies a high voltage, and a second electrode connected to the first hole crack detection wiring. Claim 2 A display device according to claim 1, characterized in that when the display device is driven in normal mode, a first signal having a low level is applied to the gate electrode of the first transistor through the first signal wiring so that the first transistor is turned on, and a second signal having a high level is applied to the gate electrode of the second transistor through the second signal wiring so that the second transistor is turned off. Claim 3 A display device according to claim 2, wherein the first electrode of the first transistor is connected to the ground of the printed circuit board, and when the display device is driven in the normal mode, a ground voltage is applied to the first hole crack detection wiring and the second hole crack detection wiring through the printed circuit board. Claim 4 A display device according to claim 2, characterized in that when the display device is driven in the normal mode, a low voltage is applied to the first hole crack detection wiring and the second hole crack detection wiring through the printed circuit board. Claim 5 A display device according to claim 2, characterized in that when the display device is driven in the normal mode, the first hole crack detection wiring and the second hole crack detection wiring are in a floating state. Claim 6 A display device according to claim 1, characterized in that when the display device is driven in a test mode, a first signal having a high level is applied to the gate electrode of the first transistor through the first signal wiring so that the first transistor is turned off, and a second signal having a low level is applied to the gate electrode of the second transistor through the second signal wiring so that the second transistor is turned on. Claim 7 A display device according to claim 6, characterized in that when the display device is driven in the inspection mode, the high voltage is applied to the first hole crack detection wiring and the second hole crack detection wiring through the high voltage wiring. Claim 8 A display device according to claim 1, further comprising a driving chip disposed in the pad area on the substrate, wherein the driving chip is connected to the first signal wiring to provide the first signal to the first signal wiring and provides the high voltage to the high voltage wiring through the printed circuit board. Claim 9 A display device according to claim 8, further comprising: first connecting wires disposed in the pad area on the substrate and providing a data signal to the pixels through the driving chip; and second connecting wires disposed in the pad area on the substrate and providing a driving voltage to the pixels through the printed circuit board. Claim 10 A display device according to claim 9, characterized in that the first hole crack detection wiring located in the pad area is disposed between the first connecting wiring and the second connecting wiring on a plane. Claim 11 A display device according to claim 1, further comprising a sensing wire adjacent to the hole area, which is disposed in the display area on the substrate and separated into one end and the other end to surround the periphery of the hole area. Claim 12 A display device according to claim 11, characterized in that one end of the sensing wiring is electrically connected to the first hole crack sensing wiring, and the other end of the sensing wiring is electrically connected to the second hole crack sensing wiring. Claim 13 A display device according to claim 1, further comprising: a semiconductor device including an active layer disposed in a display area on the substrate, a gate electrode overlapping with a channel area of ​​the active layer, a source electrode connected to a source area of ​​the active layer, and a drain electrode connected to a drain area of ​​the active layer; a connecting electrode disposed on the semiconductor device and connected to the semiconductor device; and a touch sensing structure including a sensing connection pattern disposed on the connecting electrode and a sensing electrode pattern disposed on the sensing connection pattern. Claim 14 A display device according to claim 13, wherein each of the first hole crack detection wiring and the second hole crack detection wiring comprises: a first conductive pattern disposed in the pad area on the substrate; a bridge pattern disposed in the bending area on the substrate, extending to a part of the peripheral area and a part of the pad area, and connected to the first conductive pattern; and a second conductive pattern disposed in the peripheral area on the substrate and connected to the bridge pattern. Claim 15 A display device according to claim 14, wherein the first conductive pattern is disposed on the same layer as the source electrode and the drain electrode, the bridge pattern is disposed on the same layer as the connecting electrode, and the second conductive pattern is disposed on the same layer as the sensing electrode pattern. Claim 16 A display device comprising: a display area in which a plurality of pixels are arranged; a hole area located within the display area; a peripheral area surrounding the display area; a pad area; and a bending area located between the peripheral area and the pad area on a plane; a driving chip disposed in the pad area on the substrate; a first hole crack detection wiring disposed in the peripheral area on the substrate, extending to the bending area and the pad area, and directly connected to the driving chip; and a second hole crack detection wiring disposed in the peripheral area on the substrate, extending to the bending area and the pad area, and electrically connected to the first hole crack detection wiring, wherein when the display device is operated in normal mode, the first hole crack detection wiring and the second hole crack detection wiring are connected to the ground of the driving chip or are in a floating state. Claim 17 delete Claim 18 delete Claim 19 A display device according to claim 16, characterized in that when the display device is driven in inspection mode, a high voltage is applied to the first hole crack detection wiring and the second hole crack detection wiring through the driving chip. Claim 20 A display device comprising: a substrate including a display area in which a plurality of pixels are arranged, a hole area located inside the display area, a peripheral area surrounding the display area, a pad area, and a bending area located between the peripheral area and the pad area on a plane; a first hole crack detection wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area; a second hole crack detection wiring disposed in the peripheral area on the substrate and extending to the bending area and the pad area, and electrically connected to the first hole crack detection wiring; and a transistor comprising a gate electrode connected to a signal wiring to receive a signal, a first electrode connected to a high voltage wiring that applies a high voltage, and a second electrode connected to the first hole crack detection wiring. Claim 21 A display device according to claim 20, characterized in that when the display device is driven in normal mode, a signal having a high level is applied to the gate electrode of the transistor through the signal wiring, thereby turning off the transistor. Claim 22 A display device according to claim 21, characterized in that when the display device is driven in the normal mode, the first hole crack detection wiring and the second hole crack detection wiring are in a floating state. Claim 23 A display device according to claim 20, characterized in that when the display device is driven in an inspection mode, a signal having a low level is applied to the gate electrode of the transistor through the signal wiring, thereby turning on the transistor. Claim 24 A display device according to claim 23, characterized in that when the display device is driven in the inspection mode, the high voltage is applied to the first hole crack detection wiring and the second hole crack detection wiring through the high voltage wiring. Claim 25 A display device according to claim 20, further comprising: a driving chip disposed in the pad area on the substrate; and a printed circuit board disposed in the pad area on the substrate, wherein the driving chip is connected to the signal wiring to provide the signal to the signal wiring and provides the high voltage to the high voltage wiring through the printed circuit board.

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