Light emitting display apparatus and multi screen display apparatus using the same

Abstract

A light-emitting display device according to one embodiment of the present specification may include a display portion having pixel regions disposed on a substrate, a circuit layer including pixel driving lines disposed on the pixel regions, a light-emitting element layer including a light-emitting layer disposed on the circuit layer of the pixel regions, an encapsulation layer disposed on the light-emitting element layer, and a routing portion having routing lines connected to the pixel driving lines through the encapsulation layer disposed on the front edge portion of the substrate and surrounding the front edge portion and outer surface of the substrate.

Description

Technology Field

[0001] This specification relates to a light-emitting display device and a multi-screen display device using the same. Background Technology

[0002] Emissive displays are self-emissive display devices that, unlike liquid crystal displays, do not require a separate light source, allowing them to be manufactured in lightweight and thin forms. Furthermore, emissive displays are gaining attention as next-generation display devices because they offer advantages in terms of power consumption due to low-voltage driving, as well as superior color reproduction, response speed, viewing angle, and contrast ratio.

[0003] A light-emitting display device displays an image through the light emission of a light-emitting element layer comprising a light-emitting layer interposed between two electrodes. At this time, light generated by the light emission in the light-emitting layer can be emitted to the outside through the upper or lower part of the light-emitting element layer.

[0004] The light-emitting display device includes a display panel implemented to display an image. The display panel may include a display area having a plurality of pixels for displaying an image, and a bezel area surrounding the display area.

[0005] Conventional light-emitting display devices require a bezel (or structure) to cover the bezel area placed at the border (or edge portion) of the display panel, and the bezel width may increase due to the width of the bezel. Furthermore, if the bezel width of the light-emitting display device is reduced to an extreme degree, the reliability of the light-emitting layer may be compromised due to the deterioration of the light-emitting layer caused by moisture penetration.

[0006] Recently, multi-screen display devices that realize a large screen by arranging light-emitting display devices in a grid pattern are being commercialized.

[0007] However, conventional multi-screen display devices have boundary areas called seams between adjacent displays due to the bezel areas of each display device or the bezels. These boundary areas reduce immersion by creating a sense of discontinuity (or abruptness) when displaying a single image across the entire screen of the multi-screen device. The problem to be solved

[0008] Some embodiments of the present specification aim to provide a light-emitting display device and a multi-screen display device including the same, which can prevent a decrease in the reliability of a light-emitting element due to moisture penetration.

[0009] Some embodiments of the present specification aim to provide a light-emitting display device having a zero bezel while preventing a decrease in the reliability of the light-emitting element due to moisture penetration, and a multi-screen display device including the same.

[0010] Some embodiments of the present specification may provide a display device capable of displaying an image without a sense of discontinuity when displaying a single image on a full screen, and a multi-screen display device including the same.

[0011] The problems to be solved according to the examples of this specification are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art to which the technical concept of this specification belongs from the description below. means of solving the problem

[0012] A light-emitting display device according to one embodiment of the present specification may include a substrate, a display unit having pixel regions disposed on the substrate, a circuit layer having pixel driving lines disposed on the pixel regions, a light-emitting element layer having a light-emitting layer disposed on the circuit layer of the pixel regions, an encapsulation layer disposed on the light-emitting element layer, and a routing unit having routing lines connected to the pixel driving lines through the encapsulation layer disposed on the front edge portion of the substrate and surrounding the outer surface of the substrate.

[0013] A multi-screen display device according to one embodiment of the present specification includes a plurality of display modules arranged along at least one of a first direction and a second direction crossing the first direction, each of the plurality of display modules including a light-emitting display device, and the light-emitting display device may include a substrate, a display portion having pixel regions arranged on the substrate, a circuit layer including pixel driving lines arranged in the pixel regions, a light-emitting element layer including a light-emitting layer arranged on the circuit layer of the pixel regions, an encapsulation layer arranged on the light-emitting element layer, and a routing portion having routing lines connected to the pixel driving lines through the encapsulation layer arranged on the front edge portion of the substrate and surrounding the front edge portion and outer surface of the substrate.

[0014] Specific details according to various examples of this specification, other than the means for solving the problem mentioned above, are included in the description and drawings below. Effects of the invention

[0015] One embodiment of the present specification may provide a light-emitting display device and a multi-screen display device including the same, which can prevent a decrease in the reliability of a light-emitting element due to moisture penetration.

[0016] One embodiment of the present specification may provide a light-emitting display device having a zero bezel and preventing a decrease in the reliability of the light-emitting element due to moisture penetration, and a multi-screen display device including the same.

[0017] Since the problem to be solved, the means of solving the problem, and the effects mentioned above do not specify the essential features of the claim scope, the scope of rights of the claim is not limited by the matters described in the content of the invention. Brief explanation of the drawing

[0018] FIG. 1 is a plan view showing a light-emitting display device according to one embodiment of the present specification. FIG. 2 is a side view showing a light-emitting display device according to one embodiment of the present specification. FIG. 3a is a drawing showing a single pixel according to an embodiment illustrated in FIG. 1. FIG. 3b is a drawing showing a single pixel according to another embodiment illustrated in FIG. 1. Figure 4 is an enlarged view of the 'B1' portion shown in Figure 1. Figure 5 is an equivalent circuit diagram for a single pixel shown in Figures 1 and 4. FIG. 6 is a diagram showing a gate driving circuit implemented within the display unit shown in FIG. 4. FIG. 7 is a rear perspective view showing a light-emitting display device according to one embodiment of the present specification. FIG. 8 is a rear perspective view showing a light-emitting display device according to another embodiment of the present specification. FIG. 9 is a diagram illustrating the connection structure between a pixel driving line and a routing unit according to one embodiment of the present specification. Figure 10 is a cross-sectional view of line I-I' shown in Figure 9. Figure 11 is an enlarged view of the 'B2' portion shown in Figure 10. Figure 12 is an enlarged view of the 'B3' portion shown in Figure 10. FIG. 13 is a diagram illustrating the connection structure between a pixel driving line and a routing unit according to another embodiment of the present specification. Figure 14 is an enlarged view of the 'B4' portion shown in Figure 13. FIG. 15 is a cross-sectional view of line II-II' shown in FIG. 14. Figure 16 is an enlarged view of the 'B5' portion shown in Figure 15. FIG. 17 is a cross-sectional view of line III-III' shown in FIG. 14. FIG. 18 is a diagram illustrating the connection structure between a pixel driving line, a routing unit, and an auxiliary line unit according to another embodiment of the present specification. FIG. 19 is a cross-sectional view of line IV-IV' shown in FIG. 18. FIG. 20 is a cross-sectional view of the line V-V' shown in FIG. 18. FIG. 21 is a cross-sectional view of line VI-VI' shown in FIG. 18. FIG. 22 is a cross-sectional view of line VII-VII' shown in FIG. 18. FIG. 23 is a diagram illustrating the connection structure between a pixel driving line, a routing unit, and an auxiliary line unit according to another embodiment of the present specification. FIG. 24 is a diagram illustrating the connection structure between a pixel driving line, a routing unit, and an auxiliary line unit according to another embodiment of the present specification. Fig. 25 is an enlarged view of the 'B6' portion shown in Fig. 24. FIG. 26 is a cross-sectional view of line VIII-VIII' shown in FIG. 25. FIG. 27 is a drawing for illustrating a light-emitting display device according to another embodiment of the present specification. FIG. 28 is a cross-sectional view of line IX-IX' shown in FIG. 27. FIG. 29 is an enlarged view of the 'B7' portion shown in FIG. 28. FIG. 30 is a drawing for illustrating a light-emitting display device according to another embodiment of the present specification. FIG. 31 is a cross-sectional view of line X-X' shown in FIG. 27. Fig. 32 is an enlarged view of the 'B8' portion shown in Fig. 31. FIG. 33 is a drawing showing a multi-screen display device according to one embodiment of the present specification. FIG. 34 is a cross-sectional view of line XI-XI' shown in FIG. 33. Specific details for implementing the invention

[0019] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is defined only by the scope of the claims.

[0020] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary and are not limited to the depicted items. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing this specification, if it is determined that a detailed description of related prior art could unnecessarily obscure the essence of this specification, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0021] In interpreting the components, even if there is no separate explicit description of the error range, it is interpreted as including the error range.

[0022] In the case of a description of a positional relationship, for example, when the positional relationship between two parts is described using terms such as "on," "on the upper," "on the lower," or "next to," for example, unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0023] In the case of an explanation of temporal relationships, when the temporal order is explained using "after," "followed," "next," "before," etc., cases that are not continuous may also be included unless "immediately" or "directly" is used.

[0024] First, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0025] In describing the components of this specification, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are intended only to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by the terms. Where it is stated that a component is "connected," "coupled," or "joined" to another component, it should be understood that the component may be directly connected or joined to the other component, but that other components may be "interposed" between each component that may be indirectly connected or joined unless specifically stated otherwise.

[0026] "At least one" should be understood to include all combinations of one or more associated components. For example, the meaning of "at least one of the first, second, and third components" may be said to include not only the first, second, or third components, but also all combinations of two or more of the first, second, and third components.

[0027] The features of each of the various embodiments of this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0028] The embodiments of this specification are described below through the attached drawings and examples. For the convenience of explanation, the scale of the components shown in the drawings may differ from the actual scale and is therefore not limited to the scale shown in the drawings.

[0029] FIG. 1 is a plan view showing a light-emitting display device according to one embodiment of the present specification, and FIG. 2 is a side view showing a light-emitting display device according to one embodiment of the present specification.

[0030] Referring to FIG. 1 and FIG. 2, a light-emitting display device (or light-emitting display panel) (10) according to one embodiment of the present specification may include a substrate (100) having a display portion (AA) and a plurality of pixels (P) on the display portion (AA) of the substrate (100).

[0031] The substrate (100) may be represented as a first substrate, a base substrate, or a pixel array substrate. For example, the substrate (100) may be a glass substrate, a thin glass substrate that can be bent or curved, or a plastic substrate.

[0032] A substrate (100) according to one embodiment may include a first surface (100a), a second surface (100b), and an outer surface (OS). The first surface (100a) of the substrate (100) may be defined as a front surface (or front side), an upper surface, or an upper surface facing the front (or front) of the light-emitting display device. The second surface (100b) of the substrate (100) may be defined as a back surface, a rear surface, a lower surface, or a lower surface facing the rear (or rear) of the light-emitting display device. The outer surface (OS) of the substrate (100) may be defined as a side surface, a side, or a side wall that is exposed to the air while facing the lateral surface (or side) of the light-emitting display device.

[0033] The display portion (AA) is an area where an image is displayed, and may be expressed as an active portion, an active area, or a display area. The size of the display portion (AA) may be the same as the size of the substrate (or light-emitting display device) (10). For example, the size of the display portion (AA) may be the same as the entire size of the first surface (100a) of the substrate (100). Accordingly, the display portion (AA) is implemented (or placed) over the entire front surface of the substrate (100), so that the substrate (100) does not include an opaque non-display area provided along the edge portion of the first surface (100a) to surround the entire display portion (AA). Therefore, the entire front surface of the light-emitting display device can implement the display portion (AA).

[0034] The end (or outermost) (AAa) of the display portion (AA) may overlap with the outer surface (OS) of the substrate (100) or be aligned with the outer surface (OS) of the substrate (100). For example, with respect to the thickness direction (Z) of the light-emitting display device, the lateral surface (AAa) of the display portion (AA) may be aligned with a vertical extension line (VL) that extends vertically from the outer surface (OS) of the substrate (100). The lateral surface (AAa) of the display portion (AA) may be surrounded only by air without being surrounded by a separate structure. That is, all lateral surfaces (AAa) of the display portion (AA) may be structured to be in direct contact with air without being surrounded by a separate structure. Accordingly, by having the outer surface (OS) of the substrate (100) corresponding to the end (AAa) of the display portion (AA) surrounded only by air, the light-emitting display device according to the present specification may have an air-bezel structure or a bezel-less structure in which the end (AAa) (or side) of the display portion (AA) is surrounded by air rather than an opaque non-display area.

[0035] A plurality of pixels (P) may be arranged (or positioned) on a display portion (AA) of a substrate (100) to have a first spacing (D1) along each of a first direction (X) and a second direction (Y). The first direction (X) may be a horizontal direction or a horizontal direction, or a first length direction (e.g., horizontal length direction) of the substrate (100) or the light-emitting display device. The second direction (X) may be a vertical direction or a vertical direction, or a second length direction (e.g., vertical length direction) of the substrate (100) or the light-emitting display device.

[0036] Each of the plurality of pixels (P) may be implemented on a plurality of pixel regions defined on a display portion (AA) of the substrate (100). Each of the plurality of pixel regions may have a first length (L1) parallel to a first direction (X) and a second length (L2) parallel to a second direction (Y). The first length (L1) may be the same as the second length (L2) or the same as a first interval (D1). The first length (L1) and the second length (L2) may be the same as the first interval (D1). Accordingly, the plurality of pixels (or pixel regions) (P) may all have the same size. For example, the first length (L1) may be expressed as a first width, horizontal length, or horizontal width. The second length (L2) may be expressed as a second width, vertical length, or vertical width.

[0037] Two adjacent pixels (P) along each of the first direction (X) and the second direction (Y) may have the same first interval (D1) within the error range of the manufacturing process. The first interval (D1) may be the pitch (or pixel pitch) between two adjacent pixels (P). For example, the first interval (or pixel pitch) (D1) may be the shortest distance (or shortest length) between the centers of each of two adjacent pixels (P).

[0038] Each of the plurality of pixels (P) may include a circuit layer comprising a pixel circuit implemented in a pixel area on a substrate (100), and a light-emitting element layer disposed on the circuit layer and connected to the pixel circuit. The pixel circuit outputs a data current corresponding to the data signal in response to a data signal and a scan signal supplied from pixel driving lines disposed in the pixel area. The light-emitting element layer may include a light-emitting layer that emits light by the data current supplied from the pixel circuit. These pixel driving lines, pixel circuit, and light-emitting element layer will be described later.

[0039] Multiple pixels (P) can be divided into outermost pixels (Po) and inner pixels (Pi).

[0040] The outermost pixels (Po) may be pixels among a plurality of pixels (P) that are closest to the outer surface (OS) of the substrate (100). For example, the outermost pixels (Po) may be represented as first pixels.

[0041] The second gap (D2) between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100) may be half or less than half of the first gap (D1). For example, the second gap (D2) may be the shortest distance (or shortest length) between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100).

[0042] When the second gap (D2) exceeds half of the first gap (D1), the substrate (100) must have a size larger than the display portion (AA) by the difference between half of the first gap (D1) and the second gap (D2), and thus the area between the end of the outermost pixel (Po) and the outer surface (OS) of the substrate (100) can be configured as a non-display area surrounding the entire display portion (AA). For example, when the second gap (D2) exceeds half of the first gap (D1), the substrate (100) inevitably includes a bezel area corresponding to the non-display area surrounding the entire display portion (AA). In contrast, when the second interval (D2) is half or less than half of the first interval (D1), the end of the outermost pixel (Po) may be aligned with the outer surface (OS) of the substrate (100) or the end (AAa) of the display portion (AA) may be aligned with the outer surface (OS) of the substrate (100), and as a result, the display portion (AA) may be implemented (or placed) over the entire front surface of the substrate (100).

[0043] The inner pixels (Pi) may be the remaining pixels among the plurality of pixels (P) excluding the outermost pixels (Po), or pixels surrounded by the outermost pixels (Po) among the plurality of pixels (P). The inner pixels (Pi) may be represented as second pixels. These inner pixels (Pi) may be implemented with a different configuration or structure from the outermost pixels (Po).

[0044] A light-emitting display device (10) according to one embodiment of the present specification may further include a disconnection part (115).

[0045] The disconnection portion (115) may be positioned along the edge portion of the substrate (100). The disconnection portion (115) may be implemented in a closed-loop form on the edge portion of the substrate (100). The disconnection portion (115) may be included in the outermost pixels (Po) or positioned on the edge portion of the outermost pixels (Po). For example, the disconnection portion (115) may be positioned between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100). The outermost pixels (Po) may be implemented with a different configuration or structure from the inner pixels (Pi) by including the disconnection portion (115). A light-emitting display device (10) according to one embodiment of the present specification may have a zero bezel structure (or air bezel structure) by having the disconnection portion (115) included in or positioned in the outermost pixels (Po), thereby allowing the entire front surface of the substrate (100) to be implemented as a display portion (AA).

[0046] The cutting portion (115) cuts off the light-emitting layer formed on the edge portion of the substrate (100) at least once, thereby blocking lateral moisture penetration propagating in the lateral direction of the substrate (100), so as to prevent deterioration of the light-emitting layer due to lateral moisture penetration or prevent a decrease in the reliability of the light-emitting layer. The cutting portion (115) according to one embodiment may include a plurality of cutting portions arranged side by side. Such cutting portions (115) will be described later.

[0047] A light-emitting display device (10) according to one embodiment of the present specification may further include a damper (117) and a sealing layer disposed on the light-emitting element layer and the damper (117).

[0048] The dam portion (117) may be positioned along the edge portion of the substrate (100). The dam portion (117) may be implemented in a closed-loop form on the edge portion of the substrate (100). The dam portion (117) may be included in the outermost pixels (Po) or positioned on the edge portion of the outermost pixels (Po). For example, the dam portion (117) may be positioned between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100). The dam portion (117) may be surrounded by a disconnection portion (115). The outermost pixels (Po) may be implemented in a different configuration or structure from the inner pixels (Pi) by including the dam portion (117). A light-emitting display device (10) according to one embodiment of the present specification may have a zero bezel structure (or air bezel structure) by including or arranging a disconnection part (115) and a damper part (117) in the outermost pixels (Po), and thus the entire front surface of the substrate (100) may be implemented as a display part (AA).

[0049] The encapsulation layer may be implemented to surround the light-emitting element layer. An encapsulation layer according to one embodiment may include a first inorganic encapsulation layer (or first encapsulation layer) disposed on the light-emitting element layer and the dam portion (117), a second inorganic encapsulation layer (or third encapsulation layer) disposed on the first inorganic encapsulation layer, and an organic encapsulation layer (or second encapsulation layer) interposed between the first encapsulation layer and the second encapsulation layer disposed on the light-emitting element layer surrounded by the dam portion (117). Such encapsulation layers will be described later.

[0050] The dam portion (117) can define or limit the placement area (or formation area) of the organic encapsulation layer covering the front surface (or upper surface) of the light-emitting element layer. The dam portion (117) can block or prevent overflow of the organic encapsulation layer.

[0051] A light-emitting display device (10) according to one embodiment of the present specification may further include a routing unit (400).

[0052] The routing section (400) may be implemented to wrap around or surround one side of the substrate (100) and one edge portion (or first edge portion) of the substrate (100). The routing section (400) may be included in the outermost pixels (Po) placed on one edge portion of the substrate (100) or placed on the edge portion of the outermost pixels (Po) placed on one edge portion of the substrate (100). The outermost pixels (Po) placed on one edge portion of the substrate (100) may be implemented with a different configuration or structure from the inner pixels (Pi) by including the routing section (400). The routing section (400) may be represented as a side routing section or a printing line section.

[0053] The routing section (400) can be electrically connected to pixel driving lines for driving pixels (P) by passing through an encapsulation layer and a circuit layer disposed at the edge portion of the substrate (100). According to one embodiment, the routing section (400) can be electrically connected to pixel driving lines by passing through the encapsulation layer, the disconnection section (115), and the circuit layer in sequence. According to one embodiment, the routing section (400) can be electrically connected to pixel driving lines by passing through the encapsulation layer, the dam section (117), and the circuit layer in sequence. According to one embodiment, the routing section (400) can be electrically connected to pixel driving lines by passing through the encapsulation layer, the disconnection section (115), and the circuit layer in sequence, and simultaneously electrically connected to pixel driving lines by passing through the encapsulation layer, the dam section (117), and the circuit layer in sequence. Such a routing section (400) will be described later.

[0054] A light-emitting display device (10) according to one embodiment of the present specification may have a zero bezel structure (or air bezel structure) by including or arranging a disconnection part (115), a dam part (117), and a routing part (400) in the outermost pixels (Po), and thus the entire front surface of the substrate (100) may be implemented as a display part (AA).

[0055] FIG. 3a is a drawing showing one pixel according to one embodiment shown in FIG. 1, and FIG. 3b is a drawing showing one pixel according to another embodiment shown in FIG. 1.

[0056] Referring to FIG. 1 and FIG. 3a, a pixel (or unit pixel) (P) according to one embodiment of the present specification may include first to fourth subpixels (SP1, SP2, SP3, SP4) arranged in a pixel area (PA).

[0057] The first subpixel (SP1) may be placed in the first subpixel area of ​​the pixel area (PA), the second subpixel (SP2) may be placed in the second subpixel area of ​​the pixel area (PA), the third subpixel (SP3) may be placed in the third subpixel area of ​​the pixel area (PA), and the fourth subpixel (SP4) may be placed in the fourth subpixel area of ​​the pixel area (PA).

[0058] In one embodiment, the first subpixel (SP1) may be implemented to emit light of a first color, the second subpixel (SP2) may emit light of a second color, the third subpixel (SP3) may emit light of a third color, and the fourth subpixel (SP4) may emit light of a fourth color, respectively. Each of the first to fourth colors may be different. For example, the first color may be red, the second color may be blue, the third color may be white, and the fourth color may be green.

[0059] In another embodiment, some of the first to fourth colors may be the same. For example, the first color may be red, the second color may be the first green, the third color may be the second green, and the fourth color may be blue.

[0060] Each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may include a light-emitting region (EA1, EA2, EA3, EA4) and a circuit region (CA1, CA2, CA3, CA4).

[0061] The light-emitting regions (EA1, EA2, EA3, EA4) may be positioned so as to be offset toward the center (CP) of the pixel (P) within the subpixel region. For example, the light-emitting regions (EA1, EA2, EA3, EA4) may be described as an aperture region, an aperture, or a light-emitting part.

[0062] According to one embodiment, the light-emitting regions (EA1, EA2, EA3, EA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may have the same size as each other. For example, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may have an equal quad structure or an equal stripe structure. For example, in the first to fourth subpixels (SP1, SP2, SP3, SP4) having an equal quad structure or an equal stripe structure, the light-emitting regions (EA1, EA2, EA3, EA4) may have a size smaller than the quarter size of the pixel (P) and may be positioned offset toward the center (CP) of the pixel (P) or concentrated toward the center (CP) of the pixel (P) within the subpixel area.

[0063] Referring to FIG. 1 and FIG. 3b, each of the first to fourth subpixels (SP1, SP2, SP3, SP4) according to another embodiment may have an unequal quad structure or an unequal stripe structure having different sizes. For example, each light-emitting region (EA1, EA2, EA3, EA4) of the first to fourth subpixels (SP1, SP2, SP3, SP4) may have an unequal quad structure or an unequal stripe structure.

[0064] The size of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) having an unequal quad structure (or unequal stripe structure) can be set according to resolution, luminous efficiency, or image quality, etc. In one embodiment, when the light-emitting regions (EA1, EA2, EA3, EA4) have an unequal quad structure (or unequal stripe structure), among the light-emitting regions (EA1, EA2, EA3, EA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4), the light-emitting region (EA4) of the fourth subpixel (SP4) may have the smallest size, and the light-emitting region (EA3) of the third subpixel (SP3) may have the largest size. For example, the light-emitting regions (EA1, EA2, EA3, EA4) having an unequal quad structure (or unequal stripe structure) may be arranged concentrated around the center (CP) of the pixel (P).

[0065] Each circuit area (CA1, CA2, CA3, CA4) of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be positioned around the corresponding light-emitting area (EA1, EA2, EA3, EA4). The circuit area (CA1, CA2, CA3, CA4) may include circuits and pixel driving lines for emitting light from the corresponding subpixel. For example, the circuit area (CA1, CA2, CA3, CA4) may be described as a non-light-emitting area, a non-aperture area, a non-light-emitting part, a non-aperture part, or a peripheral part.

[0066] Alternatively, in order to increase the aperture ratio of the subpixels (SP1, SP2, SP3, SP4) corresponding to the size of the light-emitting regions (EA1, EA2, EA3, EA4) or to reduce the pixel pitch (D1) according to the resolution of the pixel (P), the light-emitting regions (EA1, EA2, EA3, EA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be extended onto the circuit region (CA1, CA2, CA3, CA4) so ​​as to overlap with part or all of the circuit region (CA1, CA2, CA3, CA4). For example, the light-emitting regions (EA1, EA2, EA3, EA4) of each of the first to fourth subpixels (SP1, SP2, SP3, SP4) may be implemented on the substrate (100) so as to overlap with the corresponding circuit region (CA1, CA2, CA3, CA4). In this case, the light-emitting region (EA1, EA2, EA3, EA4) may have a size equal to or larger than the circuit region (CA1, CA2, CA3, CA4).

[0067] Alternatively, according to another embodiment, each of the plurality of pixels (P) may include first to third subpixels (SP1, SP2, SP3).

[0068] Each light-emitting region (EA1, EA2, EA3) of the first to third subpixels (SP1, SP2, SP3) has a rectangular shape having a short side parallel to the first direction (X) and a long side parallel to the second direction (Y), and can be arranged, for example, in a 1x3 shape or a 1x3 stripe shape. For example, the first subpixel (SP1) may be a red subpixel, the second subpixel (SP2) may be a blue subpixel, and the third subpixel (SP3) may be a green subpixel.

[0069] Figure 4 is an enlarged view of the 'B1' portion shown in Figure 1, and Figure 5 is an equivalent circuit diagram for a single pixel shown in Figures 1 and 4.

[0070] Referring to FIGS. 1, 4, and 5, a substrate (100) according to one embodiment of the present specification may include pixel driving lines (DL, GL, PL, CVL, RL, GCL), a plurality of pixels (P), a common electrode (CE), a plurality of common electrode connection portions (CECP), a contact pattern portion (110), and a disconnection portion (115).

[0071] Pixel driving lines (DL, GL, PL, CVL, RL, GCL) may include a plurality of data lines (DL), a plurality of gate lines (GL), a plurality of pixel driving power lines (PL), a plurality of pixel common voltage lines (CVL), a plurality of reference voltage lines (RL), and gate control lines (GCL).

[0072] Each of the plurality of data lines (DL) may be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) at a predetermined interval along the first direction (X). For example, among the plurality of data lines (DL), the odd-numbered data line (DLo) may be arranged at the first edge portion of each of the plurality of pixel regions (PA) arranged on the substrate (100) along the second direction (Y), and the even-numbered data line (DLe) may be arranged at the second edge portion of each of the plurality of pixel regions (PA) arranged on the substrate (100) along the second direction (Y), but is not limited thereto.

[0073] Each of the plurality of gate lines (GL) may be extended along the first direction (X) and arranged on the display portion (AA) of the substrate (100) with a predetermined spacing along the second direction (Y). For example, among the plurality of gate lines (GL), the odd-numbered gate line (GLo) may be arranged on the third edge portion of each of the plurality of pixel regions (PA) arranged on the substrate (100) along the first direction (X), and the even-numbered gate line (GLe) may be arranged on the fourth edge portion of each of the plurality of pixel regions (PA) arranged on the substrate (100) along the first direction (X), but is not limited thereto.

[0074] Each of the plurality of pixel driving power lines (PL) may be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) at a predetermined interval along the first direction (X). For example, among the plurality of pixel driving power lines (PL), the odd-numbered pixel driving power line (PL) may be arranged at the first edge portion of the odd-numbered pixel area (PA) with respect to the first direction (X), and the even-numbered pixel driving power line (PL) may be arranged at the second edge portion of the even-numbered pixel area (PA) with respect to the first direction (X), but is not limited thereto.

[0075] Among a plurality of pixel driving power lines (PL), two adjacent pixel driving power lines (PL) can be connected to each other through a plurality of power sharing lines (PSL) arranged in each pixel area (PA) along the second direction (Y). For example, the plurality of pixel driving power lines (PL) may have a ladder structure or a mesh structure by being electrically connected to each other by the plurality of power sharing lines (PSL). By having the plurality of pixel driving power lines (PL) have a ladder structure or a mesh structure, the voltage drop (IR drop) of the pixel driving power due to the line resistance of the pixel driving power lines (PL) can be prevented or minimized, and as a result, the light-emitting display device according to the present example can prevent or minimize image quality defects caused by deviations in the pixel driving power supplied to each pixel (P) arranged in the display unit (AA).

[0076] Each of the multiple power sharing lines (PSL) may be branched from an adjacent pixel driving power line (PL) so as to be parallel to the first direction (X) and placed in the middle area of ​​each pixel region (PA), but is not limited thereto.

[0077] Each of the plurality of pixel common voltage lines (CVL) may be extended along the second direction (Y) and arranged on the display portion (AA) of the substrate (100) with a predetermined spacing along the first direction (X). For example, each of the plurality of pixel common voltage lines (CVL) may be arranged at the first edge portion of an even-numbered pixel area (PA) with respect to the first direction (X), but is not limited thereto.

[0078] Each of the plurality of reference voltage lines (RL) may be arranged on the display portion (AA) of the substrate (100) such that it is extended along the second direction (Y) and has a predetermined spacing along the first direction (X). Each of the plurality of reference voltage lines (RL) may be arranged in the center area of ​​each pixel area (PA) arranged along the second direction (Y), but is not limited thereto.

[0079] Each of the plurality of reference voltage lines (RL) may be shared with two adjacent subpixels ((SP1, SP2)(SP3, SP4)) along a first direction (X) in each pixel area (PA). To this end, each of the plurality of reference voltage lines (RL) may include a reference branch line (RDL). The reference branch line (RDL) may branch (or protrude) toward two adjacent subpixels ((SP1, SP2)(SP3, SP4)) along a first direction (X) in each pixel area (PA) and may be electrically connected to the two adjacent subpixels ((SP1, SP2)(SP3, SP4)).

[0080] Each of the plurality of gate control lines (GCL) may be arranged on the display portion (AA) of the substrate (100) such that it extends along the second direction (Y) and has a predetermined spacing along the first direction (X). For example, each of the plurality of gate control lines (GCL) may be arranged at the boundary between a plurality of pixel regions (PA) or between two adjacent pixel regions (PA) with respect to the first direction (X).

[0081] Each of the plurality of pixels (P) may include at least three subpixels. For example, each of the plurality of pixels (P) may include first to fourth subpixels (SP1 to SP4).

[0082] Each of the first to fourth subpixels (SP1 to SP4) may include a pixel circuit (PC) and a light-emitting element layer.

[0083] A pixel circuit (PC) according to one embodiment may be placed in the circuit area of ​​a pixel area (PA) and connected to adjacent gate lines (GLo, GLe), data lines (DLo, DLe), and pixel driving power lines (PL). For example, a pixel circuit (PC) placed in a first subpixel (SP1) may be connected to an odd-numbered data line (DLo) and an odd-numbered gate line (GLo), a pixel circuit (PC) placed in a second subpixel (SP2) may be connected to an even-numbered data line (DLe) and an odd-numbered gate line (GLo), a pixel circuit (PC) placed in a third subpixel (SP3) may be connected to an odd-numbered data line (DLo) and an even-numbered gate line (GLe), and a pixel circuit (PC) placed in a fourth subpixel (SP4) may be connected to an even-numbered data line (DLe) and an even-numbered gate line (GLe).

[0084] Each pixel circuit (PC) of the first to fourth subpixels (SP1 to SP4) can sample a data signal supplied from a corresponding data line (DLo, DLe) in response to a scan signal supplied from a corresponding gate line (GLo, GLe) and control the current flowing from the pixel driving power line (PL) to the light-emitting element layer based on the sampled data signal.

[0085] A pixel circuit (PC) according to one embodiment may include, but is not limited to, a first switching thin film transistor (Tsw1), a second switching thin film transistor (Tsw2), a driving thin film transistor (Tdr), and a storage capacitor (Cst). In the following description, the thin film transistor will be referred to as "TFT".

[0086] The first switching TFT (Tsw1) may include a gate electrode connected to an odd-numbered gate line (or first gate line) (GLo), a first source / drain electrode connected to a data line (DL), and a second source / drain electrode connected to a gate node (n1) of a driving TFT (Tdr). This first switching TFT (Tsw1) may supply a data voltage supplied from the data line (DL) to the gate node (n1) of the driving TFT (Tdr) according to a first scan signal supplied to the odd-numbered gate line (GLo).

[0087] The second switching TFT (Tsw2) may include a gate node connected to an even-numbered gate line (or second gate line) (GLe), a first source / drain electrode connected to a source node (n2) of a driving TFT (Tdr), and a second source / drain electrode connected to a reference voltage line (RL). This second switching TFT (Tsw2) may supply a reference voltage supplied to the reference voltage line (RL) to the source node (n2) of the driving TFT (Tdr) according to a second scan signal supplied to the even-numbered gate line (GLe).

[0088] A storage capacitor (Cst) may be formed between a gate node (n1) and a source node (n2) of a driving TFT (Tdr). A storage capacitor (Cst) according to one embodiment may include a first capacitor electrode connected to the gate node (n1) of the driving TFT (Tdr), a second capacitor electrode connected to the source node (n2) of the driving TFT (Tdr), and a dielectric layer formed in the overlapping region of the first capacitor electrode and the second capacitor electrode. After charging the differential voltage between the gate node (n1) and the source node (n2) of the driving TFT (Tdr), the storage capacitor (Cst) switches the driving TFT (Tdr) according to the charged voltage.

[0089] The driving thin-film transistor (Tdr) may include a gate electrode (or gate node (n1)) commonly connected to the second source / drain electrode of the first switching TFT (Tsw1) and the first capacitor electrode of the storage capacitor (Cst), a first source / drain electrode (or source node (n2)) commonly connected to the first source / drain electrode of the second switching TFT (Tsw2), the second capacitor electrode of the storage capacitor (Cst), and the pixel electrode (PE) of the light-emitting element layer, and a second source / drain electrode (or drain node) connected to the pixel driving power line (PL). This driving TFT (Tdr) can control the amount of current flowing from the pixel driving power line (PL) to the light-emitting element layer by being turned on by the voltage of the storage capacitor (Cst).

[0090] According to another embodiment, each pixel circuit (PC) of the first to fourth subpixels (SP1 to SP4) may be implemented in the form of a pixel driving chip by a semiconductor manufacturing process, placed in the circuit area of ​​the corresponding pixel area (PA), and connected to adjacent gate lines (GLo, GLe), data lines (DLo, DLe), and pixel driving power lines (PL). For example, the pixel driving chip may be a semiconductor packaging device having a small size, having two or more transistors and one or more capacitors, as a minimum unit microchip or a single chip set. Such a pixel driving chip may sample a data signal supplied from the corresponding data lines (DLo, DLe) in response to a scan signal supplied from the corresponding gate lines (GLo, GLe), and control the current flowing from the pixel driving power line (PL) to the light-emitting element layer based on the sampled data signal.

[0091] The light-emitting element layer may be disposed in the light-emitting region (EA) of the pixel region (PA) and electrically connected to the pixel circuit (PC). According to one embodiment, the light-emitting element layer may include a pixel electrode (PE) electrically connected to the pixel circuit (PC), a common electrode (CE) electrically connected to a pixel common voltage line (CVL), and a light-emitting layer (EL) interposed between the pixel electrode (PE) and the common electrode (CE).

[0092] A light-emitting layer (EL) according to one embodiment may include at least one organic light-emitting layer. The light-emitting layer (EL) may further include a hole functional layer that provides holes to the organic light-emitting layer, and an electron functional layer that provides electrons to the organic light-emitting layer. Such a light-emitting layer (EL) can emit light with a brightness corresponding to the data current by emitting light through a data current supplied from a pixel circuit (PC).

[0093] A common electrode (CE) is placed on a display portion (AA) of a substrate (100) and is electrically connected to the light-emitting layer (EL) of each of a plurality of pixels (P). For example, the common electrode (CE) may be placed on the display portion (AA) of the substrate (100) excluding the contact pattern portion (110) placed on the substrate (100).

[0094] Each of the plurality of common electrode connection portions (CECP) electrically connects the common electrode (CE) to each of the plurality of pixel common voltage lines (CVL) between the plurality of pixels (P) that overlap with each of the plurality of pixel common voltage lines (CVL). Each of the plurality of common electrode connection portions (CECP) according to one embodiment is electrically connected to each of the plurality of pixel common voltage lines (CVL) at the boundary between the plurality of pixels (P) or between the plurality of pixels with respect to the second direction (Y), and can electrically connect the common electrode (CE) to each of the plurality of pixel common voltage lines (CVL) by being electrically connected to a part of the common electrode (CE).

[0095] Each of the plurality of common electrode connection portions (CECP) is arranged between each of the plurality of pixels (P) and electrically connects each of the plurality of pixel common voltage lines (CVL) to the common electrode (CE), thereby preventing or minimizing the voltage drop (IR drop) of the pixel common voltage due to the sheet resistance of the common electrode (CE). As a result, the light-emitting display device according to the present example can prevent or minimize image quality defects caused by deviations in the pixel common voltage supplied to each pixel (P) arranged in the display portion (AA).

[0096] According to one embodiment, each of a plurality of common electrode connection portions (CECP) may be formed together with a pixel electrode (PE) having at least a two-layer structure so as to be electrically connected to each of a plurality of pixel common voltage lines (CVL). Each of the plurality of common electrode connection portions (CECP) is " ( " or " < It can be electrically connected to a common electrode (CE) through a side contact structure having a cross-sectional structure of the shape. For example, when each of a plurality of common electrode connection parts (CECP) is composed of a first and a second metal layer, each of the plurality of common electrode connection parts (CECP) may have a side contact structure corresponding to an undercut structure or a tapered structure formed on the side of the first metal layer by the etching rate between the first and second metal layers. For example, when each of the plurality of common electrode connection parts (CECP) is composed of a first to third metal layer, each of the plurality of common electrode connection parts (CECP) may have a side contact structure corresponding to an undercut structure or a tapered structure formed on the side of the first metal layer by the etching rate between the first and second metal layers.

[0097] The contact pattern portion (110) may be placed on a first edge portion (or one edge portion) of a first surface of a substrate (100) parallel to the first direction (X). The contact pattern portion (110) is included (or placed) within the outermost pixel regions (PAo) placed on the first edge portion of the substrate (100), so that no non-display area (or bezel area) according to the contact pattern portion (110) is formed or does not exist on the substrate (100). For example, the contact pattern portion (110) may be placed on a third edge portion of the outermost pixel regions (PAo) placed on the first edge portion of the substrate (100).

[0098] The contact pattern portion (110) may include contact patterns (PCP, DCP, RCP, GCP, CCP) disposed on the circuit layer (111) and connected to pixel driving lines (DL, GL, PL, CVL, RL, GCL). The contact pattern portion (110) may include contact patterns (PCP, DCP, RCP, GCP, CCP) disposed parallel to each other on the circuit layer (111) along a first direction (X) on a first edge portion of the substrate (100). According to one embodiment, the contact pattern portion (110) may include five types of contact patterns (PCP, DCP, RCP, GCP, CCP). The contact pattern section (110) may include data contact patterns (DCP), pixel driving power contact patterns (PCP), pixel common voltage contact patterns (CCP), reference voltage contact patterns (RCP), and gate contact patterns (GCP), but is not limited thereto.

[0099] Data contact patterns (DCP) are for receiving data signals and may be first contact patterns. Each of the data contact patterns (DCP) according to one embodiment is placed on the same layer as the data lines (DL) and may extend (or expand) toward the outer surface (OS) of the substrate (100) with a relatively wide width from each end of the data lines (DL) located at one edge portion of the substrate (100). Each of the data contact patterns (DCP) according to another embodiment is placed on the layer below the data lines (DL) with a relatively wide width so as to overlap with each end of the data lines (DL) located at one edge portion of the substrate (100), and may be electrically connected to each end of the data lines (DL) through an internal contact hole.

[0100] Pixel driving power contact patterns (PCP) are for receiving pixel driving power and may be second contact patterns. Each pixel driving power contact pattern (PCP) according to one embodiment is disposed on the same layer as the pixel driving power lines (PL) and may extend (or expand) toward the outer surface (OS) of the substrate (100) with a relatively wide width from each end of the pixel driving power lines (PL) located at one edge portion of the substrate (100). Each pixel driving power contact pattern (PCP) according to another embodiment is disposed on the layer below the pixel driving power lines (PL) with a relatively wide width so as to overlap with each end of the pixel driving power lines (PL) located at one edge portion of the substrate (100), and may be electrically connected to each end of the pixel driving power lines (PL) through an internal contact hole.

[0101] Pixel common voltage contact patterns (CCPs) are for receiving pixel common voltage and may be third contact patterns. Each pixel common voltage contact pattern (CCP) according to one embodiment is disposed on the same layer as the pixel common voltage lines (CVL) and may extend (or expand) toward the outer surface (OS) of the substrate (100) with a relatively wide width from each end of the pixel common voltage lines (CVL) located at one edge portion of the substrate (100). Each pixel common voltage contact pattern (CCP) according to another embodiment is disposed on the layer below the pixel common voltage lines (CVL) with a relatively wide width so as to overlap with each end of the pixel common voltage lines (CVL) located at one edge portion of the substrate (100), and may be electrically connected to each end of the pixel common voltage lines (CVL) through an internal contact hole.

[0102] Reference voltage contact patterns (RCPs) are for receiving a reference voltage and may be a fourth contact pattern. Each of the reference voltage contact patterns (RCPs) according to one embodiment is disposed on the same layer as the reference voltage lines (RL) and may extend (or expand) toward the outer surface (OS) of the substrate (100) with a relatively wide width from each end of the reference voltage lines (RL) located at one edge portion of the substrate (100). Each of the reference voltage contact patterns (RCPs) according to another embodiment is disposed on the layer below the reference voltage lines (RL) with a relatively wide width so as to overlap with each end of the reference voltage lines (RL) located at one edge portion of the substrate (100), and may be electrically connected to each end of the reference voltage lines (RL) through an internal contact hole.

[0103] Gate contact patterns (GCPs) are for receiving gate control signals and may be fifth contact patterns. Each of the gate contact patterns (GCPs) according to one embodiment is disposed on the same layer as the gate control lines (GCL) and may extend (or expand) toward the outer surface (OS) of the substrate (100) with a relatively wide width from each end of the gate control lines (GCL) located at one edge portion of the substrate (100). Each of the gate contact patterns (GCPs) according to another embodiment is disposed on the layer below the gate control lines (GCL) with a relatively wide width so as to overlap with each end of the gate control lines (GCL) located at one edge portion of the substrate (100), and may be electrically connected to each end of the gate control lines (GCL) through an internal contact hole.

[0104] A contact pattern section (110) according to one embodiment may include a plurality of contact pattern groups (CPG). Among the plurality of contact pattern groups (CPG), two or more contact pattern groups (CPG) may include at least one data contact pattern and at least one gate contact pattern.

[0105] According to one embodiment, the contact pattern portion (110) may include a first contact pattern group (CPG1) and a second contact pattern group (CPG2).

[0106] A first contact pattern group (CPG1) may be placed on odd-numbered outermost pixels among the outermost pixels (Po) arranged along a first direction (X). For example, the first contact pattern group (CPG1) may include one pixel driving power contact pattern (PCP), two data contact patterns (DCP), one reference voltage contact pattern (RCP), and one gate contact pattern (GCP). For example, the contact patterns (PCP, DCP, RCP, GCP) belonging to the first contact pattern group (CPG1) may be arranged along the first direction (X) in the order of a pixel driving power contact pattern (PCP), a data contact pattern (DCP), a reference voltage contact pattern (RCP), a data contact pattern (DCP), and a gate contact pattern (GCP), but are not limited thereto.

[0107] The second contact pattern group (CPG2) may be placed on the even-numbered outermost pixels among the outermost pixels (Po) arranged along the first direction (X). For example, the second contact pattern group (CPG2) may include one pixel driving power contact pattern (PCP), two data contact patterns (DCP), one reference voltage contact pattern (RCP), and one pixel common voltage contact pattern (CCP). For example, the contact patterns (PCP, DCP, RCP, CCP) belonging to the second contact pattern group (CPG2) may be arranged along the first direction (X) in the order of the pixel common voltage contact pattern (CCP), data contact pattern (DCP), reference voltage contact pattern (RCP), data contact pattern (DCP), and pixel driving power contact pattern (PCP), but are not limited thereto.

[0108] A substrate (100) according to one embodiment may further include a plurality of pixel common power auxiliary lines (CPSL) and a plurality of pixel common auxiliary line connection portions (SLCP).

[0109] Each of the plurality of pixel common power auxiliary lines (CPSL) may be extended along a second direction (Y) and arranged adjacent to each of the plurality of pixel common voltage lines (CVL). Each of the plurality of pixel common power auxiliary lines (CPSL) may not be electrically connected to a pixel common voltage pad (CVP) but may be electrically connected to an adjacent pixel common voltage line (CVL) to receive a pixel common voltage from the adjacent pixel common voltage line (CVL). To this end, the substrate (100) according to the present specification may further include a plurality of line connection patterns (LCP) that electrically connect adjacent pixel common voltage lines (CVL) and pixel common power auxiliary lines (CPSL).

[0110] Each of the plurality of line connection patterns (LCP) is arranged on a substrate (100) to intersect adjacent pixel common voltage lines (CVL) and pixel common power auxiliary lines (CPSL), and the adjacent pixel common voltage lines (CVL) and pixel common power auxiliary lines (CPSL) can be electrically connected through a line jumping structure. For example, one side of each of the plurality of line connection patterns (LCP) can be electrically connected to a part of the pixel common power auxiliary line (CPSL) through a first line contact hole formed in an insulating layer on the pixel common power auxiliary line (CPSL), and the other side of each of the plurality of line connection patterns (LCP) can be electrically connected to a part of the pixel common voltage line (CVL) through a second line contact hole formed in an insulating layer on the pixel common voltage line (CVL).

[0111] Each of the plurality of pixel common auxiliary line connection portions (SLCP) electrically connects a common electrode (CE) to each of the plurality of pixel common auxiliary line (CPSL) between the plurality of pixels (P) that overlap with each of the plurality of pixel common auxiliary line (CPSL). Each of the plurality of pixel common auxiliary line connection portions (SLCP) according to one embodiment is electrically connected to each of the plurality of pixel common auxiliary line (CPSL) at the boundary between the plurality of pixels (P) or between the plurality of pixels with respect to the second direction (Y), and can electrically connect the common electrode (CE) to each of the plurality of pixel common auxiliary line (CPSL) by being electrically connected to a part of the common electrode (CE). Accordingly, the common electrode (CE) can be additionally connected to each of the plurality of pixel common auxiliary line (CPSL) through the plurality of pixel common auxiliary line connection portions (SLCP). As a result, the light-emitting display device according to the present example can further prevent or further minimize image quality defects caused by deviations in the pixel common voltage supplied to each pixel (P) arranged in the display portion (AA). In addition, the light-emitting display device according to the present example can supply a pixel common voltage to each of the plurality of pixel common power auxiliary lines (CPSL) through each of the pixel common voltage line (CVL) and each of the plurality of line connection patterns (LCP) without additionally arranging (or forming) a pixel common voltage contact pattern (CCP) connected to each of the plurality of pixel common power auxiliary lines (CPSL).

[0112] The disconnection portion (115) may be placed in a second region surrounding a first region of the substrate (100). For example, the second region of the substrate (100) may be an edge portion of the substrate (100) or an edge portion of the outermost pixels (Po). The first region of the substrate (100) may be the remaining portion excluding the second region. The disconnection portion (115) may be implemented in a closed-loop form on an edge portion of the substrate (100). According to one embodiment, the disconnection portion (115) may be placed on a contact pattern portion (110). For example, the disconnection portion (115) may be placed to cross the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern portion (110) along a first direction (X).

[0113] The disconnection portion (115) may be implemented to disconnect (or separate) the light-emitting layer (EL) at least once within the outermost pixels (Po) arranged along the edge portion of the substrate (100). The disconnection portion (115) disconnects the light-emitting layer formed on the edge portion of the substrate (100) at least once, thereby blocking lateral moisture penetration propagating in the lateral direction of the substrate (100), thereby preventing deterioration of the light-emitting layer due to lateral moisture penetration or preventing a decrease in the reliability of the light-emitting layer. The disconnection portion (115) according to one embodiment may include a plurality of disconnection pattern portions arranged side by side. For example, the disconnection portion (115) may include at least three disconnection pattern portions arranged side by side.

[0114] A substrate (100) according to one embodiment of the present specification may further include a damper (117).

[0115] The dam portion (117) may be positioned along the edge portion of the substrate (100). The dam portion (117) may be implemented in a closed-loop form on the edge portion of the substrate (100). The dam portion (117) may be included in the outermost pixels (Po) or positioned on the edge portion of the outermost pixels (Po). For example, the dam portion (117) may be positioned between the center of the outermost pixels (Po) and the outer surface (OS) of the substrate (100). The dam portion (117) may be surrounded by a disconnection portion (115). For example, the dam portion (117) may be implemented to surround the disconnection pattern portion positioned closest to the inner pixel (Pi) among a plurality of disconnection pattern portions. According to one embodiment, the dam portion (117) may be positioned on the contact pattern portion (110). For example, the dam portion (117) may be positioned to cross the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern portion (110) along the first direction (X).

[0116] FIG. 6 is a diagram showing a gate driving circuit implemented within the display unit shown in FIG. 4.

[0117] Referring to FIGS. 4 and FIGS. 6, a light-emitting display device according to one embodiment of the present specification may further include a gate driving circuit (150) disposed within a display portion (AA) on a substrate (100).

[0118] The gate driving circuit (150) is implemented (or embedded) within the display portion (AA) of the substrate (100) and can generate a scan signal based on a gate control signal supplied through the contact pattern portion (110) and gate control lines (GCL) and supply it sequentially to a plurality of gate lines (GL).

[0119] The gate control lines (GCL) may include a start signal line, a plurality of shift clock lines, at least one gate driving voltage line, and at least one gate common voltage line. The gate control lines (GCL) may be extended along a second direction (Y) and arranged on a display portion (AA) of the substrate (100) with a predetermined spacing along a first direction (X). For example, the gate control lines (GCL) may be arranged between at least one pixel (P) along the first direction (X).

[0120] A gate driving circuit (150) according to one embodiment may be implemented as a shift register including a plurality of stage circuit sections (1501 to 150m).

[0121] Each of the plurality of stage circuit sections (1501 to 150m) is individually arranged on each horizontal line on the first surface (100a) of the substrate (100) along the first direction (X) and can be connected dependently to each other along the second direction (Y). Each of the plurality of stage circuits (1501 to 150m) can generate a scan signal in a predetermined order in response to a gate control signal supplied through the contact pattern section (110) and the gate control lines (GCL) and supply it to the corresponding gate line (GL).

[0122] Each of the plurality of stage circuit sections (1501 to 150m) according to one embodiment may include a plurality of branch circuits (1511 to 151n) and a branch network (153).

[0123] Each of the plurality of branch circuits (1511 to 151n) is selectively connected to gate control lines (GCL) through the branch network (153) and can be electrically connected to each other through the branch network (153). Each of these plurality of branch circuits (1511 to 151n) can generate a scan signal according to the gate control signal supplied through the gate control lines (GCL) and the voltage of the branch network (153) and supply it to the corresponding gate line (GL).

[0124] Each of the plurality of branch circuits (1511 to 151n) may include at least one TFT among the plurality of TFTs constituting one stage circuit section (1501 to 150m). Any one of the plurality of branch circuits (1511 to 151n) may include a pull-up TFT connected to a gate line (GL). Another of the plurality of branch circuits (1511 to 151n) may include a pull-down TFT connected to a gate line (GL).

[0125] Each of the plurality of branch circuits (1511 to 151n) according to one embodiment may be placed in a circuit area between two adjacent pixels (P) or in a circuit area between at least two adjacent pixels (P) in each horizontal line of the substrate (100), but is not limited thereto. For example, each of the plurality of branch circuits (1511 to 151n) may be placed in a circuit area (or boundary area) between at least one adjacent pixel (P) depending on the number of TFTs constituting one stage circuit section (1501 to 150m) and the number of pixels (P) placed in one horizontal line.

[0126] A branch network (153) is arranged on each horizontal line of the substrate (100) and can electrically connect a plurality of branch circuits (1511 to 151n) to each other. A branch network (153) according to one embodiment may include a plurality of control nodes and a plurality of network lines.

[0127] A plurality of control nodes are arranged on each horizontal line of the substrate (100) and can be optionally connected to a plurality of branch circuits (1511 to 151n) on one horizontal line. For example, a plurality of control nodes may be arranged in the upper edge region (or lower edge region) among the pixel regions arranged on each horizontal line of the substrate (100).

[0128] A plurality of network lines may be selectively connected to gate control lines (GCL) disposed on the substrate (100) and may be selectively connected to a plurality of branch circuits (1511 to 151n). For example, the plurality of network lines may supply gate control signals supplied from the gate control lines (GCL) to the corresponding branch circuits (1511 to 151n) and transmit signals between the plurality of branch circuits (1511 to 151n).

[0129] Each of the plurality of stage circuit sections (1501 to 150m) according to one embodiment may include a first control node, a second control node, a node control circuit that controls the voltage of each of the first and second control nodes, an inverter circuit that controls the voltage of the second control node according to the voltage of the first control node, and an output buffer circuit that outputs a scan signal corresponding to a scan clock and a carry signal corresponding to a carry clock according to the voltage of the first control node, and outputs a scan signal and a carry signal corresponding to a gate-off voltage level according to the voltage of the second control node. For example, the node control circuit, the inverter circuit, and the output buffer circuit may include two or more branch circuits among the plurality of branch circuits (1511 to 151n). For example, the plurality of branch circuits (1511 to 151n) may be classified into a node control circuit, an inverter circuit, and an output buffer circuit, respectively.

[0130] According to this example, since the gate driving circuit (150) is positioned within the display portion (AA) of the substrate (100), the second gap (D2) between the center of the outermost pixel area (PAo) and the outer surfaces (OS) of the substrate (100) may be less than half of the first gap (or pixel pitch) (D1) between adjacent pixel areas (PA). For example, when the gate driving circuit (150) is not positioned within the display portion (AA) of the substrate (100) but is positioned at the edge portion of the substrate (100), the second gap (D2) may not be less than half of the first gap (D1). Accordingly, in a light-emitting display device according to another embodiment of the present specification, the second gap (D2) may be implemented as less than half of the first gap (D1) by positioning the gate driving circuit (150) within the display portion (AA) of the substrate (100).

[0131] FIG. 7 is a rear perspective view showing a light-emitting display device according to one embodiment of the present specification.

[0132] Referring to FIGS. 1, 4, and 7, a light-emitting display device according to one embodiment of the present specification may further include a first pad portion (210) disposed on the rear (or back) surface (100b) of a substrate (100).

[0133] The first pad portion (210) may be placed on one edge portion (or the first rear edge portion) of the rear surface (100b) of the substrate (100) that overlaps with the contact pattern portion (110) placed on the front surface (100a) of the substrate (100).

[0134] The first pad portion (210) may include a plurality of first pads (or routing pads) that are arranged at regular intervals along the first direction (X) and overlap each of the contact pads of the contact pattern portion (110).

[0135] A first pad portion (210) according to one embodiment may include first pixel driving power pads that overlap with each of the pixel driving power contact patterns (PCP), first data pads that overlap with each of the data contact patterns (DCP), first reference power pads that overlap with each of the reference voltage contact patterns (RCP), first gate pads that overlap with each of the gate contact patterns (GCP), and first pixel common voltage pads that overlap with each of the pixel common voltage contact patterns (CCP).

[0136] A light-emitting display device according to one embodiment of the present specification may further include a second pad portion (230) and a link line portion (250) disposed on the rear surface (100b) of a substrate (100).

[0137] The second pad portion (or input pad portion) (230) may be disposed on the rear surface (100b) of the substrate (100). For example, the second pad portion (230) may be disposed on an intermediate portion adjacent to one edge portion of the rear surface (100b) of the substrate (100). According to one embodiment, the second pad portion (230) may include a plurality of second pads (or input pads) spaced apart from each other to have a constant spacing. For example, the second pad portion (230) may include second pixel driving power pads, second data pads, second reference power pads, second gate pads, and second pixel common voltage pads.

[0138] The link line section (250) may include a plurality of link lines arranged between the first pad section (210) and the second pad section (230).

[0139] A link line section (250) according to one embodiment may include pixel driving power link lines connecting the first pixel driving power pads and the second pixel driving power pads individually (or one-to-one), data link lines connecting the first data pads and the second data pads individually (or one-to-one), reference power link lines connecting the first reference power pads and the second reference power pads individually (or one-to-one), gate link lines connecting the first gate pads and the second gate pads individually (or one-to-one), and a pixel common voltage link line connecting the first pixel common voltage pads and the second pixel common voltage pads.

[0140] The pixel common voltage link line may include a first common link line (251) disposed between the first pad portion (210) and the second pad portion (230) and commonly connected to the first pixel common voltage pads, and a second common link line (253) commonly connected to the second pixel common voltage pads and electrically connected to the first common link line (251). The second common link line (253) may be disposed on a different layer from the first common link line (251) and electrically connected to the first common link line (251) through a via hole. The size of the second common link line (253) may gradually increase from the second pad portion (230) toward the edge portion of the substrate (100) in order to minimize the voltage drop of the pixel common voltage.

[0141] The routing section (400) may be arranged to surround the contact pattern section (110), the outer surface (OS), and the second pad section (210) of the substrate (100). According to one embodiment, the routing section (400) may include a plurality of routing lines (410). Each of the plurality of routing lines (410) is arranged at regular intervals along a first direction (X) and formed to surround the contact pattern section (110), the outer surface (OS), and the first pad section (210) of the substrate (100), and may be electrically connected one-to-one to the contact pattern section (110) and the first pad section (210). According to one embodiment, each of the plurality of routing lines (410) may be formed by a printing process using a conductive paste. According to another embodiment, each of the plurality of routing lines (410) may be formed by a transfer process in which a conductive paste pattern is transferred to a transfer pad made of a flexible material. For example, the conductive paste may include silver (Ag) paste, but is not limited thereto.

[0142] Each of the plurality of routing lines (410) can pass through an encapsulation layer disposed on the edge portion of the substrate (100) and be electrically connected to the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern portion (110). Additionally, each of the plurality of routing lines (410) can be electrically connected to the pads disposed on the first pad portion (210).

[0143] A plurality of routing lines (410) according to one embodiment may be classified (or distinguished) into pixel power routing lines (411), data routing lines (413), reference voltage routing lines (415), gate routing lines (417), and pixel common voltage routing lines (419).

[0144] Each of the pixel power routing lines (411) is formed to surround the contact pattern portion (110) and the outer surface (OS) and the first pad portion (210) of the substrate (100), and can be electrically connected one-to-one with the pixel driving power contact patterns (PCP) of the contact pattern portion (110) and the first pixel driving power pads of the first pad portion (210).

[0145] Each of the data routing lines (413) is formed to wrap around the contact pattern portion (110) and the outer surface (OS) and the first pad portion (210) of the substrate (100), and can be electrically connected one-to-one with the data contact patterns (DCP) of the contact pattern portion (110) and the first data pads of the first pad portion (210).

[0146] Each of the reference voltage routing lines (415) is formed to surround the contact pattern portion (110) and the outer surface (OS) and the first pad portion (210) of the substrate (100), and can be electrically connected one-to-one to the reference voltage contact pattern (RCP) of the contact pattern portion (110) and the first reference power pads of the first pad portion (210).

[0147] Each of the gate routing lines (417) is formed to wrap around the contact pattern portion (110), the outer surface (OS), and the first pad portion (210) of the substrate (100), and can be electrically connected one-to-one to the gate contact patterns (GCP) of the contact pattern portion (110) and the first gate pads of the first pad portion (210).

[0148] Each of the pixel common voltage routing lines (419) is formed to surround the contact pattern portion (110) and the outer surface (OS) and the first pad portion (210) of the substrate (100), and can be electrically connected one-to-one to the pixel common voltage contact patterns (CCP) of the contact pattern portion (110) and the first pixel common voltage pads of the first pad portion (210).

[0149] A light-emitting display device according to one embodiment of the present specification may further include a driving circuit (500).

[0150] The driving circuit (500) can display an image corresponding to the image data on the display unit (AA) by driving (or emitting light) pixels (P) placed on the substrate (100) based on digital image data supplied from the display driving system and a synchronization signal. The driving circuit (500) is connected to a second pad unit (230) placed on the rear surface (100b) of the substrate (100) and can output a data signal, a gate control signal, and a driving power supply to the second pad unit (230) for driving (or emitting light) pixels (P) placed on the substrate (100).

[0151] A driving circuit section (500) according to one embodiment may include a flexible circuit film (510), a driving integrated circuit (530), a printed circuit board (550), a timing controller (570), and a power circuit section (590).

[0152] The flexible circuit film (510) can be connected to a second pad portion (230) placed on the rear surface (100b) of the substrate (100).

[0153] The driving integrated circuit (530) is mounted on the flexible circuit film (510). The driving integrated circuit (530) receives subpixel data and a data control signal provided by the timing controller (570), and can convert the subpixel data into an analog data signal according to the data control signal and output it. The data signal can be supplied to the third data pads placed on the second pad section (230) through the flexible circuit film (510).

[0154] The driving integrated circuit (530) can sense the characteristic value of a driving thin-film transistor placed in a subpixel (SP) through a plurality of reference power lines (RL) placed on the substrate (100), and generate sensing raw data for each subpixel corresponding to the sensing value for each subpixel and provide it to the timing controller (570). For example, the light-emitting display device according to the present specification can sense the characteristic value of a driving TFT placed in each subpixel (SP) through a sensing mode disclosed in Korean Published Patent Application No. 10-2016-0093179, No. 10-2017-0054654, or No. 10-2018-0002099, so a description thereof is omitted.

[0155] The printed circuit board (550) can be connected to the other edge portion of the flexible circuit film (510). The printed circuit board (550) serves to transmit signals and power between the components of the driving circuit portion (500).

[0156] The timing controller (570) is mounted on the printed circuit board (550) and receives digital image data and timing synchronization signals provided from the display driving system through a user connector placed on the printed circuit board (550). Alternatively, the timing controller (570) may not be mounted on the printed circuit board (550) but may be implemented in the display driving system or mounted on a separate control board connected between the printed circuit board (550) and the display driving system.

[0157] The timing controller (570) generates pixel data by aligning digital image data to fit the pixel array structure placed on the display unit (AA) based on the timing synchronization signal, and provides the generated pixel data to the driving integrated circuit (530).

[0158] The timing controller (570) generates a data control signal and a gate control signal, respectively, based on a timing synchronization signal, controls the driving timing of the driving integrated circuit (530) through the data control signal, and controls the driving timing of the gate driving circuit (150) through the gate control signal.

[0159] A data control signal according to one embodiment may include a source start pulse, a source shift clock, and a source output signal, etc. A gate control signal according to one embodiment may include a start signal (or gate start pulse), a plurality of shift clocks, a forward driving signal, and a reverse driving signal. The gate control signal may be supplied to third gate pads disposed in the second pad portion (230) through a flexible circuit film (510).

[0160] The power circuit section (590) is mounted on a printed circuit board (550) and generates various power voltages required to display an image on pixels (P) using an input power supplied from the outside, and provides them to the corresponding circuit. For example, the power circuit section (590) can generate and output a logic power voltage required for driving each of the timing controller (570) and the driving integrated circuit (530), a plurality of reference gamma voltages provided to the driving integrated circuit (530), at least one gate driving power and at least one gate common power required for driving the gate driving circuit (150). Additionally, the power circuit section (590) can generate and output a pixel driving power and a pixel common voltage, but is not limited thereto. For example, the driving integrated circuit (530) can generate and output a pixel driving power and a pixel common voltage, respectively, based on a plurality of reference gamma voltages.

[0161] FIG. 8 is a rear perspective view showing a light-emitting display device according to another embodiment of the present specification, which additionally comprises a wiring board in addition to the light-emitting display device shown in FIG. 1 to FIG. 7.

[0162] Referring to FIG. 8, a light-emitting display device according to another embodiment of the present specification may include a first substrate (100), a second substrate (200), a coupling member (300), and a routing part (400).

[0163] The first substrate (100) may be represented as a display substrate, a pixel array substrate, an upper substrate, a front substrate, or a base substrate. The first substrate (100) may be a glass substrate, a thin glass substrate that can be bent or curved, or a plastic substrate.

[0164] Since the first substrate (100) is substantially the same as the substrate (100) of the light-emitting display device shown in FIGS. 1 to 7, the same reference numeral is given to it, and a redundant description thereof is omitted.

[0165] The second substrate (200) may be represented as a wiring substrate, a link substrate, a bottom substrate, a rear substrate, or a link glass. The second substrate (200) may be a glass substrate, a thin glass substrate that can be bent or curved, or a plastic substrate. For example, the second substrate (200) may be made of the same material as the first substrate (100). The second substrate (200) may have the same size as the first substrate (100), but is not limited thereto, and may have a smaller size than the first substrate (100). For example, it may be preferable for the second substrate (200) to have the same size as the first substrate (100) in order to maintain or secure the rigidity of the first substrate (100).

[0166] The second substrate (200) may include a first pad portion (210), a second pad portion (230), and a link line portion (250). Since each of the first pad portion (210), the second pad portion (230), and the link line portion (250) is substantially identical to the first pad portion (210), the second pad portion (230), and the link line portion (250) described in FIG. 7, except that they are placed on the rear (or back) (200b) of the second substrate (200), the same reference numerals are assigned to them, and redundant descriptions thereof are omitted.

[0167] The second substrate (200) can be joined (or connected) to the second surface (100b) of the first substrate (100) via a joining member (300). The joining member (300) is interposed between the first substrate (100) and the second substrate (200). Accordingly, the first substrate (100) and the second substrate (200) can be joined to each other via the joining member (300).

[0168] The routing section (400) may be described as a side routing section or a printing line section. The routing section (400) is arranged to surround the outer surface (OS1a) of the first substrate (100) and the outer surface (OS1b) of the second substrate (200). According to one embodiment, the routing section (400) may include a plurality of routing lines (410) arranged on each of the first outer surface (or one side) (OS1a) of the outer surface (OS) of the first substrate (100) and the first outer surface (or one side) (OS1b) of the outer surface (OS) of the second substrate (200). Since this routing section (400) is substantially the same as the routing section (400) described in FIG. 7, except that each of the plurality of routing lines (410) is arranged to surround the contact pattern section (110) of the first substrate (100) and the first outer surface (OS1a), and the first pad section (210) of the second substrate (200) and the first outer surface (OS1b), the same reference numerals are assigned to it, and a redundant description thereof is omitted.

[0169] A light-emitting display device according to another embodiment of the present specification may further include a driving circuit (500).

[0170] The driving circuit section (500) may include a flexible circuit film (510), a driving integrated circuit (530), a printed circuit board (550), a timing controller (570), and a power circuit section (590). Since this driving circuit section (500) is substantially the same as the driving circuit section (500) described in FIG. 7, except that the flexible circuit film (510) is connected to a second pad section (230) disposed on the rear surface (200b) of the second substrate (200), the same reference numerals are assigned to it, and a redundant description thereof is omitted.

[0171] FIG. 9 is a diagram illustrating a connection structure between a pixel driving line and a routing unit according to an embodiment of the present specification, FIG. 10 is a cross-sectional view of line I-I' shown in FIG. 9, FIG. 11 is an enlarged view of part 'B2' shown in FIG. 10, and FIG. 12 is an enlarged view of part 'B3' shown in FIG. 10. In describing FIG. 9 to FIG. 12, the same reference numerals are assigned to components that are identical to or correspond to the components of FIG. 1 to FIG. 8, and redundant descriptions thereof are omitted or simplified.

[0172] Referring to FIGS. 4, FIGS. 9, FIGS. 10, and FIGS. 11, a light-emitting display device according to one embodiment of the present specification may include a first substrate (100).

[0173] The first substrate (100) may include a display portion (AA) comprising a first region and a second region surrounding the first region. The second region of the substrate (100) may be an edge portion of the substrate (100) or an edge portion of the outermost pixels. The first region of the substrate (100) may be the remaining portion excluding the second region.

[0174] The first substrate (100) may include a circuit layer (111), a flattening layer (112), a light-emitting element layer (113), a bank (114), a disconnection portion (115), a dam portion (117), and an encapsulation layer (119).

[0175] The circuit layer (111) may be disposed on the front surface (100a) of the first substrate (100). The circuit layer (111) may also be represented as a pixel array layer or a TFT array layer.

[0176] A circuit layer (111) according to one embodiment may include a buffer layer (111a) and a circuit array layer (111b).

[0177] The buffer layer (111a) serves to block substances such as hydrogen contained in the first substrate (100) from diffusing into the circuit array layer (111b) during the high-temperature process in the manufacturing process of the TFT. Additionally, the buffer layer (111a) can also serve to prevent external moisture or humidity from penetrating toward the light-emitting element layer (113). According to one embodiment, the buffer layer (111a) may include a first buffer layer (BL1) of silicon nitride (SiNx) disposed on the front surface (100a) of the first substrate (100), and a second buffer layer (BL2) of silicon oxide (SiOx) disposed on the first buffer layer (BL1). This buffer layer (111a) may be covered by at least one insulating layer.

[0178] The circuit array layer (111b) may include a pixel circuit (PC) having a driving TFT (Tdr) disposed in each pixel area (PA) on the buffer layer (111a).

[0179] A driving TFT (Tdr) placed in the circuit area (CA) of each pixel area (PA) may include an active layer (ACT), a gate insulating film (GI), a gate electrode (GE), an interlayer insulating layer (111c), a first source / drain electrode (SD1), a second source / drain electrode (SD2), and a passivation layer (111d).

[0180] The active layer (ACT) may be placed on the buffer layer (111a) on each pixel area (PA). The active layer (ACT) may include a channel area that overlaps with the gate electrode (GE), and a first source / drain area and a second source / drain area that are parallel to each other with the channel area in between. The active layer (ACT) may be used as a bridge line of a jumping structure that directly connects lines within the display (AA) or electrically connects lines placed on different layers by being conductive through a conductive process.

[0181] A gate insulating film (GI) can be placed on the channel region of the active layer (ACT). The gate insulating film (GI) functions to insulate the active layer (ACT) from the gate electrode (GE).

[0182] The gate electrode (GE) is placed on the gate insulating film (GI) and can be connected to the gate line. The gate electrode (GE) can overlap with the channel region of the active layer (ACT) with the gate insulating film (GI) in between.

[0183] An interlayer insulating layer (111c) may be disposed on the first substrate (100) to cover the gate electrode (GE) and the active layer (ACT). The interlayer insulating layer (111c) functions to electrically insulate (or separate) the gate electrode (GE) and the source / drain electrodes (SD1, SD2). For example, the interlayer insulating layer (111c) may be represented as an insulating layer or a first insulating layer.

[0184] The first source / drain electrode (SD1) is disposed on an interlayer insulating layer (111c) that overlaps with the first source / drain region of the active layer (ACL), and can be electrically connected to the first source / drain region of the active layer (ACL) through a first source / drain contact hole disposed in the interlayer insulating layer (11c). For example, the first source / drain electrode (SD1) is the source electrode of a driving TFT (Tdr), and the first source / drain region of the active layer (ACL) may be the source region.

[0185] The second source / drain electrode (SD2) is disposed on an interlayer insulating layer (11c) that overlaps with the second source / drain region of the active layer (ACL), and can be electrically connected to the second source / drain region of the active layer (ACL) through a second source / drain contact hole disposed in the interlayer insulating layer (111c). For example, the second source / drain electrode (SD2) is the drain electrode of the driving TFT (Tdr), and the second source / drain region of the active layer (ACL) may be the drain region.

[0186] According to one embodiment, the source / drain electrode (SD1, SD2) may have an electrode material that is used as a signal line extending along a first direction (X) on a first substrate (100). For example, the source / drain electrode (SD1, SD2) may be implemented together with a gate line (GL).

[0187] A passivation layer (111d) may be disposed on a first substrate (100) to cover a pixel circuit (PC) including a driving TFT (Tdr). According to one embodiment, the passivation layer (11d) may be a silicon oxide film (SiOx), a silicon nitride film (SiNx), a silicon oxynitride film (SiON), or a multilayer thereof, but is not necessarily limited thereto. The passivation layer (111d) may be represented as a protective layer or a second insulating layer.

[0188] Each of the first and second switching TFTs (Tsw1, Tsw2) constituting the pixel circuit (PC) is formed together with the driving TFT (Tdr), so a description thereof is omitted.

[0189] A circuit layer (111) according to one embodiment may further include a lower metal layer (BML) disposed between the first substrate (100) and the buffer layer (111a).

[0190] The lower metal layer (BML) may further include a light-blocking pattern (LSP) placed below the active layer (ACT) of the TFTs (Tdr, Tsw1, Tsw2) constituting the pixel circuit (PC).

[0191] The light-blocking pattern (LSP) can be arranged in an island shape between the first substrate (100) and the active layer (ACT). The light-blocking pattern (LSP) blocks light incident on the active layer (ACT) through the first substrate (100), thereby minimizing or preventing changes in the threshold voltage of the TFT caused by external light. Optionally, the light-blocking pattern (LSP) may be electrically connected to the first source / drain electrode (SD1) of the TFT to serve as the lower gate electrode of the corresponding TFT, in which case changes in the threshold voltage of the TFT due to bias voltage as well as changes in characteristics due to light can be minimized or prevented.

[0192] The lower metal layer (BML) can be used as a metal layer to implement pixel driving lines (PL, DL, RL, GCL, CVL) that are spaced apart from each other along the first direction (X) and extend along the second direction (Y) on the first substrate (100). Additionally, the lower metal layer (BML) can be used as a metal layer to implement contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern portion (110).

[0193] According to one embodiment, the lower metal layer (BML) is deposited on the front surface (100a) of the first substrate (100) and then can be patterned by a patterning process into a light-blocking pattern (LSP), pixel driving power lines (PL), data lines (DL), reference voltage lines (RL), gate control lines (GCL), pixel common voltage lines (CVL), and contact patterns (PCP, DCP, RCP, GCP, CCP), respectively.

[0194] A flattening layer (112) may be disposed on a first substrate (100) and may provide a flat surface on a circuit layer (111). The flattening layer (112) covers a circuit layer (111) including a driving TFT (Tdr) disposed in each pixel area (PA). A flattening layer (112) according to one embodiment may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin, but is not limited thereto.

[0195] According to one embodiment, the flattening layer (112) may be formed to cover the circuit layer (111) excluding the edge portion of the first substrate (100). Accordingly, the passivation layer (111d) of the circuit layer (111) disposed at the edge portion of the first substrate (100) may be exposed without being covered by the flattening layer (112).

[0196] The light-emitting element layer (113) may be disposed on the planarization layer (112). The light-emitting element layer (113) according to one embodiment may include a pixel electrode (PE), a light-emitting layer (EL), and a common electrode (CE).

[0197] The pixel electrode (PE) may also be represented as an anode electrode, a reflective electrode, a bottom electrode, or a first electrode.

[0198] A pixel electrode (PE) can be placed on a flattening layer (112) that overlaps with the light-emitting region (EA) of each pixel region (PA). The pixel electrode (PE) is patterned in an island shape and placed within each pixel region (PA), and can be electrically connected to the first source / drain electrode (SD1) of the driving TFT (Tdr) of the corresponding pixel circuit (PC). One side of the pixel electrode (PE) can be electrically connected to the first source / drain electrode (SD1) of the driving TFT (Tdr) through an electrode contact hole (ECH) provided in the flattening layer (112).

[0199] The pixel electrode (PE) may include a metal material having a low work function and excellent reflection efficiency, but is not limited thereto.

[0200] A pixel electrode (PE) according to one embodiment may have a two-layer structure comprising a first pixel electrode layer (PEL1) (or a first metal layer) and a second pixel electrode layer (PEL2) (or a second metal layer). The first and second pixel electrode layers (PEL1, PEL2) may be sequentially deposited on a planarization layer (112) and then simultaneously patterned.

[0201] The first pixel electrode layer (PEL1) may be placed on the planarization layer (102). The second pixel electrode layer (PEL2) may be placed (or laminated) on the first pixel electrode layer (PEL1). For example, the first pixel electrode layer (PEL1) may serve as an adhesive layer with the planarization layer (102) and as an auxiliary electrode for the self-emissive element (ED), and may be made of ITO or IZO material, but is not limited thereto. For example, the second pixel electrode layer (PEL2) may serve as a reflector and as a component that reduces the resistance of the pixel electrode (PE), and may be made of one of aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and molybdenum titanium alloy (MoTi), but is not limited thereto. For example, a pixel electrode (PE) according to one example may be composed of a two-layer structure of ITO / MoTi or a two-layer structure of MoTi / ITO.

[0202] A pixel electrode (PE) according to another embodiment may have a three-layer structure comprising a first pixel electrode layer (PEL1), a second pixel electrode layer (PEL2) on the first pixel electrode layer (PEL1), and a third pixel electrode layer (or a third metal layer) on the second pixel electrode layer (PEL2). For example, the third pixel electrode layer serves as an electrode for the light-emitting layer (EL) and may be made of ITO or IZO material. For example, a pixel electrode (PE) according to another example may have a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0203] A pixel electrode (PE) according to another embodiment may have a four-layer structure comprising a first pixel electrode layer (PEL1), a second pixel electrode layer (PEL2) on the first pixel electrode layer (PEL1), a third pixel electrode layer (or a third metal layer) on the second pixel electrode layer (PEL2), and a fourth pixel electrode layer (or a fourth metal layer) on the third pixel electrode layer.

[0204] In a pixel electrode (PE) with a four-layer structure, the first pixel electrode layer can serve as an adhesive layer with the planarization layer (112) and as an auxiliary electrode for the light-emitting layer (EL), and can be made of one of ITO, molybdenum (Mo), and molybdenum titanium alloy (MoTi). The second pixel electrode layer can serve to reduce the resistance of the pixel electrode (PE) and can be made of copper (Cu). The third pixel electrode layer can serve as a reflector and can be made of one of aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and molybdenum titanium alloy (MoTi). The fourth pixel electrode layer can serve as an electrode for the light-emitting layer (EL) and can be made of ITO or IZO. For example, a pixel electrode (PE) according to another embodiment can be made of a four-layer structure of ITO / Cu / MoTi / ITO.

[0205] According to another example, the pixel electrode (PE) may be composed of a 5-layer structure including a first pixel electrode layer made of ITO, a second pixel electrode layer made of molybdenum titanium alloy (MoTi), a third pixel electrode layer made of ITO, a fourth pixel electrode layer made of silver (Ag), and a fifth pixel electrode layer made of ITO.

[0206] The light-emitting layer (EL) may be disposed on a first region of the substrate (100) and may be disposed on a part of a second region of the first substrate (100). The light-emitting layer (EL) may be formed on a pixel electrode (PE) and may be in direct contact with the pixel electrode (PE). The pixel electrode (PE) may be disposed below the light-emitting layer (EL). For example, the pixel electrode (PE) may be disposed between the planarization layer (112) and the light-emitting layer (EL).

[0207] According to one embodiment, the light-emitting layer (EL) may be a common layer formed commonly across subpixels without being separated by subpixel. The light-emitting layer (EL) may emit white light (or blue light) in response to the current flowing between the pixel electrode (PE) and the common electrode (CE). According to one embodiment, the light-emitting layer (EL) may include an organic light-emitting layer, or may include a stacked or mixed structure of an organic light-emitting layer and a quantum dot light-emitting layer.

[0208] A light-emitting layer (EL) according to one embodiment may include two or more organic light-emitting layers for emitting white light. For example, the light-emitting layer (EL) may include a first organic light-emitting layer and a second organic light-emitting layer for emitting white light by mixing a first light and a second light. Here, the first organic light-emitting layer may include at least one of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting layer may include at least one light-emitting layer for emitting a second light that can be mixed with a first light emitted from the first organic light-emitting layer to produce white light, among the blue light-emitting layer, the green light-emitting layer, the red light-emitting layer, the yellow light-emitting layer, and the yellow-green light-emitting layer.

[0209] An organic light-emitting layer according to one embodiment may further include at least one functional layer to improve light emission efficiency and / or lifespan, etc. For example, the organic light-emitting layer may be interposed between a hole functional layer and an electronic functional layer.

[0210] The common electrode (CE) can be represented as a cathode electrode, a transparent electrode, an upper electrode, a negative electrode, or a second electrode. The common electrode (CE) is formed on the light-emitting layer (EL) and can be in direct contact with the light-emitting element layer or in direct electrical contact. The common electrode (CE) may include a transparent conductive material so that light emitted from the light-emitting layer (EL) can be transmitted.

[0211] A common electrode (CE) according to one embodiment may be composed of at least one single-layer or multi-layer structure of a transparent conductive material having a relatively high work function or graphene. For example, the common electrode (CE) may be composed of a metal oxide such as ITO or IZO, or a mixture of a metal and an oxide such as ZnO:Al or SnO2:Sb.

[0212] Additionally, the light-emitting element layer (113) may further include a capping layer disposed on the common electrode (CE). The capping layer is disposed on the common electrode (CE) and can improve the light emission efficiency by controlling the refractive index of the light emitted from the light-emitting layer (EL).

[0213] A bank (114) may be placed on a flattening layer (112) and may define a pixel region (PA) on a first substrate (100). A bank (114) may be placed on the flattening layer (112) to cover the edge portions of a pixel electrode (PE). A bank (114) defines a light-emitting region (or opening) (EA) of each subpixel and may electrically isolate the pixel electrode (PE) placed on adjacent subpixels. A bank (114) may be formed to cover an electrode contact hole (ECH) placed in each pixel region (PA). A bank (114) may be covered by a light-emitting layer (EL) of a light-emitting element layer (113). For example, the light-emitting layer (EL) may be placed on the bank (114) as well as on the pixel electrode (PE) of each subpixel (SP).

[0214] A bank (114) according to one embodiment may be a transparent bank made of a transparent material or a black bank containing black pigment.

[0215] Referring to FIGS. 4, 9, 10, and 12, a disconnection portion (115) according to one embodiment of the present specification may be disposed on a second region of a first substrate (100). The disconnection portion (115) may be disposed on an edge portion of the first substrate (100) or on an edge portion of the outermost pixels (Po) so as to have a closed-loop shape (or a closed-loop line shape) that surrounds the display portion (AA) planarly. The disconnection portion (115) may be implemented on a buffer layer (111a) or an interlayer insulating layer (111c) at an edge portion of the first substrate (100). For example, the interlayer insulating layer (111c) may be disposed on the remaining portion excluding the edge portion of the first substrate (100), in which case the disconnection portion (115) may be implemented on the buffer layer (111a).

[0216] A disconnection portion (115) according to one embodiment may be implemented to disconnect (or separate) a light-emitting element layer (113) disposed on a second region of a first substrate (100) at least once. Accordingly, the disconnection portion (115) may be expressed as a separation portion, a separation line portion, a disconnection portion, or a disconnection line portion.

[0217] A disconnection section (115) according to one embodiment may include at least one disconnection structure (115a, 115b, 115c, 115d) having a closed-loop line shape. For example, when the disconnection section (115) has a plurality of disconnection structures (115a, 115b, 115c, 115d), the disconnection section (115) may include an external disconnection section disposed around the outer side of the dam section (117), and an internal disconnection section disposed around the inner side of the dam section (117). According to one embodiment, the disconnection portion (115) may include first to fourth disconnection structures (115a, 115b, 115c, 115d), wherein the outer disconnection portion may include first to third disconnection structures (115a, 115b, 115c) and the inner disconnection portion may include the fourth disconnection structure (115d). For example, the first to third disconnection structures (115a, 115b, 115c) may be represented as a plurality of outer disconnection structures, and the fourth disconnection structure (115d) may be represented as at least one inner disconnection structure.

[0218] Each of the first to fourth disconnected structures (115a, 115b, 115c, 115d) according to the above may include a first trench structure (TS1) and a second trench structure (TS2).

[0219] A first trench structure (TS1) according to one embodiment may be implemented as a stacked structure of an interlayer insulating layer (111c) and a passivation layer (111d). The first trench structure (TS1) may be formed by a patterning process of the interlayer insulating layer (111c) and the passivation layer (111d) disposed in a second region of the first substrate (100). For example, the first trench structure (TS1) may be expressed by terms such as a first structure, a first separation structure, a first tapered structure, or a substructure.

[0220] According to one embodiment, the side of the first trench structure (TS1) may be implemented as an inclined structure or a regular taper structure. The bottom surface of the first trench structure (TS1) may be in direct contact with the top surface (or surface) of the buffer layer (111a), and the top surface of the first trench structure (TS1) may be positioned on the bottom surface of the first trench structure (TS1) and may have a narrower width than the bottom surface. The side of the first trench structure (TS1) may be formed at an angle between the top surface and the bottom surface. In the first trench structure (TS1), the angle between the bottom surface and the side may be an acute angle, and the angle between the top surface and the side may be an obtuse angle. For example, the cross-section of the first trench structure (TS1) cut along the width direction may have a trapezoidal cross-sectional structure in which the top side is narrower than the bottom side.

[0221] According to another embodiment, the first trench structure (TS1) may be implemented with only the passivation layer (111d) when the interlayer insulating layer (111c) is not placed at the edge portion of the first substrate (100). The first trench structure (TS1) may be formed by a patterning process of the passivation layer (111d) placed in the second region of the first substrate (100).

[0222] The second trench structure (TS2) may be placed on the first trench structure (TS1). For example, the second trench structure (TS2) may be referred to by terms such as a second structure, a second separation structure, a second tapered structure, or a superstructure.

[0223] The second trench structure (TS2) may have a width greater than the top surface of the first trench structure (TS1). The second trench structure (TS2) may have a width equal to or greater than the bottom surface of the first trench structure (TS1). For example, the side of the second trench structure (TS2) may be implemented as a slanted structure or a regular taper structure. For example, the second trench structure (TS2) cut along the width direction may have a trapezoidal cross-sectional structure identical to that of the first trench structure (TS1). Based on the width direction, one edge portion and the other edge portion of the second trench structure (TS2) may each protrude outside the side of the first trench structure (TS1).

[0224] The second trench structure (TS2) may include an organic material. According to one embodiment, the second trench structure (TS2) may be made of the same material as the bank (114), but is not limited thereto. For example, the second trench structure (TS2) may be implemented with the bank material remaining on the first trench structure (TS1) without being patterned (or removed) during the patterning process of the bank material. The second trench structure (TS2) may be implemented with the same height (or thickness) as the bank (114).

[0225] The side of the first trench structure (TS1) may have an undercut structure with respect to the second trench structure (TS2). For example, the cut portion (115) may include a boundary portion between the first trench structure (TS1) and the second trench structure (TS2) or an undercut area located on the upper side of the first trench structure (TS1). The second trench structure (TS2) may cover the side of the first trench structure (TS1) by protruding outside the side of the first trench structure (TS1) due to the undercut structure of the first trench structure (TS1). Accordingly, the second trench structure (TS2) may have an eaves structure with respect to the first trench structure (TS1).

[0226] A disconnection section (115) comprising first to fourth disconnection structures (115a, 115b, 115c, 115d) according to one embodiment can disconnect (or separate) the light-emitting layer (EL) or disconnect (or separate) the light-emitting layer (EL) and the common electrode (CE). For example, the light-emitting layer (EL) formed (or deposited) on the disconnection section (115) can be automatically disconnected (or separated) during the deposition process by the undercut structure (or eaves structure) of each of the first to fourth disconnection structures (115a, 115b, 115c, 115d) without a separate disconnection process. Accordingly, the light-emitting layer (EL) disposed on the first substrate (100) can be disconnected (or separated) four times in the second region of the first substrate (100) and may include four disconnection regions (or separation regions). For example, since the deposition material of the light-emitting layer (EL) has directional properties, it is not deposited on the side of the first trench structure (TS1) that is obscured by the second trench structure (TS2) according to the undercut structure (or eaves structure) of each of the first to fourth disconnect structures (115a, 115b, 115c, 115d). Accordingly, the light-emitting layer (EL) formed (or deposited) on the first to fourth disconnect structures (115a, 115b, 115c, 115d) can be disconnected (or separated) between the first trench structure (TS1) and the second trench structure (TS2). Accordingly, the light-emitting layer (EL) can be automatically cut (or separated) by the first to fourth cut structures (115a, 115b, 115c, 115d) of the cut portion (115) during the deposition process, and thus a separate patterning process for cutting (or disconnecting) the light-emitting layer (EL) placed at the edge portion of the first substrate (100) to prevent lateral moisture penetration can be omitted.

[0227] Optionally, the common electrode (CE) placed on the light-emitting layer (EL) may be automatically disconnected (or separated) by the first to fourth disconnected structures (115a, 115b, 115c, 115d) of the disconnected portion (115) during the deposition process according to the deposition method, or may be formed so as to be continuously connected without a disconnected area by being deposited on the side of the first trench structure (TS1) which is covered by the second trench structure (TS2).

[0228] The dam portion (117) may be disposed on the circuit layer (111) to have a closed-loop line shape on the second region of the first substrate (100). According to one embodiment, the dam portion (117) may be disposed on the passivation (111d) of the circuit layer (111). For example, the dam portion (117) may be surrounded by a disconnect portion (115). For example, the dam portion (117) may be disposed between a third disconnect structure (115c) and a fourth disconnect structure (115d). The dam portion (117) may be surrounded by the third disconnect structure (115c) and may surround the fourth disconnect structure (115d). Such a dam portion (117) serves to block the spreading or overflow of the encapsulation layer (119).

[0229] According to one embodiment, the dam portion (117) may be formed of the same material as the flattening layer (112). The dam portion (117) may have the same height (or thickness) as the flattening layer (112) or may have a higher height than the flattening layer (112). For example, the height (or thickness) of the dam portion (117) may be twice the height (or thickness) of the flattening layer (112).

[0230] According to another embodiment, the dam portion (117) may include a first dam (or lower dam) (117a) formed of the same material as the flattening layer (112), and a second dam (or upper dam) (117b) laminated on the first dam (117a) with the same material as the bank (114). The first dam (117a) may have the same height (or thickness) as the flattening layer (112) or may have a higher height than the flattening layer (112). For example, the height (or thickness) of the first dam (117a) may be twice the height (or thickness) of the flattening layer (112).

[0231] An encapsulation layer (119) can be disposed on the light-emitting element layer (113). For example, the encapsulation layer (119) can be implemented to surround both the front surface and the lateral surfaces of the light-emitting element layer (113).

[0232] A bag layer (119) according to one embodiment may include first to third bag layers (119a, 119b, 119c).

[0233] The first encapsulation layer (119a) may be implemented to block oxygen or moisture from penetrating into the light-emitting element layer (113). The first encapsulation layer (119a) may be placed on the common electrode (CE) and surround the light-emitting element layer (113). Accordingly, both the front surface and the lateral surfaces of the light-emitting element layer (113) may be surrounded by the first encapsulation layer (119a). For example, the first encapsulation layer (119a) may prevent or minimize lateral moisture penetration by covering the boundary (or interface) between the common electrode (CE) and the passivation layer (111d) by being in direct contact with the upper surface of the passivation layer (111d) at each of the disconnection portion (115), the dam portion (117), and the outer portion of the disconnection portion (115). According to one embodiment, the first encapsulation layer (119a) may be made of an inorganic material. For example, the first encapsulation layer (119a) can be represented as the first inorganic encapsulation layer.

[0234] The second encapsulation layer (119b) may be implemented on the first encapsulation layer (119a) to have a thickness that is relatively thicker than that of the first encapsulation layer (119a). The second encapsulation layer (119b) may have a thickness sufficient to cover foreign substances (or unnecessary materials or unnecessary structures) that are present or may be present on the first encapsulation layer (119a). Due to its relatively thick thickness, this second encapsulation layer (119b) may spread to the edge portion of the first substrate (100), but the spreading of this second encapsulation layer (119b) may be blocked by the dam (117).

[0235] According to one embodiment, a second sealing layer (119b) may be placed on a first sealing layer (119a) and surrounded by a dam (117). The end of the second sealing layer (119b) may be in direct contact with the first sealing layer (119a) on the dam (117). Such a second sealing layer (119b) may be described as a foreign matter cover layer or an organic sealing layer. According to one embodiment, the second sealing layer (119b) may be made of an organic material such as silicon oxycarbon (SiOCz) acrylic or epoxy-based resin.

[0236] The third encapsulation layer (119c) may be implemented to primarily block oxygen or moisture from penetrating into the light-emitting element layer (113). The third encapsulation layer (119c) may be placed on the second encapsulation layer (119b) and the first encapsulation layer (119a) on the dam portion (117). The third encapsulation layer (119c) may be implemented to surround both the second encapsulation layer (119b) and the first encapsulation layer (119a) that is not covered by the second encapsulation layer (119b). For example, the second encapsulation layer (119b) may be interposed between the first encapsulation layer (119a) and the second encapsulation layer placed on the light-emitting element layer (113) surrounded by the dam portion (117). According to one embodiment, the third encapsulation layer (119c) may be made of an inorganic material. For example, the third encapsulation layer (119c) may be represented as a second inorganic encapsulation layer.

[0237] A first substrate (100) according to one embodiment may include a first margin region (MA1), a second margin region (MA2), and a dam region (DA) defined in a second region.

[0238] A first margin area (MA1) may be positioned between the light-emitting area (EA) of the outermost pixel (Po) and the damper (117). Based on the reliability margin of the light-emitting element layer (113) due to lateral moisture penetration, the first margin area (MA1) may have a first width between the end of the light-emitting area (EA) (or bank (114)) of the outermost pixel (Po) and the damper (117). Accordingly, the damper (117) may be implemented to be spaced apart from the end of the light-emitting area (EA) by a first width of the first margin area (MA1) with respect to the first direction (X).

[0239] A second margin area (MA2) may be positioned between the outer surface (OS) of the first substrate (100) and the damper (117). The second margin area (MA2) may have a second width between the outer surface (OS) of the first substrate (100) and the damper (117), based on the reliability margin of the light-emitting element layer (113) due to lateral moisture penetration. Accordingly, the damper (117) may be implemented to be spaced apart from the outer surface (OS) of the first substrate (100) by a second margin area (MA2) of a second width with respect to the first direction (X).

[0240] The dam area (DA) may be positioned between the first margin area (MA1) and the second margin area (MA2). The dam area (DA) may have a third width corresponding to the width of the lowest bottom surface (or lower surface) of the dam section (117).

[0241] Based on the first direction (X), the width of each of the first margin area (MA1), the second margin area (MA2), and the dam area (DA) can be implemented such that the second gap (D2) between the center of the outermost pixel (Po) and the outer surface (OS) of the first substrate (100) is less than or equal to half the pixel pitch.

[0242] A light-emitting display device according to one embodiment of the present specification may further include a wavelength conversion layer (121) disposed on a first substrate (100).

[0243] The wavelength conversion layer (121) converts the wavelength of light incident from the light-emitting region (EA) of each pixel region (PA). For example, the wavelength conversion layer (121) may convert white light (or blue light) incident from the light-emitting region (EA) into color light corresponding to a subpixel, or allow only color light corresponding to a subpixel to pass through. For example, the wavelength conversion layer (121) may include at least one of a wavelength conversion member and a color filter layer.

[0244] A wavelength conversion layer (121) according to one embodiment may include a plurality of wavelength conversion members (121a) and an overcoat layer (121b).

[0245] According to one embodiment, a plurality of wavelength conversion members (121a) may be disposed on an encapsulation layer (119) on a light-emitting region (EA) of each subpixel area. For example, the plurality of wavelength conversion members (121a) may have a size equal to or larger than the light-emitting region (EA) of each subpixel area.

[0246] An overcoat layer (or protective layer) (121b) may be implemented to cover the wavelength conversion members (121a) and provide a flat surface on the wavelength conversion members (121a). For example, the overcoat layer (121b) may be disposed to cover the wavelength conversion members (121a) and the encapsulation layer (119) on which the wavelength conversion members (121a) are not disposed. According to one embodiment, the overcoat layer (121b) may comprise an organic material. Optionally, the overcoat layer (121b) may further comprise a getter material capable of adsorbing moisture and / or oxygen.

[0247] Optionally, the wavelength conversion layer (121) according to one embodiment may further include a quantum dot member interposed between the wavelength conversion member (121a) and the encapsulation layer (119). The quantum dot member may be configured to re-emit light by white light or blue light incident from the light-emitting element layer (113) to re-emit color light set in the subpixel.

[0248] Alternatively, the wavelength conversion layer (121) may be changed to a wavelength conversion sheet having a sheet form and disposed on the encapsulation layer (119). In this case, the wavelength conversion sheet (or quantum dot sheet) may include wavelength conversion members (121a) interposed between a pair of films. The wavelength conversion members (121a) of the wavelength conversion sheet may include quantum dot members configured to re-emit light by white light or blue light incident from the light-emitting element layer (113) to re-emit color light set in the subpixel.

[0249] A substrate (100) according to one embodiment may further include a functional film (123).

[0250] A functional film (123) can be placed on a wavelength conversion layer (121). For example, the functional film (123) can be bonded to the wavelength conversion layer (121) via a transparent adhesive member (122).

[0251] A functional film (123) according to one embodiment may include an anti-reflection layer (or anti-reflection film) to prevent reflection of external light and improve outdoor visibility and contrast ratio for an image displayed on a display panel (10). For example, the anti-reflection layer may include a circularly polarized layer (or circularly polarized film) that blocks reflected light that is reflected by TFTs and / or pixel driving lines disposed on a first substrate (100) and travels outward again.

[0252] A functional film (123) according to one embodiment may further include a barrier layer (or barrier film) for primarily preventing moisture or oxygen penetration, and the barrier layer may be made of a material with low moisture permeability, for example, a polymer material.

[0253] A functional film (123) according to one embodiment may further include a light path control layer (or light path control film) that controls the path of light emitted outward from each pixel (P). The light path control layer may include a structure in which a high-refractive index layer and a low-refractive index layer are alternately stacked, thereby changing the path of light incident from each pixel (P) and minimizing the color shift phenomenon according to the viewing angle.

[0254] A substrate (100) according to one embodiment may further include a side sealing member (125).

[0255] The side sealing member (125) is formed between the substrate (100) and the functional film (123) and can cover all sides of the circuit layer (111), the flattening layer (112), and the wavelength conversion layer (121), respectively. That is, the side sealing member (125) can cover all sides of the circuit layer (111), the flattening layer (112), and the wavelength conversion layer (121), respectively, that are exposed to the outside of the display device between the functional film (123) and the substrate (100). For example, the outermost side of the substrate (100), the outer side of the side sealing member (125), and the outer side of the functional film (13) can each be located on the same vertical line (VL). A side sealing member (109) according to one embodiment may be made of a silicone-based or UV-curing sealing agent (or resin), but considering the process tack time, it is preferable to be made of a UV-curing sealing agent. In addition, the side sealing member (109) may be colored (e.g., blue, red, cyan, or black), but is not limited thereto, and it is preferable to be made of a colored resin or a light-blocking resin to prevent side light leakage. Optionally, the side sealing member (125) may further include a getter material capable of adsorbing moisture and / or oxygen.

[0256] A light-emitting display device according to one embodiment of the present specification may further include a second substrate (200) disposed on the rear surface of a first substrate (100).

[0257] The second substrate (200) may include a metal pattern layer and an insulating layer that insulates the metal pattern layer.

[0258] A metal pattern layer (or conductive pattern layer) may include a plurality of metal layers. A metal pattern layer according to one embodiment may include a first metal layer (201), a second metal layer (203), and a third metal layer. An insulating layer may include a plurality of insulating layers. For example, an insulating layer may include a first insulating layer (202), a second insulating layer (204), and a third insulating layer (206). An insulating layer may be described as a back insulating layer or a pattern insulating layer.

[0259] The first metal layer (201), the second metal layer (203), and the third metal layer can be used as pads (211) of the first pad portion (210), pads of the second pad portion (230), and link lines of the link line portion (250) disposed on the rear surface (200b) of the second substrate (200). For example, the first metal layer (201) can be used as a link line of some of the plurality of link lines, and the third metal layer can be used as the remaining link lines and pads (211) of the plurality of link lines. The second metal layer (203) can be used as a jumping line (or bridge line) for electrically connecting link lines disposed on different layers.

[0260] A first insulating layer (202) may be implemented on the rear surface (200b) of the second substrate (200) to cover the first metal layer (201). A second insulating layer (204) may be implemented on the rear surface (200b) of the second substrate (200) to cover the second metal layer (203). A third insulating layer (206) may be implemented on the rear surface (200b) of the second substrate (200) to cover the third metal layer.

[0261] The second substrate (200) can be coupled to the rear surface of the first substrate (100) via a coupling member (300).

[0262] A bonding member (300) is interposed between a first substrate (100) and a second substrate (200). According to one embodiment, the bonding member (300) may be a transparent adhesive member comprising an optically clear adhesive (OCA) or an optically clear resin (OCR), or a double-sided tape. According to another embodiment, the bonding member (300) may include glass fibers.

[0263] A coupling member (300) according to one embodiment may be disposed in the entire space between the first substrate (100) and the second substrate (200). For example, the entire rear surface of the first substrate (100) may be coupled to the entire one side of the coupling member (300), and the entire front surface of the second substrate (200) may be coupled to the entire other side of the coupling member (300).

[0264] A coupling member (300) according to another embodiment may be arranged in a pattern structure between a first substrate (100) and a second substrate (200). For example, the coupling member (300) may have an intermediate pattern structure or a mesh pattern structure. The mesh pattern structure may further include a vent portion through which bubbles generated between the first substrate (100) and the second substrate (200) during the bonding of the first substrate (100) and the second substrate (200) can be discharged to the outside.

[0265] A light-emitting display device according to one embodiment of the present specification may further include a routing unit (400).

[0266] The routing unit (400) can electrically connect the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern unit (110) disposed on one edge portion of the first substrate (100) and the pads (211) of the first pad unit (210) disposed on one edge portion of the second substrate (200) in a one-to-one manner. The routing unit (400) is implemented to wrap the contact pattern unit (110) of the first substrate (100) and the outer surface (OS1a), and the first pad unit (210) of the second substrate (200) and the outer surface (OS1a), thereby enabling the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern unit (110) and the pads (211) of the first pad unit (210) to be electrically directly connected (or connected). This routing portion (400) is positioned on one edge portion of the first and second substrates (100, 200) and is electrically directly connected to the contact pattern portion (110) through both the dam portion (117) or the disconnect portion (115) and the dam portion (117), thereby replacing (or substituting) the pad portion positioned on the outermost edge portion of the first substrate (100). Accordingly, the light-emitting display device according to the present specification does not require the pad portion positioned on the outermost edge portion of the first substrate (100), and thus can have an air bezel structure without a bezel area.

[0267] According to one embodiment, the routing section (400) can be electrically connected to the contact pattern section (110) through a routing contact hole (CH) that penetrates at least one of the dam section (117) and the disconnection section (115) disposed on the contact pattern section (110).

[0268] The routing section (400) according to the first example can be electrically connected to the contact pattern section (110) by passing through the third encapsulation layer (119c), the first encapsulation layer (119a), and the dam section (117) disposed on the contact pattern section (110). For example, the routing section (400) according to the first example can be electrically connected to the contact pattern section (110) through a routing contact hole (CH) that penetrates the dam section (117) disposed on the contact pattern section (110). For example, the routing section (400) according to the first example can be electrically connected to the contact pattern section (110) through a routing contact hole (CH) that sequentially penetrates the third encapsulation layer (119c), the first encapsulation layer (119a), the disconnected light-emitting element layer (113), the damping section (117), and the circuit layer (111) disposed on the contact pattern section (110).

[0269] The routing section (400) according to the second example can be electrically connected to the contact pattern section (110) by passing through the third encapsulation layer (119c), the first encapsulation layer (119a), and the disconnection section (115) disposed on the contact pattern section (110). For example, the routing section (400) according to the second example can be electrically connected to the contact pattern section (110) through a routing contact hole (CH) that penetrates the disconnection section (115) disposed on the contact pattern section (110). For example, the routing section (400) according to the second example can be electrically connected to the contact pattern section (110) through a routing contact hole (CH) that sequentially penetrates the third encapsulation layer (119c), the first encapsulation layer (119a), the disconnected light-emitting element layer (113), the disconnection section (115), and the circuit layer (111) disposed on the contact pattern section (110).

[0270] The routing section (400) according to the third example can be electrically connected to the contact pattern section (110) through a routing contact hole (CH) that penetrates each of the dam section (117) and the disconnection section (115) placed on the contact pattern section (110).

[0271] A routing contact hole (CH) can be implemented by at least one hole patterning process that patterns layers disposed on a contact pattern portion (110) of a first substrate (100) to expose at least a portion of a contact pattern (PCP, DCP, RCP, GCP, CCP). A routing contact hole (CH) according to one embodiment may include at least one first to fifth routing contact hole (CH1, CH2, CH3, CH4, CH5).

[0272] At least one first routing contact hole (CH1) may be implemented to penetrate the first disconnect structure (115a) of the disconnection section (115). At least one second routing contact hole (CH2) may be implemented to penetrate the second disconnect structure (115b) of the disconnection section (115). At least one third routing contact hole (CH3) may be implemented to penetrate the third disconnect structure (115c) of the disconnection section (115). At least one fourth routing contact hole (CH4) may be implemented to penetrate the fourth disconnect structure (115d) of the disconnection section (115). At least one fifth routing contact hole (CH5) may be implemented to penetrate the dam section (117).

[0273] At least one first to fourth routing contact hole (CH1, CH2, CH3, CH4) can be implemented to penetrate layers on a contact pattern portion (110) including each of the first to fourth disconnect structures (115a, 115b, 115c, 115d) of the disconnect portion (115) and a sealing layer (119). Each of at least one first to fourth routing contact hole (CH1, CH2, CH3, CH4) according to one embodiment may be implemented to sequentially penetrate an overcoat layer (121b), a second inorganic encapsulation layer (119c) and a first inorganic encapsulation layer (119b) of an encapsulation layer (119) disposed on a contact pattern portion (110) to expose at least a portion of the contact pattern (PCP, DCP, RCP, GCP, CCP) of the contact pattern portion (110), a disconnected common electrode (CEa) and an emitting layer (ELa) of an emitting element layer (113), disconnected structures (115a, 115b, 115c, 115d), and a buffer layer (111a). For example, at least one second routing contact hole (CH2) may be implemented to sequentially penetrate an overcoat layer (121b) disposed on a contact pattern portion (110) to expose at least a portion of a data contact pattern (DCP), a second inorganic encapsulation layer (119c) and a first inorganic encapsulation layer (119b) of an encapsulation layer (119), a disconnected common electrode (CEa) and an emitting layer (ELa) of an emitting element layer (113), disconnected structures (115a, 115b, 115c, 115d), and a buffer layer (111a).

[0274] At least one fifth routing contact hole (CH5) may be implemented to penetrate layers on a contact pattern portion (110) including a dam portion (117) and an encapsulation layer (119). According to one embodiment, at least one fifth routing contact hole (CH5) may be implemented to penetrate in sequence an overcoat layer (121b), a second inorganic encapsulation layer (119c) and a first inorganic encapsulation layer (119b) of an encapsulation layer (119) disposed on the contact pattern portion (110) to expose at least a portion of the contact pattern (PCP, DCP, RCP, GCP, CCP) of the contact pattern portion (110), a disconnected common electrode (CEa) and an emitting layer (ELa) of an emitting element layer (113), a dam portion (117), and a buffer layer (111a).

[0275] A routing section (400) according to one embodiment may include a plurality of routing lines (410). Each of the plurality of routing lines (410) may be arranged at regular intervals along a first direction (X) and may be implemented to surround the contact pattern section (110) and outer surface (OS1a) of the first substrate (100), and the first pad section (210) and outer surface (OS1b) of the second substrate (200). For example, each of the plurality of routing lines (410) may be formed by a printing method using a conductive paste. For example, the conductive paste may include silver (Ag) paste, but is not limited thereto.

[0276] Each of the plurality of routing lines (410) may include a first part (or front part) (410a) disposed on the contact pattern portion (110) of the first substrate (100), a second part (or rear part) (410b) disposed on the first pad portion (210) of the second substrate (200), and a third part (or side part or middle part) (410c) disposed on the outer surface (OS1a) of the first substrate (100) and the outer surface (OS1b) of the second substrate (200) between the first part (410a) and the second part (410b).

[0277] Each of the first part (410a), second part (410b), and third part (410c) of each of the multiple routing lines (410) can be simultaneously implemented by a printing method using conductive paste.

[0278] Each first part (410a) of a plurality of routing lines (410) can be directly connected to the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern part (110) through a routing contact hole (CH).

[0279] According to one embodiment, the first part (410a) can be directly connected to the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern part (110) through a routing contact hole (CH). For example, the first part (410a) may include at least five connection parts (or contact parts) filled in at least one first to fifth routing contact hole (CH1, CH2, CH3, CH5) so as to be directly connected to one contact pattern (PCP, DCP, RCP, GCP, CCP).

[0280] A second part (410b) of each of the plurality of routing lines (410) is positioned on a first pad portion (210) positioned on the rear surface (200b) of the second substrate (200) and can be electrically directly connected to the pads (211) of the first pad portion (210). A third part (410c) of each of the plurality of routing lines (410) is positioned between the first part (410a) and the second part (410b) and can wrap around or surround the outer surface (OS1a) of the first substrate (100) and the outer surface (OS1b) of the second substrate (200).

[0281] The contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern section (110) can be electrically connected to the pad (211) of the first pad section (210) through the first part (410a), the third part (410c), and the second part (410b) of the routing line (410).

[0282] According to one embodiment, a plurality of routing lines (410) may be classified (or distinguished) into pixel driving power routing lines (411), data routing lines (413), reference voltage routing lines (415), gate routing lines (417), and pixel common voltage routing lines (419).

[0283] Each of the pixel driving power routing lines (411) is electrically directly connected to each of the pixel driving power contact patterns (PCP) of the contact pattern section (110) through a routing contact hole (CH) that passes through the encapsulation layer (119), the disconnection section (115), and the circuit layer (111) in sequence, and can be electrically connected to each of the first pixel driving power pads of the first pad section (210). Accordingly, the pixel driving power output from the driving circuit section can be supplied to the pixel driving power lines (PL) through the second pixel driving power pads, pixel driving power link lines, first pixel driving power pads, pixel driving power routing lines (411), and pixel driving power contact patterns (PCP), respectively.

[0284] Each of the data routing lines (413) is electrically directly connected to each of the data contact patterns (DCP) of the contact pattern section (110) through a routing contact hole (CH) that passes through the encapsulation layer (119), the disconnection section (115), and the circuit layer (111) in sequence, and can be electrically connected to each of the first data pads of the first pad section (210). Accordingly, a data signal output from the driving circuit section can be supplied to the data lines (DL) through the second data pads, data link lines, first data pads, data routing lines (413), and data contact patterns (DCP), respectively.

[0285] Each of the reference voltage routing lines (415) is electrically directly connected to each of the reference voltage contact patterns (RCP) of the contact pattern section (110) through a routing contact hole (CH) that passes through the encapsulation layer (119), the disconnection section (115), and the circuit layer (111) in sequence, and can be electrically connected to each of the first reference power pads of the first pad section (210) and the reference voltage contact pattern (RCP) of the contact pattern section (110). Accordingly, the reference voltage can be supplied to the reference voltage lines (RL) through the second reference power pads, reference power link lines, first reference power pads, reference voltage routing lines (415), and reference voltage contact patterns (RCP) output from the driving circuit section.

[0286] Each of the gate routing lines (417) is electrically directly connected to each of the gate contact patterns (GCP) of the contact pattern section (110) through a routing contact hole (CH) that passes through the encapsulation layer (119), the disconnection section (115), and the circuit layer (111) in sequence, and can be electrically connected to each of the first gate pads of the first pad section (210). Accordingly, a gate control signal output from the driving circuit section can be supplied to the gate control lines (GCL) through the second gate pads, gate link lines, first gate pads, gate routing lines (417), and gate contact patterns (GCP), respectively.

[0287] Each of the pixel common voltage routing lines (419) is electrically directly connected to each of the pixel common voltage contact patterns (CCP) of the contact pattern section (110) through a routing contact hole (CH) that passes through the encapsulation layer (119), the disconnection section (115), and the circuit layer (111) in sequence, and can be electrically connected to each of the first pixel common voltage pads of the first pad section (210). Accordingly, the pixel common voltage output from the driving circuit section can be supplied to the pixel common voltage lines (CVL) through the second pixel common voltage pads, pixel common voltage link lines, first pixel common voltage pads, pixel common voltage routing lines (419), and pixel common voltage contact patterns (CCP), respectively.

[0288] In FIGS. 10 to 12, the routing line (410) of the routing section (400) is described as being electrically directly connected to the contact pattern (PCP, DCP, RCP, GCP, CCP) through all of the at least one first to fourth routing contact hole (CH1, CH2, CH3, CH4) formed in each of the first to fourth disconnection structures (115a, 115b, 115c, 115d) of the disconnection section (115) and the at least one fifth routing contact hole (CH5) formed in the dam section (117), but is not limited thereto. For example, the routing line (410) of the routing section (400) may be electrically directly connected to the contact pattern (PCP, DCP, RCP, GCP, CCP) through at least one of the first to fifth routing contact holes (CH1, CH2, CH3, CH4, CH5).

[0289] The second substrate (200) placed on the rear surface of the first substrate (100) described in FIGS. 10 to 12 may be omitted. In this case, the first pad portion (210), the second pad portion (230), and the link line portion (250) placed on the second substrate (200) may each be placed on the rear surface (100b) of the substrate (100) as shown in FIG. 7. The routing line (410) of the routing portion (400) is formed to wrap around the front edge portion of the substrate (100), the outer surface (OS), and the rear edge portion of the substrate (100). Since it is substantially the same except that it is electrically connected one-to-one with the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern portion (110) and the pads (211) of the first pad portion (210), a redundant description thereof is omitted.

[0290] A routing section (400) according to one embodiment may further include an edge coating layer (450).

[0291] The edge coating layer (450) may be implemented to cover a plurality of routing lines (411). According to one embodiment, the edge coating layer (450) may be implemented to cover not only the plurality of routing lines (410) but also the entire first edge portion and first outer surface (OS1a) of the first substrate (100) and the first edge portion and first outer surface (OS1b) of the second substrate (200). Such an edge coating layer (450) can prevent corrosion of each of the plurality of routing lines (410) made of metal material or electrical short circuits between the plurality of routing lines (410). Additionally, the edge coating layer (450) can prevent or minimize reflection of external light by the plurality of routing lines (410) and the pads of the first pad portion (110). According to one embodiment, the edge coating layer (450) may be made of a light-blocking material including black ink.

[0292] The upper surface of the edge coating layer (450) disposed on the first surface (100a) of the first substrate (100) can be covered by a side sealing member (125).

[0293] The outer surface of the edge coating layer (450) may be the outermost outer surface of the first substrate (100), and accordingly, the outermost outer surface of the first substrate (100), the outer surface of the side sealing member (125), and the outer surface of the functional film (123) may each be located on the same vertical line (VL).

[0294] A light-emitting display device according to one embodiment of the present specification includes a routing portion (400) directly connected to a contact pattern disposed at the edge portion of a first substrate (or substrate) (100), thereby eliminating the need for a pad portion disposed at the outermost edge portion of the first substrate (or substrate) (100), and thus can have an air bezel structure without a bezel area.

[0295] In addition, in a light-emitting display device according to one embodiment of the present specification, the light-emitting layer (EL) disposed at the edge portion of the first substrate (or substrate) (100) is cut off (or separated) at least once by the cutting portion (115), thereby preventing or minimizing the deterioration and / or reliability degradation of the light-emitting layer (EL) due to lateral moisture penetration.

[0296] FIG. 13 is a diagram illustrating a connection structure between a pixel driving line and a routing unit according to another embodiment of the present specification, FIG. 14 is an enlarged view of the 'B4' portion shown in FIG. 13, FIG. 15 is a cross-sectional view of line II-II' shown in FIG. 14, FIG. 16 is an enlarged view of the 'B5' portion shown in FIG. 15, and FIG. 17 is a cross-sectional view of line III-III' shown in FIG. 14, which additionally configures an auxiliary line unit in the light-emitting display device shown in FIG. 9 to FIG. 12. In describing FIG. 13 to FIG. 16, only the auxiliary line unit and the related configurations will be described, and the remaining configurations will be given the same reference numerals as in FIG. 9 to FIG. 12, and redundant descriptions thereof will be omitted.

[0297] Referring to FIGS. 13 to 16, a light-emitting display device according to another embodiment of the present specification may further include an auxiliary pattern part (116) disposed between a contact pattern part (110) connected to pixel driving lines (PL, DL, RL, GCL, CVL) and a routing part (400).

[0298] The auxiliary pattern section (116) may be represented as an intermediate metal section or a signal transmission section. According to one embodiment, the auxiliary pattern section (116) may include first to fifth intermediate patterns (116a, 116b, 116c, 116d, 116e) electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern section (110) and the routing lines (410) of the routing section (400). For example, each of the first to fifth intermediate patterns (116a, 116b, 116c, 116d, 116e) may be represented as an auxiliary pattern, a conductive auxiliary pattern, or a conductive intermediate pattern.

[0299] Each of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) may be placed in the disconnection section (115). For example, the first intermediate pattern (116a) may be placed in the first disconnection structure (115a) of the disconnection section (115). The second intermediate pattern (116b) may be placed in the second disconnection structure (115b) of the disconnection section (115). The third intermediate pattern (116c) may be placed in the third disconnection structure (115c) of the disconnection section (115). The fourth intermediate pattern (116d) may be placed in the fourth disconnection structure (115d) of the disconnection section (115).

[0300] The fifth intermediate pattern (116e) can be placed in the dam area (DA). For example, the fifth intermediate pattern (116e) can be placed below the dam section (117). For example, the fifth intermediate pattern (116e) can be placed between the dam section (117) and the circuit layer (111).

[0301] Each of the first to fifth intermediate patterns (116a, 116b, 116c, 116d, 116e) can serve as an intermediate metal layer or signal transmission layer interposed between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410). Each of the first to fifth intermediate patterns (116a, 116b, 116c, 116d, 116e) can prevent electrical or physical contact failure between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410) that may occur depending on the distance between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410). Additionally, each of the first to fifth intermediate patterns (116a, 116b, 116c, 116d, 116e) is interposed between the first trench structure (TS1) and the second trench structure (TS2) of each of the first to fourth disconnected structures (115a, 115b, 115c, 115d) of the disconnected section (115), thereby improving the adhesion between the first trench structure (TS1) and the second trench structure (TS2).

[0302] Each of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) is respectively placed in the first to fourth disconnect structures (115a, 115b, 115c, 115d) of the disconnect section (115) that overlap with each of the contact patterns (PCP, DCP, RCP, GCP, CCP), and can be electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410) of the routing section (400). For example, each of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) is respectively placed in the first to fourth disconnect structures (115a, 115b, 115c, 115d) that overlap with the data contact pattern (DCP), and can be electrically connected between the data contact pattern (DCP) and the data routing line (413). For example, each of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) can be commonly connected to the data contact pattern (DCP) and commonly connected to the first part (410a) of the data routing line (413).

[0303] The fifth intermediate pattern (116e) is placed in a dam (117) that overlaps with each of the contact patterns (PCP, DCP, RCP, GCP, CCP) and can be electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410) of the routing section (400). For example, the fifth intermediate pattern (116e) is placed in a dam (117) that overlaps with the data contact pattern (DCP) and can be electrically connected between the data contact pattern (DCP) and the data routing line (413).

[0304] In FIGS. 13 to 16, the auxiliary pattern section (116) is described as including the first to fifth intermediate patterns (116a, 116b, 116c, 116d, 116e), but is not limited thereto. For example, the auxiliary pattern section (116) may include at least one of the first to fifth intermediate patterns (116a, 116b, 116c, 116d, 116e). For example, the auxiliary pattern section (116) may include only one intermediate pattern (116e) that is placed in a damper section (117) that overlaps with each of the contact patterns (PCP, DCP, RCP, GCP, CCP) and is electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410) of the routing section (400). For example, the auxiliary pattern section (116) may include at least one of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) which are placed in a disconnection section (115) that overlaps with each of the contact patterns (PCP, DCP, RCP, GCP, CCP) and are electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410) of the routing section (400).

[0305] Each of the first to fifth intermediate patterns (116a, 116b, 116c, 116d, 116e) according to one embodiment may include a first metal layer (MLa) and a second metal layer (MLb).

[0306] The first metal layer (MLa) may be placed in a circuit layer (111) that overlaps with contact patterns (PCP, DCP, RCP, GCP, CCP). For example, the first metal layer (MLa) may be placed between the disconnection portion (115) and the damp portion (117) and the contact patterns (PCP, DCP, RCP, GCP, CCP), respectively. For example, the first metal layer (MLa) may be placed between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the interlayer insulating layer (111c).

[0307] According to one embodiment, a first metal layer (MLa) may be implemented on a buffer layer (111a) to be electrically connected to contact patterns (PCP, DCP, RCP, GCP, CCP). For example, the first metal layer (MLa) may be disposed on a buffer layer (111a) that overlaps with contact patterns (PCP, DCP, RCP, GCP, CCP) and may be electrically connected to contact patterns (PCP, DCP, RCP, GCP, CCP) through a first via hole (or lower via hole) (VH1) penetrating the buffer layer (111a). For example, the first metal layer (MLa) may be covered by at least one insulating layer disposed on the buffer layer (111a). For example, the first metal layer (MLa) may be covered by an interlayer insulating layer (111c).

[0308] According to one embodiment, the first metal layer (MLa) of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) can be electrically connected to the contact patterns (PCP, DCP, RCP, GCP, CCP) through a first via hole (VH1) penetrating the buffer layer (111a) disposed below the disconnection portion (115).

[0309] According to one embodiment, the first metal layer (MLa) of the fifth intermediate pattern (116e) can be electrically connected to contact patterns (PCP, DCP, RCP, GCP, CCP) through a first via hole (VH1) penetrating a buffer layer (111a) placed below the dam (117).

[0310] According to one embodiment, the first metal layer (MLa) may be implemented in the form of a dot that overlaps with the contact patterns (PCP, DCP, RCP, GCP, CCP) or in the form of a line that intersects the contact patterns (PCP, DCP, RCP, GCP, CCP) along the first direction (X). For example, since the first metal layer (MLa) of the fifth intermediate pattern (116e) is placed in the dam portion (117), it may have a relatively larger size than the first metal layer (MLa) of the first to fourth intermediate patterns (116a, 116b, 116c, 116d), but is not limited thereto.

[0311] According to one embodiment, the first metal layer (MLa) may be implemented together with the gate electrode of the TFTs (Tdr) disposed in the pixel area (PA) or with the source / drain electrode. For example, the first metal layer (MLa) may be implemented with the same material and structure as the gate electrode of the TFTs (Tdr) or with the same material and structure as the source / drain electrode.

[0312] The second metal layer (MLb) can be implemented to be electrically connected between the first metal layer (MLa) and the routing lines (410). For example, the second metal layer (MLb) may be placed on a passivation layer (111d) that overlaps the first metal layer (MLa) and may be electrically connected to the first metal layer (MLa) through a second via hole (or upper via hole) (VH2) that passes through the passivation layer (111d) and the interlayer insulation layer (111c) in turn.

[0313] According to one embodiment, the second metal layer (MLb) of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) is disposed on the first trench structure (TS1) of each of the first to fourth disconnect structures (115a, 115b, 115c, 115d) of the disconnect portion (115) that overlaps with the first metal layer (MLa), and can be electrically connected between the first metal layer (MLa) and the routing lines (410). For example, the second metal layer (MLb) of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) is disposed between the first trench structure (TS1) and the second trench structure (TS2) of each of the first to fourth disconnect structures (115a, 115b, 115c, 115d) of the disconnect section (115), and can be electrically connected to the first metal layer (MLa) through a second via hole (or upper via hole) (VH2) that sequentially penetrates the passivation layer (111d) and the interlayer insulation layer (111c) of the first trench structure (TS1). For example, the second metal layer (MLb) of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) can be placed between the first trench structure (TS1) and the second trench structure (TS2) to improve the adhesion between the first trench structure (TS1) and the second trench structure (TS2).

[0314] According to one embodiment, the second metal layer (MLb) of the fifth intermediate pattern (116e) is positioned between the first dam (117a) of the dam portion (117) and the first metal layer (MLa), and can be electrically connected between the first metal layer (MLa) and the routing lines (410). For example, the second metal layer (MLb) of the fifth intermediate pattern (116e) is positioned between the first dam (117a) of the dam portion (117) and the passivation layer (111d), and can be electrically connected to the first metal layer (MLa) through a second via hole (or upper via hole) (VH2) that passes through the passivation layer (111d) and the interlayer insulation layer (111c) below the first dam (117a) in sequence. For example, the second metal layer (MLb) of the fifth intermediate pattern (116e) can be placed between the passivation layer (111d) and the first dam (117a) to improve the adhesion between the passivation layer (111d) and the first dam (117a).

[0315] According to one embodiment, the second metal layer (MLb) may be implemented in the same dot shape as the first metal layer (MLa) or in the same line shape. For example, since the second metal layer (MLb) of the fifth intermediate pattern (116e) is placed in the dam portion (117), it may have a relatively larger size than the second metal layer (MLb) of the first to fourth intermediate patterns (116a, 116b, 116c, 116d), but is not limited thereto.

[0316] According to one embodiment, the second metal layer (MLa) can be implemented together with the pixel electrode (PE) disposed in the pixel region (PA). For example, the second metal layer (MLb) can be implemented with the same material and structure as the pixel electrode (PE).

[0317] Referring to FIGS. 13, 14 and 17, a light-emitting display device according to another embodiment of the present specification may further include an auxiliary line portion (118) disposed in each of a disconnection portion (115) and a dam portion (117) disposed in the remaining edge portions excluding one edge portion of the first substrate (100).

[0318] The auxiliary line section (118) may be represented as a conductive line section. According to one embodiment, the auxiliary line section (118) may include first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) disposed in the disconnection section (115) and the dam section (117). For example, each of the first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) may be represented as a conductive line, an electrically floating line, a conductive auxiliary line, or an electrically floating auxiliary line.

[0319] Each of the first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) may be implemented with the same material and structure as the pixel electrode (PE) placed in the pixel area (PA). For example, each of the first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) may be formed together with the second metal layer (MLb) of the auxiliary pattern portion (116).

[0320] Each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) may be placed in the first to fourth disconnecting structures (115a, 115b, 115c, 115d) of the disconnecting section (115) to have a line shape. For example, the first auxiliary line (118a) may be placed in the first disconnecting structure (115a) of the disconnecting section (115). The second auxiliary line (118b) may be placed in the second disconnecting structure (115b) of the disconnecting section (115). The third auxiliary line (118c) may be placed in the third disconnecting structure (115c) of the disconnecting section (115). The fourth auxiliary line (118d) can be placed in the fourth disconnect structure (115d) of the disconnect section (115).

[0321] Each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) according to one embodiment may be placed on a passivation layer (111d) that overlaps with each of the first to fourth disconnect structures (115a, 115b, 115c, 115d) of the disconnect section (115). For example, each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) may be placed between the first trench structure (TS1) and the second trench structure (TS2) of each of the first to fourth disconnect structures (115a, 115b, 115c, 115d) of the disconnect section (115), thereby improving the adhesion between the first trench structure (TS1) and the second trench structure (TS2).

[0322] Each of the first to fourth disconnected structures (115a, 115b, 115c, 115d) of the disconnected section (115) may include a third via hole (VH3) that overlaps with each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d). For example, the third via hole (VH3) may sequentially penetrate the passivation layer (111d) and the interlayer insulation layer (111c) that implement the first trench structure (TS1). For example, the third via hole (VH3) may be formed together with the first via hole (VH2) of the auxiliary pattern section (116). Accordingly, each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) can be placed on the passivation layer (111d) of the first trench structure (TS1) and inserted into the third via hole (VH3).

[0323] The fifth auxiliary line (116e) may be placed in the dam area (DA) to have a line shape. For example, the fifth auxiliary line (116e) may be placed below the dam section (117). For example, the fifth auxiliary line (116e) may be placed between the dam section (117) and the circuit layer (111).

[0324] According to one embodiment, the fifth auxiliary line (118e) may be placed on the passivation layer (111d) that overlaps with the dam portion (117). For example, the fifth auxiliary line (118e) may be placed between the passivation layer (111d) and the first dam (117a) of the dam portion (117) to improve the adhesion between the passivation layer (111d) and the first dam (117a).

[0325] The dam area (DA) or dam section (117) may include a fourth via hole (VH4) that overlaps with the fifth auxiliary line (118e). For example, the fourth via hole (VH4) may sequentially penetrate the passivation layer (111d) and the interlayer insulation layer (111c) placed below the first dam (117a) of the dam section (117). For example, the fourth via hole (VH4) may be formed together with the first via hole (VH2) of the auxiliary pattern section (116). Accordingly, the fifth auxiliary line (118e) may be placed on the passivation layer (111d) below the dam section (117) and inserted into the fourth via hole (VH4).

[0326] As such, a light-emitting display device according to another embodiment of the present specification may have an air bezel structure without a bezel area, similar to the light-emitting display device according to one embodiment, and the deterioration and / or reduction in reliability of the light-emitting layer (EL) due to lateral moisture permeability may be prevented or minimized. In addition, a light-emitting display device according to another embodiment of the present specification may further include an auxiliary pattern portion (116) disposed between the contact pattern (PCP, DCP, RCP, GCP, CCP) and the routing line (410), thereby preventing electrical or physical contact failure between the contact pattern (PCP, DCP, RCP, GCP, CCP) and the routing line (410). In addition, a light-emitting display device according to another embodiment of the present specification can improve adhesion between the first trench structure (TS1) and the second trench structure (TS2) of each of the first to fourth disconnection structures (115a, 115b, 115c, 115d) of the disconnection section (115) by further including an auxiliary line section (118) disposed between the dam section (117) and the circuit layer (111), thereby improving adhesion between the first trench structure (TS1) and the second trench structure (TS2) and improving adhesion between the dam section (117) and the circuit layer (111).

[0327] FIG. 18 is a diagram illustrating a connection structure between a pixel driving line, a routing unit, and an auxiliary line unit according to another embodiment of the present specification, FIG. 19 is a cross-sectional view of line IV-IV' shown in FIG. 18, FIG. 20 is a cross-sectional view of line V-V' shown in FIG. 18, FIG. 21 is a cross-sectional view of line VI-VI' shown in FIG. 18, and FIG. 22 is a cross-sectional view of line VII-VII' shown in FIG. 18, wherein the auxiliary line unit shown in FIG. 13 to FIG. 17 is configured as a signal supply line. In describing FIG. 18 to FIG. 22, only the auxiliary line unit and related configurations are described, and the remaining configurations are given the same reference numerals as in FIG. 13 to FIG. 17, and redundant descriptions thereof are omitted.

[0328] Referring to FIG. 18, an auxiliary line section (118) according to another embodiment of the present specification may include first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) disposed in a disconnection section (115) and a dam section (117).

[0329] The first auxiliary line (118a) may be formed to have a closed-loop line shape on the first substrate (100). For example, the first intermediate pattern of the auxiliary pattern portion (116) placed on one edge portion of the first substrate (100) and the first auxiliary line (118a) of the auxiliary line portion (118) placed on the remaining edge portion excluding one edge portion of the first substrate (100) may be electrically connected to each other to have a closed-loop line shape. For example, the first auxiliary line (118a) may be expressed as a first closed-loop auxiliary line or a first conductive closed-loop line.

[0330] A first auxiliary line (118a) disposed on one edge portion of the first substrate (100) may be disposed to cross the contact pattern portion (110) along the first direction (X). For example, the first auxiliary line (118a) disposed on one edge portion of the first substrate (100) may be disposed on a first disconnect structure (115a) between the contact pattern portion (110) and the routing portion (400).

[0331] The first auxiliary line (118a) may be electrically connected to pixel common voltage lines (CVL) at one edge portion of the first substrate (100). Additionally, the first auxiliary line (118a) may be electrically connected only to the pixel common voltage routing lines (419) among the plurality of routing lines (411, 413, 415, 417, 419) disposed in the routing portion (400). For example, the first auxiliary line (118a) may be electrically (or commonly) connected to the first portion (410a) of each pixel common voltage routing line (419) through at least one first routing contact hole (CH1).

[0332] Additionally, the first auxiliary line (118a) may be electrically connected to each of the pixel common voltage lines (CVL) at the other edge portion of the first substrate (100) parallel to one edge portion of the first substrate (100). For example, the first auxiliary line (118a) may be electrically (or commonly) connected to the other side of each of the pixel common voltage lines (CVL) through the fifth via hole (VH5) at the other edge portion of the first substrate (100).

[0333] The first auxiliary line (118a) is positioned at the outermost edge portion of the first substrate (100) and can be maintained at the same potential as the pixel common voltage lines (CVL), thereby primarily blocking static electricity flowing from the outside into the inside of the display portion (AA) and preventing defects caused by static electricity. For example, the first auxiliary line (118a) can prevent defects caused by static electricity by discharging static electricity flowing from the outside into the pixel common voltage routing lines (419) and / or the pixel common voltage line (CVL).

[0334] Each of the second and third auxiliary lines (118b, 118c) may be placed on the remaining edge portion of the first substrate (100), excluding the one-sided edge portion. Each of the second and third auxiliary lines (118b, 118c) may be electrically connected to the first and last pixel driving power lines (PL) among the pixel driving power lines (PL) at one side (or one-sided edge portion) and the other side (or other-sided edge portion) of the one-sided edge portion of the first substrate (100). Additionally, each of the second and third auxiliary lines (118b, 118c) may be electrically connected to the first portion (410a) of each of the first and last pixel driving power routing lines (411) through at least one routing contact hole (CH2, CH3).

[0335] Additionally, each of the second and third auxiliary lines (118b, 118c) may be electrically (or commonly) connected to the pixel driving power lines (PL) at the other edge portion of the first substrate (100). For example, each of the second and third auxiliary lines (118b, 118c) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) through the fifth via hole (VH5) at the other edge portion of the first substrate (100).

[0336] Each of the second and third auxiliary lines (118b, 118c) can be maintained at the same potential as the pixel driving power lines (PL). Each of the second and third auxiliary lines (118b, 118c) can be electrically connected to the pixel driving power lines (PL) to reduce the voltage drop (IR drop) of the pixel driving power due to the line resistance of the pixel driving power lines (PL).

[0337] The fourth auxiliary line (118d) may be formed to have a closed-loop line shape on the first substrate (100). For example, the fourth intermediate pattern of the auxiliary pattern portion (116) placed on one edge portion of the first substrate (100) and the fourth auxiliary line (118d) of the auxiliary line portion (118) placed on the remaining edge portion excluding one edge portion of the first substrate (100) may be electrically connected to each other to have a closed-loop line shape. For example, the fourth auxiliary line (118d) may be represented as a second closed-loop auxiliary line or a second conductive closed-loop line.

[0338] A fourth auxiliary line (118d) disposed on one edge portion of the first substrate (100) may be disposed to cross the contact pattern portion (110) along the first direction (X). For example, the fourth auxiliary line (118d) disposed on one edge portion of the first substrate (100) may be disposed on the fourth disconnect structure (115d) of the disconnect portion (115) between the contact pattern portion (110) and the routing portion (400).

[0339] The fourth auxiliary line (118d) may be electrically connected to the pixel common voltage lines (CVL) at one edge portion of the first substrate (100). Additionally, the fourth auxiliary line (118d) may be electrically connected only to the pixel common voltage routing lines (419) among the plurality of routing lines (411, 413, 415, 417, 419) disposed in the routing portion (400). For example, the fourth auxiliary line (118d) may be electrically (or commonly) connected to the first portion (410a) of each of the pixel common voltage routing lines (419) through at least one fourth routing contact hole (CH4).

[0340] Additionally, the fourth auxiliary line (118d) may be electrically (or commonly) connected to each of the pixel common voltage lines (CVL) at the other edge portion of the first substrate (100). For example, the fourth auxiliary line (118d) may be electrically (or commonly) connected to the other side of each of the pixel common voltage lines (CVL) through the fifth via hole (VH5) at the other edge portion of the first substrate (100).

[0341] The fourth auxiliary line (118d) is positioned in the inner part of the dam (117) and can be maintained at the same potential as the pixel common voltage lines (CVL), thereby secondarily blocking static electricity flowing from the outside into the inside of the display (AA) and preventing defects caused by static electricity. For example, the fourth auxiliary line (118d) can prevent defects caused by static electricity by discharging static electricity flowing from the outside into the pixel common voltage routing lines (419) and / or the pixel common voltage line (CVL).

[0342] The fifth auxiliary line (118e) may be placed on the remaining edge portion of the first substrate (100), excluding the one-sided edge portion. The fifth auxiliary line (118e) may be electrically connected to the first and last pixel driving power lines (PL) among the pixel driving power lines (PL) at one side (or one-sided edge portion) and the other side (or other-sided edge portion) of the one-sided edge portion of the first substrate (100). Additionally, the fifth auxiliary line (118e) may be electrically connected to the first portion (410a) of each of the first and last pixel driving power routing lines (411) through at least one fifth routing contact hole (CH5).

[0343] Additionally, the fifth auxiliary line (118e) may be electrically (or commonly) connected to the pixel driving power lines (PL) at the other edge portion of the first substrate (100). For example, the fifth auxiliary line (118e) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) through the sixth via hole (VH6) at the other edge portion of the first substrate (100).

[0344] The fifth auxiliary line (118e) can be maintained at the same potential as the pixel driving power lines (PL). By being electrically connected to the pixel driving power lines (PL), the voltage drop (IR drop) of the pixel driving power due to the line resistance of the pixel driving power lines (PL) can be reduced.

[0345] Referring to FIGS. 18 and 19, in another embodiment of the present specification, a first auxiliary line (118a) may be electrically connected to a first portion (410a) of each pixel common voltage routing line (419) of a routing section (400) through at least one first routing contact hole (CH1) on a pixel common voltage contact pattern (CCP) disposed on a contact pattern section (110). Additionally, the first auxiliary line (118a) may be electrically connected to the pixel common voltage contact pattern (CCP) through a first via hole (VH1) formed in a buffer layer (111a) disposed on the pixel common voltage contact pattern (CCP). Additionally, the first auxiliary line (118a) can be electrically connected to pixel common voltage contact patterns (CCP) through a metal layer (MLa) placed in the first via hole (VH1) of the buffer layer (111a).

[0346] In another embodiment of the present specification, the fourth auxiliary line (118d) may be electrically connected to the first portion (410a) of each of the pixel common voltage routing lines (419) of the routing section (400) through at least one fourth routing contact hole (CH4) on the pixel common voltage contact patterns (CCP) disposed on the contact pattern section (110). Additionally, the fourth auxiliary line (118d) may be electrically connected to the pixel common voltage contact patterns (CCP) through a first via hole (VH1) formed in the buffer layer (111a) disposed on the pixel common voltage contact patterns (CCP). Additionally, the fourth auxiliary line (118d) may be electrically connected to the pixel common voltage contact patterns (CCP) through a metal layer (MLa) disposed in the first via hole (VH1) of the buffer layer (111a).

[0347] Each first part (410a) of each pixel common voltage routing line (419) arranged in the routing section (400) is electrically (or commonly) connected to a first auxiliary line (118a) through at least one first routing contact hole (CH1) and to a fourth auxiliary line (118d) through at least one first routing contact hole (CH1), and can be electrically (or commonly) connected to pixel common voltage contact patterns (CCP) through the first auxiliary line (118a) and the fourth auxiliary line (118d). Additionally, each first part (410a) of the pixel common voltage routing lines (419) arranged in the routing section (400) may be electrically (or commonly) connected to the second, third, and fifth intermediate patterns (116b, 116c, 116e) through at least one second routing contact hole (CH2), at least one third routing contact hole (CH3), and at least one fourth routing contact hole (CH4), and may be electrically (or commonly) connected to the pixel common voltage contact patterns (CCP) through the second, third, and fifth intermediate patterns (116b, 116c, 116e).

[0348] Accordingly, in another embodiment of the present specification, the light-emitting display device can supply a more uniform pixel common voltage to the pixel common voltage lines (CVL) disposed on the display portion (AA) of the first substrate (100), thereby improving the uniformity of the pixel common voltage. Additionally, in another embodiment of the present specification, the light-emitting display device can prevent or minimize defects caused by static electricity introduced from the outside by electrically connecting the first and fourth auxiliary lines (118a, 118d), which have a closed-loop line shape on the first substrate (100), to the pixel common voltage lines (CVL).

[0349] Referring to FIG. 18 and FIG. 20, in another embodiment of the present specification, a first auxiliary line (118a) may be electrically (or commonly) connected to the other side of the pixel common voltage lines (CVL) through at least one fifth via hole (VH5) at the other side edge portion of the first substrate (100). At least one fifth via hole (VH5) may be formed in a buffer layer (111a) disposed between the other side of each pixel common voltage line (CVL) and the intersection area of ​​the first auxiliary line (118a). At least one fifth via hole (VH5) may be formed together with at least one first via hole. Additionally, the first auxiliary line (118a) can be electrically (or commonly) connected to the other side of the pixel common voltage lines (CVL) through a metal layer (MLa) placed in the fifth via hole (VH5) of the buffer layer (111a).

[0350] The fourth auxiliary line (118d) may be electrically (or commonly) connected to the other side of each pixel common voltage line (CVL) through at least one fifth via hole (VH5) at the other edge portion of the first substrate (100). At least one fifth via hole (VH5) may be formed in a buffer layer (111a) disposed between the other side of each pixel common voltage line (CVL) and the intersection area of ​​the fourth auxiliary line (118d). Additionally, the fourth auxiliary line (118d) may be electrically (or commonly) connected to the other side of the pixel common voltage line (CVL) through a metal layer (MLa) disposed in the fifth via hole (VH5) of the buffer layer (111a).

[0351] A light-emitting display device according to another embodiment of the present specification may further include first auxiliary contact patterns (SCCP). For example, the first auxiliary contact pattern (SCCP) may be represented as a pixel common voltage auxiliary contact pattern.

[0352] According to one embodiment, the first auxiliary contact patterns (SCCP) are placed on the same layer as the pixel common voltage lines (CVL) and may extend (or be extended) toward the outer surface (OS) of the substrate (100) with a relatively wide width from each end of the pixel common voltage lines (CVL) located at the other edge portion of the substrate (100). According to another embodiment, each of the first auxiliary contact patterns (SCCP) is placed on the layer below the pixel common voltage lines (CVL) with a relatively wide width so as to overlap with each end of the pixel common voltage lines (CVL) located at the other edge portion of the substrate (100), and may be electrically connected to each end of the pixel common voltage lines (CVL) through an internal contact hole.

[0353] The first auxiliary line (118a) may be electrically (or commonly) connected to the first auxiliary contact patterns (SCCP) through at least one fifth via hole (VH5) at the other edge portion of the first substrate (100). Additionally, the first auxiliary line (118a) may be electrically (or commonly) connected to the first auxiliary contact patterns (SCCP) through a metal layer (MLa) placed in the fifth via hole (VH5) of the buffer layer (111a).

[0354] The fourth auxiliary line (118d) may be electrically (or commonly) connected to the first auxiliary contact patterns (SCCP) through at least one fifth via hole (VH5) at the other edge portion of the first substrate (100). Additionally, the fourth auxiliary line (118d) may be electrically (or commonly) connected to the first auxiliary contact patterns (SCCP) through a metal layer (MLa) placed in the fifth via hole (VH5) of the buffer layer (111a).

[0355] Accordingly, in another embodiment of the present specification, the light-emitting display device can simultaneously supply a pixel common voltage to one side and the other side of the pixel common voltage lines (CVL) through each of the first and fourth auxiliary lines (118a, 118d) having a closed-loop line shape, thereby further improving the uniformity of the pixel common voltage. In addition, in another embodiment of the present specification, the light-emitting display device can further prevent or further minimize defects caused by static electricity introduced from the outside by electrically connecting the first and fourth auxiliary lines (118a, 118d) having a closed-loop line shape on the first substrate (100) to one side and the other side of the pixel common voltage lines (CVL).

[0356] Referring to FIG. 18 and FIG. 21, in another embodiment of the present specification, a second auxiliary line (118b) may be electrically connected to a first portion (410a) of each of the first and last pixel driving power routing lines (411) of the routing section (400) through at least one second routing contact hole (CH2) on the first and last pixel driving power contact patterns (PCP) disposed on the contact pattern section (110). Additionally, the second auxiliary line (118b) may be electrically connected to the first and last pixel driving power contact patterns (PCP) through a first via hole (VH1) formed in a buffer layer (111a) disposed on the first and last pixel driving power contact patterns (PCP). Additionally, the second auxiliary line (118b) can be electrically connected to the first and last pixel driving power contact patterns (PCP) through a metal layer (MLa) placed in the first via hole (VH1) of the buffer layer (111a).

[0357] The third auxiliary line (118c) can be electrically connected to the first portion (410a) of each of the first and last pixel driving power routing lines (411) of the routing section (400) through at least one third routing contact hole (CH3) on the first and last pixel driving power contact patterns (PCP) disposed on the contact pattern section (110). Additionally, the third auxiliary line (118c) can be electrically connected to the first and last pixel driving power contact patterns (PCP) through a first via hole (VH1) formed in the buffer layer (111a) disposed on the first and last pixel driving power contact patterns (PCP). Additionally, the third auxiliary line (118c) can be electrically connected to the first and last pixel driving power contact patterns (PCP) through a metal layer (MLa) disposed in the first via hole (VH1) of the buffer layer (111a).

[0358] The fifth auxiliary line (118e) can be electrically connected to the first portion (410a) of each of the first and last pixel driving power routing lines (411) of the routing section (400) through at least one fifth routing contact hole (CH5) on the first and last pixel driving power contact patterns (PCP) disposed on the contact pattern section (110). Additionally, the fifth auxiliary line (118e) can be electrically connected to the first and last pixel driving power contact patterns (PCP) through a first via hole (VH1) formed in the buffer layer (111a) disposed on the first and last pixel driving power contact patterns (PCP). Additionally, the fifth auxiliary line (118e) can be electrically connected to the first and last pixel driving power contact patterns (PCP) through a metal layer (MLa) disposed in the first via hole (VH1) of the buffer layer (111a).

[0359] Accordingly, in another embodiment of the present specification, the first and last pixel driving voltage lines (PL) placed in the display portion (AA) of the first substrate (100) are electrically connected to the second, third, and third auxiliary lines (118b, 118c, 118e), respectively, so that the voltage drop (IR drop) of the pixel driving power according to the line resistance of the pixel driving power line (PL) can be reduced.

[0360] Referring to FIG. 18 and FIG. 22, in another embodiment of the specification, a second auxiliary line (118b) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) through at least one fifth via hole (VH5) at the other edge portion of the first substrate (100). At least one fifth via hole (VH5) may be formed in a buffer layer (111a) disposed between the other side of the pixel driving power lines (PL) and the intersection area of ​​the second auxiliary line (118b). Additionally, the second auxiliary line (118b) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) through a metal layer (MLa) disposed in the fifth via hole (VH5) of the buffer layer (111a).

[0361] The third auxiliary line (118c) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) through at least one fifth via hole (VH5) at the other edge portion of the first substrate (100). At least one fifth via hole (VH5) may be formed in a buffer layer (111a) disposed between the other side of the pixel driving power lines (PL) and the intersection area of ​​the third auxiliary line (118c). Additionally, the third auxiliary line (118c) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) through a metal layer (MLa) disposed in the fifth via hole (VH5) of the buffer layer (111a).

[0362] The fifth auxiliary line (118e) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) through at least one sixth via hole (VH6) at the other edge portion of the first substrate (100). At least one sixth via hole (VH6) may be formed in a buffer layer (111a) disposed between the other side of the pixel driving power lines (PL) and the intersection area of ​​the fifth auxiliary line (118e). At least one sixth via hole (VH6) may be formed together with at least one fifth via hole (VH5). Additionally, the fifth auxiliary line (118e) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) through a metal layer (MLa) disposed in the sixth via hole (VH6) of the buffer layer (111a).

[0363] A light-emitting display device according to another embodiment of the present specification may further include second auxiliary contact patterns (SPCP). For example, the second auxiliary contact pattern (SPCP) may be represented as a pixel driving power auxiliary contact pattern.

[0364] According to one embodiment, the second auxiliary contact patterns (SPCP) are disposed on the same layer as the pixel driving power lines (PL) and may extend (or expand) toward the outer surface (OS) of the substrate (100) with a relatively wide width from each end of the pixel driving power lines (PL) located at the other edge portion of the substrate (100). According to another embodiment, each of the second auxiliary contact patterns (SPCP) is disposed on the layer below the pixel driving power lines (PL) with a relatively wide width so as to overlap with each end of the pixel driving power lines (PL) located at the other edge portion of the substrate (100), and may be electrically connected to each end of the pixel driving power lines (PL) through an internal contact hole.

[0365] The second auxiliary line (118b) may be electrically (or commonly) connected to the second auxiliary contact patterns (SPCP) through at least one fifth via hole (VH5) at the other edge portion of the first substrate (100). Additionally, the second auxiliary line (118b) may be electrically (or commonly) connected to the second auxiliary contact patterns (SPCP) through a metal layer (MLa) placed in the fifth via hole (VH5) of the buffer layer (111a).

[0366] The third auxiliary line (118c) may be commonly connected to the second auxiliary contact patterns (SPCP) through at least one fifth via hole (VH5) at the other edge portion of the first substrate (100). Additionally, the third auxiliary line (118c) may be electrically (or commonly) connected to the second auxiliary contact patterns (SPCP) through a metal layer (MLa) placed in the fifth via hole (VH5) of the buffer layer (111a).

[0367] The fifth auxiliary line (118e) may be commonly connected to the second auxiliary contact patterns (SPCP) through at least one sixth via hole (VH6) at the other edge portion of the first substrate (100). Additionally, the fifth auxiliary line (118e) may be electrically (or commonly) connected to the second auxiliary contact patterns (SPCP) through a metal layer (MLa) placed in the sixth via hole (VH6) of the buffer layer (111a).

[0368] Accordingly, in another embodiment of the present specification, the light-emitting display device can simultaneously supply pixel driving power to one side and the other side of the pixel driving power lines (PL), thereby further reducing the voltage drop (IR drop) of the pixel driving power due to the line resistance of the pixel driving power line (PL) and thereby further improving the uniformity of the pixel driving power.

[0369] Additionally, in FIGS. 18 to 22, the third auxiliary line (118c) is not electrically connected to the pixel driving power line (PL) and can be implemented to be formed as a closed-loop line in the same way as the first and fourth auxiliary lines (118d) and electrically connected to the pixel common voltage line (CVL).

[0370] FIG. 23 is a drawing for explaining the connection structure between a pixel driving line, a routing unit, and an auxiliary line unit according to another embodiment of the present specification, which is a modified version of the fifth auxiliary lines shown in FIG. 18 to FIG. 22. In describing FIG. 23, only the fifth auxiliary line and the components related thereto will be described, and the remaining components will be given the same reference numerals as in FIG. 18 to FIG. 22, and redundant descriptions thereof will be omitted.

[0371] Referring to FIG. 23, in another embodiment of the present specification, the fifth auxiliary line (118e) may be used as a reference voltage supply line to additionally supply a reference voltage to the reference voltage lines (RL).

[0372] According to one embodiment, the fifth auxiliary line (118e) may be formed to be electrically connected to the first and last reference voltage contact patterns (RCP) among the reference contact patterns (RCP) disposed in the contact pattern portion (110).

[0373] The fifth auxiliary line (118e) can be electrically connected to the first portion of each of the first and last reference voltage routing lines (415) through at least one fifth routing contact hole (CH5). Additionally, the fifth auxiliary line (118e) can be electrically connected to the first and last reference voltage contact patterns (RCP) through a first via hole formed in the buffer layer (111a) disposed on the first and last reference voltage contact patterns (RCP). Additionally, the fifth auxiliary line (118e) can be electrically connected to the first and last reference voltage contact patterns (RCP) through a metal layer disposed in the first via hole of the buffer layer (111a).

[0374] Additionally, the fifth auxiliary line (118e) may be electrically (or commonly) connected to the reference voltage lines (RL) at the other edge portion of the first substrate (100). For example, the fifth auxiliary line (118e) may be electrically (or commonly) connected to the other side of the reference voltage lines (RL) through the sixth via hole (VH6) at the other edge portion of the first substrate (100).

[0375] The fifth auxiliary line (118e) can be maintained at the same potential as the reference voltage lines (RL). By being electrically connected to the reference voltage lines (RL), the voltage drop (IR drop) of the reference voltage due to the line resistance of the reference voltage lines (RL) can be reduced.

[0376] A light-emitting display device according to another embodiment of the present specification may further include third auxiliary contact patterns (SRCP). For example, the third auxiliary contact pattern (SRCP) may be represented as a reference voltage auxiliary contact pattern.

[0377] According to one embodiment, the third auxiliary contact patterns (SRCP) are placed on the same layer as the reference voltage lines (RL) and may extend (or be extended) toward the outer surface (OS) of the substrate (100) with a relatively wide width from each end of the reference voltage lines (RL) located at the other edge portion of the substrate (100). According to another embodiment, each of the third auxiliary contact patterns (SRCP) is placed on the layer below the reference voltage lines (RL) with a relatively wide width so as to overlap with each end of the reference voltage lines (RL) located at the other edge portion of the substrate (100), and may be electrically connected to each end of the reference voltage lines (RL) through an internal contact hole.

[0378] The fifth auxiliary line (118e) may be commonly connected to the third auxiliary contact patterns (SRCP) through at least one sixth via hole (VH6) at the other edge portion of the first substrate (100). Additionally, the fifth auxiliary line (118e) may be electrically (or commonly) connected to the third auxiliary contact patterns (SRCP) through a metal layer placed in the sixth via hole (VH6) of the buffer layer (111a).

[0379] Accordingly, in another embodiment of the present specification, the light-emitting display device can simultaneously supply a reference voltage to one side and the other side of the reference voltage lines (RL), thereby further reducing the voltage drop (IR drop) of the reference voltage due to the line resistance of the reference voltage lines (RL) and thereby further improving the uniformity of the reference voltage.

[0380] FIG. 24 is a drawing for explaining the connection structure between a pixel driving line, a routing unit, and an auxiliary line unit according to another embodiment of the present specification, FIG. 25 is an enlarged view of the 'B6' portion shown in FIG. 24, and FIG. 26 is a cross-sectional view of line VIII-VIII' shown in FIG. 25, which is configured as a pixel common voltage supply line for the auxiliary line unit shown in FIG. 13 to FIG. 17. In describing FIG. 24 to FIG. 26, only the auxiliary line unit and the related configurations will be described, and the remaining configurations will be given the same reference numerals as in FIG. 13 to FIG. 17, and redundant descriptions thereof will be omitted.

[0381] Referring to FIGS. 24 to 26, a light-emitting display device according to another embodiment of the present specification may further include at least one auxiliary connection line (SCL) disposed on a first substrate (100).

[0382] At least one auxiliary connection line (SCL) may be positioned parallel to the second direction (Y) and across the auxiliary line section (118). For example, at least one auxiliary connection line (SCL) may be positioned parallel to the second direction (Y) and across the first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) of the auxiliary line section (118).

[0383] At least one auxiliary connection line (SCL) can be placed on the same layer as the pixel common voltage line (CVL).

[0384] At least one auxiliary connection line (SCL) can be electrically (or commonly) connected to each of the first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) of the auxiliary line section (118).

[0385] At least one auxiliary connection line (SCL) may be electrically (or commonly) connected to each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) through at least one fifth via hole (VH5). At least one fifth via hole (VH5) may be formed in a buffer layer (111a) disposed between each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) and the intersection area of ​​at least one auxiliary connection line (SCL). At least one fifth via hole (VH5) may be formed together with at least one first via hole. Additionally, at least one auxiliary connection line (SCL) may be electrically (or commonly) connected to each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) through a metal layer (MLa) disposed in the fifth via hole (VH5) of the buffer layer (111a).

[0386] At least one auxiliary connection line (SCL) can be electrically connected to the fifth auxiliary line (118e) through at least one sixth via hole (VH6). At least one sixth via hole (VH6) can be formed together with at least one fifth via hole (VH5). Additionally, at least one auxiliary connection line (SCL) can be electrically connected to the fifth auxiliary line (118e) through a metal layer (MLa) placed in the sixth via hole (VH6) of the buffer layer (111a).

[0387] In another embodiment of the present specification, the fourth auxiliary line (118d) may be formed to have a closed-loop line shape on the first substrate (100). For example, the fourth intermediate pattern of the auxiliary pattern portion (116) placed on one edge portion of the first substrate (100) and the fourth auxiliary line (118d) of the auxiliary line portion (118) placed on the remaining edge portion excluding one edge portion of the first substrate (100) may be electrically connected to each other to have a closed-loop line shape. Since such a fourth auxiliary line (118d) is substantially the same as the fourth auxiliary line (118d) described in FIGS. 18 and 19, a redundant description thereof is omitted. For example, in this example, the fourth auxiliary line (118d) may be represented as a closed-loop auxiliary line or a conductive closed-loop line.

[0388] Each of the first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) of the auxiliary line section (118) can be maintained at the same potential as the pixel common voltage lines (CVL), thereby blocking static electricity flowing from the outside into the inside of the display section (AA) and preventing defects caused by static electricity.

[0389] In another embodiment of the present specification, each of the first to fifth auxiliary lines (118a, 118b, 118c, 118d, 118e) of the auxiliary line portion (118) may be electrically (or commonly) connected to the other side of the pixel common voltage lines (CVL) at the other side edge portion of the first substrate (100).

[0390] Each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) may be electrically (or commonly) connected to the other side of the pixel common voltage lines (CVL) through at least one fifth via hole (VH5) at the other side edge portion of the first substrate (100). At least one fifth via hole (VH5) may be formed in a buffer layer (111a) disposed between the other side of each pixel common voltage line (CVL) and the intersection area of ​​each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d). Additionally, each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) can be electrically (or commonly) connected to the other side of the pixel common voltage lines (CVL) through a metal layer disposed in the fifth via hole (VH5) of the buffer layer (111a).

[0391] The fifth auxiliary line (118e) may be electrically (or commonly) connected to the other side of the pixel common voltage lines (CVL) through at least one sixth via hole (VH6) at the other edge portion of the first substrate (100). At least one sixth via hole (VH6) may be formed in a buffer layer (111a) disposed between the other side of each pixel common voltage line (CVL) and the intersection area of ​​each fifth auxiliary line (118e). Additionally, the fifth auxiliary line (118e) may be electrically (or commonly) connected to the other side of the pixel common voltage lines (CVL) through a metal layer disposed in the sixth via hole (VH6) of the buffer layer (111a).

[0392] Accordingly, in another embodiment of the present specification, the light-emitting display device can simultaneously supply a pixel common voltage to one side and the other side of the pixel common voltage lines (CVL) through an auxiliary line section (118), thereby further improving the uniformity of the pixel common voltage. In addition, in another embodiment of the present specification, the light-emitting display device includes a fifth auxiliary line (118e) having a closed-loop line shape on a first substrate (100) and first to fourth auxiliary lines (118a, 118b, 118c, 118d) electrically connected to the fifth auxiliary line (118e), so that defects caused by static electricity introduced from the outside can be further prevented or further minimized.

[0393] FIG. 27 is a drawing for explaining a light-emitting display device according to another embodiment of the present specification, FIG. 28 is a cross-sectional view of line IX-IX' shown in FIG. 27, and FIG. 29 is an enlarged view of the 'B7' portion shown in FIG. 28, which is a modified version of the light-emitting display device shown in FIG. 9 to FIG. 12. In describing FIG. 27 to FIG. 29, only the dam and related components will be described, and the remaining components will be given the same reference numerals as in FIG. 9 to FIG. 12, and redundant descriptions thereof will be omitted.

[0394] Referring to FIGS. 27 to 29, in a light-emitting display device according to another embodiment of the present specification, a dam portion (117) may include a first dam portion (117-1) and a second dam portion (117-2) arranged side by side with each other.

[0395] The first damper (117-1) may be disposed on the circuit layer (111) to have a closed-loop line shape on the second region of the first substrate (100). According to one embodiment, the first damper (117-1) may be disposed on the buffer layer (111a) of the circuit layer (111). The first damper (117-1) serves to primarily block the spreading or overflow of the encapsulation layer (119). Additionally, the first damper (117-1) may also serve to disconnect (or separate) the light-emitting element layer (113).

[0396] The second dam (117-2) may be disposed on the circuit layer (111) to have a closed-loop line shape surrounding the first dam (117-1) on the second region of the first substrate (100). According to one embodiment, the second dam (117-2) may be disposed on the buffer layer (111a) of the circuit layer (111). The second dam (117-2) serves to secondarily block the spreading or overflow of the encapsulation layer (119). Additionally, the first dam (117-1) may also serve to additionally disconnect (or separate) the light-emitting element layer (113).

[0397] Each of the first dam section (117-1) and the second dam section (117-2) according to one embodiment may include a dam trench structure (DTS), a first dam (117a), and a second dam (117b).

[0398] A dam trench structure (DTS) can be placed on a circuit layer (111). According to one embodiment, a dam trench structure (DTS) can be implemented as a stacked structure of an interlayer insulating layer (111c) and a passivation layer (111d) placed in a dam region (DA) of a first substrate (100). The dam trench structure (DTS) can be formed by a patterning process of the interlayer insulating layer (111c) and the passivation layer (111d).

[0399] According to one embodiment, the side of the dam trench structure (DTS) may be implemented as an inclined structure or a regular taper structure. The bottom surface of the dam trench structure (DTS) may be in direct contact with the top surface (or surface) of the buffer layer (111a), and the top surface of the dam trench structure (DTS) may be positioned on the bottom surface of the dam trench structure (DTS) and may have a narrower width than the bottom surface. The side of the dam trench structure (DTS) may be formed at an angle between the top surface and the bottom surface. In the dam trench structure (DTS), the angle between the bottom surface and the side may be acute, and the angle between the top surface and the side may be obtuse. For example, the cross-section of the dam trench structure (DTS) cut along the width direction may have a trapezoidal cross-sectional structure in which the top side is narrower than the bottom side.

[0400] In another embodiment, the dam trench structure (DTS) may be implemented with only the passivation layer (111d) when the interlayer insulating layer (111c) is not placed at the edge portion of the first substrate (100). The dam trench structure (DTS) may be formed by a patterning process of the passivation layer (111d) placed in the second region of the first substrate (100).

[0401] The first dam (or lower dam) (117a) may be placed on the dam trench structure (DTS). The first dam (117a) may have a width greater than the top surface of the dam trench structure (DTS). The first dam (117a) may have a width equal to or greater than the bottom surface of the dam trench structure (DTS). For example, the sides of the first dam (117a) may be implemented as a slanted structure or a regular taper structure. For example, the first dam (117a) cut along the width direction may have a trapezoidal cross-sectional structure identical to that of the dam trench structure (DTS). Based on the width direction, one edge portion and the other edge portion of the first dam (117a) may each protrude outside the side of the dam trench structure (DTS).

[0402] According to one embodiment, the side of the dam trench structure (DTS) may have an undercut structure with respect to the first dam (117a). For example, each of the first dam section (117-1) and the second dam section (117-2) may include an undercut area located at the boundary between the dam trench structure (DTS) and the first dam (117a) or on the upper side of the dam trench structure (DTS). The first dam (117a) may cover the side of the dam trench structure (DTS) by protruding outside the side of the dam trench structure (DTS) due to the undercut structure of the dam trench structure (DTS). Accordingly, the first dam (117a) may have an eaves structure with respect to the dam trench structure (DTS).

[0403] According to one embodiment, the first dam (117a) may have the same height (or thickness) as the leveling layer (112) or may have a higher height than the leveling layer (112). For example, the height (or thickness) of the first dam (117a) may be twice the height (or thickness) of the leveling layer (112).

[0404] A second dam (or upper dam) (117b) may be placed on the first dam (117a). According to one embodiment, the second dam (117b) may be laminated on the first dam (117a) with the same material as the bank (114). For example, the sides of the second dam (117b) may be implemented with a slanted structure or a regular taper structure. For example, the second dam (117b) cut along the width direction may have a trapezoidal cross-sectional structure identical to that of the first dam (117a).

[0405] According to one embodiment, the first dam portion (117-1) and the second dam portion (117-2) can each disconnect (or separate) the light-emitting layer (EL) of the light-emitting element layer (113) or disconnect (or separate) the light-emitting layer (EL) and the common electrode (CE). For example, the light-emitting layer (EL) formed (or deposited) on the dam portion (117) can be automatically disconnected (or separated) during the deposition process by the undercut structure (or eaves structure) of the first dam portion (117-1) and the second dam portion (117-2) respectively, without a separate disconnection process. Accordingly, the light-emitting layer (EL) placed on the first substrate (100) can be disconnected (or separated) twice in the dam area (DA) of the first substrate (100) and may include two disconnection areas (or separation areas). For example, since the deposition material of the light-emitting layer (EL) has directional properties, it is not deposited on the side of the dam trench structure (DTS) that is covered by the first dam (117a) according to the undercut structure (or eaves structure) of each of the first dam (117-1) and the second dam (117-2). Accordingly, the light-emitting layer (EL) formed (or deposited) on the first dam (117-1) and the second dam (117-2) can be disconnected (or separated) between the dam trench structure (DTS) and the first dam (117a). Accordingly, the light-emitting layer (EL) can be automatically cut off (or separated) by the first dam part (117-1) and the second dam part (117-2) of the dam part (117) during the deposition process, and thus a separate patterning process to cut off (or disconnect) the light-emitting layer (EL) placed at the edge portion of the first substrate (100) to prevent lateral moisture penetration can be omitted.

[0406] Optionally, the common electrode (CE) placed on the light-emitting layer (EL) can be formed so that it is automatically disconnected (or separated) by the first dam part (117-1) and the second dam part (117-2) of the dam part (117) during the deposition process according to the deposition method, or is also deposited on the side of the dam trench structure (DTS) covered by the first dam part (117a) so that it is not disconnected (or separated) and continues continuously without a disconnected area.

[0407] In a light-emitting display device according to another embodiment of the present specification, the disconnection portion (115) may be implemented to disconnect (or separate) the light-emitting element layer (113) disposed on a second region of the first substrate (100) at least once.

[0408] A disconnection section (1215) according to one embodiment may include a first disconnection section (115a) that surrounds a dam section (117) while having a closed-loop line shape, and a second disconnection section (115b) that surrounds the dam section (117) in a closed-loop line shape.

[0409] The first section (115a) may include a first trench structure (TS1) and a second trench structure (TS2). Since this first section (115a) is substantially identical to the first section (115a) described in FIGS. 9 to 12, the same reference numeral is assigned to it, and a redundant description thereof is omitted.

[0410] The second section (115b) may include the first trench structure (TS1) and the second trench structure (TS2). Since this second section (115b) is substantially identical to the fourth section (115d) described in FIGS. 9 to 12, a redundant description thereof is omitted.

[0411] In a light-emitting display device according to another embodiment of the present specification, the routing unit (400) may be electrically connected to the contact pattern unit (110) through a routing contact hole (CH) that penetrates at least one of the dam unit (117) and the disconnection unit (115) disposed on the contact pattern unit (110). Since this routing unit (400) is substantially identical to the routing unit (400) described in FIGS. 9 to 12, except that it is electrically connected to the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern unit (110) through routing contact holes (CH1, CH2, CH3, CH4) that penetrate the first dam unit (117-1) and the second dam unit (117-2) of the dam unit (117) and the first and second disconnection units (115a, 115b) of the disconnection unit (115), a redundant description thereof is omitted.

[0412] Additionally, the routing section (400) can be electrically connected to the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern section (110) only through the first and second routing contact holes (CH1, CH2) that penetrate the first dam section (117-1) and the second dam section (117-2) of the dam section (117), respectively, in this case, the third and fourth routing contact holes (CH3, CH4) that penetrate the first and second disconnect sections (115a, 115b) of the disconnect section (115), respectively, can be omitted.

[0413] In a light-emitting display device according to another embodiment of the present specification as such, the overflow of the encapsulation layer (119) can be more reliably prevented by the first dam portion (117-1) and the second dam portion (117-2) of the dam portion (117), and the light-emitting element layer (113) can be cut (or separated) by the undercut structure of each of the first dam portion (117-1) and the second dam portion (117-2) of the dam portion (117), thereby minimizing the number of cut portions (115).

[0414] FIG. 30 is a drawing for explaining a light-emitting display device according to another embodiment of the present specification, FIG. 31 is a cross-sectional view of line X-X' shown in FIG. 27, and FIG. 32 is an enlarged view of the 'B8' portion shown in FIG. 31, which additionally configures an auxiliary line section in the light-emitting display device shown in FIG. 27 to 29. In describing FIG. 30 to 32, only the auxiliary line section and the configurations related thereto will be described, and the remaining configurations will be given the same reference numerals as in FIG. 27 to 29, and redundant descriptions thereof will be omitted.

[0415] Referring to FIGS. 30 to 32, a light-emitting display device according to another embodiment of the present specification may further include an auxiliary pattern section (116) disposed between a contact pattern section (110) connected to pixel driving lines (PL, DL, RL, GCL, CVL) and a routing section (400). Since this auxiliary pattern section (116) has substantially the same structure as the auxiliary pattern section (116) shown in FIGS. 13 to 16, a redundant description thereof is omitted or brief.

[0416] The auxiliary pattern portion (116) according to the present example may include first to fourth intermediate patterns (116a, 116b, 116c, 116d) that are disposed on one edge portion of the first substrate (100) and are electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) of the contact pattern portion (110) and the routing lines (410) of the routing portion (400).

[0417] Each of the first and second intermediate patterns (116a, 116b) can be placed in the dam (117).

[0418] The first intermediate pattern (116a) may be placed in the first dam section (117-1) of the dam section (117). For example, the first intermediate pattern (116a) may be placed between the dam trench structure (DTS) of the first dam section (117-1) and the first dam (117a) and may be electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410).

[0419] The second intermediate pattern (116b) may be placed in the second dam section (117-2) of the dam section (117). For example, the second intermediate pattern (116b) may be placed between the dam trench structure (DTS) of the second dam section (117-2) and the first dam (117a) and may be electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410).

[0420] Each of the third and fourth intermediate patterns (116c, 116d) can be placed in the disconnection section (115).

[0421] The third intermediate pattern (116c) may be placed on the first disconnect structure (115a) of the disconnect section (115). For example, the third intermediate pattern (116c) may be placed on the first trench structure (TS1) of the first disconnect structure (115a) and electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410).

[0422] The fourth intermediate pattern (116d) may be placed on the second disconnect structure (115b) of the disconnect section (115). For example, the fourth intermediate pattern (116d) may be placed on the first trench structure (TS1) of the second disconnect structure (115b) and electrically connected between the contact patterns (PCP, DCP, RCP, GCP, CCP) and the routing lines (410).

[0423] Each of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) can prevent electrical or physical contact failure between the contact pattern (PCP, DCP, RCP, GCP, CCP) and the routing line (410) that may occur depending on the distance between the contact pattern (PCP, DCP, RCP, GCP, CCP) and the routing line (410).

[0424] Each of the first to fourth intermediate patterns (116a, 116b, 116c, 116d) according to the present example may include a first metal layer (MLa) and a second metal layer (MLb).

[0425] According to one embodiment, a first metal layer (MLa) may be implemented on a buffer layer (111a) to be electrically connected to contact patterns (PCP, DCP, RCP, GCP, CCP). For example, the first metal layer (MLa) may be placed on a buffer layer (111a) that overlaps with contact patterns (PCP, DCP, RCP, GCP, CCP) and may be electrically connected to contact patterns (PCP, DCP, RCP, GCP, CCP) through a first via hole (VH1) penetrating the buffer layer (111a). According to one embodiment, the first metal layer (MLa) may be implemented in the form of a point that overlaps with contact patterns (PCP, DCP, RCP, GCP, CCP) or in the form of a line that intersects contact patterns (PCP, DCP, RCP, GCP, CCP) along a first direction (X). According to one embodiment, the first metal layer (MLa) may be implemented with the same material and structure as the gate electrode of the TFTs (Tdr) placed in the pixel area (PA) or with the same material and structure as the source / drain electrode.

[0426] The second metal layer (MLb) can be implemented to be electrically connected between the first metal layer (MLa) and the routing lines (410). For example, the second metal layer (MLb) may be placed on a passivation layer (111d) that overlaps the first metal layer (MLa) and may be electrically connected to the first metal layer (MLa) through a second via hole (VH2) that passes through the passivation layer (111d) and the interlayer insulation layer (111c) in sequence. According to one embodiment, the second metal layer (MLb) may be implemented in the same dot form as the first metal layer (MLa) or in the same line form. According to one embodiment, the second metal layer (MLa) may be implemented with the same material and structure as the pixel electrode (PE) placed in the pixel area (PA).

[0427] The second metal layer (MLb) of each of the first and second intermediate patterns (116a, 116b) can improve adhesion between the dam trench structure (DTS) of the dam section (117) and the first dam (117a). The second metal layer (MLb) of each of the third and fourth intermediate patterns (116c, 116d) can improve adhesion between the first trench structure (TS1) and the second trench structure (TS2) of the disconnection section (115).

[0428] A light-emitting display device according to another embodiment of the present specification may further include an auxiliary line section (118) disposed in each of a disconnection section (115) and a damp section (117) disposed in the remaining edge portions excluding one edge portion of the first substrate (100). Since this auxiliary line section (118) has substantially the same structure as the auxiliary line section (118) shown in FIG. 13, FIG. 14, and FIG. 17, a redundant description thereof is omitted or brief.

[0429] The auxiliary line section (118) according to the present example may include first to fourth auxiliary lines (118a, 118b, 118c, 118d) arranged in the disconnection section (115) and the dam section (117).

[0430] Each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) may be electrically floating. Each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) according to one embodiment may be implemented with the same material and structure as the pixel electrode (PE) placed in the pixel area (PA). For example, each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) may be formed together with the second metal layer (MLb) of the auxiliary pattern portion (116).

[0431] Each of the first and second auxiliary lines (118a, 118b) can be placed in the dam (117).

[0432] The first auxiliary line (118a) may be placed in the first dam section (117-1) of the dam section (117). For example, the first auxiliary line (118a) may be placed between the dam trench structure (DTS) of the first dam section (117-1) and the first dam (117a).

[0433] The second auxiliary line (118b) may be placed in the second dam section (117-2) of the dam section (117). For example, the second auxiliary line (118b) may be placed between the dam trench structure (DTS) of the second dam section (117-2) and the first dam (117a).

[0434] The first and second auxiliary lines (118a, 118b) can improve adhesion between the dam trench structure (DTS) of the dam section (117) and the first dam (117a).

[0435] Each of the third and fourth auxiliary lines (118c, 118d) can be placed in the disconnection section (115).

[0436] The third auxiliary line (118c) may be placed on the first disconnect structure (115a) of the disconnect section (115). For example, the third auxiliary line (118c) may be placed on the first trench structure (TS1) of the first disconnect structure (115a).

[0437] The fourth auxiliary line (118d) may be placed on the second disconnect structure (115b) of the disconnect section (115). For example, the fourth auxiliary line (118d) may be placed on the first trench structure (TS1) of the second disconnect structure (115b).

[0438] Each of the third and fourth auxiliary lines (118c, 118d) can improve the adhesion between the first trench structure (TS1) and the second trench structure (TS2) of the disconnection section (115).

[0439] A light-emitting display device according to another embodiment of the present specification, as described above, can prevent electrical or physical contact failure between the contact pattern (PCP, DCP, RCP, GCP, CCP) and the routing line (410) by further including an auxiliary pattern portion (116) disposed between the contact pattern (PCP, DCP, RCP, GCP, CCP) and the routing line (410).

[0440] Additionally, in a light-emitting display device according to another embodiment of the present specification, the auxiliary line section (118) can be used as a signal supply line, as in the light-emitting display device shown in FIGS. 18 to 26.

[0441] According to one embodiment, each of the first and second auxiliary lines (118a, 118b) may be electrically connected to the first and last pixel driving power lines (PL) among the pixel driving power lines (PL) at one side (or one side corner portion) and the other side (or the other side corner portion) of the one side edge portion of the first substrate (100), as shown in FIGS. 18 to 22, and may be electrically connected to the first portion (410a) of each of the first and last pixel driving power routing lines (411) through at least one routing contact hole (CH1, CH2). Additionally, each of the first and second auxiliary lines (118a, 118b) may be electrically (or commonly) connected to the other side of the pixel driving power lines (PL) at the other side edge portion of the first substrate (100). Accordingly, as the pixel driving power lines (PL) are connected to the first and second auxiliary lines (118a, 118b), the voltage drop (IR drop) of the reference voltage due to the line resistance of the pixel driving power lines (PL) is reduced, and thereby the uniformity of the pixel driving power can be improved.

[0442] According to one embodiment, each of the third and fourth auxiliary lines (118c, 118d) may be formed to have a closed-loop line shape on the first substrate (100), as shown in FIGS. 18 to 22. Each of the third and fourth auxiliary lines (118c, 118d) may be electrically connected to the pixel common voltage lines (CVL) at one edge portion of the first substrate (100) and may be electrically connected only to the first portion (410a) of each of the pixel common voltage routing lines (419) through at least one routing contact hole (CH3, CH4). Additionally, each of the third and fourth auxiliary lines (118c, 118d) may be electrically (or commonly) connected to the other side of the pixel common voltage lines (CVL) at the other edge portion of the first substrate (100). Accordingly, each of the third and fourth auxiliary lines (118c, 118d) can be maintained at the same potential as the pixel common voltage lines (CVL), thereby blocking static electricity flowing from the outside into the inside of the display unit (AA) and preventing defects caused by static electricity.

[0443] According to one embodiment, either of the first and second auxiliary lines (118a, 118b) or the fourth auxiliary line (118d) may be formed to be electrically connected to the first and last reference voltage contact patterns (RCPs) among the reference contact patterns (RCPs) disposed in the contact pattern portion (110) as shown in FIG. 23. Additionally, either of the first and second auxiliary lines (118a, 118b) or the fourth auxiliary line (118d) may be electrically (or commonly) connected to the other side of the reference voltage lines (RL) at the other edge portion of the first substrate (100). Accordingly, as the reference voltage lines (RL) are connected to either of the first and second auxiliary lines (118a, 118b) or the fourth auxiliary line (118d), the voltage drop (IR drop) of the reference voltage due to the line resistance of the reference voltage lines (RL) is reduced, and the uniformity of the reference voltage can be improved.

[0444] According to one embodiment, each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) may be electrically (or commonly) connected to each other through an auxiliary connection line (SCL), as shown in FIGS. 24 to 26. Additionally, the fourth auxiliary line (118c) may be formed to have a closed-loop line shape on the first substrate (100) and may be formed to be electrically connected only to pixel common voltage contact patterns (CCPs) disposed on the contact pattern portion (110). Accordingly, each of the first to fourth auxiliary lines (118a, 118b, 118c, 118d) may be maintained at the same potential as the pixel common voltage lines (CVL), thereby blocking static electricity flowing from the outside into the inside of the display portion (AA) and preventing defects caused by static electricity.

[0445] FIG. 33 is a drawing showing a multi-screen display device according to one embodiment of the present specification, and FIG. 34 is a cross-sectional view along line XI-XI' shown in FIG. 33, which shows a multi-screen display device implemented by tiling the light-emitting display devices according to the embodiments of the present specification shown in FIG. 1 to FIG. 30.

[0446] Referring to FIGS. 33 and 34, a multi-screen display device (or tiling display device) according to one embodiment of the present specification may include a plurality of display modules (DM1, DM2, DM3, DM4).

[0447] Each of the plurality of display modules (DM1, DM2, DM3, DM4) can display individual images or divide and display a single image. Each of these plurality of display modules (DM1, DM2, DM3, DM4) includes a light-emitting display device according to the embodiment of the present specification illustrated in FIGS. 1 to 30, and a redundant description thereof may be omitted. Each of the plurality of display modules (DM1, DM2, DM3, DM4) illustrated in FIG. 34 represents a light-emitting display device illustrated in FIGS. 13 to 17, but is not limited thereto.

[0448] Each of the multiple display modules (DM1, DM2, DM3, DM4) can be tiled on a separate tiling frame so that their sides are in contact with each other. For example, each of the multiple display modules (DM1, DM2, DM3, DM4) can be tiled to have an N×M shape to implement a large-screen multi-screen display device. For example, N can be a positive integer greater than or equal to 1, and M can be a positive integer greater than or equal to 2. For example, N can be a positive integer greater than or equal to 2, and M can be a positive integer greater than or equal to 1.

[0449] Each of the plurality of display modules (DM1, DM2, DM3, DM4) does not include a bezel area (or non-display area) surrounding the entire display portion (AA) where an image is displayed, and has an air-bezel structure in which the display portion (AA) is surrounded by air. That is, for each of the plurality of display modules (DM1, DM2, DM3, DM4), the entire first surface of the first substrate (100) can be implemented as the display portion (AA).

[0450] According to the present example, in each of the plurality of display modules (DM1, DM2, DM3, DM4), the second gap (D2) between the center (CP) of the outermost pixel (Po) and the outermost outer surface (VL) of the first substrate (100) is implemented to be less than half of the first gap (D1) (or pixel pitch) between adjacent pixels. Accordingly, in two adjacent display modules (DM1, DM2, DM3, DM4) that are connected (or in contact) side by side along the first direction (X) and the second direction (Y) according to the side coupling method, the gap (D2+D2) between adjacent outermost pixels (Po) becomes equal to or smaller than the first gap (D1) between two adjacent pixels. For example, in FIG. 34, in a first display module (DM1) and a third display module (DM3) that are connected (or in contact) side by side along a second direction (Y), the gap (D2+D2) between the center (CP) of the outermost pixel (Po) of the first display module (DM1) and the center (CP) of the outermost pixel (Po) of the third display module (DM3) may be equal to or smaller than the first gap (D1) (or pixel pitch) between two adjacent pixels placed in each of the first display module (DM1) and the third display module (DM3).

[0451] Accordingly, since the gap (D2+D2) between the center (CP) of the outermost pixel (Po) of each of two adjacent display modules (DM1, DM2, DM3, DM4) that are connected (or in contact) side by side along the first direction (X) and the second direction (Y) is equal to or smaller than the first gap (D1) between two adjacent pixels placed in each display module (DM1, DM2, DM3, DM4), there is no boundary or seam between two adjacent display modules (DM1, DM2, DM3, DM4), and as a result, there is no dark area caused by the boundary provided between multiple display modules (DM1, DM2, DM3, DM4). Consequently, an image displayed on a multi-screen display device in which each of the multiple display modules (DM1, DM2, DM3, DM4) is tiled in an N×M shape can be displayed continuously without a sense of discontinuity (or break) at the boundary between the multiple display modules (DM1, DM2, DM3, DM4).

[0452] FIGS. 33 and 34 show a plurality of display modules (DM1, DM2, DM3, DM4) tiled in a 2×2 shape, but are not limited thereto, and the plurality of display modules (DM1, DM2, DM3, DM4) may be tiled in an x×1 shape, a 1×y shape, or an x×y shape. Here, x and y may be two or more natural numbers that are the same or different from each other.

[0453] The multi-screen display device according to the present specification can display a single image on a single screen using a display portion (AA) of each of the plurality of display modules (DM1, DM2, DM3, DM4), and can display a continuously connected image without being interrupted at the boundary portion between the plurality of display modules (DM1, DM2, DM3, DM4), thereby improving the immersion of the viewer watching the image displayed on the multi-screen display device.

[0454] A light-emitting display device according to the examples of the present specification may be applied to any electronic device including a light-emitting display panel. For example, a light-emitting display device according to the present specification may be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic notebooks, e-books, PMPs (portable multimedia players), PDAs (personal digital assistants), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, in-vehicle navigation systems, in-vehicle display devices, televisions, wallpaper display devices, signage devices, game devices, laptops, monitors, cameras, camcorders, and home appliances, etc.

[0455] Features, structures, effects, etc. described in the various examples of this specification described above are included in at least one example of this specification and are not necessarily limited to only one example. Furthermore, features, structures, effects, etc. exemplified in at least one example of this specification may be combined or modified and implemented in other embodiments by a person skilled in the art to which the technical concept of this specification belongs. Accordingly, contents related to such combinations and modifications should be interpreted as being included within the technical scope or scope of rights of this specification.

[0456] It will be obvious to those skilled in the art that the specification described above is not limited to the aforementioned embodiments and attached drawings, and that various substitutions, modifications, and changes are possible within the scope of the technical concept of the specification. Therefore, the scope of the specification is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the specification. Explanation of the symbols

[0457] 10: Light-emitting display device 100: Substrate or first substrate 110: Contact pattern section 111: Circuit layer 111a: Buffer layer 111c: Interlayer insulation layer 111d: Passivation layer 112: Flattening layer 113: Light-emitting element layer 114: Bank 115: Disconnection section 116: Auxiliary pattern section 117: Dam Pattern Section 118: Auxiliary Line Section 119: Encapsulation layer 200: Second substrate 210: 1st pad section 230: 2nd pad section 300: Connecting member 500: Driving circuit part

Claims

Claim 1 A light-emitting display device comprising: a substrate; a display portion having pixel regions disposed on the substrate; a circuit layer having pixel driving lines disposed on the pixel regions; a light-emitting element layer having a light-emitting layer disposed on the circuit layer of the pixel regions; an encapsulation layer disposed on the light-emitting element layer; and a routing portion provided on the encapsulation layer, having routing lines that surround the front edge portion and outer surface of the substrate and penetrate the encapsulation layer disposed on the front edge portion of the substrate and are connected to the pixel driving lines. Claim 2 A light-emitting display device according to claim 1, further comprising a contact pattern portion including contact patterns disposed on the circuit layer and connected to the pixel driving lines, wherein the routing lines pass through the encapsulation layer disposed on the edge portion of the substrate and are electrically directly connected to the contact patterns. Claim 3 In claim 2, each of the contact patterns is disposed on the same layer as the pixel driving lines and extends from each of the pixel driving lines, a light-emitting display device. Claim 4 A light-emitting display device according to claim 2, further comprising auxiliary patterns electrically connected between the contact patterns and the routing lines. Claim 5 A light-emitting display device according to claim 4, wherein each of the auxiliary patterns comprises: a first metal layer electrically connected to the contact pattern; and a second metal layer disposed on the first metal layer and electrically connected to the routing line. Claim 6 In claim 4, the circuit layer further comprises: a buffer layer disposed on the pixel driving lines and the contact patterns; and at least one insulating layer disposed on the buffer layer; the auxiliary pattern comprises: a first metal layer disposed on the buffer layer overlapping the contact patterns and electrically connected to the contact patterns through a first via hole formed in the buffer layer; and a second metal layer disposed on the at least one insulating layer overlapping the first metal layer and electrically connected to the first metal layer through a second via hole formed in the at least one insulating layer; and the routing lines are electrically connected to the second metal layer of the auxiliary pattern through a routing contact hole passing through the encapsulation layer, a light-emitting display device. Claim 7 A light-emitting display device according to claim 2, further comprising a dam portion disposed on the circuit layer along the edge portion of the substrate, wherein the encapsulation layer comprises: a first encapsulation layer disposed on the light-emitting element layer and the dam portion; a second encapsulation layer disposed on the first encapsulation layer and surrounded by the dam portion; and a third encapsulation layer disposed on the second encapsulation layer and the first encapsulation layer on the dam portion, wherein the routing lines are electrically connected to the contact patterns through routing contact holes passing through the third encapsulation layer, the first encapsulation layer, and the dam portion. Claim 8 A light-emitting display device according to claim 7, further comprising auxiliary patterns disposed in the dam portion and electrically connected between the contact patterns and the routing lines. Claim 9 A light-emitting display device according to claim 7, wherein the dam portion comprises: a first dam portion disposed on the circuit layer along the edge portion of the substrate; and a second dam portion disposed on the circuit layer to surround the first dam portion, wherein the routing lines are electrically connected to the contact patterns through at least one first routing contact hole passing through the third encapsulation layer, the first encapsulation layer, and the first dam portion, and are electrically connected to the contact patterns through at least one second routing contact hole passing through the third encapsulation layer, the first encapsulation layer, and the second dam portion. Claim 10 A light-emitting display device according to claim 9, further comprising auxiliary patterns disposed in each of the first dam portion and the second dam portion and electrically connected between the contact patterns and the routing lines. Claim 11 A light-emitting display device according to claim 9, wherein each of the first dam portion and the second dam portion comprises: a dam trench structure disposed on the circuit layer; a first dam disposed on the dam trench structure; a second dam disposed on the first dam; and an undercut area disposed at the boundary between the dam trench structure and the first dam. Claim 12 A light-emitting display device according to claim 2, further comprising: a dam portion disposed on the circuit layer along the edge portion of the substrate; and a disconnecting portion disposed on the circuit layer along the edge portion of the substrate and disconnecting the light-emitting layer, wherein the encapsulation layer comprises: a first encapsulation layer disposed on the light-emitting element layer, the dam portion, and the disconnecting portion; a second encapsulation layer disposed on the first encapsulation layer and surrounded by the dam portion; and a third encapsulation layer disposed on the first encapsulation layer on the second encapsulation layer and the dam portion, wherein the routing lines are electrically connected to the contact patterns through routing contact holes that pass through the third encapsulation layer and the first encapsulation layer and additionally pass through at least one of the dam portion and the disconnecting portion. Claim 13 In claim 12, the disconnection portion comprises at least one disconnection structure disposed on the circuit layer along the edge portion of the substrate, wherein the at least one disconnection structure comprises: a first trench structure disposed on the circuit layer; a second trench structure disposed on the first trench structure; and an undercut region disposed at the boundary between the first trench structure and the second trench structure, a light-emitting display device. Claim 14 A light-emitting display device according to claim 12, further comprising auxiliary patterns disposed in at least one of the dam portion and the disconnect portion and electrically connected between the contact patterns and the routing lines. Claim 15 A light-emitting display device according to claim 14, wherein each of the auxiliary patterns comprises: a first metal layer electrically connected to the contact pattern; and a second metal layer disposed on the first metal layer and electrically connected to the routing line. Claim 16 A light-emitting display device according to claim 14, further comprising an auxiliary line portion disposed on the remaining edge portion excluding one edge portion of the substrate on which the contact patterns are disposed, wherein the auxiliary line portion comprises an auxiliary line disposed on at least one of the dam portion and the disconnect portion. Claim 17 In claim 16, the pixel driving lines include a data line, a pixel driving power line, and a pixel common voltage line, and the auxiliary line is electrically connected to the pixel driving power line or the pixel common voltage line, a light-emitting display device. Claim 18 A light-emitting display device according to claim 14, further comprising an auxiliary line portion disposed on an edge portion of the substrate, wherein the auxiliary line portion comprises: a plurality of auxiliary lines disposed on the remaining edge portion excluding one edge portion of the substrate on which the contact patterns are disposed; and at least one closed-loop line disposed in the form of a closed-loop line along the edge portion of the substrate. Claim 19 In claim 18, the pixel driving lines include a data line, a pixel driving power line, and a pixel common voltage line, and the at least one closed-loop line is electrically connected to the pixel common voltage line, a light-emitting display device. Claim 20 In claim 19, the plurality of auxiliary lines are electrically connected to the pixel driving power line, in a light-emitting display device. Claim 21 A light-emitting display device according to claim 19, further comprising an auxiliary connection line commonly connected to the plurality of auxiliary lines and the at least one closed-loop line. Claim 22 A light-emitting display device according to claim 1, wherein the size of the display portion is the same as the size of the substrate. Claim 23 A multi-screen display device comprising a plurality of display modules arranged along at least one of a first direction and a second direction crossing the first direction, wherein each of the plurality of display modules includes a light-emitting display device according to any one of claims 1 to 22. Claim 24 In claim 23, in each of the plurality of display modules, the display unit comprises a plurality of pixels arranged to have a pixel pitch along the first direction and the second direction, wherein the pixel pitch is the distance between the centers of adjacent pixels along the first direction and the second direction, and in the first display module and the second display module adjacent along the first direction and the second direction, the distance between the center of the outermost pixel of the first display module and the center of the outermost pixel of the second display module is equal to or smaller than the pixel pitch, a multi-screen display device.

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