NANO rod emitting element and display device comprising the same

Abstract

A nano rod light-emitting device according to one embodiment of the present invention may include a rod-shaped first semiconductor layer, a first active layer covering a portion of a side extending from the upper surface of the first semiconductor layer, a second semiconductor layer covering the first active layer, a second active layer covering a portion of a side extending from the lower surface of the first semiconductor layer and spaced apart from the first active layer, and a third semiconductor layer covering the second active layer and spaced apart from the second semiconductor layer.

Description

Technology Field

[0001] The present invention relates to a nanorod light-emitting element and a display device including the same, and more specifically, to a nanorod light-emitting element capable of a repair process and a display device including the same. Background Technology

[0002] Display devices used in computer monitors, TVs, mobile phones, etc., include Organic Light Emitting Displays (OLEDs) that emit light on their own, and Liquid Crystal Displays (LCDs) that require a separate light source.

[0003] The application range of display devices is expanding to include not only computer monitors and TVs but also personal portable devices, and research is underway on display devices that have a large display area while possessing reduced volume and weight.

[0004] Furthermore, recently, display devices including LEDs are attracting attention as next-generation display devices. Since LEDs are composed of inorganic materials rather than organic ones, they offer superior reliability and a longer lifespan compared to liquid crystal displays or organic light-emitting diodes (OLEDs). In addition, LEDs not only have fast lighting speeds but also excellent luminous efficiency and strong shock resistance, ensuring high stability and the ability to display high-brightness images. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a nanorod light-emitting element capable of improving luminance uniformity and luminous efficiency by controlling the number of light sources within a subpixel, and a display device including the same.

[0006] Another problem that the present invention aims to solve is to provide a nano-rod light-emitting element and a display device including the same, which can reduce the manufacturing cost of a display device by reducing the process steps consumed in the repair process.

[0007] The problems of the present invention are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0008] A nano rod light-emitting device according to one embodiment of the present invention may include a rod-shaped first semiconductor layer, a first active layer covering a portion of a side extending from the upper surface of the first semiconductor layer, a second semiconductor layer covering the first active layer, a second active layer covering a portion of a side extending from the lower surface of the first semiconductor layer and spaced apart from the first active layer, and a third semiconductor layer covering the second active layer and spaced apart from the second semiconductor layer.

[0009] A display device according to another embodiment of the present invention may include a substrate comprising a display area including a plurality of subpixels and a non-display area surrounding the display area, a first transistor disposed on the substrate, a planarization layer disposed on the first transistor, a first alignment wiring disposed on the planarization layer, a second alignment wiring located on both sides of the first alignment wiring, a first insulating layer disposed to cover the second alignment wiring, a nanorod light-emitting element disposed on the first alignment wiring and the first insulating layer, a second insulating layer disposed on the nanorod light-emitting element and exposing one of a second semiconductor layer and a third semiconductor layer, and a first connecting wiring connecting the first transistor and one semiconductor layer.

[0010] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0011] The present invention can self-align a plurality of light-emitting elements at specific locations on a substrate.

[0012] The present invention can improve brightness uniformity by forming two light-emitting regions in a single light-emitting element and selectively using the two light-emitting regions.

[0013] In the present invention, by placing a first electrode in the center of a light-emitting element and placing a plurality of second electrodes on both sides of the light-emitting element, repair configuration can be facilitated and the process steps consumed in the repair process can be reduced.

[0014] The effects according to the present invention are not limited to those exemplified above, and a wider variety of effects are included within the present invention. Brief explanation of the drawing

[0015] FIGS. 1a to 1j are process diagrams for explaining a method for manufacturing a light-emitting element according to one embodiment of the present invention. FIG. 2 is a perspective view of a light-emitting element according to another embodiment of the present invention. FIG. 3 is a schematic plan view of a display device according to one embodiment of the present invention. FIGS. 4a to 4d are drawings for explaining a method of manufacturing a display device according to an embodiment of the present invention. FIG. 5 is a plan view of a display device according to one embodiment of the present invention. Figure 6 is a cross-sectional view along VI-VI' of Figure 5. FIG. 7 is a plan view of a display device according to another embodiment of the present invention. FIG. 8 is a cross-sectional view according to VIII-VIII' of FIG. 7. FIG. 9 is a plan view of a display device according to another embodiment of the present invention. FIG. 10 is a cross-sectional view according to IX-IX' of FIG. 9. FIG. 11 is a plan view of a display device according to another embodiment of the present invention. FIG. 12 is a cross-sectional view along XI-XI' of FIG. 11. Specific details for implementing the invention

[0016] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0017] Shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the depicted details. Throughout the specification, the same reference numerals refer to the same components. Furthermore, in describing the present invention, if it is determined that a detailed description of related prior art may unnecessarily obscure the essence of the present invention, such detailed description is omitted. Where terms such as "includes," "has," or "is made up" are used in the present invention, other parts may be added unless "only" is used. When a component is expressed in the singular, it includes cases where it is included in the plural unless specifically stated otherwise.

[0018] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0019] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0020] When an element or layer is referred to as "on" another element or layer, it includes cases where another layer or element is placed directly on top of or in between.

[0021] Additionally, terms such as first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0022] Throughout the specification, the same reference numerals refer to the same components.

[0023] The area and thickness of each component shown in the drawings are illustrated for convenience of explanation, and the present invention is not necessarily limited to the area and thickness of the illustrated components.

[0024] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0025] The present invention will be described below with reference to the drawings.

[0026] FIGS. 1a to 1j are process diagrams for explaining a method for manufacturing a light-emitting element of a display device according to one embodiment of the present invention.

[0027] Referring to FIG. 1a, a buffer layer (BF) and an insulating film (IL) are formed on a growth substrate (WF). The buffer layer (BF) covers the growth substrate (WF) to prevent moisture or impurities from the growth substrate (WF) from diffusing into an upper structure. The buffer layer (BF) can be formed by Metal Organic Chemical Vapor Deposition (MOCVD). Then, an insulating film (IL) is formed on the buffer layer (BF). The insulating film (IL) may include a plurality of holes. That is, the insulating film (IL) can be patterned and placed on the buffer layer (BF). Accordingly, the upper surface of the buffer layer (BF) may be partially exposed by the holes in the insulating film (IL).

[0028] Referring to FIG. 1b, a first semiconductor layer (131) is formed on the upper surface of a buffer layer (BF) exposed from a hole in an insulating film (IL). For example, the first semiconductor layer (131) can be formed by growing a rod-shaped semiconductor crystal of the material forming the first semiconductor layer (131) using Metal Organic Chemical Vapor Deposition (MOCVD).

[0029] The first semiconductor layer (131) may be a layer formed by doping an n-type impurity into a specific material. The first semiconductor layer (131) may be a layer in which n-type impurities are doped into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc., but is not limited thereto.

[0030] Referring to FIG. 1c, an active material layer (132m) can be formed on the first semiconductor layer (131). The active material layer (132m) can be positioned to surround the upper surface and side surface of the first semiconductor layer (131). The active material layer (132m) can be formed as a single layer or a multi-quantum well (MQW) structure, and can be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto. The active material layer (132m) can be formed, for example, by metal organic chemical vapor deposition (MOCVD). In this case, the active material layer (132m) can grow by inheriting the crystallinity of the first semiconductor layer (131).

[0031] Referring to FIG. 1d, a second semiconductor material layer (133m) is formed on an active material layer (132m). The second semiconductor material layer (133m) may be positioned to surround the upper surface and side surface of the active material layer (132m). The second semiconductor material layer (133m) may be a layer formed by doping a specific material with p-type impurities. For example, the second semiconductor material layer (133m) may be a layer in which p-type impurities are doped into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The p-type impurities may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., but are not limited thereto. For example, the second semiconductor material layer (133m) may be formed by Metal Organic Chemical Vapor Deposition (MOCVD). Accordingly, the second semiconductor material layer (133m) can grow by inheriting the crystallinity of the active material layer (132m).

[0032] Referring to FIG. 1e, a first temporary protective layer (PR1) is formed on a growth substrate (WF) in a portion where the first semiconductor layer (131), the active material layer (132m), and the second semiconductor material layer (133m) are not disposed. The first temporary protective layer (PR1) may be formed, for example, by coating a photoresist (PR) and etching it by an ashing process, but is not limited thereto. At this time, the first temporary protective layer (PR1) is disposed to cover only a portion of the side extending from the lower surface of the second semiconductor material layer (133m).

[0033] Referring to FIG. 1f, a mask (MS) is formed on a first temporary protective layer (PR1) and a second semiconductor material layer (133m). The mask (MS) is formed on a side portion and an upper surface of the second semiconductor material layer (133m) exposed from the first temporary protective layer (PR1). For example, the mask (MS) may be made of silicon oxide (SiO2).

[0034] Referring to FIG. 1g, the first temporary protective layer (PR1) placed between the insulating film (IL) and the mask (MS) is removed. Accordingly, a portion of the side extending from the upper surface of the insulating film (IL) and the lower surface of the second semiconductor material layer (133m) may be exposed.

[0035] Referring to FIG. 1h, a second temporary protective layer (PR2) is formed again on the insulating film (IL). At this time, the second temporary protective layer (PR2) is formed with a height that exposes a portion of the side of the second semiconductor material layer (133m).

[0036] Referring to FIG. 1h, a second temporary protective layer (PR2) is formed on the insulating film (IL). At this time, the second temporary protective layer (PR2) is formed with a height that exposes a portion of the side of the second semiconductor material layer (133m).

[0037] Referring to FIG. 1i, a portion of the side of the second semiconductor material layer (133m) exposed from the second temporary protective layer (PR2) and the mask (MS), and a portion of the side of the active material layer (132m) overlapping with the exposed second semiconductor material layer (133m) are removed. The method of removing the second semiconductor material layer (133m) and the active material layer (132m) may, for example, use an inductively coupled plasma (IPC) etching method, but is not limited thereto. Accordingly, the second semiconductor material layer (133m) can be separated into a second semiconductor layer (133a) and a third semiconductor layer (133b), and the active material layer (132m) can be separated into a first active layer (132a) and a second active layer (132b).

[0038] Next, by removing the second temporary protective layer (PR2) and separating the first semiconductor layer (131), the first active layer (132a), the second active layer (132b), the second semiconductor layer (133a), and the third semiconductor layer (133b) disposed on the growth substrate (WF) from the growth substrate (WF), a nano rod light-emitting device (130) as illustrated in FIG. 1J can be formed. Specifically, by removing the second temporary protective layer (PR2) and cutting the first semiconductor layer (131) based on the boundary between the insulating film (IL), the second active layer (132b), and the third semiconductor layer (133b), a rod-shaped nano rod light-emitting device (130) can be formed.

[0039] Referring to FIG. 1J, the light-emitting element (130) may be a dumbbell-shaped nanorod light-emitting element (130) comprising a first semiconductor layer (131), a first active layer (132a), a second active layer (132b), a second semiconductor layer (133a) and a third semiconductor layer (133b).

[0040] The first active layer (132a) covers a portion of the side extending from the upper surface of the first semiconductor layer (131) and covers the entire upper surface of the first semiconductor layer (131). The first active layer (132a) can emit light by receiving holes and electrons from the first semiconductor layer (131), the second semiconductor layer (133a), and the third semiconductor layer (133b). The first active layer (132a) may be formed as a single layer or a multi-quantum well (MQW) structure, and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0041] The second active layer (132b) covers a portion of the side extending from the lower surface of the first semiconductor layer (131) and is spaced apart from the first active layer (132a). That is, a portion of the central side of the first semiconductor layer (131) can be exposed to the outside by the first active layer (132a) and the second active layer (132b). The second active layer (132b) may be made of the same material as the first active layer (132a). Referring to FIGS. 1a through 1i, the lower surface of the second active layer (132b) is a portion separated from the growth substrate (WF). Accordingly, the second active layer (132b) can expose the lower surface of the first semiconductor layer (131).

[0042] The second semiconductor layer (133a) covers the first active layer (132a). Accordingly, the second semiconductor layer (133a) can cover the entire upper surface of the first semiconductor layer (131). The second semiconductor layer (133a) may be made of the same material as the second semiconductor material layer (133m).

[0043] The third semiconductor layer (133b) covers the second active layer (132b) and is spaced apart from the second semiconductor layer (133a). That is, a portion of the central side of the first semiconductor layer (131) can be exposed to the outside by the third semiconductor layer (133b) and the second semiconductor layer (133a). At this time, the third semiconductor layer (133b) may be made of the same material as the second semiconductor layer (133a). Referring to FIGS. 1a to 1i, the lower surface of the third semiconductor layer (133b) is a portion separated from the growth substrate (WF). Accordingly, the third semiconductor layer (133b) can expose the lower surface of the first semiconductor layer (131).

[0044] Generally, in the case of nanorod light-emitting devices, only a single light-emitting region existed within the device. That is, only one light-emitting region existed, formed by a single n-type semiconductor layer, a single active layer, and a single p-type semiconductor layer. Consequently, if any of the n-type, active, or p-type semiconductor layers—which are components of the light-emitting device—were damaged or failed to align properly during the display device manufacturing process, the device would fail to emit light. In such cases where the light-emitting device fails to emit light, repairing the display device requires undergoing the manufacturing process again; therefore, the repair process is highly complex and may be practically impossible.

[0045] Accordingly, a light-emitting element (130) according to one embodiment of the present invention is configured to include two light-emitting regions, so that a repair process can be easily performed in a display device (100). The light-emitting element (130) may include one light-emitting region formed by a first semiconductor layer (131) made of an n-type semiconductor material, a first active layer (132a), and a second semiconductor layer (133a) made of a p-type semiconductor material, and another light-emitting region formed by a first semiconductor layer (131) made of an n-type semiconductor material, a second active layer (132b), and a third semiconductor layer (133b) made of a p-type semiconductor material. Accordingly, even if a component constituting one of the two light-emitting regions is damaged or not properly aligned, the light-emitting element (130) can emit light using the other light-emitting region. Accordingly, a light-emitting element (130) according to one embodiment of the present invention may be configured to include two light-emitting regions, and since the two light-emitting regions can selectively emit light, it is very advantageous in terms of the repair process when used in a display device (100) and can improve brightness uniformity. A more detailed description of the repair process, etc. in the display device (100) will be described in more detail later with reference to FIGS. 3 to 11.

[0046] FIG. 2 is a perspective view of a light-emitting element according to another embodiment of the present invention. The light-emitting element (230) of FIG. 2 is substantially identical to the light-emitting element (130) of FIG. 1a to FIG. 1j, differing only in the first active layer (232a) and the second semiconductor layer (233a), so a redundant description is omitted.

[0047] Referring to FIG. 2, the first active layer (232a) and the second semiconductor layer (233a) of the light-emitting element (230) may expose the upper surface of the first semiconductor layer (131). Specifically, a process of cutting a portion of the upper part of the light-emitting element (230) may be added after the manufacturing process of FIG. 1a to FIG. 1i. That is, in order to manufacture the light-emitting element (230) into a symmetrical structure, the first active layer (232a) and the second semiconductor layer (233a) located on the upper part of the light-emitting element (230) may be cut to expose the upper surface of the first semiconductor layer (131).

[0048] A light-emitting element (230) according to another embodiment of the present invention is configured to include two light-emitting regions, so that a repair process can be easily performed in a display device (200). That is, the light-emitting element (230) may include one light-emitting region formed by a first semiconductor layer (131) made of an n-type semiconductor material, a first active layer (232a), and a second semiconductor layer (233a) made of a p-type semiconductor material, and another light-emitting region formed by a first semiconductor layer (131) made of an n-type semiconductor material, a second active layer (132b), and a third semiconductor layer (133b) made of a p-type semiconductor material. Accordingly, the light-emitting element (230) according to another embodiment of the present invention may be configured to include two light-emitting regions, and since the two light-emitting regions can be selectively emitted, it is very advantageous in terms of the repair process when used in a display device (100) and can improve brightness uniformity.

[0049] FIG. 3 is a schematic plan view of a display device according to an embodiment of the present invention. For convenience of explanation, FIG. 3 shows only the substrate (110), display area (AA), non-display area (NA), and a plurality of subpixels (SP) among the various components of the display device (100).

[0050] The substrate (110) is configured to support various components included in the display device (100) and may be made of an insulating material. For example, the substrate (110) may be made of glass or resin, etc. Additionally, the substrate (110) may be made of a polymer or plastic, or may be made of a material having flexibility.

[0051] The substrate (110) includes a display area (AA) and a non-display area (NA).

[0052] The display area (AA) is an area where a plurality of subpixels (SP) are arranged to display an image. Each of the plurality of subpixels (SP) is an individual unit that emits light, and a light-emitting element (130) and a driving circuit are formed in each of the plurality of subpixels (SP). For example, the plurality of subpixels (SP) may include a red subpixel, a green subpixel, a blue subpixel and / or a white subpixel, but are not limited thereto.

[0053] Meanwhile, a plurality of light-emitting elements (130) are arranged in one subpixel (SP). At this time, the plurality of light-emitting elements (130) can all emit light of the same color. The process of arranging a plurality of light-emitting elements (130) in one subpixel will be described later with reference to FIGS. 4a to 4d.

[0054] The non-display area (NA) is an area where an image is not displayed, and is an area where various wiring, driving ICs, etc. are placed to drive the subpixel (SP) placed in the display area (AA). For example, various ICs and driving circuits, such as gate driver ICs and data driver ICs, may be placed in the non-display area (NA). Meanwhile, the non-display area (NA) may be the back side of the substrate (110), that is, a side without subpixels (SP), or it may be omitted, and is not limited to what is shown in the drawing.

[0055] Hereinafter, with reference to FIGS. 4a to 4d, the self-alignment process of the light-emitting element (130) in the manufacturing method of the display device (100) will be explained.

[0056] FIGS. 4a to 4d are drawings for explaining a method of manufacturing a display device according to an embodiment of the present invention. FIGS. 4a to 4d only illustrate the self-alignment process of a light-emitting element (130) among the methods of manufacturing a display device (100).

[0057] Although not shown in FIGS. 4a and 4b, various wiring and transistors may be disposed on the substrate (110), and a flattening layer (114) for flattening the upper surface of the transistors may be disposed. Accordingly, FIGS. 4b and 4d only show the flattening layer (114) and the components disposed on the flattening layer (114).

[0058] Referring to FIG. 4a, a first alignment electrode (121E) and a first alignment wire (121) extending from the first alignment electrode (121E) may be disposed on the flattening layer (114). Additionally, a second alignment electrode (122E) and a second alignment wire (122) extending from the second alignment electrode (122E) may be disposed on both sides of the first alignment wire (121) on the flattening layer (114). The first alignment wire (121) and the second alignment wire (122) may receive an electrical signal from an external source for self-alignment of the light-emitting element (130). A first insulating layer (115) is disposed on the second alignment wire (122). The first insulating layer (115) is disposed to insulate the second alignment wire (122).

[0059] The first alignment electrode (121E), the second alignment electrode (122E), the first alignment wiring (121), and the second alignment wiring (122) may be made of a conductive material, for example, copper (Cu), chromium (Cr), molybdenum (Mo), molybdenum titanium (MoTi), etc., but are not limited thereto.

[0060] The first insulating layer (115) can also function as an insulating layer to prevent short circuit defects caused by migration between a plurality of first alignment wires (121) and a plurality of second alignment wires (122) during the manufacture of the display device (100). The first insulating layer (115) may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0061] Referring to FIG. 4b, a solution (SL) in which a plurality of light-emitting elements (130) are dispersed is applied onto a substrate (110) having a plurality of first alignment wires (121), a plurality of second alignment wires (122), and a first insulating layer (115). Since the light-emitting elements (130) are freely dispersed in the solution (SL), they may not be aligned in a specific direction.

[0062] Next, a voltage can be applied to a plurality of first alignment wires (121) and a plurality of second alignment wires (122) to self-align a plurality of light-emitting elements (130).

[0063] Specifically, an electric field can be formed by applying an alternating voltage to a plurality of first alignment wires (121) and a plurality of second alignment wires (122). Due to this electric field, the light-emitting element (130) can be dielectrically polarized and have polarity. The dielectrically polarized light-emitting element (130) can be moved or fixed in a specific direction by dielectrophoresis (DEP), that is, by the electric field. Therefore, a plurality of light-emitting elements (130) can be aligned and fixed between a plurality of first alignment wires (121) and a plurality of second alignment wires (122) using dielectrophoresis.

[0064] Referring to FIGS. 4c and 4d, a plurality of light-emitting elements (130) may have their central portions aligned toward a first alignment wire (121) and their two ends aligned toward a second alignment wire (122) adjacent to the first alignment wire (121).

[0065] At this time, when forming an electric field to align the light-emitting elements (130), different voltages can be easily applied to the plurality of first alignment wires (121) and the plurality of second alignment wires (122). For example, although not shown in the drawing, during the manufacturing process of the display device (100), an electric field can be formed by applying voltage from the outside through a separate component to the first alignment electrode (121E) and the second alignment electrode (122E) connected to each of the plurality of first alignment wires (121) and the plurality of second alignment wires (122). Accordingly, an electric field for aligning the plurality of light-emitting elements (130) can be formed by applying different voltages to the plurality of first alignment wires (121) and the plurality of second alignment wires (122). Accordingly, as shown in FIGS. 4c and 4d, a plurality of light-emitting elements (130) may have their central portions aligned toward the first alignment wiring (121) and their two ends aligned toward the second alignment wiring (122) adjacent to the first alignment wiring (121).

[0066] For a more detailed explanation of the multiple subpixels (SP) below, refer to FIG. 5 and FIG. 6 together.

[0067] FIG. 5 is a plan view of a display device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view along VI-VI' of FIG. 5. In FIG. 5, only one subpixel (SP) among a plurality of subpixels (SP) is shown.

[0068] Referring to FIGS. 5 and 6, a buffer layer (111), a first driving transistor (DT1), a gate insulating layer (112), an interlayer insulating layer (113), a flattening layer (114), a first alignment wiring (121), a second alignment wiring (122), a first insulating layer (115), a plurality of light-emitting elements (130), and a first connecting wiring (123) are arranged on a substrate (110).

[0069] A buffer layer (111) is disposed on a substrate (110). The buffer layer (111) can reduce the penetration of moisture or impurities through the substrate (110). The buffer layer (111) may be composed of, for example, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, the buffer layer (111) may be omitted depending on the type of substrate (110) or the type of thin-film transistor, and is not limited thereto.

[0070] A first driving transistor (DT1) is disposed on a buffer layer (111). The first driving transistor (DT1) includes a first active layer (ACT1), a first gate electrode (GE1), a first source electrode (SE1), and a first drain electrode (DE1).

[0071] First, a first active layer (ACT1) is disposed on the buffer layer (111). The first active layer (ACT1) may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0072] A gate insulating layer (112) is disposed on the first active layer (ACT1). The gate insulating layer (112) is an insulating layer for insulating the first active layer (ACT1) and the gate electrode (GE), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0073] A first gate electrode (GE1) is disposed on a gate insulating layer (112). The first gate electrode (GE1) may be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0074] An interlayer insulating layer (113) is disposed on the first gate electrode (GE1). Contact holes are formed in the interlayer insulating layer (113) for connecting the first source electrode (SE1) and the first drain electrode (DE1) to the first active layer (ACT1), respectively. The interlayer insulating layer (113) is an insulating layer for protecting the structure below the interlayer insulating layer (113), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0075] A first source electrode (SE1) and a first drain electrode (DE1) are disposed on an interlayer insulating layer (113). Each of the first source electrode (SE1) and the first drain electrode (DE1) can be electrically connected to a first active layer (ACT1) through a contact hole formed in the interlayer insulating layer (113). The first source electrode (SE1) and the first drain electrode (DE1) may be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0076] A flattening layer (114) is disposed on the first driving transistor (DT1). The flattening layer (114) is an insulating layer that protects the configuration below the flattening layer (114) and can flatten the upper portion of the first driving transistor (DT1). The flattening layer (114) may be composed of a single layer or multiple layers and, for example, may be made of an acrylic organic material, but is not limited thereto.

[0077] A plurality of first alignment wires (121) and a plurality of second alignment wires (122) are disposed on the flattening layer (114). The first alignment wires (121) can be used as wiring for applying a low potential voltage even after the manufacturing process described above. That is, a low potential voltage is applied through the first alignment electrode (121E) connected to the first alignment wires (121), and since the first alignment wires (121) are in contact with the first semiconductor layer (131) of the light-emitting element (130), the light-emitting element (130) can receive a low potential voltage through the first alignment wires (121). However, since the second alignment wires (122) are covered by the first insulating layer (115), they are not used as wiring for applying voltage in the display device (100).

[0078] Additionally, a first alignment electrode (121E), a second alignment electrode (122E), and a first connecting electrode (123E) may be disposed on the flattening layer (114). The first alignment electrode (121E), the second alignment electrode (122E), and the first connecting electrode (123E) may all be simultaneously formed from the same material as the first alignment wiring (121) and the second alignment wiring (122), but are not limited thereto. The first alignment electrode (121E) may be connected to the first alignment wiring (121), the second alignment electrode (122E) may be connected to the second alignment wiring (122), and the first connecting electrode (123E) may be connected to the first drain electrode (DE1), which is the output terminal of the first driving transistor (DT1).

[0079] A first insulating layer (115) is placed on the second alignment wiring (122) to cover the second alignment wiring (122). At this time, the first insulating layer (115) may be placed to cover an area of ​​the upper surface of the first connecting electrode (123E) excluding the contact hole, as shown in FIG. 6.

[0080] A plurality of light-emitting elements (130) are disposed on a first insulating layer (115). Each of the plurality of light-emitting elements (130) is disposed in the space between a plurality of second alignment wires (122). The central portion of the plurality of light-emitting elements (130) may be aligned toward the first alignment wire (121), and both ends may be aligned toward the second alignment wire (122) adjacent to the first wire (121). At this time, the first semiconductor layer (131) located in the central portion of the light-emitting element (130) is in contact with the first alignment wire (121), but the second semiconductor layer (133a) and the third semiconductor layer (133b) are insulated from the second alignment wire (122) by the first insulating layer (115).

[0081] A second insulating layer (116) is disposed on a plurality of light-emitting elements (130). The second insulating layer (116) can flatten the upper surface of the plurality of light-emitting elements (130). The second insulating layer (116) may be composed of a single layer or multiple layers, and, for example, may be made of an acrylic-based organic material, but is not limited thereto, and may also be made of an inorganic material.

[0082] The second insulating layer (116) includes a contact hole that exposes one end of each of the plurality of light-emitting elements (130). Although FIG. 6 is illustrated such that the second insulating layer (116) exposes the second semiconductor layer (133a) of the light-emitting element (130), it is not possible to predict which position the second semiconductor layer (133a) and the third semiconductor layer (133b) of the light-emitting element (130) will be aligned to, between the second alignment wiring (122) located to the left of the first alignment wiring (121) and the second alignment wiring (122) located to the right. That is, one of the second semiconductor layer (133a) and the third semiconductor layer (133b) is aligned to the second alignment wiring (122) located to the left of the first alignment wiring (121), and the other of the second semiconductor layer (133a) and the third semiconductor layer (133b) is aligned to the second alignment wiring (122) located to the right. Accordingly, a third semiconductor layer (133b), rather than the second semiconductor layer (133a), may be disposed at the location where the contact hole of the second insulating layer (116) is disposed. Accordingly, the second insulating layer (116) may include a contact hole that exposes one of the semiconductor layers of the second semiconductor layer (133a) and the third semiconductor layer (133b).

[0083] Then, a plurality of first connecting wires (123) are disposed on the second insulating layer (116). The plurality of first connecting wires (123) can be electrically connected to a plurality of light-emitting elements (130) through the contact holes of the second insulating layer (116). That is, the first connecting wires (123) can be electrically connected to one of the second semiconductor layer (133a) and the third semiconductor layer (133b) of the light-emitting element (130) through the contact holes of the second insulating layer (116). In addition, the first connecting wires (123) can be connected to the first connecting electrode (121) and electrically connected to the first drain electrode (DE1) of the first driving transistor (DT1). Accordingly, the first connecting wires (121) electrically connect the first driving transistor (DT1) and the plurality of light-emitting elements (130), thereby driving the plurality of light-emitting elements (130) to emit light.

[0084] In a display device (100) according to one embodiment of the present invention, by configuring the light-emitting elements (130) to self-align, a plurality of light-emitting elements (130) can be self-aligned at specific locations on a substrate (110).

[0085] Specifically, in a display device (100) according to one embodiment of the present invention, a plurality of first alignment lines (121) and a plurality of second alignment lines (122) for aligning a plurality of light-emitting elements (130) are formed on a substrate (110) on which a first driving transistor (DT1) is formed, and the plurality of light-emitting elements (130) can be self-aligned. Specifically, an electric field can be formed on the substrate (110) by applying an alternating voltage to the plurality of first alignment lines (121) and the plurality of second alignment lines (122). Then, the plurality of light-emitting elements (130) coated on the substrate (110) can be self-aligned on the plurality of first alignment lines (121) and the plurality of second alignment lines (122) by the electric field between the plurality of first alignment lines (121) and the plurality of second alignment lines (122). Therefore, the transfer process of aligning and transferring the plurality of light-emitting elements (130) at a specific location can be simplified. And, a plurality of first connecting wires (123) can be formed on a plurality of self-aligned light-emitting elements (130) to drive the plurality of light-emitting elements (130).

[0086] Accordingly, in a display device (100) according to one embodiment of the present invention, by configuring the light-emitting elements (130) to self-align, a plurality of light-emitting elements (130) can be self-aligned at specific locations on a substrate (110), thereby simplifying the transfer process of the light-emitting elements (130) and reducing manufacturing costs.

[0087] In addition, a light-emitting element (130) according to one embodiment of the present invention is configured to include two light-emitting regions. That is, the light-emitting element (130) may include one light-emitting region formed by a first semiconductor layer (131) made of an n-type semiconductor material, a first active layer (132a), and a second semiconductor layer (133a) made of a p-type semiconductor material, and another light-emitting region formed by a first semiconductor layer (131) made of an n-type semiconductor material, a second active layer (132b), and a third semiconductor layer (133b) made of a p-type semiconductor material. Accordingly, as shown in FIG. 6, when a second connecting wire (122) is connected to the second semiconductor layer (133a), light can be emitted through the light-emitting region formed by the first semiconductor layer (131), the first active layer (132a), and the second semiconductor layer (133a). Additionally, although not shown in the drawing, if the second connecting wire (122) is connected to the third semiconductor layer (133b), light can be emitted through the light-emitting region formed by the first semiconductor layer (131), the second active layer (132b), and the third semiconductor layer (133b). Accordingly, in the display device (100) according to one embodiment of the present invention, light can be emitted using one of the two light-emitting regions of the light-emitting element (130) regardless of which direction the light-emitting element (130) is aligned.

[0088] FIG. 7 is a plan view of a display device according to another embodiment of the present invention. FIG. 8 is a cross-sectional view according to VIII-VIII' of FIG. 7. The display device (700) of FIG. 7 and FIG. 8 further includes a second connecting wire (724) compared to the display device (100) of FIG. 5 and FIG. 6, and since the other configurations are substantially the same except for the connection relationship between the second insulating layer (716), the first alignment wire (121), and the light-emitting element (130), a redundant description is omitted.

[0089] First, referring to FIG. 8, the first semiconductor layer (131) of the light-emitting element (130) can be spaced apart from the first alignment wiring (121). That is, after the self-alignment process of the light-emitting element (130) is completed, the first semiconductor layer (131) can be spaced apart from the first alignment wiring (121) without coming into contact with it.

[0090] Referring to FIGS. 7 and 8, a second connecting wire (724) may be arranged to transmit a low potential voltage to a light-emitting element (130). The second connecting wire (724) is connected to a first alignment electrode (121E) to receive a low potential voltage. Additionally, the second insulating layer (716) may include a contact hole that exposes the first semiconductor layer (131). Accordingly, the second insulating layer (716) may expose the upper portion of the first semiconductor layer (131). The second connecting wire (724) is placed on the first semiconductor layer (131) exposed by the second insulating layer (716) and may come into contact with the first semiconductor layer (131). Accordingly, the second connecting wire (724) can connect the first alignment electrode (121E), to which a low potential voltage is supplied, and the first semiconductor layer (131) of the light-emitting element (130), so that the low potential voltage can be transmitted to the first semiconductor layer (131).

[0091] The light-emitting element (130) may not be accurately aligned due to errors in the manufacturing process of the light-emitting element (130) or errors in the process of self-aligning the light-emitting element (130) to the display device (700). For example, the first semiconductor layer (131) of the light-emitting element (130) is designed to come into contact with the first alignment wiring (121) after the self-alignment process is completed, but due to the various errors described above, the first semiconductor layer (131) may not ultimately come into contact with the first alignment wiring (121). In such a case, since the first semiconductor layer (131) does not receive a low potential voltage, a defect may occur in which the light-emitting element (130) cannot emit light. Additionally, during the process of self-aligning multiple light-emitting elements (130), a problem may occur in which the first semiconductor layer (131) of some light-emitting elements (130) comes into contact with the first alignment wiring (121), while the first semiconductor layer (131) of other light-emitting elements (130) does not come into contact with the first alignment wiring (121). In this case, since a difference in the number of light-emitting elements (130) normally connected between multiple subpixels (SP) may occur, a problem of non-uniform brightness may also occur for each subpixel (SP).

[0092] Accordingly, in a display device (700) according to another embodiment of the present invention, the second insulating layer (716) includes a contact hole that exposes the upper portion of the first semiconductor layer (131), and since the second connecting wire (724) that transmits a low potential voltage contacts the first semiconductor layer (131) exposed by the second insulating layer (716), a low potential voltage can be transmitted normally to the light-emitting element (130). Therefore, even if the first semiconductor layer (131) of all light-emitting elements (130) cannot contact the first alignment wire (121) due to various errors, a low potential voltage can be transmitted to the first semiconductor layer (131) of the light-emitting element (130) through the second connecting wire (724). In addition, even if the first semiconductor layer (131) of some light-emitting elements (130) does not come into contact with the first alignment wiring (121), the repair process can be performed very easily so that the first semiconductor layer (131) of the said some light-emitting elements (130) receives a low potential voltage through the second connection wiring (724), thereby improving the uniformity of brightness between subpixels (SP). Furthermore, by reducing the number of light-emitting elements (130) that do not emit light among the multiple self-aligned light-emitting elements (130) within a single subpixel (SP), the light-emitting efficiency relative to the number of light-emitting elements (130) introduced can be maximized.

[0093] FIG. 9 is a plan view of a display device according to another embodiment of the present invention. FIG. 10 is a cross-sectional view according to IX-IX' of FIG. 9. The display device (900) of FIG. 9 and FIG. 10 further includes a second driving transistor (DT2), a third insulating layer (917), a third connecting electrode (925E), and a third connecting wire (925) compared to the display device (100) of FIG. 5 and FIG. 6, and since only the second insulating layer (916) is different and the other configurations are substantially the same, a redundant description is omitted.

[0094] A second driving transistor (DT2) is disposed on a substrate (110) and a buffer layer (111). The second driving transistor (DT2) includes a second active layer (ACT2), a second gate electrode (GE2), a second source electrode (SE2), and a second drain electrode (DE2).

[0095] First, a second active layer (ACT2) is disposed on the buffer layer (111). The second active layer (ACT2) may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0096] A gate insulating layer (112) is disposed on the second active layer (ACT2). The gate insulating layer (112) is an insulating layer for insulating the second active layer (ACT2) and the second gate electrode (GE2), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0097] A second gate electrode (GE2) is disposed on the gate insulating layer (112). The second gate electrode (GE2) may be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0098] An interlayer insulating layer (113) is disposed on the second gate electrode (GE2). Contact holes are formed in the interlayer insulating layer (113) for connecting the second source electrode (SE2) and the second drain electrode (DE2) to the second active layer (ACT2), respectively. The interlayer insulating layer (113) is an insulating layer for protecting the configuration below the interlayer insulating layer (113), and may be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0099] A second source electrode (SE2) and a second drain electrode (DE2) are disposed on an interlayer insulating layer (113). Each of the second source electrode (SE2) and the second drain electrode (DE2) can be electrically connected to a second active layer (ACT2) through a contact hole formed in the interlayer insulating layer (113). The second source electrode (SE2) and the second drain electrode (DE2) may be composed of a conductive material, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but are not limited thereto.

[0100] A flattening layer (114) is disposed on the second driving transistor (DT2), and a third connecting electrode (925E) is disposed on the flattening layer (114). The third connecting electrode (925E) can be connected to the second drain electrode (DE2), which is the output terminal of the second driving transistor (DT2).

[0101] Referring to FIG. 10, a third insulating layer (917) is arranged to cover the first connecting wire (123) and the second insulating layer (916). At this time, the second insulating layer (916) and the third insulating layer (917) may expose a semiconductor layer different from the semiconductor layer that the first connecting wire (123) contacts. For example, as shown in FIG. 10, if the semiconductor layer that the first connecting wire (123) contacts is the second semiconductor layer (133a), the second insulating layer (916) and the third insulating layer (917) may further include a contact hole that exposes the third semiconductor layer (133b).

[0102] Referring to FIG. 10, a plurality of third connecting wires (925) are disposed on the third insulating layer (917). That is, the third connecting wires (925) may be disposed on a layer different from the first connecting wires (123). The plurality of third connecting wires (925) may be electrically connected to a plurality of light-emitting elements (130) through contact holes in the second insulating layer (916) and the third insulating layer (917). That is, the third connecting wires (925) may be electrically connected to one semiconductor layer and another semiconductor layer among the second semiconductor layer (133a) and the third semiconductor layer (133b) of the light-emitting element (130) to which the first connecting wires (123) are connected, through contact holes in the second insulating layer (916) and the third insulating layer (917). That is, when the first connecting wire (123) is connected to the second semiconductor layer (133a), the third connecting wire (925) can be connected to the third semiconductor layer (133b), and when the first connecting wire (123) is connected to the third semiconductor layer (133b), the third connecting wire (925) can be connected to the second semiconductor layer (133a). Additionally, the third connecting wire (925) can be connected to the third connecting electrode (925E) and electrically connected to the second drain electrode (DE2) of the second driving transistor (DT2). Accordingly, the third connecting wire (925) electrically connects the second driving transistor (DT2) and a plurality of light-emitting elements (130) to drive the plurality of light-emitting elements (130) to emit light.

[0103] The first driving transistor (DT1) and the second driving transistor (DT2) may be driven independently or driven together in the same way. For example, the first driving transistor (DT1) may be driven independently regardless of whether the second driving transistor (DT2) is driven. Alternatively, the first driving transistor (DT1) and the second driving transistor (DT2) may be connected to the same wiring so that the first driving transistor (DT1) and the second driving transistor (DT2) are driven in the same way.

[0104] In a display device (900) according to another embodiment of the present invention, the light-emitting element (130) is configured to include two light-emitting regions, and may include a structure that allows for easy repair. That is, the light-emitting element (130) may include one light-emitting region formed by a first semiconductor layer (131) made of an n-type semiconductor material, a first active layer (132a), and a second semiconductor layer (133a) made of a p-type semiconductor material, and another light-emitting region formed by a first semiconductor layer (131) made of an n-type semiconductor material, a second active layer (132b), and a third semiconductor layer (133b) made of a p-type semiconductor material. Accordingly, repair is possible even when the first connecting wire (123) is connected to the second semiconductor layer (133a) as shown in FIG. 10. For example, the light-emitting region formed by the first semiconductor layer (131), the first active layer (132a), and the second semiconductor layer (133a) may not emit light normally due to defects caused by problems such as the manufacturing process. Alternatively, the light-emitting element (130) may not emit light normally because the first connecting wire (123) is not properly connected to the second semiconductor layer (133a). In a display device (900) according to another embodiment of the present invention, in order to resolve defects that occur when the first connecting wire (123) is designed to be connected to the second semiconductor layer (133a), a third connecting wire (925) connected to a third semiconductor layer (133b) different from the second semiconductor layer (133a) may be additionally arranged. Accordingly, when a defect occurs in the light-emitting region formed by the first semiconductor layer (131), the first active layer (132a), and the second semiconductor layer (133a), the light-emitting element (130) can emit light normally through the light-emitting region formed by the first semiconductor layer (131), the second active layer (132b), and the third semiconductor layer (133b).In addition, even if a defect occurs where the first connecting wire (123) is not properly connected to the second semiconductor layer (133a), the third semiconductor layer (133b) and the second driving transistor (DT2) can be connected through the third connecting wire (925), so the light-emitting element (130) can emit light normally. Accordingly, a display device (900) according to another embodiment of the present invention may include a repairable structure including a light-emitting element (130) having two light-emitting regions.

[0105] Meanwhile, even if there is no defect in the light-emitting region and no problem with the connection through the first connecting wire (123) and the second semiconductor layer (133a), the third connecting wire (925) and the third semiconductor layer (133b) can be connected.

[0106] At this time, the first driving transistor (DT1) and the second driving transistor (DT2) can be driven independently. For example, during the first time interval, the first driving transistor (DT1) can be driven to emit light through a light-emitting region formed by the first semiconductor layer (131), the first active layer (132a), and the second semiconductor layer (133a), and during the second time interval, the second driving transistor (DT2) can be driven to emit light through a light-emitting region formed by the first semiconductor layer (131), the second active layer (132b), and the third semiconductor layer (133b). As the first driving transistor (DT1) and the second driving transistor (DT2) are driven alternately in this way, the two light-emitting regions can be used alternately. Accordingly, in the display device (900) according to another embodiment of the present invention, the lifespan of the light irradiation can be improved by efficiently using the two light-emitting regions of the light-emitting element (130).

[0107] In addition, the first driving transistor (DT1) and the second driving transistor (DT2) can be driven together. That is, the first driving transistor (DT1) and the second driving transistor (DT2) can be driven together in the same way throughout the entire time interval. Accordingly, in the display device (900) according to another embodiment of the present invention, by configuring the two light-emitting regions of the light-emitting element (130) to emit light simultaneously, the brightness can be improved and the light-emitting efficiency can be enhanced.

[0108] FIG. 11 is a plan view of a display device according to another embodiment of the present invention. FIG. 12 is a cross-sectional view along XI-XI' of FIG. 11. The display device (1100) of FIG. 11 and FIG. 12 is substantially identical to the display device (900) of FIG. 9 and FIG. 10 in that the third insulating layer (917) is omitted and only the third connecting wiring (1125) is different, so a redundant description is omitted.

[0109] Referring to FIG. 12, the second insulating layer (1116) may expose a semiconductor layer different from the semiconductor layer that the first connecting wire (123) contacts. For example, as shown in FIG. 12, if the semiconductor layer that the first connecting wire (123) contacts is the second semiconductor layer (133a), the second insulating layer (1116) may further include a contact hole that exposes a third semiconductor layer (133b).

[0110] Referring to FIGS. 11 and 12, a plurality of third connecting wires (1125) are disposed on the second insulating layer (1116). That is, the third connecting wires (1125) may be disposed on the same layer as the first connecting wires (123). The plurality of third connecting wires (1125) may be electrically connected to a plurality of light-emitting elements (130) through contact holes in the second insulating layer (1116). That is, the third connecting wires (1125) may be electrically connected to one semiconductor layer and another semiconductor layer among the second semiconductor layer (133a) and the third semiconductor layer (133b) of the light-emitting element (130) to which the first connecting wires (123) are connected, through contact holes in the second insulating layer (1116). That is, when the first connecting wire (123) is connected to the second semiconductor layer (133a), the third connecting wire (1125) can be connected to the third semiconductor layer (133b), and when the first connecting wire (123) is connected to the third semiconductor layer (133b), the third connecting wire (1125) can be connected to the second semiconductor layer (133a). Additionally, the third connecting wire (1125) can be connected to the third connecting electrode (925E) and electrically connected to the second drain electrode (DE2) of the second driving transistor (DT2). Accordingly, the third connecting wire (1125) electrically connects the second driving transistor (DT2) and a plurality of light-emitting elements (130) to drive the plurality of light-emitting elements (130) to emit light.

[0111] In a display device (1100) according to another embodiment of the present invention, the light-emitting element (130) is configured to include two light-emitting regions, and may include a structure that allows for easy repair. That is, in a display device (1100) according to another embodiment of the present invention, to resolve a defect that occurs when a first connecting wire (123) is designed to be connected to a second semiconductor layer (133a), a third connecting wire (1125) connected to a third semiconductor layer (133b) different from the second semiconductor layer (133a) may be additionally arranged. Accordingly, when a defect occurs in the light-emitting region formed by the first semiconductor layer (131), the first active layer (132a), and the second semiconductor layer (133a), the light-emitting element (130) can emit light normally through the light-emitting region formed by the first semiconductor layer (131), the second active layer (132b), and the third semiconductor layer (133b). In addition, even if a defect occurs where the first connecting wire (123) is not properly connected to the second semiconductor layer (133a), the third semiconductor layer (133b) and the second driving transistor (DT2) can be connected through the third connecting wire (1125), so the light-emitting element (130) can emit light normally. Accordingly, in a display device (1100) according to another embodiment of the present invention, a repairable structure including a light-emitting element (130) having two light-emitting regions may be included.

[0112] In addition, in a display device (1100) according to another embodiment of the present invention, the first connecting wire (123) and the third connecting wire (1125) can be formed simultaneously, so that the third connecting wire (1125) for repair can be formed in the same process as the first connecting wire (123). That is, the third connecting wire (1125) for repair can be formed on the same layer as the first connecting wire (123) using the same material, so that the first connecting wire (123) and the third connecting wire (1125) can be formed simultaneously in a single mask process. That is, if no defect occurs, it is not necessary to drive the second driving transistor (DT2) connected to the third connecting wire (1125), so the first connecting wire (123) and the third connecting wire (1125) can be formed simultaneously. Accordingly, in the display device (1100) according to another embodiment of the present invention, a third connecting wire (1125) for repair can be formed without an additional process, thereby reducing the process steps consumed in the repair process and reducing manufacturing costs.

[0113] A display device according to various embodiments of the present invention can be described as follows.

[0114] A nano rod light-emitting device according to one embodiment of the present invention may include a rod-shaped first semiconductor layer, a first active layer covering a portion of a side extending from the upper surface of the first semiconductor layer, a second semiconductor layer covering the first active layer, a second active layer covering a portion of a side extending from the lower surface of the first semiconductor layer and spaced apart from the first active layer, and a third semiconductor layer covering the second active layer and spaced apart from the second semiconductor layer.

[0115] According to another feature of the present invention, the first active layer and the second active layer may be made of the same material, and the second semiconductor layer and the third semiconductor layer may be made of the same material.

[0116] According to another feature of the present invention, the first active layer can further cover the entire upper surface of the first semiconductor layer.

[0117] According to another feature of the present invention, the first active layer can expose the upper surface of the first semiconductor layer.

[0118] According to another feature of the present invention, the second active layer can expose the lower surface of the first semiconductor layer.

[0119] According to another feature of the present invention, the substrate may include a display area comprising a plurality of subpixels and a non-display area surrounding the display area, a first transistor disposed on the substrate, a planarization layer disposed on the first transistor, a first alignment wiring disposed on the planarization layer, a second alignment wiring located on both sides of the first alignment wiring, a first insulating layer disposed to cover the second alignment wiring, a nanorod light-emitting element described in any one of claims 1 to 5 disposed on the first alignment wiring and the first insulating layer, a second insulating layer disposed on the nanorod light-emitting element and exposing one of a second semiconductor layer and a third semiconductor layer, and a first connecting wiring connecting the first transistor and one semiconductor layer.

[0120] According to another feature of the present invention, the first alignment wiring can be in contact with the first semiconductor layer.

[0121] According to another feature of the present invention, the first alignment wiring may be a low-potential voltage wiring.

[0122] According to another feature of the present invention, a second connecting wire is further included that is disposed on a first semiconductor layer and contacts the first semiconductor layer, and the second insulating layer exposes the first semiconductor layer, and the second connecting wire can contact the first semiconductor layer exposed by the second insulating layer.

[0123] According to another feature of the present invention, the first semiconductor layer may be spaced apart from the first alignment wiring.

[0124] According to another feature of the present invention, the invention further comprises a second transistor disposed on a substrate, a third connecting wire connecting the second transistor to another semiconductor layer among a second semiconductor layer and a third semiconductor layer, wherein the second insulating layer exposes another semiconductor layer, and the third connecting wire can come into contact with the other semiconductor layer exposed by the second insulating layer.

[0125] According to another feature of the present invention, the first connecting wire and the third connecting wire may be disposed on the same layer and made of the same material.

[0126] According to another feature of the present invention, a third insulating layer covering a first connecting wire and a second insulating layer is further included, wherein the third insulating layer exposes another semiconductor layer, and the third connecting wire can come into contact with the other semiconductor layer exposed by the second insulating layer and the third insulating layer.

[0127] According to another feature of the present invention, the first connecting wire and the third connecting wire may be placed on different layers.

[0128] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not to limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims below, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0129] 100, 700, 900, 1100: Display device 110: Substrate 111: Buffer layer 112: Gate insulation layer 113: Interlayer insulation layer 114: Leveling layer 115: First insulating layer 116, 716, 916, 1116: Second insulating layer 917: Third insulating layer DT1: First driving transistor ACT1: 1st active layer GE1: First gate electrode SE1: First source electrode DE1: First drain electrode DT2: Second driving transistor ACT2: Second active layer GE2: Second gate electrode SE2: Second source electrode DE2: 2nd Drain 121: 1st alignment wiring 121E: First alignment electrode 122: Second alignment wiring 122E: Second alignment electrode 123: First connecting wire 123E: First connecting electrode 724: Second connecting wiring 925, 1125: Third connecting wiring 925E: Third connecting electrode 130, 230: Light-emitting elements 131: First semiconductor layer 132a: First active layer 132b: Second active layer 133a: Second semiconductor layer 133b: Third semiconductor layer SP: Subpixel AA: Display area NA: Non-display area WF: Growth substrate BF: Buffer layer IL: Insulating film 132m: Active material layer 133m: Second semiconductor material layer MS: Mask SL: Solution PR1: 1st Temporary Protection Layer PR2: 2nd Temporary Protection Layer

Claims

Claim 1 A nano rod light-emitting device comprising: a first semiconductor layer having a rod shape; a first active layer covering a portion of a side extending from the upper surface of the first semiconductor layer; a second semiconductor layer covering the first active layer; a second active layer covering a portion of a side extending from the lower surface of the first semiconductor layer and spaced apart from the first active layer; and a third semiconductor layer covering the second active layer and spaced apart from the second semiconductor layer. Claim 2 A nanorod light-emitting device according to claim 1, wherein the first active layer and the second active layer are made of the same material, and the second semiconductor layer and the third semiconductor layer are made of the same material. Claim 3 A nano-rod light-emitting device according to claim 1, wherein the first active layer further covers the entire upper surface of the first semiconductor layer. Claim 4 A nano-rod light-emitting device according to claim 1, wherein the first active layer exposes the upper surface of the first semiconductor layer. Claim 5 A nano-rod light-emitting device according to claim 1, wherein the second active layer exposes the lower surface of the first semiconductor layer. Claim 6 A display device comprising: a substrate including a display area including a plurality of subpixels and a non-display area surrounding the display area; a first transistor disposed on the substrate; a planarization layer disposed on the first transistor; a first alignment wiring disposed on the planarization layer; a second alignment wiring located on both sides of the first alignment wiring; a first insulating layer disposed to cover the second alignment wiring; a nanorod light-emitting element described in any one of claims 1 to 5 disposed on the first alignment wiring and the first insulating layer; a second insulating layer disposed on the nanorod light-emitting element and exposing one of the second semiconductor layer and the third semiconductor layer; and a first connecting wiring connecting the first transistor and the one semiconductor layer. Claim 7 In claim 6, the first alignment wiring is in contact with the first semiconductor layer, a display device. Claim 8 In claim 7, the first alignment wiring is a low-potential voltage wiring, a display device. Claim 9 A display device according to claim 6, further comprising a second connecting wire disposed on the first semiconductor layer and in contact with the first semiconductor layer, wherein the second insulating layer exposes the first semiconductor layer, and the second connecting wire is in contact with the first semiconductor layer exposed by the second insulating layer. Claim 10 In claim 9, the first semiconductor layer is spaced apart from the first alignment wiring, in a display device. Claim 11 A display device according to claim 6, further comprising: a second transistor disposed on the substrate; a third connecting wire connecting the second transistor and another semiconductor layer among the second semiconductor layer and the third semiconductor layer, wherein the second insulating layer exposes the other semiconductor layer and the third connecting wire contacts the other semiconductor layer exposed by the second insulating layer. Claim 12 In claim 11, the first connecting wire and the third connecting wire are arranged on the same layer and are made of the same material, forming a display device. Claim 13 A display device according to claim 11, further comprising a third insulating layer covering the first connecting wire and the second insulating layer, wherein the third insulating layer exposes the other semiconductor layer, and the third connecting wire contacts the other semiconductor layer exposed by the second insulating layer and the third insulating layer. Claim 14 In paragraph 13, a display device wherein the first connecting wire and the third connecting wire are disposed on different layers.

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