Pixel circuit and display device including the same

Abstract

A pixel circuit and a display device including the same are disclosed. The pixel circuit of the present invention comprises: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node; a light-emitting element including an anode electrode connected to the third node and a cathode electrode connected to a VSS line to which a pixel reference voltage lower than the pixel driving voltage is applied, and which is driven by a current from the driving element; a first switch element that supplies a data voltage of pixel data to the second node in response to a scan pulse; a second switch element that supplies an initialization voltage to the second node in response to an initialization pulse; a third switch element that supplies a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a fourth switch element that connects the third node to the VSS line in response to an anode reset pulse; and a capacitor connected between the second node and the third node.

Description

Technology Field

[0001] The present invention relates to a pixel circuit and a display device including the same. Background Technology

[0002] Electroluminescence displays can be classified into inorganic and organic light-emitting displays depending on the material of the light-emitting layer. Active matrix type organic light-emitting displays include self-emissive Organic Light Emitting Diodes (OLEDs) and have the advantages of fast response speed, high luminous efficiency, brightness, and high viewing angles. In organic light-emitting displays, OLEDs are formed in each pixel. Organic light-emitting displays not only offer fast response speeds, excellent luminous efficiency, brightness, and viewing angles, but also superior contrast ratio and color reproduction because they can express black gradations as perfect black.

[0003] The frame frequency of an image input to pixels of an organic light-emitting display device may change. When the frame frequency of the input image changes, the holding interval between the time a pixel data voltage is charged and the time the next pixel data voltage is charged changes. When the holding interval changes, the amount of current flowing through the light-emitting element decreases, and the brightness of the pixels decreases. As a result, flicker may be visible on the screen. The problem to be solved

[0004] The present invention aims to solve the aforementioned necessities and / or problems.

[0005] The present invention provides a pixel circuit capable of improving image quality by suppressing fluctuations in the brightness of pixels when the frame frequency is varied, and a display device including the same.

[0006] The problems of the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A pixel circuit according to one embodiment of the present invention includes: a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node; a light-emitting element including an anode electrode connected to the third node and a cathode electrode connected to a VSS line to which a pixel reference voltage (EVSS) lower than the pixel driving voltage is applied, and driven by a current from the driving element; a first switch element that supplies a data voltage of pixel data to the second node in response to a scan pulse; a second switch element that supplies an initialization voltage to the second node in response to an initialization pulse; a third switch element that supplies a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a fourth switch element that connects the third node to the VSS line in response to an anode reset pulse; and a capacitor connected between the second node and the third node.

[0008] A pixel circuit according to another embodiment of the present invention includes: a driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node; a light-emitting element including an anode electrode connected to the third node and a cathode electrode connected to a VSS line to which a pixel reference voltage lower than the pixel driving voltage is applied, and driven by a current from the driving element; a first switch element that supplies a data voltage of pixel data to the second node in response to a scan pulse; a second switch element that supplies an initialization voltage to the second node in response to an initialization pulse; a third switch element that supplies a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a fourth switch element that connects the third node to a fourth node in response to an anode reset pulse (AR); and a capacitor connected between the second node and the fourth node.

[0009] A pixel circuit according to another embodiment of the present invention comprises: a driving element including a first electrode connected to a VDD line to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node; a light-emitting element including an anode electrode connected to the third node and a cathode electrode connected to a VSS line to which a pixel reference voltage lower than the pixel driving voltage is applied, and driven by a current from the driving element; a first switching element that supplies a data voltage of pixel data to the second node in response to a scan pulse (SCAN); a second switching element that supplies an initialization voltage to the second node in response to an initialization pulse; a third switching element that supplies a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a first capacitor connected between the second node and the third node; and a second capacitor connected between the VDD line and the third node and having a smaller capacitance than the first capacitor.

[0010] The display device of the present invention includes the pixel circuit. Effects of the invention

[0011] The present invention can improve image quality by suppressing fluctuations in pixel brightness through performing anode resets at a constant frequency in pixels when the frame frequency of an input image varies.

[0012] The present invention can perform an anode reset without additionally connecting an anode reset voltage wiring to the pixel circuit.

[0013] The present invention can suppress fluctuations in the anode voltage of a light-emitting element when performing an anode reset.

[0014] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art from the description in the claims. Brief explanation of the drawing

[0015] FIG. 1 is a circuit diagram showing a pixel circuit according to a first embodiment of the present invention. Figure 2 is a waveform diagram showing the gate signal and data voltage applied to the pixel circuit illustrated in Figure 1. Figure 3 is a circuit diagram showing the initialization step of the pixel circuit illustrated in Figure 1. Figure 4 is a circuit diagram showing the sensing step of the pixel circuit illustrated in Figure 1. Figure 5 is a circuit diagram showing the data writing step of the pixel circuit illustrated in Figure 1. Figure 6 is a circuit diagram showing the anode reset step of the pixel circuit illustrated in Figure 1. Figure 7 is a circuit diagram showing the boosting and light-emitting stages of the pixel circuit illustrated in Figure 1. FIG. 8 is a diagram showing the period of the sensing pulse and the anode reset pulse applied to the pixel circuit illustrated in FIG. 1 when the frame frequency is varied. FIGS. 9a and FIGS. 9b are circuit diagrams showing pixel circuits according to a second embodiment of the present invention. FIG. 10 is a waveform diagram showing the gate signal and data voltage applied to the pixel circuits illustrated in FIG. 9a and FIG. 9b. FIGS. 11a and FIGS. 11b are circuit diagrams showing the operation of the pixel circuit illustrated in FIGS. 9a and FIGS. 9b during the anode reset step. FIG. 12 is a diagram showing the period of the sensing pulse and anode reset pulse applied to the pixel circuit shown in FIG. 9a and FIG. 9b when the frame frequency is varied. FIG. 13 is a waveform diagram showing the gate signal generated during the anode reset period illustrated in FIG. 12. FIG. 14 is a waveform diagram showing the gate signal generated during the EM OFF period illustrated in FIG. 12. FIG. 15 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention. FIG. 16 is a waveform diagram showing the gate signal and data voltage applied to the pixel circuit illustrated in FIG. 15. Figure 17 is a circuit diagram showing the initialization step of the pixel circuit illustrated in Figure 15. Figure 18 is a circuit diagram showing the sensing step of the pixel circuit illustrated in Figure 15. Figure 19 is a circuit diagram showing the data writing step of the pixel circuit illustrated in Figure 15. FIG. 20 is a circuit diagram showing the anode reset step of the pixel circuit illustrated in FIG. 15. FIG. 21 is a circuit diagram showing the boosting and light-emitting stages of the pixel circuit illustrated in FIG. 15. FIGS. 22a and FIGS. 22b are circuit diagrams showing pixel circuits according to a fourth embodiment of the present invention. FIG. 23 is a waveform diagram showing the gate signal and data voltage applied to the pixel circuits illustrated in FIG. 22a and FIG. 22b. FIGS. 24a and FIGS. 24b are circuit diagrams showing the operation of the pixel circuit illustrated in FIGS. 22a and FIGS. 22b during the anode reset step. FIG. 25 is a waveform diagram showing the gate signal supplied to the pixel circuit shown in FIG. 22a and FIG. 22b during the anode reset interval when the frame frequency of the input image is varied as shown in FIG. 12. FIG. 26 is a waveform diagram showing a gate signal supplied to the pixel circuit shown in FIG. 22a and FIG. 22b of the present invention during the EM OFF period when the frame frequency of the input image is varied as shown in FIG. 12. FIG. 27 is a circuit diagram showing pixel circuits according to the fifth embodiment of the present invention. FIG. 28 is a waveform diagram showing the gate signal and data voltage applied to the pixel circuits illustrated in FIG. 27. FIG. 29 is a circuit diagram showing the initialization step of the pixel circuit illustrated in FIG. 27. FIG. 30 is a circuit diagram showing the sensing step of the pixel circuit illustrated in FIG. 27. FIG. 31 is a circuit diagram showing the data writing step of the pixel circuit illustrated in FIG. 1 in FIG. 27. FIG. 32 is a circuit diagram showing the anode reset step of the pixel circuit illustrated in FIG. 1 in FIG. 27. FIG. 33 is a circuit diagram showing the boosting and light-emitting stages of the pixel circuit illustrated in FIG. 27. FIGS. 34a and FIGS. 34b are circuit diagrams showing pixel circuits according to the sixth embodiment of the present invention. FIG. 35 is a waveform diagram showing the gate signal and data voltage applied to the pixel circuits illustrated in FIG. 34a and FIG. 34b. FIGS. 36a and FIGS. 36b are circuit diagrams showing the operation of the pixel circuit illustrated in FIGS. 34a and FIGS. 34b during the anode reset step. FIG. 37 is a waveform diagram showing the gate signal supplied to the pixel circuit shown in FIG. 34a and FIG. 34b during the anode reset interval when the frame frequency of the input image is varied as shown in FIG. 12. FIG. 38 is a waveform diagram showing a gate signal supplied to the pixel circuit shown in FIG. 34a and FIG. 34b of the present invention during the EM OFF period when the frame frequency of the input image is varied as shown in FIG. 12. FIG. 39 is a block diagram showing a display device according to one embodiment of the present invention. FIG. 40 is a cross-sectional view showing the cross-sectional structure of the display panel illustrated in FIG. 39. Specific details for implementing the invention

[0016] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. The present invention is not limited to the embodiments disclosed below but may be implemented in various different forms; the embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0017] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Throughout the specification, the same reference numerals refer to substantially the same components. Furthermore, in describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may unnecessarily obscure the essence of the present invention.

[0018] Where terms such as “comprising,” “including,” “having,” “consisting of,” etc. are used in this specification, other parts may be added unless “~ only” is used. Where a component is expressed in the singular, it may be interpreted as plural unless specifically stated otherwise.

[0019] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0020] In the case of a description of a positional relationship, for example, when the positional relationship between two components is described using expressions such as 'on top of,' 'above,' 'below,' or 'next to,' one or more other components may be interposed between those components where 'immediately' or 'directly' is not used.

[0021] First, second, etc. may be used to distinguish components, but the function or structure of these components is not limited by the ordinal number or component name preceding the component.

[0022] The following embodiments may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or together in an associated relationship.

[0023] Each pixel is divided into multiple subpixels of different colors for color implementation, and each subpixel includes a transistor used as a switching element or a driving element. Such a transistor can be implemented as a TFT (Thin Film Transistor).

[0024] The driving circuit of the display device writes pixel data of the input image to the pixels. The driving circuit of the flat panel display device includes a data driving circuit that supplies data signals to data lines, a gate driving circuit that supplies gate signals to gate lines, and the like.

[0025] In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be Oxide TFTs including oxide semiconductors or LTPS TFTs including Low Temperature Poly Silicon (LTPS). Hereinafter, the transistors constituting the pixel circuit and the gate driving circuit are described with reference to examples implemented as n-channel Oxide TFTs implemented as Oxide TFTs, but the present invention is not limited thereto.

[0026] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. Within the transistor, carriers begin to flow from the source. The drain is the electrode from which carriers exit the transistor. In a transistor, the flow of carriers is from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage to allow electrons to flow from the source to the drain. In an n-channel transistor, the direction of current flows from the drain toward the source. In the case of a p-channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage to allow holes to flow from the source toward the drain. In a p-channel transistor, current flows from the source toward the drain because holes flow from the source toward the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change depending on the applied voltage. Therefore, the invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first and second electrodes.

[0027] The gate signal can swing between the gate-on voltage and the gate-off voltage. The gate-on voltage is set to a voltage higher than the transistor's threshold voltage. The gate-off voltage is set to a voltage lower than the transistor's threshold voltage.

[0028] A transistor is turned on in response to a gate-on voltage, while it is turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage can be a gate high voltage, and the gate-off voltage can be a gate low voltage.

[0029] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings. In the following embodiments, the display device is described primarily as an organic light-emitting display device, but the present invention is not limited thereto. Furthermore, the present invention is not limited by the names of components or signals in the following embodiments and claims.

[0030] FIG. 1 is a circuit diagram showing a pixel circuit according to a first embodiment of the present invention. FIG. 2 is a waveform diagram showing a gate signal and a data voltage applied to the pixel circuit shown in FIG. 1. FIG. 3 to 7 are drawings showing the operation of the pixel circuit shown in FIG. 1 in steps.

[0031] Referring to FIGS. 1 to 7, the pixel circuit includes a light-emitting element (EL), a driving element (DT) for driving the light-emitting element (EL), a plurality of switching elements (T1 to T4), and a capacitor (Cst). The driving element (DT) and the switching elements (T1 to T4) can be implemented as n-channel oxide TFTs.

[0032] The pixel circuit is connected to a data line (DL) to which a data voltage (Vdata) is applied, and to gate lines to which gate signals (SCAN, INIT, SENSE, AR) are applied. Additionally, the pixel circuit is connected to power lines to which DC voltage (or constant voltage) is applied, such as the VDD line to which the pixel driving voltage (EVDD) is applied, the VSS line to which the pixel reference voltage (EVSS) is applied, the INIT line to which the initialization voltage (Vinit) is applied, and the REF line (RL) to which the reference voltage (Vref) is applied. The power lines can be connected in common to all pixels.

[0033] The pixel driving voltage (EVDD) is set to a voltage higher than the maximum voltage of the data voltage (Vdata) and at which the driving element (DT) can operate in the saturation region. The initialization voltage (Vinit) can be set to a voltage between the maximum and minimum voltages of the data voltage (Vdata). The pixel reference voltage (ELVSS) is set to a voltage lower than the minimum voltage of the data voltage (Vdata). The reference voltage (Vref) can be set to a voltage lower than the pixel reference voltage (EVSS).

[0034] Gate signals (SCAN, INIT, SENSE, AR) are generated as pulses that swing between the gate-on voltage (VGH) and the gate-off voltage (VGL). The gate signals (SCAN, INIT, SENSE, AR) include a scan pulse (SCAN), an initialization pulse (INIT), a sensing pulse (SENSE), and an anode reset pulse (AR). The gate-on voltage (VGH) can be set to a voltage higher than the pixel driving voltage (EVDD). The gate-off voltage (VGL) can be set to a voltage lower than the reference voltage (Vref). The gate driver of the display device may include a first shift register that generates a scan pulse (SCAN), a second shift register that generates an initialization pulse (INIT), a third shift register that generates a sensing pulse (SENSE), and a fourth shift register that generates an anode reset pulse (AR).

[0035] The driving period of the pixel circuit can be divided into an initialization step (Pi), a sensing step (Ps), a data writing step (Pwr), an anode reset step (Par), a boosting step (Pb), and a light emission step (Pem), as shown in FIG. 2.

[0036] In the initialization step (Pi), as shown in FIG. 2, the initialization pulse (INIT) and the sensing pulse (SENSE) are generated as the gate-on voltage (VGH). In the initialization step (Pi), the scan pulse (SCAN) and the anode reset pulse (AR) are the gate-off voltage (VGL).

[0037] In the sensing phase (Ps), as shown in FIG. 2, the initialization pulse (INIT) is generated as the gate-on voltage (VGH). The sensing pulse (SENSE), scan pulse (SCAN), and anode reset pulse (AR) are the gate-off voltage (VGL) in the sensing phase (Ps).

[0038] In the data write step (Pwr), as shown in FIG. 2, the scan pulse (SCAN) is generated as a gate-on voltage (VGH) synchronized with the data voltage (Vdata) of the pixel data. The initialization pulse (INIT), sensing pulse (SENSE), and anode reset pulse (AR) are generated as a gate-off voltage (VGL) in the data write step (Pwr).

[0039] In the anode reset step (Par), as shown in FIG. 2, the anode reset pulse (AR) is generated as the gate-on voltage (VGH). The initialization pulse (INIT), sensing pulse (SENSE), and scan pulse (SCAN) are generated as the gate-off voltage (VGL) in the anode reset step (Par).

[0040] In the boosting phase (Pb) and the emission phase (Pem), all gate signals (SCAN, INIT, SENSE, AR) maintain the gate off voltage (VGL).

[0041] The light-emitting element (EL) can be implemented as an OLED. The OLED includes an organic compound layer formed between the anode electrode and the cathode electrode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). When voltage is applied to the anode electrode and the cathode electrode of the OLED, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML), forming excitons. At this time, visible light is emitted from the emission layer (EML). The anode electrode of the light-emitting element (EL) is connected to a third node (DTS). A pixel reference voltage (EVSS) is applied to the cathode electrode of the light-emitting element (EL). The light-emitting element (EL) includes a capacitor connected between the anode electrode and the cathode electrode. The capacitor of the light-emitting element (EL) is omitted from the drawing.

[0042] A driving element (DT) generates current according to the gate-source voltage (Vgs) to drive a light-emitting element (EL). The driving element (DT) includes a first electrode connected to a first node (DTD), a gate electrode connected to a second node (DTG), and a second electrode connected to a third node (DTS). The first node (DTD) may be connected to a VDD line to which a pixel driving voltage (EVDD) is applied.

[0043] The capacitor (Cst) is connected between the second node (DTG) and the third node (DTS) to store the gate-source voltage of the driving element (DT).

[0044] The switch elements (T1 to T4) of the pixel circuit include a first switch element (T1) that supplies the data voltage (Vdata) of the pixel data to a second node (DTG) in response to a scan pulse (SCAN), a second switch element (T2) that supplies the initialization voltage (Vinit) to the second node (DTG) in response to an initialization pulse (INIT), a third switch element (T3) that supplies the reference voltage (Vref) to a third node (DTS) in response to a sensing pulse (SENSE), and a fourth switch element (EVSS) that connects the third node (DTS) to the VSS line to which the pixel reference voltage (EVSS) is applied in response to an anode reset pulse (AR).

[0045] The first switch element (T1) is turned on according to the gate-on voltage (VGH) of a scan pulse (SCAN) synchronized with the data voltage (Vdata) of the pixel data in the data writing step (Pwr), and connects the data line (DL) to the second node (DTG). The data voltage (Vdata) is applied to the second node (DTG) in the data writing step (Pwr). The first switch element (T1) includes a first electrode connected to the data line (DL) to which the data voltage (Vdata) is applied, a gate electrode connected to the first gate line to which the scan pulse (SCAN) is applied, and a second electrode connected to the second node (DTG).

[0046] The second switch element (T2) is turned on according to the gate-on voltage (VGH) of the initialization pulse (INIT) in the initialization step (Pi) and the sensing step (Ps) to supply the initialization voltage (Vinit) to the second node (DTG). The second switch element (T2) includes a first electrode connected to the INIT line to which the initialization voltage (Vinit) is applied, a gate electrode connected to the second gate line to which the initialization pulse (INIT) is applied, and a second electrode connected to the second node (DTG).

[0047] The third switch element (T3) is turned on according to the gate-on voltage (VGH) of the sensing pulse (SENSE) in the initialization step (Pi) to supply a reference voltage (Vref) to the third node (DTS). The third switch element (T3) includes a first electrode connected to the third node (DTS), a gate electrode connected to a third gate line to which the sensing pulse (SENSE) is applied, and a second electrode connected to a REF line (RL) to which the reference voltage (Vref) is applied.

[0048] The fourth switch element (T4) is turned on according to the gate-on voltage (VGH) of the anode reset pulse (INIT2) in the anode reset step (Par) to connect the third node (DRS) to the VSS line. The fourth switch element (T4) includes a gate electrode connected to the fourth gate line to which the anode reset pulse (AR) is applied, a first electrode connected to the third node (DTS), and a second electrode connected to the VSS line.

[0049] In the initialization step (Pi), as shown in FIG. 3, the second and third switch elements (T2, T3) and the driving element (DT) are turned on, and the first and fourth switch elements (T1, T4) are turned off. At this time, the light-emitting element (EL) is not turned on. In the initialization step (Pi), the main nodes of the pixel circuit are initialized. In the initialization step (Pi), the voltage (Vg) of the second node (DRG) is Vg = Vinit, and the voltage (Vs) of the third node (DTS) is Vref. Therefore, in the initialization step (Pi), the gate-source voltage (Vgs) of the driving element (DT) is Vgs = Vinit - Vref.

[0050] In the sensing step (Ps), as shown in FIG. 4, the second switch element (T2) is turned on, while the first, third, and fourth switch elements (T1, T3, T4) are turned off. In the sensing step (Ps), the gate-source voltage (Vgs) of the driving element (DT) reaches the threshold voltage (Vth). In the sensing step (Ps), the voltage (Vs) of the third node (DTS) changes to Vs = Vinit - Vth, where Vth is the threshold voltage of the driving element (DT). Therefore, when the sensing step (Ps) ends, the gate-source voltage (Vgs) of the driving element (DT) becomes Vgs = Vth, and this threshold voltage (Vth) is sampled and stored in the capacitor (Cst).

[0051] In the data writing step (Pwr), as shown in FIG. 5, the first switch element (T1) is turned on, and other switch elements (T2, T3, T4), excluding the first switch element (T1), are turned off. At this time, the data voltage (Vdata) of the pixel data is applied to the second node (DTG). In the data writing step (Pwr), the voltage of the second node (DTG) changes to the data voltage (Vdata). At the end of the data writing step (Pwr), the voltage (Vg) of the second node (DTG) is Vg=Vdata, and the voltage (Vs) of the third node (DTS) is Vs=Vinit-Vth. Therefore, the gate-source voltage (Vgs) of the driving element (DT) changes to Vgs=Vdata-Vinit+Vth in the data writing step (Pwr).

[0052] In the anode reset step (Par), as shown in FIG. 6, the fourth switch element (T4) is turned on, and the other switch elements (T1, T2, T3), excluding the fourth switch element (T4), are turned off. In the anode reset step (Par), the voltage (Vs) of the third node (DTS) changes to Vs=EVSS, and the voltage (Vg) of the second node (DTG) changes to Vg=Vdata-Vinit+Vth+EVSS. The gate-source voltage (Vgs) of the driving element (DT) is maintained at Vgs=Vdata-Vinit+Vth.

[0053] In the boosting step (Pb), all switch elements (T1, T2, T3, T4) are turned off as shown in FIG. 7. At this time, the capacitor of the light-emitting element (EL) is charged. In the boosting step (Pb), the second and third nodes (DTG, DTS) are floated, and the voltages (Vg, Vs) of the second and third nodes (DTG, DTS) are raised by the capacitor voltage (Voled) of the light-emitting element (EL), changing to Vg = Vdata - Vinit + Vth + EVSS + Voled and Vs = EVSS + Voled. In the boosting step (Pb), the gate-source voltage (Vgs) of the driving element (DT) is maintained at Vgs = Vdata - Vinit + Vth. After the boosting step (Pb), in the light emission step (Pem), the current generated by the light-emitting element (EL) according to the gate-source voltage (Vgs) of the driving element (DT), i.e., Iel = K(Vdata-Vth) 2 The light-emitting element (EL) can emit light by this. Here, K is a constant value including the capacitance and mobility of the driving element.

[0054] The frame frequency of the input video can be varied over a wide frequency range, such as 30Hz, 60Hz, and 120Hz, as shown in FIG. 8. For example, a timing controller of a host system or display device can vary the frame frequency to match the movement or content characteristics of the input video. When the frame frequency is lowered, the 1 frame period (1FR) during which pixel data is written becomes longer, and the time period during which the data voltage (Vdata) is charged to the pixels becomes longer, causing the voltage of the third node (DTS) to change. In this case, the gate-source voltage (Vgs) of the driving element (DT) at the pixels changes, and the amount of current supplied to the light-emitting element (EL) changes. Therefore, the brightness of the pixels may change when the frame frequency is varied.

[0055] The present invention can prevent voltage fluctuations in the third node (DTS) by regularly repeating the anode reset step (Par) as shown in FIG. 8, even if the period during which pixel data is written to the pixels changes. The present invention can prevent fluctuations in the anode voltage by connecting the anode electrode of the light-emitting element (EL) to the VSS line, which is the power wiring with the lowest resistance, during the anode reset step (Par), thereby making the anode voltage and cathode voltage of the light-emitting element (EL) equal. The present invention can perform an anode reset without the need to additionally connect a separate anode reset voltage wiring to the pixel circuit.

[0056] FIG. 8 is a diagram showing the period of the sensing pulse and the anode reset pulse applied to the pixel circuit illustrated in FIG. 1 when the frame frequency is varied. In FIG. 8, the scan pulse (SCAN) is omitted.

[0057] Referring to FIG. 8, the frame frequency can be varied to 30Hz, 60Hz, 120Hz, etc. Since the frame period (1FR) is inversely proportional to the frame frequency, it can be varied according to the frame frequency. The frequency of the data addressing interval (B), where pixel data is written to pixels, varies in proportion to the frame frequency. In contrast, the frequency of the anode reset interval (A) is controlled to the same frequency, for example, 120Hz, even if the frame frequency is varied. The anode reset interval (A) is performed repeatedly at a constant time period even if the frame frequency changes, thereby suppressing voltage fluctuations of the third node (DRS).

[0058] The data addressing interval (B) includes an initialization step (Pi), a sensing step (Ps), a data writing step (Pwr), an anode reset step (Par), a boosting step (Pb), and a light emission step (Pem). Accordingly, in the data addressing interval (B), all gate signals (SCAN, INIT, SENSE, AR) and data voltage (Vdata) shown in FIG. 2 are generated.

[0059] In the anode reset period (A), the anode reset pulse (AR) is generated at the gate-on voltage (VGH), and other gate signals (SCAN, INIT, SENSE) are not generated. In other words, in the anode reset period (A), the voltages of the first to third gate lines are maintained at the gate-off voltage (VGL), and the anode pulse (AR) is applied to the fourth gate line.

[0060] At a frame frequency of 120Hz, the data addressing interval (B) is repeated at 120Hz to sense the threshold voltage of the driving element (DT) and write pixel data to the pixels, and pulses of gate signals (SCAN, INIT, SENSE, AR) as shown in FIG. 2 are supplied to the pixels.

[0061] At a frame frequency of 60Hz, the data addressing interval (B) is repeated at 60Hz, and pulses of gate signals (SCAN, INIT, SENSE, AR) as shown in FIG. 2 are supplied to the pixels. In contrast, the anode reset interval (A) is repeated at 120Hz, which is higher than the frame frequency, and an anode reset pulse (AR) is supplied to the pixels at that frequency. As a result, while pixel data is written to the pixels at a frame frequency of 60Hz, the voltage of the third node (DTS) is reset to a frequency of 120Hz, so that voltage fluctuations of the third node (DTS) can be suppressed.

[0062] 30Hz의 프레임 주파수에서, 데이터 어드레싱 구간(B)은 30Hz로 반복되어 도 2와 같은 게이트 신호들(SCAN, INIT, SENSE, AR)의 펄스가 픽셀들이 공급된다. 이에 비하여, 애노드 리셋 구간(A)은 프레임 주파수 보다 높은 120Hz로 반복되어 그 주파수로 애노드 리셋 펄스(AR)가 픽셀들에 공급된다. 그 결과, 30Hz의 프레임 주파수로 픽셀들에 픽셀 데이터가 기입되는 동안, 제3 노드(DTS)의 전압이 120Hz의 주파수로 리셋되어 제3 노드(DTS)의 전압 변동이 억제될 수 있다.

[0063] When the frame frequency of the input image changes, the frequency of the data addressing interval (B) changes accordingly, so the frequencies of the initialization pulse (INIT), sensing pulse (SENSE), and scan pulse (SCAN) applied to the pixels change in proportion to the frame frequency. In contrast, the anode reset pulse (AR) is applied to the pixels at a constant fixed frequency regardless of how the frame frequency of the input image changes, so it is possible to prevent changes in the brightness of the pixels that occur when the frame frequency changes.

[0064] FIGS. 9a and 9b are circuit diagrams showing pixel circuits according to a second embodiment of the present invention. FIG. 10 is a waveform diagram showing gate signals and data voltages applied to the pixel circuits illustrated in FIGS. 9a and 9b. FIG. 11a is a circuit diagram showing the operation of the pixel circuit illustrated in FIG. 9a during the anode reset step (Par). FIG. 11b is a circuit diagram showing the operation of the pixel circuit illustrated in FIG. 9b during the anode reset step (Par). In this embodiment, components substantially identical to those in the first embodiment described above are given the same reference numerals, and a detailed description thereof is omitted.

[0065] 도 9a 내지 도 11b를 참조하면, 픽셀 회로는 발광 소자(EL), 발광 소자(EL)를 구동하는 구동 소자(DT), 복수의 스위치 소자들(T1~T52), 및 커패시터(Cst)를 포함한다. 구동 소자(DT)와 스위치 소자들(T1~T52)은 n 채널 Oxide TFT로 구현될 수 있다.

[0066] The pixel circuit is connected to a data line (DL) to which a data voltage (Vdata) is applied, and to gate lines to which gate signals (SCAN, INIT, SENSE, AR) are applied. Additionally, the pixel circuit is connected to power lines to which DC voltage (or constant voltage) is applied, such as the VDD line to which the pixel driving voltage (EVDD) is applied, the VSS line to which the pixel reference voltage (EVSS) is applied, the INIT line to which the initialization voltage (Vinit) is applied, and the REF line (RL) to which the reference voltage (Vref) is applied. The power lines can be connected in common to all pixels.

[0067] The constant voltage, data voltage, and the voltages (VGH, VGL) of the gate signals (SCAN, INIT, SENSE, AR) applied to the pixel circuit can be set in the same way as in the first embodiment described above. In this embodiment, the gate signal further includes a light emission control pulse (hereinafter referred to as “pulse”) for controlling the fifth switch element (T51, T52). The gate-on voltage (VEH) of the EM pulse can be set to be the same as or different from the gate-on voltage (VGH) of the other gate signals (SCAN, INIT, SENSE, AR). The gate-off voltage (VEL) of the EM pulse can be set to be the same as or different from the gate-off voltage (VEL) of the other gate signals (SCAN, INIT, SENSE, AR).

[0068] Gate signals (SCAN, INIT, SENSE, AR, EM) are generated as pulses swinging between gate-on voltages (VGH, VEH) and gate-off voltages (VGL, VEL). The gate driver of the display device may include a first shift register that generates a scan pulse (SCAN), a second shift register that generates an initialization pulse (INIT), a third shift register that generates a sensing pulse (SENSE), a fourth shift register that generates an anode reset pulse (AR), and a fifth shift register that generates an EM pulse.

[0069] The driving period of the pixel circuit can be divided into an initialization step (Pi), a sensing step (Ps), a data writing step (Pwr), an anode reset step (Par), a boosting step (Pb), and a light emission step (Pem), as shown in FIG. 10.

[0070] In the initialization step (Pi), as shown in FIG. 10, the initialization pulse (INIT), sensing pulse (SENSE), and EM pulse (EM) are generated as gate-on voltages (VGH, VEH). In the initialization step (Pi), the scan pulse (SCAN) and anode reset pulse (AR) are gate-off voltages (VGL).

[0071] In the sensing stage (Ps), as shown in FIG. 10, the initialization pulse (INIT) and the EM pulse (EM) are generated as the gate-on voltage (VGH, VEH). The sensing pulse (SENSE), scan pulse (SCAN), and anode reset pulse (AR) are the gate-off voltage (VGL) in the sensing stage (Ps).

[0072] In the data write step (Pwr), as shown in FIG. 10, a scan pulse (SCAN) is generated at a gate-on voltage (VGH) synchronized with the data voltage (Vdata) of the pixel data. In the data write step (Pwr), an EM pulse (EM) maintains the gate-on voltage (VEH). An initialization pulse (INIT), a sensing pulse (SENSE), and an anode reset pulse (AR) are generated at the gate-off voltage (VGL) in the data write step (Pwr).

[0073] In the anode reset step (Par), as shown in FIG. 10, the anode reset pulse (AR) is generated as the gate-on voltage (VGH). In the anode reset step (Par), the EM pulse is inverted to the gate-off voltage (VEL) to block the current path between the pixel driving voltage (EVDD) and the light-emitting element (EL). The initialization pulse (INIT), sensing pulse (SENSE), and scan pulse (SCAN) are generated as the gate-off voltage (VGL) in the anode reset step (Par).

[0074] In the boosting phase (Pb) and the emission phase (Pem), the EM pulse (EM) is generated as the gate-on voltage (VEH), and other gate signals (SCAN, INIT, SENSE, AR) are the gate-off voltage (VGL).

[0075] The fifth switch element (T51, T52) may include one or more of the following: a fifth-1 switch element (T51) connected between the VDD line to which the pixel driving voltage (EVDD) is applied and the first node (DTD) as shown in FIG. 9a, and a fifth-2 switch element (T52) connected between the driving element (DT) and the light-emitting element (EL).

[0076] The 5-1 switch element (T51) supplies a pixel driving voltage (EVDD) to the first node (DTD) according to the gate-on voltage (VEH) of the EM pulse and blocks the current path between the VDD line and the first node (DTD) in the anode reset step (A). The 5-1 switch element (T51) includes a gate electrode connected to a fifth gate line to which the EM pulse (EM) is applied, a first electrode connected to the VDD line, and a second electrode connected to the first node (DTD).

[0077] The 5-2 switch element (T52) connects the third node (DTS) to the anode electrode of the light-emitting element (EL) according to the gate-on voltage (VEH) of the EM pulse, and blocks the current path between the third node (DTS) and the anode electrode of the light-emitting element (EL) in the anode reset step (A). The 5-2 switch element (T52) includes a gate electrode connected to a fifth gate line to which the EM pulse (EM) is applied, a first electrode connected to the third node (DTS), and a second electrode connected to the anode electrode of the light-emitting element (EL).

[0078] In the initialization step (Pi), the second, third, and fifth switch elements (T2, T3, T51, T52) and the driving element (DT) are turned on, and the first and fourth switch elements (T1, T4) are turned off. At this time, the light-emitting element (EL) is not turned on. In the initialization step (Pi), the main nodes of the pixel circuit are initialized.

[0079] In the sensing step (Ps), the second and fifth switch elements (T2, T51, T52) are turned on, while the first, third, and fourth switch elements (T1, T3, T4) are turned off. In the sensing step (Ps), the gate-source voltage (Vgs) of the driving element (DT) reaches a threshold voltage (Vth). In the sensing step (Ps), the threshold voltage (Vth) of the driving element (DT) is sampled and stored in the capacitor (Cst).

[0080] In the data writing step (Pwr), the first and fifth switch elements (T1, T51, T52) are turned on, and the other switch elements (T2, T3, T4) are turned off. At this time, the data voltage (Vdata) of the pixel data is applied to the second node (DTG).

[0081] In the anode reset step (Par), as shown in FIG. 11a and FIG. 11b, the fourth switch element (T4) is turned on, and the other switch elements (T1, T2, T3, T51, T52) are turned off.

[0082] In the boosting step (Pb), other switch elements (T1, T2, T3, T4), excluding the fifth switch element (T51, T52), are turned off. At this time, the capacitor of the light-emitting element (EL) is charged. In the boosting step (Pb), the second and third nodes (DTG, DTS) are floated, and the voltages (Vg, Vs) of the second and third nodes (DTG, DTS) are raised by the capacitor voltage (Voled) of the light-emitting element (EL). After the boosting step (Pb), in the light-emitting step (Pem), the light-emitting element (EL) can emit light due to the current generated according to the gate-source voltage (Vgs) of the driving element (DT).

[0083] The frame frequency of the input video can be varied over a wide frequency range, such as 30Hz, 60Hz, 120Hz, and 240Hz, as shown in FIG. 12. For example, a timing controller of a host system or display device can vary the frame frequency to match the movement or content characteristics of the input video. When the frame frequency is lowered, the 1 frame period (1FR) during which pixel data is written becomes longer, and the time period during which the data voltage (Vdata) is charged to the pixels becomes longer, causing the voltage of the third node (DTS) to change. In this case, the gate-source voltage (Vgs) of the driving element (DT) at the pixels changes, and the amount of current supplied to the light-emitting element (EL) changes. Therefore, the brightness of the pixels may change when the frame frequency is varied.

[0084] The present invention can prevent voltage fluctuations in the third node (DTS) by regularly repeating the anode reset step (Par) as shown in FIG. 12, even if the period during which pixel data is written to the pixels changes. The present invention can prevent fluctuations in the anode voltage by connecting the anode electrode of the light-emitting element (EL) to the VSS line, which is the power wiring with the lowest resistance, during the anode reset step (Par), thereby making the anode voltage and cathode voltage of the light-emitting element (EL) equal. The present invention can perform an anode reset without the need to additionally connect a separate anode reset voltage wiring to the pixel circuit.

[0085] FIG. 12 is a diagram showing the period of the sensing pulse and anode reset pulse applied to the pixel circuit shown in FIG. 9a and FIG. 9b when the frame frequency is varied.

[0086] Referring to FIG. 12, the frame frequency can be varied to 30Hz, 60Hz, 120Hz, 240Hz, etc. Since the frame period (1FR) is inversely proportional to the frame frequency, it can be varied according to the frame frequency. The frequency of the data addressing interval (B), where pixel data is written to pixels, varies in proportion to the frame frequency. In contrast, the frequency of the anode reset interval (A) is controlled to the same frequency, for example, 120Hz, even if the frame frequency is varied. The anode reset interval (A) is performed repeatedly at a constant time interval even if the frame frequency changes, thereby suppressing voltage fluctuations of the third node (DRS).

[0087] The data addressing interval (B) includes an initialization step (Pi), a sensing step (Ps), a data writing step (Pwr), an anode reset step (Par), a boosting step (Pb), and a light emission step (Pem). Accordingly, during the data addressing interval (B), all gate signals (SCAN, INIT, SENSE, AR, EM) and data voltage (Vdata) shown in FIG. 10 are generated.

[0088] During the anode reset period (A), as shown in FIG. 13, an anode reset pulse (AR) is generated as the gate-on voltage (VGH) and an EM pulse (EM) is generated as the gate-off voltage (VEL). During the anode reset period (A), other gate signals (SCAN, INIT, SENSE) and the pixel data data voltage (Vdata) are not generated.

[0089] An EM OFF period (C) can be set in which the fifth switch elements (T51, T52) are turned off without data addressing and anode reset. During the EM OFF period (C), as shown in FIG. 14, among the gate signals (SCAN, INIT, SENSE, AR, EM), only the EM pulse (EM) of the gate off voltage (VEL) is generated, and the pulses of the other gate signals (SCAN, INIT, SENSE, AR) and the data voltage (Vdata) of the pixel data are not generated. Since the EM pulse (EM) is generated in the anode reset period (A), the data addressing period (B), and the EM OFF period (C), the frequency of the EM pulse (EM) may be higher than the frequency of the anode reset pulse (AR).

[0090] At a frame frequency of 120 Hz, the data addressing interval (B) is repeated at 120 Hz to sense the threshold voltage of the driving element (DT) and write pixel data to the pixels, and pulses of gate signals (SCAN, INIT, SENSE, AR, EM) as shown in FIG. 10 are supplied to the pixels. The EM OFF interval (C) can be set after the data addressing interval (B). The EM OFF interval (C) can be repeated at 120 Hz at a frame frequency of 120 Hz. Since the EM pulse (EM) occurs during the data addressing interval (B) and the EM OFF interval (C), it can be supplied to the pixels at a frequency of 240 Hz.

[0091] At a frame frequency of 60Hz, the data addressing interval (B) is repeated at 60Hz, and pulses of gate signals (SCAN, INIT, SENSE, AR, EM) as shown in FIG. 10 are supplied to the pixels. The anode reset interval (A) can be set after the EM OFF interval (OFF). The anode reset pulse (AR) is generated during the anode reset interval (A) and the data addressing interval (B). As a result, while pixel data is written to the pixels at a frame frequency of 60Hz, the voltage of the third node (DTS) is reset to a frequency of 120Hz, thereby suppressing voltage fluctuations of the third node (DTS). The EM OFF interval (C) is allocated between the data addressing interval (B) and the anode reset interval (A) at a frame frequency of 60Hz. The EM pulse (EM) can be supplied to the pixels at a frequency of 240Hz even if the frame frequency is lowered to 60Hz.

[0092] At a frame frequency of 30Hz, the data addressing interval (B) is repeated at 30Hz, and pulses of gate signals (SCAN, INIT, SENSE, AR, EM) as shown in FIG. 10 are supplied to the pixels. The anode reset interval (A) can be set after the EM OFF interval (OFF). The anode reset pulse (AR) is generated during the anode reset interval (A) and the data addressing interval (B). As a result, while pixel data is written to the pixels at a frame frequency of 30Hz, the voltage of the third node (DTS) is reset to a frequency of 120Hz, thereby suppressing voltage fluctuations of the third node (DTS). The EM OFF interval (C) is allocated between the data addressing interval (B) and the anode reset interval (A) at a frame frequency of 30Hz. The EM pulse (EM) can be supplied to the pixels at a frequency of 240Hz even if the frame frequency is lowered to 60Hz.

[0093] Therefore, the present invention can prevent changes in the brightness of pixels that occur when the frame frequency changes because the anode reset pulse (AR) is applied to the pixels at the same frequency regardless of how the frame frequency changes.

[0094] FIG. 15 is a circuit diagram showing a pixel circuit according to a third embodiment of the present invention. FIG. 16 is a waveform diagram showing a gate signal and a data voltage applied to the pixel circuit illustrated in FIG. 15. FIG. 17 to 21 are drawings showing the operation of the pixel circuit illustrated in FIG. 15 in steps. In this embodiment, components substantially identical to those in the previously described embodiments are given the same reference numerals, and a detailed description thereof is omitted.

[0095] Referring to FIGS. 15 to 21, the pixel circuit includes a light-emitting element (EL), a driving element (DT) that drives the light-emitting element (EL), a plurality of switching elements (T1 to T42), and a capacitor (Cst). The driving element (DT) and the switching elements (T1 to T42) can be implemented as n-channel oxide TFTs.

[0096] The pixel circuit is connected to a data line (DL) to which a data voltage (Vdata) is applied, and to gate lines to which gate signals (SCAN, INIT, SENSE, AR) are applied. Additionally, the pixel circuit is connected to power lines to which DC voltage (or constant voltage) is applied, such as the VDD line to which the pixel driving voltage (EVDD) is applied, the VSS line to which the pixel reference voltage (EVSS) is applied, the INIT line to which the initialization voltage (Vinit) is applied, and the REF line (RL) to which the reference voltage (Vref) is applied. The power lines can be connected in common to all pixels.

[0097] The voltages (VGH, VGL) of the constant voltage, data voltage, and gate signals (SCAN, INIT, SENSE, AR) applied to the pixel circuit can be set in the same way as in the aforementioned embodiments.

[0098] Gate signals (SCAN, INIT, SENSE, AR) are generated as pulses swinging between the gate-on voltage (VGH) and the gate-off voltage (VGL). The gate driver of the display device may include a first shift register that generates a scan pulse (SCAN), a second shift register that generates an initialization pulse (INIT), a third shift register that generates a sensing pulse (SENSE), and a fourth shift register that generates an anode reset pulse (AR).

[0099] The driving period of the pixel circuit can be divided into an initialization step (Pi), a sensing step (Ps), a data writing step (Pwr), an anode reset step (Par), a boosting step (Pb), and a light emission step (Pem), as shown in FIG. 16.

[0100] In the initialization step (Pi), as shown in FIG. 16, the initialization pulse (INIT), sensing pulse (SENSE), and anode reset pulse (AR) are generated as the gate-on voltage (VGH). In the initialization step (Pi), the scan pulse (SCAN) is the gate-off voltage (VGL).

[0101] In the sensing phase (Ps), as shown in FIG. 16, the initialization pulse (INIT) and the anode reset pulse (AR) are generated as the gate-on voltage (VGH). The sensing pulse (SENSE) and the scan pulse (SCAN) are the gate-off voltage (VGL) in the sensing phase (Ps).

[0102] In the data write step (Pwr), as shown in FIG. 16, a scan pulse (SCAN) is generated at a gate-on voltage (VGH) synchronized with the data voltage (Vdata) of the pixel data. In the data write step (Pwr), an anode reset pulse (AR) maintains the gate-on voltage (VGH). An initialization pulse (INIT) and a sensing pulse (SENSE) are generated at the gate-off voltage (VGL) in the data write step (Pwr).

[0103] In the anode reset phase (Par), as illustrated in FIG. 16, the sensing pulse (SENSE) is generated at the gate-on voltage (VGH), and the anode reset pulse (AR) is generated at the gate-off voltage (VGL). In the anode reset phase (Par), the initialization pulse (INIT) and the sensing pulse (SENSE) are the gate-off voltage (VGL). The rising timing of the change from the gate-on voltage (VGH) to the gate-off voltage (VGL) in the anode reset pulse (AR) may lead the rising timing of the change from the gate-off voltage (VGL) to the gate-on voltage (VGH) in the sensing pulse (SENSE). Additionally, the falling timing of the change from the gate-off voltage (VGL) to the gate-on voltage (VGH) in the anode reset pulse (AR) may lead the falling timing of the change from the gate-on voltage (VGH) to the gate-off voltage (VGL) in the sensing pulse (SENSE).

[0104] In the boosting phase (Pb) and the emission phase (Pem), the anode reset pulse (AR) is generated as the gate-on voltage (VGH), and the other gate signals (SCAN, INIT, SENSE) are the gate-off voltage (VGL).

[0105] In this pixel circuit, a capacitor (Cst) that stores the gate-source voltage (Vgs) of the driving element is connected between the second node (DTG) and the fourth node (n4).

[0106] The fourth switch element (T42) connects the capacitor (Cst) to the third node (DTS) in the initialization step (Pi), sensing step (Ps), data writing step (Pwr), boosting step (Pwr), and light emission step (Pem) in response to the gate-on voltage (VGH) of the anode reset pulse (AR). The fourth switch element (T42) is turned off in the anode reset step (Par) according to the gate-off voltage (VGL) of the anode reset pulse (AR), thereby blocking the current path between the capacitor (Cst) and the third node (DTS). The fourth switch element (T42) includes a gate electrode connected to a fifth gate line to which the EM pulse (EM) is applied, a first electrode connected to the fourth node (n4), and a second electrode connected to the third node (DTS).

[0107] In the initialization step (Pi), as illustrated in FIG. 17, the second, third, and fourth switch elements (T2, T3, T42) and the driving element (DT) are turned on, and the first switch element (T1, T4) is turned off. At this time, the light-emitting element (EL) is not turned on. In the initialization step (Pi), the main nodes of the pixel circuit are initialized. In the initialization step (Pi), the voltage (Vg) of the second node (DRG) is Vg = Vinit, and the voltage (Vs) of the third node (DTS) is Vref. Therefore, in the initialization step (Pi), the gate-source voltage (Vgs) of the driving element (DT) is Vgs = Vinit - Vref.

[0108] In the sensing step (Ps), as shown in FIG. 18, the second and fourth switch elements (T2, T42) are turned on, while the first and third switch elements (T1, T3) are turned off. In the sensing step (Ps), the gate-source voltage (Vgs) of the driving element (DT) reaches a threshold voltage (Vth). In the sensing step (Ps), the voltage (Vs) of the third node (DTS) changes to Vs = Vinit - Vth. Therefore, at the end of the sensing step (Ps), the gate-source voltage (Vgs) of the driving element (DT) becomes Vgs = Vth, and this threshold voltage (Vth) is sampled and stored in the capacitor (Cst).

[0109] In the data writing step (Pwr), as illustrated in FIG. 19, the first and fourth switch elements (T1, T42) are turned on, and the other switch elements (T2, T3) are turned off. At this time, the data voltage (Vdata) of the pixel data is applied to the second node (DTG). In the data writing step (Pwr), the voltage of the second node (DTG) changes to the data voltage (Vdata). At the end of the data writing step (Pwr), the voltage (Vg) of the second node (DTG) is Vg=Vdata, and the voltage (Vs) of the third node (DTS) is Vs=Vinit-Vth. Therefore, the gate-source voltage (Vgs) of the driving element (DT) changes to Vgs=Vdata-Vinit+Vth in the data writing step (Pwr).

[0110] In the anode reset step (Par), as shown in FIG. 20, the third switch element (T3) is turned on, and the other switch elements (T1, T2, T3, T42) are turned off. At this time, the third node (DTS) is reset to a reference voltage (Vref). In the anode reset step (Par), the voltage (Vs) of the third node (DTS) changes to Vs=Vref, and the voltage (Vg) of the second node (DTG) changes to Vg=Vdata-Vinit+Vth+Vref. The gate-source voltage (Vgs) of the driving element (DT) maintains Vgs=Vdata-Vinit+Vth.

[0111] In the boosting step (Pb), other switch elements (T1, T2, T3), excluding the fourth switch element (T42), are turned off. At this time, the capacitor of the light-emitting element (EL) is charged. In the boosting step (Pb), the second and third nodes (DTG, DTS) are floated, and the voltages (Vg, Vs) of the second and third nodes (DTG, DTS) are increased by the capacitor voltage (Voled) of the light-emitting element (EL). In the boosting step (Pb), the second and third nodes (DTG, DTS) are floated, and the voltages (Vg, Vs) of the second and third nodes (DTG, DTS) are increased by the capacitor voltage (Voled) of the light-emitting element (EL), changing to Vg = Vdata - Vinit + Vth + Vref + Voled, and Vs = Vref + Voled. In the boosting step (Pb), the gate-source voltage (Vgs) of the driving element (DT) is maintained as Vgs = Vdata - Vinit + Vth. After the boosting step (Pb), in the light-emitting step (Pem), as shown in FIG. 21, the light-emitting element (EL) can emit light due to the current generated according to the gate-source voltage (Vgs) of the driving element (DT).

[0112] In this embodiment, the frame frequency of the input image can be varied over a wide frequency range, such as 30 Hz, 60 Hz, or 120 Hz, as shown in FIG. 8. For example, a timing controller of a host system or a display device can vary the frame frequency to match the movement or content characteristics of the input image. When the frame frequency is lowered, the 1 frame period (1FR) during which pixel data is written becomes longer, and the time period during which the data voltage (Vdata) is charged to the pixels becomes longer, causing the voltage of the third node (DTS) to change. In this case, the gate-source voltage (Vgs) of the driving element (DT) at the pixels changes, and the amount of current supplied to the light-emitting element (EL) changes. Therefore, the brightness of the pixels may change when the frame frequency is varied.

[0113] When the frame frequency of the input image varies, the pixel circuit illustrated in FIG. 15 can be driven as illustrated in FIG. 8. Even if the period during which pixel data is written to the pixels changes, the pixel circuit illustrated in FIG. 15 can prevent voltage fluctuations of the third node (DTS) by regularly repeating the anode reset step (Par), as can be seen in the anode reset section (A) illustrated in FIG. 8. The present invention can prevent fluctuations in the anode voltage by resetting the anode voltages of the third node (DTS) and the light-emitting element (EL) to a reference voltage (Vref) during the anode reset step (Par). The present invention can perform an anode reset without the need to additionally connect a separate anode reset voltage wiring to the pixel circuit.

[0114] FIGS. 22a and 22b are circuit diagrams showing pixel circuits according to a fourth embodiment of the present invention. FIG. 23 is a waveform diagram showing gate signals and data voltages applied to the pixel circuits illustrated in FIGS. 22a and 22b. FIGS. 24a and 24b are circuit diagrams showing the operation of the pixel circuits illustrated in FIGS. 22a and 22b during the anode reset step. Detailed descriptions of components in FIGS. 22a through 24b that are substantially the same as those in the previously described embodiments are omitted.

[0115] Referring to FIGS. 22a through 24b, the pixel circuit includes a light-emitting element (EL), a driving element (DT) for driving the light-emitting element (EL), a plurality of switching elements (T1 to T54), and a capacitor (Cst). The driving element (DT) and the switching elements (T1 to T54) can be implemented as n-channel oxide TFTs.

[0116] The voltages (VGH, VGL) of the constant voltage, data voltage, and gate signals (SCAN, INIT, SENSE, AR) applied to the pixel circuit can be set in the same way as in the aforementioned embodiments.

[0117] Gate signals (SCAN, INIT, SENSE, AR, EM) are generated as pulses swinging between gate-on voltages (VGH, VEH) and gate-off voltages (VGL, VEL). The gate driver of the display device may include a first shift register that generates a scan pulse (SCAN), a second shift register that generates an initialization pulse (INIT), a third shift register that generates a sensing pulse (SENSE), a fourth shift register that generates an anode reset pulse (AR), and a fifth shift register that generates an EM pulse.

[0118] The driving period of the pixel circuit can be divided into an initialization step (Pi), a sensing step (Ps), a data writing step (Pwr), an anode reset step (Par), a boosting step (Pb), and a light emission step (Pem), as shown in FIG. 23.

[0119] In the initialization step (Pi), as shown in FIG. 23, the initialization pulse (INIT), sensing pulse (SENSE), anode reset pulse (AR), and EM pulse (EM) are generated as gate-on voltages (VGH, VEH). In the initialization step (Pi), the scan pulse (SCAN) is the gate-off voltage (VGL).

[0120] In the sensing stage (Ps), as shown in FIG. 23, the initialization pulse (INIT), anode reset pulse (AR), and EM pulse (EM) are generated as gate-on voltages (VGH, VEH). The sensing pulse (SENSE) and scan pulse (SCAN) are the gate-off voltage (VGL) in the sensing stage (Ps).

[0121] In the data write step (Pwr), as shown in FIG. 23, a scan pulse (SCAN) is generated at a gate-on voltage (VGH) synchronized with the data voltage (Vdata) of the pixel data. In the data write step (Pwr), an anode reset pulse (AR) and an EM pulse (EM) maintain the gate-on voltage (VEH). An initialization pulse (INIT) and a sensing pulse (SENSE) are generated at the gate-off voltage (VGL) in the data write step (Pwr).

[0122] In the anode reset phase (Par), as shown in FIG. 23, the sensing pulse (SENSE) is generated as the gate-on voltage (VGH). In the anode reset phase (Par), the anode reset pulse (AR) and the EM pulse (EM) are inverted to the gate-off voltage (VEL). The initialization pulse (INIT) and the scan pulse (SCAN) are generated as the gate-off voltage (VGL) in the anode reset phase (Par).

[0123] In the boosting phase (Pb) and the emitting phase (Pem), the anode reset pulse (AR) and the EM pulse (EM) are generated as the gate-on voltage (VEH), and other gate signals (SCAN, INIT, SENSE) are the gate-off voltage (VGL).

[0124] 제5 스위치 소자(T53, T54)는 도 22a에 도시된 바와 같이 픽셀 구동 전압(EVDD)이 인가되는 VDD 라인과 제1 노드(DTD) 사이에 연결된 제5-1 스위치 소자(T53)와, 구동 소자(DT)와 발광 소자(EL) 사이에 연결된 제5-2 스위치 소자(T54) 중 하나 이상을 포함할 수 있다.

[0125] The 5-1 switch element (T53) includes a gate electrode connected to a 5th gate line to which an EM pulse (EM) is applied, a first electrode connected to a VDD line, and a second electrode connected to a 1st node (DTD). The 5-2 switch element (T52) includes a gate electrode connected to a 5th gate line to which an EM pulse (EM) is applied, a first electrode connected to a 3rd node (DTS), and a second electrode connected to the anode electrode of a light-emitting element (EL).

[0126] 초기화 단계(Pi)에서, 제2, 제3, 제4 및 제5 스위치 소자들(T2, T3, T42, T53, T54)과 구동 소자(DT)가 턴-온되고, 제1 스위치 소자(T1)는 턴-오프된다. 이 때, 발광 소자(EL)는 턴-온되지 않는다. 초기화 단계(Pi)에서, 픽셀 회로의 주요 노드들이 초기화된다.

[0127] In the sensing step (Ps), the second, fourth, and fifth switch elements (T2, T42, T53, T54) are turned on, while the first and third switch elements (T1, T3) are turned off. In the sensing step (Ps), the gate-source voltage (Vgs) of the driving element (DT) reaches a threshold voltage (Vth). In the sensing step (Ps), the threshold voltage (Vth) of the driving element (DT) is sampled and stored in the capacitor (Cst).

[0128] 데이터 기입 단계(Pwr)에서, 제1, 제4 및 제5 스위치 소자들(T1, T42, T53, T54)가 턴-온되고, 다른 스위치 소자들(T2, T3)은 턴-오프된다. 이 때, 픽셀 데이터의 데이터 전압(Vdata)이 제2 노드(DTG)에 인가된다.

[0129] In the anode reset step (Par), as shown in FIG. 24a and FIG. 24b, the third switch element (T3) is turned on, and the other switch elements (T1, T2, T42, T53, T54) are turned off.

[0130] In the boosting step (Pb), other switch elements (T1, T2, T3) are turned off, excluding the fourth and fifth switch elements (T42, T53, T54). At this time, the capacitor of the light-emitting element (EL) is charged. In the boosting step (Pb), the second and third nodes (DTG, DTS) are floated, and the voltages (Vg, Vs) of the second and third nodes (DTG, DTS) are raised by the capacitor voltage (Voled) of the light-emitting element (EL). After the boosting step (Pb), in the light-emitting step (Pem), the light-emitting element (EL) can emit light due to the current generated according to the gate-source voltage (Vgs) of the driving element (DT).

[0131] When the frame frequency of the input image is varied, the pixel circuit shown in FIG. 22a and FIG. 22b can be driven as shown in FIG. 12.

[0132] The frame frequency of the input image can be varied over a wide frequency range, such as 30Hz, 60Hz, 120Hz, and 240Hz, as shown in FIG. 12. Even if the period during which pixel data is written to the pixels changes, voltage fluctuations of the third node (DTS) can be prevented by regularly repeating the anode reset step (Par), as can be seen in the anode reset section (A) shown in FIG. 12. The present invention can perform an anode reset without the need to additionally connect a separate anode reset voltage wiring to the pixel circuit.

[0133] During the anode reset period (A), as shown in FIG. 25, a sensing pulse (SENSE) is generated as the gate-on voltage (VGH), and the anode reset pulse (AR) and EM pulse (EM) are inverted to the gate-off voltage (VEL). During the anode reset period (A), other gate signals (SCAN, INIT) and the data voltage (Vdata) of the pixel data are not generated. Therefore, the present invention can prevent changes in the luminance of pixels that occur when the frame frequency changes, because the anode reset pulse (AR) is applied to the pixels at the same frequency regardless of how the frame frequency changes.

[0134] During the EM OFF period (C), as shown in FIG. 26, the sensing pulse (SENSE) is generated as the gate-on voltage (VGH) and the EM pulse (EM) is inverted to the gate-off voltage (VEL). During the EM OFF period (C), pulses of other gate signals (SCAN, INIT) and the data voltage (Vdata) of the pixel data are not generated.

[0135] FIG. 27 is a circuit diagram showing a pixel circuit according to a fifth embodiment of the present invention. FIG. 28 is a waveform diagram showing a gate signal and a data voltage applied to the pixel circuit shown in FIG. 27. FIG. 29 to 33 are drawings showing the operation of the pixel circuit shown in FIG. 27 in steps. In this embodiment, components substantially identical to those in the previously described embodiments are given the same reference numerals, and a detailed description thereof is omitted.

[0136] Referring to FIGS. 27 to 33, the pixel circuit includes a light-emitting element (EL), a driving element (DT) for driving the light-emitting element (EL), a plurality of switching elements (T1 to T3), and a plurality of capacitors (Cst, Cel, C2). The driving element (DT) and the switching elements (T1 to T3) can be implemented as n-channel oxide TFTs.

[0137] The pixel circuit is connected to a data line (DL) to which a data voltage (Vdata) is applied, and to gate lines to which gate signals (SCAN, INIT, SENSE) are applied. Additionally, the pixel circuit is connected to power lines to which DC voltage (or constant voltage) is applied, such as the VDD line to which the pixel driving voltage (EVDD) is applied, the VSS line to which the pixel reference voltage (EVSS) is applied, the INIT line to which the initialization voltage (Vinit) is applied, and the REF line (RL) to which the reference voltage (Vref) is applied. The power lines can be connected in common to all pixels.

[0138] Gate signals (SCAN, INIT, SENSE) are generated as pulses that swing between the gate-on voltage (VGH) and the gate-off voltage (VGL). The gate signals (SCAN, INIT, SENSE) include a scan pulse (SCAN), an initialization pulse (INIT), and a sensing pulse (SENSE). The gate driver of the display device may include a first shift register that generates a scan pulse (SCAN), a second shift register that generates an initialization pulse (INIT), and a third shift register that generates a sensing pulse (SENSE).

[0139] The driving period of the pixel circuit can be divided into an initialization step (Pi), a sensing step (Ps), a data writing step (Pwr), an anode reset step (Par), a boosting step (Pb), and a light emission step (Pem), as shown in FIG. 28.

[0140] In the initialization step (Pi), as shown in FIG. 28, the initialization pulse (INIT) and the sensing pulse (SENSE) are generated as the gate-on voltage (VGH). In the initialization step (Pi), the scan pulse (SCAN) is the gate-off voltage (VGL).

[0141] In the sensing step (Ps), as shown in FIG. 28, the initialization pulse (INIT) is generated as the gate-on voltage (VGH). The sensing pulse (SENSE) and scan pulse (SCAN) are the gate-off voltage (VGL) in the sensing step (Ps).

[0142] In the data writing step (Pwr), as shown in FIG. 28, the scan pulse (SCAN) is generated as a gate-on voltage (VGH) synchronized with the data voltage (Vdata) of the pixel data. The initialization pulse (INIT) and the sensing pulse (SENSE) are generated as a gate-off voltage (VGL) in the data writing step (Pwr).

[0143] In the anode reset phase (Par), as shown in FIG. 28, the sensing pulse (SENSE) is generated as the gate-on voltage (VGH). The initialization pulse (INIT) and scan pulse (SCAN) are generated as the gate-off voltage (VGL) in the anode reset phase (Par).

[0144] In the boosting phase (Pb) and the emission phase (Pem), all gate signals (SCAN, INIT, SENSE) maintain the gate off voltage (VGL).

[0145] The light-emitting element (EL) can be implemented as an OLED. The anode electrode of the light-emitting element (EL) is connected to a third node (DTS). A pixel reference voltage (EVSS) is applied to the cathode electrode of the light-emitting element (EL). The light-emitting element (EL) includes a capacitor (Cel) connected between the anode electrode and the cathode electrode.

[0146] A driving element (DT) generates current according to the gate-source voltage (Vgs) to drive a light-emitting element (EL). The driving element (DT) includes a first electrode connected to a first node (DTD), a gate electrode connected to a second node (DTG), and a second electrode connected to a third node (DTS). The first node (DTD) may be connected to a VDD line to which a pixel driving voltage (EVDD) is applied.

[0147] The first capacitor (Cst) is connected between the second node (DTG) and the third node (DTS) to store the gate-source voltage of the driving element (DT). The second capacitor (C2) is connected between the VDD line, to which the pixel driving voltage (EVDD) is applied, and the third node (DTS). The second capacitor (C2) suppresses the ripple voltage generated when current is rapidly applied to the third node (DTS) when the second switch element (T3) is turned on, thereby preventing fluctuations in the brightness of the light-emitting element (EL). The second capacitor (C2) has a smaller capacitance than the first capacitor (Cst).

[0148] The switch elements (T1~T3) of the pixel circuit include a first switch element (T1) that supplies a data voltage (Vdata) of pixel data to a second node (DTG) in response to a scan pulse (SCAN), a second switch element (T2) that supplies an initialization voltage (Vinit) to the second node (DTG) in response to an initialization pulse (INIT), and a third switch element (T3) that supplies a reference voltage (Vref) to a third node (DTS) in response to a sensing pulse (SENSE).

[0149] In the initialization step (Pi), as illustrated in FIG. 29, the second and third switch elements (T2, T3) and the driving element (DT) are turned on, and the first switch element (T1) is turned off. At this time, the light-emitting element (EL) is not turned on. In the initialization step (Pi), the main nodes of the pixel circuit are initialized. In the initialization step (Pi), the voltage (Vg) of the second node (DRG) is Vg = Vinit, and the voltage (Vs) of the third node (DTS) is Vref. Therefore, in the initialization step (Pi), the gate-source voltage (Vgs) of the driving element (DT) is Vgs = Vinit - Vref.

[0150] In the sensing step (Ps), as illustrated in FIG. 30, the second switch element (T2) is turned on, while the first and third switch elements (T1, T3) are turned off. In the sensing step (Ps), the gate-source voltage (Vgs) of the driving element (DT) reaches a threshold voltage (Vth). In the sensing step (Ps), the voltage (Vs) of the third node (DTS) changes to Vs = Vinit - Vth. Thus, at the end of the sensing step (Ps), the gate-source voltage (Vgs) of the driving element (DT) becomes Vgs = Vth, and this threshold voltage (Vth) is sampled and stored in the capacitor (Cst).

[0151] In the data writing step (Pwr), as illustrated in FIG. 31, the first switch element (T1) is turned on, and other switch elements (T2, T3), excluding the first switch element (T1), are turned off. At this time, the data voltage (Vdata) of the pixel data is applied to the second node (DTG). In the data writing step (Pwr), the voltage of the second node (DTG) changes to the data voltage (Vdata). At the end of the data writing step (Pwr), the voltage (Vg) of the second node (DTG) is Vg=Vdata, and the voltage (Vs) of the third node (DTS) is Vs=Vinit-Vth. Therefore, the gate-source voltage (Vgs) of the driving element (DT) changes to Vgs=Vdata-Vinit+Vth in the data writing step (Pwr).

[0152] In the anode reset step (Par), as shown in FIG. 32, the third switch element (T3) is turned on, and the other switch elements (T1, T2) are turned off. In the anode reset step (Par), the voltage (Vs) of the third node (DTS) changes to Vs=Vref, and the voltage (Vg) of the second node (DTG) changes to Vg=Vdata-Vinit+Vth+Vref. The gate-source voltage (Vgs) of the driving element (DT) is maintained at Vgs=Vdata-Vinit+Vth.

[0153] In the boosting step (Pb), all switch elements (T1, T2, T3) are turned off as shown in FIG. 33. At this time, the capacitor (Cel) of the light-emitting element (EL) is charged. In the boosting step (Pb), the second and third nodes (DTG, DTS) are floated, and the voltages (Vg, Vs) of the second and third nodes (DTG, DTS) are raised by the capacitor voltage (Voled) of the light-emitting element (EL), changing to Vg = Vdata - Vinit + Vth + Vref + Voled and Vs = Vref + Voled. In the boosting step (Pb), the gate-source voltage (Vgs) of the driving element (DT) is maintained at Vgs = Vdata - Vinit + Vth. After the boosting step (Pb), in the light emission step (Pem), the current generated by the light-emitting element (EL) according to the gate-source voltage (Vgs) of the driving element (DT), i.e., Iel = K(Vdata-Vth) 2 The light-emitting element (EL) can emit light by means of.

[0154] When the frame frequency of the input image varies, the pixel circuit illustrated in FIG. 27 can be driven as illustrated in FIG. 8. Even if the period during which pixel data is written to the pixels changes, the present invention can prevent voltage fluctuations of the third node (DTS) by regularly repeating the anode reset step (Par), as can be seen in the anode reset section (A) illustrated in FIG. 8. The present invention can perform an anode reset without the need to additionally connect a separate anode reset voltage wiring to the pixel circuit.

[0155] FIGS. 34a and FIGS. 34b are circuit diagrams showing pixel circuits according to a sixth embodiment of the present invention. FIG. 35 is a waveform diagram showing gate signals and data voltages applied to the pixel circuits illustrated in FIGS. 34a and FIGS. 34b. FIGS. 36a and FIGS. 36b are circuit diagrams showing the operation of the pixel circuits illustrated in FIGS. 34a and FIGS. 34b during the anode reset step. Detailed descriptions of components in FIGS. 34a through FIGS. 36b that are substantially the same as those in the previously described embodiments are omitted.

[0156] Referring to FIGS. 34a through 36b, the pixel circuit includes a light-emitting element (EL), a driving element (DT) for driving the light-emitting element (EL), a plurality of switching elements (T1 to T44), and a plurality of capacitors (Cst, Cel, C2). The driving element (DT) and the switching elements (T1 to T56) can be implemented as n-channel oxide TFTs.

[0157] The voltages (VGH, VEH, VGL, VEL) of the constant voltage, data voltage, and gate signals (SCAN, INIT, SENSE, EM) applied to the pixel circuit can be set in the same way as in the aforementioned embodiments.

[0158] Gate signals (SCAN, INIT, SENSE, EM) are generated as pulses swinging between gate-on voltages (VGH, VEH) and gate-off voltages (VGL, VEL). The gate driver of the display device may include a first shift register that generates a scan pulse (SCAN), a second shift register that generates an initialization pulse (INIT), a third shift register that generates a sensing pulse (SENSE), and a fourth shift register that generates an EM pulse.

[0159] The driving period of the pixel circuit can be divided into an initialization step (Pi), a sensing step (Ps), a data writing step (Pwr), an anode reset step (Par), a boosting step (Pb), and a light emission step (Pem), as shown in FIG. 35.

[0160] In the initialization step (Pi), as shown in FIG. 35, the initialization pulse (INIT), sensing pulse (SENSE), and EM pulse (EM) are generated as gate-on voltages (VGH, VEH). In the initialization step (Pi), the scan pulse (SCAN) is the gate-off voltage (VGL).

[0161] In the sensing step (Ps), as shown in FIG. 35, the initialization pulse (INIT) and the EM pulse (EM) are generated as the gate-on voltage (VGH, VEH). The sensing pulse (SENSE) and the scan pulse (SCAN) are the gate-off voltage (VGL) in the sensing step (Ps).

[0162] In the data write step (Pwr), as shown in FIG. 35, a scan pulse (SCAN) is generated at a gate-on voltage (VGH) synchronized with the data voltage (Vdata) of the pixel data. In the data write step (Pwr), an EM pulse (EM) maintains the gate-on voltage (VEH). An initialization pulse (INIT) and a sensing pulse (SENSE) are generated at the gate-off voltage (VGL) in the data write step (Pwr).

[0163] In the anode reset phase (Par), as shown in FIG. 35, the sensing pulse (SENSE) is generated as the gate-on voltage (VGH). In the anode reset phase (Par), the EM pulse (EM) is inverted to the gate-off voltage (VEL). The initialization pulse (INIT) and scan pulse (SCAN) are generated as the gate-off voltage (VGL) in the anode reset phase (Par).

[0164] In the boosting phase (Pb) and the emission phase (Pem), the EM pulse (EM) is generated as the gate-on voltage (VEH), and other gate signals (SCAN, INIT, SENSE) are the gate-off voltage (VGL).

[0165] The fourth switch element (T43, T44) may include one or more of the following: a fourth-1 switch element (T43) connected between the VDD line to which the pixel driving voltage (EVDD) is applied and the first node (DTD) as shown in FIG. 34a, and a fourth-2 switch element (T44) connected between the driving element (DT) and the light-emitting element (EL).

[0166] In the initialization step (Pi), the second, third, and fourth switch elements (T2, T3, T43, T44) and the driving element (DT) are turned on, and the first switch element (T1) is turned off. At this time, the light-emitting element (EL) is not turned on. In the initialization step (Pi), the main nodes of the pixel circuit are initialized.

[0167] In the sensing step (Ps), the second and fourth switch elements (T2, T43, T44) are turned on, while the first and third switch elements (T1, T3) are turned off. In the sensing step (Ps), the gate-source voltage (Vgs) of the driving element (DT) reaches a threshold voltage (Vth). In the sensing step (Ps), the threshold voltage (Vth) of the driving element (DT) is sampled and stored in the capacitor (Cst).

[0168] In the data writing step (Pwr), the first and fourth switch elements (T1, T43, T44) are turned on, and the other switch elements (T2, T3) are turned off. At this time, the data voltage (Vdata) of the pixel data is applied to the second node (DTG).

[0169] In the anode reset step (Par), as shown in FIGS. 36a and 36b, the third switch element (T3) is turned on, and the other switch elements (T1, T2, T43, T44) are turned off.

[0170] In the boosting step (Pb), other switch elements (T1, T2, T3), excluding the fourth switch element (T43, T44), are turned off. At this time, the capacitor of the light-emitting element (EL) is charged. In the boosting step (Pb), the second and third nodes (DTG, DTS) are floated, and the voltages (Vg, Vs) of the second and third nodes (DTG, DTS) are raised by the capacitor voltage (Voled) of the light-emitting element (EL). After the boosting step (Pb), in the light-emitting step (Pem), the light-emitting element (EL) can emit light due to the current generated according to the gate-source voltage (Vgs) of the driving element (DT).

[0171] When the frame frequency of the input image is varied, the pixel circuit shown in FIG. 34a and FIG. 34b can be driven as in FIG. 12.

[0172] The frame frequency of the input image can be varied over a wide frequency range, such as 30Hz, 60Hz, 120Hz, and 240Hz, as shown in FIG. 12. Even if the period during which pixel data is written to the pixels changes, voltage fluctuations of the third node (DTS) can be prevented by regularly repeating the anode reset step (Par), as can be seen in the anode reset section (A) shown in FIG. 12. The present invention can perform an anode reset without the need to additionally connect a separate anode reset voltage wiring to the pixel circuit.

[0173] During the anode reset period (A), as illustrated in FIG. 37, a sensing pulse (SENSE) is generated as the gate-on voltage (VGH) and an EM pulse (EM) is inverted as the gate-off voltage (VEL). During the anode reset period (A), other gate signals (SCAN, INIT) and the data voltage (Vdata) of the pixel data are not generated. Therefore, the present invention can prevent changes in the luminance of pixels that occur when the frame frequency changes, because the anode reset pulse (AR) is applied to the pixels at the same frequency regardless of how the frame frequency changes.

[0174] During the EM OFF period (C), as shown in FIG. 38, the sensing pulse (SENSE) is generated as the gate-on voltage (VGH) and the EM pulse (EM) is inverted to the gate-off voltage (VEL). During the EM OFF period (C), pulses of other gate signals (SCAN, INIT) and the data voltage (Vdata) of the pixel data are not generated.

[0175] FIG. 39 is a block diagram showing a display device according to an embodiment of the present invention. FIG. 40 is a cross-sectional view showing the cross-sectional structure of a display panel shown in FIG. 39.

[0176] Referring to FIGS. 39 and 40, a display device according to an embodiment of the present invention includes a display panel (100), a display panel driving unit for writing pixel data to pixels of the display panel (100), and a power supply unit (140) that generates power necessary for driving the pixels and the display panel driving unit.

[0177] The display panel (100) may be a rectangular panel having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel (100) includes a pixel array that displays an input image on a screen. The pixel array includes a plurality of data lines (102), a plurality of gate lines (103) that intersect the data lines (102), and pixels arranged in a matrix form. The display panel (100) may further include power lines commonly connected to the pixels. The power lines supply a constant voltage required for driving the pixels (101) to the pixels (101). For example, the display panel (100) may include a VDD line to which a pixel driving voltage (EVDD) is applied, and a VSS line to which a low-potential pixel reference voltage (EVSS) is applied. Additionally, the power lines may further include a REF line to which a reference voltage (Vref) is applied, and an INIT line to which an initialization voltage (Vinit) is applied.

[0178] The cross-sectional structure of the display panel (100) may include a circuit layer (12), a light-emitting element layer (14), and an encapsulation layer (16) stacked on a substrate (10) as shown in FIG. 40.

[0179] The circuit layer (12) may include a TFT array including a pixel circuit connected to wiring such as data lines, gate lines, and power lines, a demultiplexer array (112), a gate driver (120), etc. The wiring and circuit elements of the circuit layer (12) may include a plurality of insulating layers, two or more metal layers separated by insulating layers, and an active layer including a semiconductor material. All transistors formed in the circuit layer (12) may be implemented as n-channel oxide TFTs.

[0180] The light-emitting element layer (14) may include a light-emitting element (EL) driven by a pixel circuit. The light-emitting element (EL) may include a red (R) light-emitting element, a green (G) light-emitting element, and a blue (B) light-emitting element. In another embodiment, the light-emitting element layer (14) may include a white light-emitting element and a color filter. The light-emitting elements (EL) of the light-emitting element layer (14) may be covered by a protective layer including an organic film and a protective film.

[0181] The encapsulation layer (16) covers the light-emitting element layer (14) to seal the circuit layer (12) and the light-emitting element layer (14). The encapsulation layer (16) may be a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic film flattens the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the path of movement of moisture or oxygen is longer compared to a single layer, so the penetration of moisture and oxygen affecting the light-emitting element layer (14) can be effectively blocked.

[0182] A touch sensor layer, which is omitted from the drawing, may be formed on the encapsulation layer (16), and a polarizer or a color filter layer may be disposed thereon. The touch sensor layer may include capacitive touch sensors that sense touch input based on a change in capacitance before and after touch input. The touch sensor layer may include metal wiring patterns that form the capacitance of the touch sensors and insulating films. The insulating films may insulate the intersecting portions of the metal wiring patterns and flatten the surface of the touch sensor layer. The polarizer may improve visibility and contrast ratio by converting the polarization of external light reflected by the metal of the touch sensor layer and the circuit layer. The polarizer may be implemented as a polarizer or a circular polarizer in which a linear polarizer and a phase delay film are bonded. A cover glass may be adhered to the polarizer. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer absorbs a portion of the wavelengths of light reflected from the circuit layer and the touch sensor layer, acting as a polarizer and enhancing the color purity of the image reproduced in the pixel array.

[0183] A pixel array includes multiple pixel lines (L1 to Ln). Each of the pixel lines (L1 to Ln) includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel (100). Pixels arranged in one pixel line share gate lines (103). Subpixels arranged in the column direction (Y) along the data line direction share the same data line (102). One horizontal period is the time obtained by dividing one frame period (1FR) by the total number of pixel lines (L1 to Ln).

[0184] The display panel (100) can be implemented as a non-transparent display panel or a transparent display panel. A transparent display panel can be applied to a transparent display device in which an image is displayed on the screen and the actual background is visible. The display panel (100) can be manufactured as a flexible display panel.

[0185] Each of the pixels (101) may be divided into a red subpixel, a green subpixel, and a blue subpixel for color implementation. Each of the pixels may further include a white subpixel. Each of the subpixels may be implemented by any one of the aforementioned pixel circuits. Hereinafter, pixel may be interpreted as having the same meaning as subpixel. Each pixel circuit is connected to data lines, gate lines, and power lines.

[0186] Pixels can be arranged as real color pixels and pentile pixels. Pentile pixels can achieve a higher resolution than real color pixels by using a pre-set pixel rendering algorithm to drive two sub-pixels of different colors into one pixel (101). The pixel rendering algorithm can compensate for the lack of color representation in each pixel with the color of light emitted from an adjacent pixel.

[0187] The power supply unit (140) generates a DC voltage (or constant voltage) required to drive the pixel array of the display panel (100) and the display panel driver using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply unit (140) can generate constant voltages such as a gamma reference voltage (VGMA), a gate-on voltage (VGH, VEH), a gate-off voltage (VGL, VEL), a pixel driving voltage (EVDD), a low-potential pixel reference voltage (EVSS), and an initialization voltage (Vinit) reference voltage (Vref) by adjusting the level of a DC input voltage applied from a host system not shown. The gamma reference voltage (VGMA) is supplied to the data driver (110). The gate-on voltage (VGH, VEH) and gate-off voltage (VGL, VEL) are supplied to the gate driver (120). Constant voltages such as the pixel driver voltage (EVDD), low-potential pixel reference voltage (EVSS), initialization voltage (Vinit), and reference voltage (Vref) are supplied to the pixels (101) through power lines that are commonly connected to the pixels (101).

[0188] The display panel driving unit writes pixel data of the input image to the pixels of the display panel (100) under the control of the timing controller (130).

[0189] The display panel driver includes a data driver (110) and a gate driver (120). The display panel driver may further include a demultiplexer array (112) disposed between the data driver (110) and the data lines (102).

[0190] The demultiplexer array (112) sequentially supplies data voltages output from the channels of the data driver (110) to the data lines (102) using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switch elements placed on the display panel (100). If the demultiplexer is placed between the output terminals of the data driver (110) and the data lines (102), the number of channels of the data driver (110) may be reduced. The demultiplexer array (112) may be omitted.

[0191] The display panel driver may further include a touch sensor driver for driving touch sensors. The touch sensor driver is omitted in FIG. 39. The data driver (110) and the touch sensor driver may be integrated into a single drive IC (Integrated Circuit). In a mobile device or wearable device, the timing controller (130), power supply (140), data driver (110), etc. may be integrated into a single drive IC.

[0192] The display panel driving unit can operate in a low speed driving mode under the control of the timing controller (130). The low speed driving mode can be set to reduce the power consumption of the display device when the input image does not change for a preset number of frames by analyzing the input image. The low speed driving mode can reduce the power consumption of the display panel driving unit and the display panel (100) by lowering the refresh rate of the pixels when a still image is input for a certain period of time or longer. The low speed driving mode is not limited to when a still image is input. For example, when the display device operates in standby mode, or when a user command or input image is not input to the display panel driving circuit for a predetermined period of time or longer, the display panel driving circuit may operate in a low speed driving mode.

[0193] The data driver (110) receives pixel data of an input image received as a digital signal from the timing controller (130) and outputs a data voltage. The data driver (110) uses a Digital to Analog Converter (DAC) to convert the pixel data of the input image into a gamma compensation voltage for each frame period to generate a data voltage (Vdata). The gamma reference voltage (VGMA) is divided into gamma compensation voltages for each grayscale level through a voltage divider circuit. The gamma compensation voltages for each grayscale level are provided to the DAC of the data driver (110). The data voltage (Vdata) is output through an output buffer in each of the channels of the data driver (110).

[0194] The gate driver (120) can be implemented as a GIP (Gate in panel) circuit formed on a circuit layer (12) on a display panel (100) together with the TFT array and wiring of the pixel array. The gate driver (120) can be placed on a bezel area (BZ), which is a non-display area of ​​the display panel (100), or distributed within a pixel array where an input image is reproduced. The gate driver (120) sequentially outputs gate signals to gate lines (103) under the control of a timing controller (130). The gate driver (120) can sequentially supply the signals to the gate lines (103) by shifting the gate signals using a shift register. The gate signals may include various gate pulses such as a scan pulse (SCAN), a sensing pulse (SENSE), an initialization pulse (INIT), an anode reset pulse (AR), and an EM pulse (EM).

[0195] The timing controller (130) receives digital video data (DATA) of an input image from a host system and a timing signal synchronized therewith. The timing signal may include a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock (CLK), and a data enable signal (DE). Since the vertical period and the horizontal period can be determined by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) may be omitted. The data enable signal (DE) has a period of 1 horizontal period (1H).

[0196] The host system may be any one of a TV (Television) system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, or a vehicle system. The host system can scale a video signal from a video source to the resolution of the display panel (100) and transmit it to a timing controller (130) along with a timing signal.

[0197] The timing controller (130) can control the operation timing of the display panel driving unit by multiplying the input frame frequency by i in normal driving mode to a frame frequency of input frame frequency × i (i is a natural number) Hz. The input frame frequency is 60Hz in the NTSC (National Television Standards Committee) system and 50Hz in the PAL (Phase-Alternating Line) system.

[0198] The host system or timing controller (130) can vary the frame frequency according to the movement or content characteristics of the input video.

[0199] The timing controller (130) lowers the frequency of the frame rate at which pixel data is written to pixels in the low-speed driving mode compared to the normal driving mode. For example, the data refresh frame frequency at which pixel data is written to pixels in the normal driving mode may occur at a refresh rate of 60Hz or higher, for example, 60Hz, 120Hz, 144Hz, or 240Hz, and the data refresh frame (DRF) in the low-speed driving mode may occur at a refresh rate with a frequency lower than that of the low-speed driving mode. The timing controller (130) may lower the frame frequency to lower the refresh rate of the pixels in the low-speed driving mode, thereby lowering the driving frequency of the display panel driving unit.

[0200] The timing controller (130) generates a data timing control signal for controlling the operation timing of the data driver (110), a control signal for controlling the operation timing of the demultiplexer array (112), and a gate timing control signal for controlling the operation timing of the gate driver (120) based on timing signals (Vsync, Hsync, DE) received from the host system. The timing controller (130) controls the operation timing of the display panel driver to synchronize the data driver (110), the demultiplexer array (112), the touch sensor driver, and the gate driver (120).

[0201] A gate timing control signal generated from a timing controller (130) can be input to a shift register of a gate driver (120) through a level shifter (not shown). The level shifter receives the gate timing control signal, generates a start pulse and a shift clock, and provides them to the shift registers of the gate driver (120).

[0202] Since the contents of the specification described above regarding the problem to be solved, the means for solving the problem, and the effect do not specify the essential features of the claim, the scope of the claim is not limited by the matters described in the specification.

[0203] Although embodiments of the present invention have been described in more detail with reference to the attached drawings, the present invention is not necessarily limited to these embodiments and may be modified in various ways within the scope of the technical spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical spirit of the present invention, and the scope of the technical spirit of the present invention is not limited by these embodiments. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of protection of the present invention shall be interpreted by the claims, and all technical spirits within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0204] 100: Display panel 110: Data driver 120: Gate driver 130: Timing controller 140: Power supply EL: Light-emitting element of pixel circuit DT: Driving element Cst1, Cst2, C2: Capacitors T1~T54: Switch elements of the pixel circuit Pi: Initialization step Ps: Sensing stage Pwr: Data entry stage Par: Anode reset phase Pb: Boosting phase Pem: Luminescence stage

Claims

Claim 1 A driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node; a light-emitting element including an anode electrode connected to the third node and a cathode electrode connected to a VSS line to which a pixel reference voltage lower than the pixel driving voltage is applied, and driven by current from the driving element; a first switching element that supplies a data voltage of pixel data to the second node in response to a scan pulse; a second switching element that supplies an initialization voltage to the second node in response to an initialization pulse; a third switching element that supplies a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a fourth switching element that connects the third node to the VSS line in response to an anode reset pulse; and a capacitor connected between the second node and the third node, wherein the frequency of the anode reset pulse applied to the fourth switching element when the frame frequency of an input image input to the pixel changes is fixed at the same frequency even if the frame frequency changes. Claim 2 In claim 1, the driving period of the pixel circuit is divided into an initialization step, a sensing step, a data writing step, an anode reset step, a boosting step, and a light emission step; in the initialization step, the initialization pulse and the sensing pulse are generated as a gate-on voltage, and the scan pulse and the anode reset pulse are gate-off voltages; in the sensing step, the initialization pulse is generated as the gate-on voltage, and the sensing pulse, the scan pulse, and the anode reset pulse are gate-off voltages; in the data writing step, the scan pulse is generated as the gate-on voltage synchronized with the data voltage, and the initialization pulse, the sensing pulse, and the anode reset pulse are gate-off voltages; in the anode reset step, the anode reset pulse is generated as the gate-on voltage, and the initialization pulse, the sensing pulse, and the scan pulse are gate-off voltages; in the boosting step and the light emission step, the initialization pulse, the sensing pulse, the scan pulse, and the anode reset pulse are gate-off voltages; and the first to fourth switches A pixel circuit in which each of the elements is turned on in response to the gate-on voltage and turned off according to the gate-off voltage. Claim 3 A driving element comprising a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node; a light-emitting element including an anode electrode connected to the third node and a cathode electrode connected to a VSS line to which a pixel reference voltage lower than the pixel driving voltage is applied, and driven by current from the driving element; a first switch element that supplies a data voltage of pixel data to the second node in response to a scan pulse; a second switch element that supplies an initialization voltage to the second node in response to an initialization pulse; a third switch element that supplies a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a fourth switch element that connects the third node to a fourth node in response to an anode reset pulse; and a capacitor connected between the second node and the fourth node, wherein the frequency of the anode reset pulse applied to the fourth switch element when the frame frequency of an input image input to the pixel changes is fixed at the same frequency even if the frame frequency changes. Claim 4 In claim 3, the driving period of the pixel circuit is divided into an initialization step, a sensing step, a data writing step, an anode reset step, a boosting step, and a light emission step; in the initialization step, the initialization pulse, the sensing pulse, and the anode reset pulse are generated as a gate-on voltage, and the scan pulse is a gate-off voltage; in the sensing step, the initialization pulse and the anode reset pulse are generated as a gate-on voltage, and the sensing pulse and the scan pulse are a gate-off voltage; in the data writing step, the scan pulse and the anode reset pulse are generated as a gate-on voltage, and the initialization pulse and the sensing pulse are a gate-off voltage; in the anode reset step, the sensing pulse is generated as a gate-on voltage, and the initialization pulse, the scan pulse, and the anode reset pulse are a gate-off voltage; in the boosting step and the light emission step, the anode reset pulse is generated as a gate-on voltage, and the initialization pulse, the sensing pulse, and the scan pulse are a gate-off voltage; and the first to fourth switches A pixel circuit in which each of the elements is turned on in response to the gate-on voltage and turned off according to the gate-off voltage. Claim 5 delete Claim 6 A pixel circuit according to claim 1 or 3, wherein the frequency of each of the initialization pulse, the sensing pulse, and the scan pulse changes in proportion to the frame frequency when the frame frequency of the input image changes. Claim 7 A pixel circuit according to claim 2 or 4, further comprising: a 5-1 switch element connected between the VDD line to which the pixel driving voltage is applied and the first node; and one or more of a 5-2 switch element connected between the driving element and the light-emitting element, wherein the 5-1 switch element and the 5-2 switch element are turned on according to the gate-on voltage of the light-emitting control pulse and turned off according to the gate-off voltage of the light-emitting control pulse, and the light-emitting control pulse is generated as the gate-on voltage in the initialization step, the sensing step, the data writing step, the boosting step, and the light-emitting step, and is generated as the gate-off voltage in the anode reset step. Claim 8 delete Claim 9 delete Claim 10 A display device for displaying pixel data of an input image comprises: a display panel having a plurality of pixel circuits; a data driving unit for generating a data voltage of the pixel data; and a gate driving unit for generating an initialization pulse, a sensing pulse, a scan pulse, and an anode reset pulse to gate lines, wherein each of the pixel circuits comprises: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a third electrode connected to a third node; an anode electrode connected to the third node and a cathode electrode connected to a VSS line to which a pixel reference voltage lower than the pixel driving voltage is applied, and a light-emitting element driven by a current from the driving element. A display device comprising: a first switch element that supplies a data voltage of pixel data to the second node in response to a scan pulse; a second switch element that supplies an initialization voltage to the second node in response to an initialization pulse; a third switch element that supplies a reference voltage lower than the initialization voltage to the third node in response to a sensing pulse; a fourth switch element that connects the third node to the VSS line in response to an anode reset pulse; and a capacitor connected between the second node and the third node, wherein the frequency of the anode reset pulse applied to the fourth switch element when the frame frequency of an input image input to the pixel changes is fixed at the same frequency even if the frame frequency changes. Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete Claim 25 delete Claim 26 delete Claim 27 delete Claim 28 delete Claim 29 delete Claim 30 delete

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