Display device

Abstract

The display device may include a display panel comprising a hole area, a display area around the hole area, and a non-display area around the display area; an insulating layer disposed in the hole area; a plurality of sensing electrodes disposed on the display area; a crack detection pattern disposed on the insulating layer in the hole area; a crack detection line disposed on the non-display area; and a connection pattern disposed on the display area, insulated from the sensing electrodes, and connected to the crack detection pattern and the crack detection line. The edge of the insulating layer disposed at the boundary between the display area and the hole area may have a stepped structure of at least two steps.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] Generally, electronic devices that provide video to users, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions, include a display device for displaying the video. The display device generates video and provides the generated video to the user through a display screen.

[0003] The display device includes a display panel that generates an image, an input detection unit disposed on the display panel for detecting external input, and functional elements that provide various functions to the user. The input detection unit includes a plurality of detection electrodes for detecting external input. The functional elements include a speaker, a camera, and a sensor, etc. A plurality of holes are defined in the display panel and the input detection unit, and the functional elements are disposed in the holes. The problem to be solved

[0004] The objective of the present invention is to provide a display device with improved reliability. means of solving the problem

[0005] A display device according to one embodiment of the present invention may include a display panel comprising a hole area, a display area around the hole area, and a non-display area around the display area; an insulating layer disposed in the hole area; a plurality of sensing electrodes disposed on the display area; a crack detection pattern disposed on the insulating layer in the hole area; a crack detection line disposed on the non-display area; and a connection pattern disposed on the display area, insulated from the sensing electrodes, and connected to the crack detection pattern and the crack detection line. The edge of the insulating layer disposed at the boundary between the display area and the hole area may have a stepped structure of at least two steps.

[0006] A display device according to one embodiment of the present invention may include a display panel comprising a first region, a second region surrounding the first region, and a third region surrounding the second region; an insulating layer disposed in the first region; a plurality of sensing electrodes disposed on the second region; and a crack detection unit disposed on the insulating layer in the first region and insulated from the sensing electrodes, extending to the second region and the third region. The edge of the insulating layer disposed at the boundary between the first region and the second region may have a stepped structure of at least two stages.

[0007] A display device according to one embodiment of the present invention may include a display panel comprising a first region, a second region around the first region, and a third region around the second region; an insulating layer disposed in the first region; a plurality of sensing electrodes disposed on the second region; a crack detection pattern disposed on the insulating layer in the first region; a crack detection line disposed on the third region; a connecting pattern disposed on the second region, insulated from the sensing electrodes, and connecting the crack detection pattern and the crack detection line; and a capping layer disposed on the insulating layer to cover the boundary of the insulating layer. Effects of the invention

[0008] According to an embodiment of the present invention, by placing a crack detection unit in a display device, the presence or absence of a crack in the display device can be easily detected.

[0009] In addition, the edge of the insulating layer on which the crack detection part is placed is formed with a stepped structure of at least two steps, thereby preventing damage to the crack detection part.

[0010] In addition, by positioning the capping layer to cover the edge of the insulating layer placed in the hole area, peeling of the edge of the insulating layer can be prevented. Brief explanation of the drawing

[0011] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention. Figure 2 is a block diagram of the display device shown in Figure 1. Figure 3 is a cross-sectional view of the line I-I' shown in Figure 1. FIG. 4 is a drawing exemplarily illustrating a cross-section of the display panel shown in FIG. 3. Figure 5 is a plan view of the display panel shown in Figure 4. Figure 6 is an enlarged view of the periphery of the hole area shown in Figure 5. FIG. 7 is a diagram illustrating, by way of example, the cross-sectional configuration of a pixel shown in FIG. 5. Figure 8 is a plan view of the input detection unit shown in Figure 3. FIG. 9 is an enlarged view of the first and second sensing units positioned around the hole area. FIG. 10 is a cross-sectional view of the line II-II' shown in FIG. 9. FIG. 11 is a cross-sectional view of the line III-III' shown in FIG. 9. FIG. 12 is a diagram illustrating, in an exemplary manner, the cross-sectional configuration from the hole area and crack detection pattern to the first connection pattern. FIG. 12 is a diagram exemplarily illustrating the cross-sectional configuration from the hole area and crack detection pattern shown in FIG. 9 to the first connection pattern. FIG. 13 is a diagram illustrating, in an exemplary manner, the cross-sectional configuration from the hole area and crack detection pattern shown in FIG. 9 to the second connection pattern. FIG. 14 is a diagram illustrating an exemplary cross-sectional configuration from the hole area and bypass line shown in FIG. 9 to the first detection part adjacent to the hole area. FIG. 15 is a drawing showing the mesh structure of the sensing electrodes and the connection pattern adjacent to the top of the hole area illustrated in FIG. 9. FIG. 16 is an enlarged view of the first connection pattern, the first extension line, and the first crack detection line shown in FIG. 9. FIG. 17 is a cross-sectional view along line IV-IV' shown in FIG. 16. Figure 18 is a cross-sectional view of the V-V' line shown in Figure 16. FIG. 19 is an enlarged view of the second connection pattern, the second extension line, and the second crack detection line shown in FIG. 9. FIG. 20 is a cross-sectional view along the line VI-VI' shown in FIG. 19. Figure 21 is an enlarged view of the hole area shown in Figure 9. FIG. 22 is a cross-sectional view along line VII-VII' shown in FIG. 21. FIG. 23 is a cross-sectional view along line VIII-VIII' shown in FIG. 21. FIG. 24 is a cross-sectional view along the line IX-IX' shown in FIG. 21. FIGS. 25 to 30 are drawings for explaining a method of manufacturing the capping layer and the second connecting line shown in FIG. 21. FIGS. 31 to 35 are drawings illustrating methods for manufacturing other display devices. Specific details for implementing the invention

[0012] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0013] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of the components are exaggerated for the effective illustration of the technical content.

[0014] "And / or" includes all one or more combinations that the associated configurations can define.

[0015] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0016] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0017] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Additionally, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and are explicitly defined herein unless interpreted in an ideal or overly formal sense.

[0018] Terms such as "include" or "have" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0020] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention.

[0021] Referring to FIG. 1, a display device (DD) may include a hole area (HA), a display area (DA) disposed around the hole area (HA), and a non-display area (NDA) around the display area (DA). The hole area (HA) may be defined as a first area, the display area (DA) may be defined as a second area, and the non-display area (NDA) may be defined as a third area.

[0022] The display area (DA) surrounds the hole area (HA), and the non-display area (NDA) can surround the display area (DA). The display area (DA) displays an image, and the non-display area (NDA) may not display an image. The non-display area (NDA) can define the border of a display device (DD) that is printed in a predetermined color.

[0023] A camera may be placed in the hole area (HA) as a functional element. The camera will be illustrated in FIG. 3 below. For example, the hole area (HA) may be placed in the upper part of the display device (DD) and in the part of the display area (DA) adjacent to the right side of the display device (DD), but the location of the hole area (HA) is not limited thereto.

[0024] The display device (DD) may have a rectangular shape having long sides extending in a first direction (DR1) and short sides extending in a second direction (DR2) that intersects the first direction (DR1). However, it is not limited thereto, and the display device (DD) may have various shapes such as a circle and a polygon. The vertices of the rectangular shape of the display device (DD) may be formed as curves.

[0025] The direction that intersects substantially perpendicularly with the plane defined by the first and second directions (DR1, DR2) below is defined as the third direction (DR3). In this specification, the meaning of "when viewed in a plane" may mean the state viewed from the third direction (DR3).

[0026] The upper surface of the display device (DD) can be defined as a display surface and may have a plane defined by a first direction (DR1) and a second direction (DR2). An image generated by the display device (DD) can be provided to the user through the display surface. When the user touches the icon images (IM) displayed on the display surface, main images corresponding to the icon images can be provided to the user.

[0027] In FIG. 1, the display device (DD) is exemplarily illustrated as a mobile phone. However, the display device (DD) may be used in large electronic devices such as televisions or external billboards, as well as in small and medium-sized electronic devices such as personal computers, laptop computers, car navigation systems, game consoles, and tablets. Furthermore, these are presented merely as examples and may be adopted in other electronic devices as long as they do not deviate from the concept of the invention.

[0028] Figure 2 is a block diagram of the display device shown in Figure 1.

[0029] Referring to FIG. 2, a display device (DD) according to an embodiment of the present invention may include a display module (DM), a power supply module (PM), a first electronic module (EM1), and a second electronic module (EM2). The display module (DM), the power supply module (PM), the first electronic module (EM1), and the second electronic module (EM2) may be electrically connected to each other.

[0030] The power supply module (PM) can supply power necessary for the overall operation of the display device (DD). The power supply module (PM) may include a conventional battery module.

[0031] The first electronic module (EM1) and the second electronic module (EM2) may include various functional modules for operating the display device (DD). The first electronic module (EM1) may be directly mounted on a main board electrically connected to the display module (DM), or mounted on a separate board and electrically connected to the main board through a connector (not shown), etc.

[0032] The first electronic module (EM1) may include a control module (CM), a wireless communication module (TM), an image input module (IIM), an audio input module (AIM), a memory (MM), and an external interface (IF). Some of the modules may not be mounted on the main board but may be electrically connected to the main board through a flexible circuit board.

[0033] The control module (CM) can control the overall operation of the display device (DD). The control module (CM) can enable or disable the display module (DM). The control module (CM) can control other modules, such as the image input module (IIM) or the audio input module (AIM), based on the touch signal received from the display module (DM).

[0034] The wireless communication module (TM) can transmit and receive wireless signals with another terminal using a Bluetooth or Wi-Fi line. The wireless communication module (TM) can transmit and receive voice signals using a general communication line. The wireless communication module (TM) may include a transmitting unit (TM1) that modulates and transmits a signal to be transmitted, and a receiving unit (TM2) that demodulates a received signal.

[0035] The video input module (IIM) can process video signals and convert them into video data that can be displayed on the display module (DM). The audio input module (AIM) can receive external audio signals via a microphone in recording mode or voice recognition mode and convert them into electrical audio data.

[0036] The external interface (IF) can serve as an interface connected to an external charger, wired / wireless data port, card socket (e.g., memory card, SIM / UIM card), etc.

[0037] The second electronic module (EM2) may include an acoustic output module (AOM), a light-emitting module (LM), a light-receiving module (LRM), and a camera module (CMM), etc. The above components may be mounted directly on the main board or mounted on a separate board and electrically connected to a display module (DM) or to a first electronic module (EM1) through a connector (not shown), etc.

[0038] The acoustic output module (AOM) can convert acoustic data received from the wireless communication module (TM) or acoustic data stored in the memory (MM) and output it externally. The light-emitting module (LM) can generate and output light. The light-emitting module (LM) can output infrared light. The light-emitting module (LM) may include an LED element. The light-receiving module (LRM) can detect infrared light. The light-receiving module (LRM) may be activated when infrared light above a predetermined level is detected. The light-receiving module (LRM) may include a CMOS sensor.

[0039] After infrared light generated by the light-emitting module (LM) is output, it is reflected by an external object (e.g., a user's finger or face), and the reflected infrared light can be incident on the light-receiving module (LRM). The camera module (CMM) is placed in the Hall area (HA) to capture an external image.

[0040] The display module (DM) may include a display panel (DP) and an input detection unit (ISP). The display panel (DP) can display an image using image data provided from the control module (CM).

[0041] The input detection unit (ISP) detects external input (such as a user's hand or a touch pen), and the detected signal can be converted into an input signal and transmitted to the control module (CM). The input detection unit (ISP) can detect external input using a capacitive method. The control module (CM) can control the operation of the display panel (DP) in response to the input signal from the input detection unit (ISP).

[0042] Figure 3 is a cross-sectional view of the line I-I' shown in Figure 1.

[0043] Referring to FIG. 3, the display module (DM) of the display device (DD) may include a display panel (DP), an input detection unit (ISP), an anti-reflection layer (RPL), a window (WIN), a panel protection film (PPF), a cushion layer (CSL), and first to fourth adhesive layers (AL1 to AL4). The input detection unit (ISP), the anti-reflection layer (RPL), and the window (WIN) may be disposed on the display panel (DP). The panel protection film (PPF) and the cushion layer (CSL) may be disposed below the display panel (DP).

[0044] The display module (DM) may include a hole area (HA), a display area (DA), and a non-display area (NDA), identical to the area shown in FIG. 1. A hole (HO) may be defined in the hole area (HA). The hole area (HA) may be defined around the hole (HO). The hole (HO) may be defined in the anti-reflective layer (RPL), the input sensing unit (ISP), the display panel (DP), the panel protection film (PPF), the cushion layer (CSL), and the first to fourth adhesive layers (AL1 to AL4). A camera (CAM) may be placed in the hole (HO).

[0045] The display panel (DP) may be a flexible display panel. Additionally, the display panel (DP) according to one embodiment of the present invention may be a light-emitting display panel, but is not particularly limited. For example, the display panel (DP) may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0046] The input detection unit (ISP) may be placed on the display panel (DP). The input detection unit (ISP) may include a plurality of sensor units (not shown) for detecting external input. The sensor units may detect external input in a capacitive manner. The input detection unit (ISP) may be manufactured directly on the display panel (DP) during the manufacturing of the display panel (DP). However, it is not limited thereto, and the input detection unit (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) by an adhesive layer.

[0047] An anti-reflection layer (RPL) may be placed on an input sensing unit (ISP). The anti-reflection layer (RPL) may be defined as an external light anti-reflection film. The anti-reflection layer (RPL) may reduce the reflectivity of external light incident from above the display device (DD) toward the display panel (DP). For example, the anti-reflection layer (RPL) may include a phase retarder and / or a polarizer.

[0048] The window (WIN) can be placed on the anti-reflective layer (RPL). The window (WIN) can protect the display panel (DP), the input sensing unit (ISP), and the anti-reflective layer (RPL) from external scratches and impacts. The window (WIN) can be optically transparent. External light can be provided to the camera (CAM) through the window (WIN).

[0049] A panel protection film (PPF) may be placed under a display panel (DP). The panel protection film (PPF) may be defined as a protective substrate. The panel protection film (PPF) may protect the underside of the display panel (DP). The panel protection film (PPF) may include a flexible plastic material. For example, the panel protection film (PPF) may include polyethyleneterephthalate (PET).

[0050] A cushion layer (CSL) may be placed under the panel protection film (PPF). The cushion layer (CSL) can protect the display panel (DP) by absorbing external shocks applied to the lower part of the display module (DM). The cushion layer may include a foam sheet having a predetermined elasticity.

[0051] A first adhesive layer (AL1) can be placed between a display panel (DP) and a panel protection film (PPF). The display panel (DP) and the panel protection film (PPF) can be bonded together by the first adhesive layer (AL1). A second adhesive layer (AL2) can be placed between an anti-reflection layer (RPL) and an input detection unit (ISP). The anti-reflection layer (RPL) and the input detection unit (ISP) can be bonded together by the second adhesive layer (AL2).

[0052] A third adhesive layer (AL3) can be placed between the window (WIN) and the anti-reflective layer (RPL). The window (WIN) and the anti-reflective layer (RPL) can be bonded together by the third adhesive layer (AL3). A fourth adhesive layer (AL4) can be placed between the panel protection film (PPF) and the cushion layer (CSL). The panel protection film (PPF) and the cushion layer (CSL) can be bonded together by the fourth adhesive layer (AL4).

[0053] FIG. 4 is a drawing exemplarily illustrating a cross-section of the display panel shown in FIG. 3.

[0054] Referring to FIG. 4, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0055] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) around the display area (DA). The substrate (SUB) may include a flexible plastic material. For example, the substrate (SUB) may include polyimide (PI). Although not illustrated, holes (HO) as shown in FIG. 3 may be defined in the substrate (SUB), the circuit element layer (DP-CL), and the display element layer (DP-OLED).

[0056] A display element layer (DP-OLED) can be placed on a display area (DA). A thin film encapsulation layer (TFE) can be placed on a circuit element layer (DP-CL) to cover the display element layer (DP-OLED).

[0057] Multiple pixels may be disposed in the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor disposed in the circuit element layer (DP-CL) and a light-emitting element disposed in the display element layer (DP-OLED) and connected to the transistor. The configuration of the pixel will be described in detail below.

[0058] Figure 5 is a plan view of the display panel shown in Figure 4.

[0059] Referring to FIG. 5, a display device (DD) according to an embodiment of the present invention may include a display panel (DP), a scan driver (SDV), a data driver (DDV), and an emission driver (EDV). The scan driver (SDV), the data driver (DDV), and the emission driver (EDV) may be disposed on the display panel (DP).

[0060] The display panel (DP) may have long sides extending in a first direction (DR1) and short sides extending in a second direction (DR2). The display panel (DP) may include a hole area (HA) in which a hole (HO) is defined, a display area (DA) surrounding the hole area (HA), and a non-display area (NDA) surrounding the display area (DA).

[0061] A display panel (DP) may include a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of data lines (DL), and a plurality of light-emitting lines (EL). m and n are natural numbers. Pixels (PX) may be placed in a display area (DA) and connected to scan lines (SL), data lines (DL), and light-emitting lines (EL). Pixels (PX) may be placed around a hole area (HA). Pixels (PX) may not be placed in the hole area (HA).

[0062] The scanning driver (SDV), data driver (DDV), and light-emitting driver (EDV) may be placed in the non-display area (NDA). The scanning driver (SDV) and the light-emitting driver (EDV) may be placed adjacent to the long sides of the display panel (DP), respectively. The data driver (DDV) may be manufactured in the form of an integrated circuit chip and placed adjacent to one of the short sides of the display panel (DP).

[0063] Scan lines (SL) can be extended in a second direction (DR2) and connected to a scan driver (SDV). Data lines (DL) can be extended in a first direction (DR1) and connected to a data driver (DDV). Light emission lines (EL) can be extended in a second direction (DR2) and connected to a light emission driver (EDV).

[0064] The scanning driver (SDV) generates multiple scanning signals, and the scanning signals can be applied to pixels (PX) through scanning lines (SL). The scanning signals can be applied to pixels (PX) sequentially. The data driver (DDV) generates multiple data voltages, and the data voltages can be applied to pixels (PX) through data lines (DL). The light emission driver (EDV) generates multiple light emission signals, and the light emission signals can be applied to pixels (PX) through light emission lines (EL).

[0065] Although not illustrated, the display device (DD) may include a timing controller (not illustrated) for controlling the operation of the scanning driver (SDV), the data driver (DDV), and the light-emitting driver (EDV).

[0066] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display an image by emitting light of a brightness corresponding to the data voltages in response to light emission signals. The light emission time of the pixels (PX) can be controlled by the light emission signals.

[0067] Figure 6 is an enlarged view of the periphery of the hole area shown in Figure 5.

[0068] Referring to FIG. 6, a groove (GV) may be defined between the boundary of the hole region (HA) and the hole (HO). The groove (GV) may be placed along the boundary of the hole (HO) to surround the hole (HO). Multiple grooves (GV) may be provided. The cross-sectional structure of the groove (GV) will be described in detail below in FIG. 12, which illustrates a cross-section around the hole (HO).

[0069] The groove (GV) may have a circular ring shape. However, this is illustrated as an example, and the groove (GV) may be formed as a closed line of polygonal and elliptical shapes. Additionally, the groove (GV) may be formed as a shape including multiple partially disconnected patterns.

[0070] Pixels (PX) can be arranged to surround a hole region (HA). Pixels (PX) surrounding the hole region (HA) can be connected to a scan line (SL), a data line (DL), and an emission line (EL) that extend through the hole region (HA). The row described below corresponds to a second direction (DR2), and the column corresponds to a first direction (DR1).

[0071] Pixels (PX) of the h-th row (ROW_h) positioned with respect to the hole region (HA) can be connected to a scanning line (SL) that extends in the second direction (DR2) and along the boundary of the hole region (HA) within the hole region (HA). Pixels (PX) of the h-th row (ROW_h) can be connected to a light emission line (EL) that extends in the second direction (DR2) and along the boundary of the hole region (HA) within the hole region (HA). h is a natural number.

[0072] Pixels (PX) of the k-th column (COL_k) arranged with the hole region (HA) in between extend in the first direction (DR1) and can be connected to a data line (DL) extended along the boundary of the hole region (HA) within the hole region (HA). k is a natural number.

[0073] FIG. 7 is a diagram illustrating, by way of example, the cross-sectional configuration of a pixel shown in FIG. 5.

[0074] Referring to FIG. 7, a pixel (PX) is disposed on a substrate (SUB) and may include a light-emitting element (OLED) and a transistor (TR) connected to the light-emitting element (OLED). The light-emitting element (OLED) may include a first electrode (E1), a second electrode (E2), and a light-emitting layer (EML). The first electrode (E1) may be an anode electrode, and the second electrode (E2) may be a cathode electrode. The light-emitting element (OLED) may be defined as an organic light-emitting element.

[0075] A barrier layer (BR) may be disposed on a substrate (SUB), and a buffer layer (BF) may be disposed on the barrier layer (BR). The barrier layer (BR) and the buffer layer (BF) can block oxygen or moisture entering through the substrate (SUB) from penetrating into the pixel (PX). Additionally, the barrier layer (BR) and the buffer layer (BF) can reduce the surface energy of the substrate (SUB) so that the pixel (PX) can be stably formed on the substrate (SUB).

[0076] For example, a barrier layer (BR) and a buffer layer (BF) are disposed on a substrate (SUB), but embodiments of the present invention are not limited thereto. For example, at least one of the barrier layer (BR) and the buffer layer (BF) may be omitted. Additionally, additional layers other than the barrier layer (BR) and the buffer layer (BF) may be further laminated on the substrate (SUB).

[0077] A semiconductor layer (SM) of a transistor (TR) may be disposed on a buffer layer (BFL). The semiconductor layer (SM) may include a semiconductor or organic semiconductor made of an inorganic material such as amorphous silicon or polycrystalline silicon. Additionally, the semiconductor layer (SM) may include an oxide semiconductor. Although not shown in FIG. 7, the semiconductor layer (SM) may include a source region, a drain region, and a channel region between the source region and the drain region.

[0078] A first insulating layer (IL1) may be disposed on a buffer layer (BFL) to cover a semiconductor layer (SM). A gate electrode (GE) of a transistor (TR) that overlaps with the semiconductor layer (SM) may be disposed on the first insulating layer (IL1). The gate electrode (GE) may be disposed to overlap with the channel region of the semiconductor layer (SM). A second insulating layer (IL2) may be disposed on the first insulating layer (IL1) to cover the gate electrode (GE).

[0079] An upper electrode (UE) may be disposed on the second insulating layer (IL2). When viewed in a planar view, the upper electrode (UE) may overlap with the gate electrode (GE). The pixel (PX) may include a capacitor, and the upper electrode (UE) may function as one electrode of the capacitor by receiving an electrical signal different from that of the gate electrode (GE). However, this is described by way of example, and in an embodiment of the present invention, the upper electrode (UE) may be omitted. A third insulating layer (IL3) may be disposed on the second insulating layer (IL2) to cover the upper electrode (UE).

[0080] The source electrode (SE) and drain electrode (DE) of the transistor (TR) may be spaced apart from each other on the third insulating layer (IL3). The source electrode (SE) may be connected to the source region of the semiconductor layer (SM) through a first contact hole (CH1) defined in the first, second, and third insulating layers (IL1, IL2, IL3). The drain electrode (DE) may be connected to the drain region of the semiconductor layer (SM) through a second contact hole (CH2) defined in the first, second, and third insulating layers (IL1, IL2, IL3).

[0081] A fourth insulating layer (IL4) may be placed on a third insulating layer (IL3) to cover the source electrode (SE) and drain electrode (DE) of the transistor (TR).

[0082] A first electrode (E1) may be placed on the fourth insulating layer (IL4). The first electrode (E1) may be connected to a drain electrode (DE) through a third contact hole (CH3) defined in the fourth insulating layer (IL4).

[0083] A pixel defining film (PDL) that exposes a predetermined portion of the first electrode (E1) may be disposed on the first electrode (E1) and the fourth insulating layer (IL4). An opening (PX_OP) for exposing a predetermined portion of the first electrode (E1) may be defined in the pixel defining film (PDL).

[0084] A light-emitting layer (EML) may be disposed on the first electrode (E1) and the pixel defining film (PDL). A second electrode (E2) may be disposed on the light-emitting layer (EML). The light-emitting layer (EML) and the second electrode (E2) may be disposed in common on the first electrode (E1) and the pixel defining film (PDL). The light-emitting layer (EML) may include at least one of materials that emit red, green, and blue light, and may include a fluorescent material or a phosphorescent material. The light-emitting layer (EML) may include an organic light-emitting material or an inorganic light-emitting material.

[0085] In an embodiment of the present invention, the light-emitting layer (EML) is illustrated as a layer having an integral shape on the first electrode (E1) and the pixel defining film (PDL). However, this is illustrated as an example, and the light-emitting layer (EML) may be disposed only in the area corresponding to the aperture (PX_OP). The light-emitting layer (EML) may further include a charge control layer. The charge control layer can improve the luminous efficiency and lifespan of the light-emitting device (OLED) by controlling the movement of charges. The charge control layer may include at least one of a hole transport material, a hole injection material, an electron transport material, and an electron injection material.

[0086] A thin film encapsulation layer (TFE) may be disposed on a second electrode (E2). The thin film encapsulation layer (TFE) may include a first encapsulation layer (EN1) disposed on the second electrode (E2), a second encapsulation layer (EN2) disposed on the first encapsulation layer (EN1), and a third encapsulation layer (EN3) disposed on the second encapsulation layer (EN2). The first and third encapsulation layers (EN1, EN3) may be inorganic insulating layers, and the second encapsulation layer (EN2) may be an organic insulating layer.

[0087] The first and third encapsulation layers (EN1, EN3) can protect the pixels from moisture / oxygen. The second encapsulation layer (EN2) can protect the pixels (PX) from foreign substances such as dust particles. The aforementioned input sensing unit (ISP) can be disposed on the thin film encapsulation layer (TFE).

[0088] The layer from the barrier layer (BR) to the fourth insulating layer (IL4) can be defined as a circuit element layer (DP-CL). The layer from the first electrode (E1) to the second electrode (E2) can be defined as a display element layer (DP-OLED).

[0089] A first voltage is applied to the first electrode (E1), and a second voltage having a level lower than the first voltage can be applied to the second electrode (E2). Holes and electrons injected into the light-emitting layer (EML) combine to form excitons, and as the excitons transition to the ground state, the light-emitting element (OLED) can emit light. As the light-emitting element (OLED) emits light, an image can be displayed.

[0090] Figure 8 is a plan view of the input detection unit shown in Figure 3.

[0091] Referring to FIG. 8, an input detection unit (ISP) may be placed on a display panel (DP). The input detection unit (ISP) may include a plurality of detection electrodes (SE1, SE2), a plurality of detection lines (SNL1, SNL2, SNL3), a plurality of detection pads (SPD1, SPD2, SPD3), a plurality of first to fourth pads (PD1~PD4), and a crack detection unit (CDT).

[0092] The input detection unit (ISP) may include a hole area (HA) where a hole (HO) is defined, an active area (AA) surrounding the hole area (HA), and an inactive area (NAA) surrounding the active area (AA). The active area (AA) may overlap with a display area (DA), and the inactive area (NAA) may overlap with a non-display area (NDA). The active area (AA) may be defined as a second area, and the inactive area (NAA) may be defined as a third area.

[0093] The sensing electrodes (SE1, SE2) may be placed in the active area (AA). The sensing electrodes (SE1, SE2) may not be placed in the hole area (HA). The sensing lines (SNL1, SNL2, SNL3) are connected to one end of the sensing electrodes (SE1, SE2) and extend into the inactive area (NAA) to be connected to the sensing pads (SPD1, SPD2, SPD3).

[0094] The crack detection unit (CDT) is positioned within the hole region (HA) and can be insulated from the detection electrodes (SE1, SE2) by extending into the active region (AA). The crack detection unit (CDT) can be connected to the first to fourth pads (PD1, PD2, PD3, PD4) by extending into the inactive region (NAA).

[0095] The sensing pads (SPD1, SPD2, SPD3) and the first to fourth pads (PD1, PD2, PD3, PD4) can be connected to an input sensing control unit (not shown) for controlling an input sensing unit (ISP) through a flexible printed circuit board (not shown).

[0096] The sensing electrodes (SE1, SE2) may include a plurality of first sensing electrodes (SE1) arranged in a second direction (DR2) extending in a first direction (DR1) and a plurality of second sensing electrodes (SE2) arranged in a first direction (DR1) extending in a second direction (DR2). The second sensing electrodes (SE2) may extend to intersect the first sensing electrodes (SE1) while being insulated from each other. The first sensing electrodes (SE1) may be defined as output sensing electrodes, and the second sensing electrodes (SE2) may be defined as input sensing electrodes.

[0097] The sensing lines (SNL1, SNL2, SNL3) may include a plurality of first sensing lines (SNL1), a plurality of second sensing lines (SNL2), and a plurality of third sensing lines (SNL3). The first sensing lines (SNL1) may be connected to the lower ends of the first sensing electrodes (SE1) and extend to an inactive region (NAA). The second sensing lines (SNL2) may be connected to one end of the second sensing electrodes (SE2) and extend to an inactive region (NAA). The third sensing lines (SNL3) may be connected to the upper ends of the first sensing electrodes (SE1) and extend to an inactive region (NAA).

[0098] The sensing pads (SPD1, SPD2, SPD3) may include a plurality of first sensing pads (SPD1), a plurality of second sensing pads (SPD2), and a plurality of third sensing pads (SPD3). When viewed in a planar view, the first, second, and third sensing pads (SPD1, SPD2, SPD3) may be positioned adjacent to the bottom of the input sensing unit (ISP). When viewed in a planar view, the first, second, and third sensing pads (SPD1, SPD2, SPD3) may be positioned with the area where the data driving unit (DDV) is positioned in between.

[0099] The data driver (DDV) may be positioned between the second sensing pads (SPD2) and the first and third sensing pads (SPD1, SPD3). For example, the first and third sensing pads (SPD1, SPD3) may be positioned to the right of the data driver (DDV), and the second sensing pads (SPD2) may be positioned to the left of the data driver (DDV). The first sensing pads (SPD1) may be positioned between the third sensing pads (SPD3) and the data driver (DDV).

[0100] The first sensing lines (SNL1) can be extended into the inactive area (NAA) and connected to the first sensing pads (SPD1). The second sensing lines (SNL2) can be extended into the inactive area (NAA) and connected to the second sensing pads (SPD2). The third sensing lines (SNL3) can be extended into the inactive area (NAA) and connected to the third sensing pads (SPD3).

[0101] The input sensing unit (ISP) can be driven in a mutual sensing mode. For example, driving signals can be applied to the second sensing electrodes (SE2) through the second sensing lines (SNL2), and sensing signals can be output from the first sensing electrodes (SE1) through the first and third sensing lines (SNL1, SNL3).

[0102] Each of the first sensing electrodes (SE1) may include a plurality of first sensing parts (SP1) arranged in a first direction (DR1) and a plurality of connecting parts (CP) connecting the first sensing parts (SP1). Each of the connecting parts (CP) may be positioned between two first sensing parts (SP1) adjacent to each other in the first direction (DR1) to electrically connect the two first sensing parts (SP1).

[0103] Each of the second sensing electrodes (SE2) may include a plurality of second sensing units (SP2) arranged in the second direction (DR2) and branching units (BP) disposed between the second sensing units (SP2). Each of the branching units (BP) may be disposed between two second sensing units (SP2) adjacent to each other in the second direction (DR2) and may extend from the two second sensing units (SP2). The branching units (BP) may be formed integrally with the second sensing units (SP2).

[0104] The first sensing parts (SP1) and the second sensing parts (SP2) may be spaced apart from each other without overlapping and may be arranged alternately. Capacitance may be formed by the first sensing parts (SP1) and the second sensing parts (SP2). The connecting parts (CP) may be extended to intersect with the branching parts (BP) while being insulated from each other.

[0105] The first and second sensing units (SP1, SP2) and branching units (BP) may be placed on the same floor. The connecting units (CP) may be placed on a different floor from the first and second sensing units (SP1, SP2) and branching units (BP). The connecting units (CP) may be placed below the first and second sensing units (SP1, SP2) and branching units (BP).

[0106] Among the first and second sensing parts (SP1, SP2), the first and second sensing parts (SP1, SP2) adjacent to the hole region (HA) may have a different shape from the other first and second sensing parts (SP1, SP2). For example, four second sensing parts (SP2) may surround the hole region (HA). A portion of each of the four second sensing parts (SP2) adjacent to the hole region (HA) may be deformed to have a shape corresponding to the boundary of the hole region (HA). However, not limited thereto, depending on the location of the hole region (HA), a portion of each of the four first sensing parts (SP1) adjacent to the hole region (HA) may also be deformed.

[0107] The crack detection unit (CDT) may include a crack detection pattern (CDP), a crack detection line (CDL), and a connection unit (CPT). The crack detection pattern (CDP), the crack detection line (CDL), and the connection unit (CPT) may include a conductive material.

[0108] A crack detection pattern (CDP) can be placed within a hole area (HA). The crack detection pattern (CDP) can be formed as an open curve including one end and the other end. The crack detection pattern (CDP) can be placed to surround a hole (HO) within the hole area (HA).

[0109] The crack detection line (CDL) may be placed in the inactive area (NAA) and extend along the edge of the input detection unit (ISP). The crack detection line (CDL) may be connected to the first to fourth pads (PD1 to PD4). The crack detection line (CDL) may be placed outside the first, second, and third detection lines (SNL1, SNL2, SNL3).

[0110] The crack detection line (CDL) may include a first crack detection line (CDL1) and a second crack detection line (CDL2) positioned outside the first crack detection line (CDL1) and adjacent to the edge of the input detection unit (ISP). The first crack detection line (CDL1) and the second crack detection line (CDL2) may be positioned in an inactive area (NAA) and extend along the top and left and right sides of the input detection unit (ISP). The first crack detection line (CDL1) and the second crack detection line (CDL2) may extend toward the bottom of the input detection unit (ISP).

[0111] The first pad (PD1) and the second pad (PD2) may be positioned to the left of the second detection pad (SPD2). The first pad (PD1) may be positioned between the second pad (PD2) and the second detection pad (SPD2). The third pad (PD3) and the fourth pad (PD4) may be positioned to the right of the third detection pad (SPD3). The third pad (PD3) may be positioned between the fourth pad (PD4) and the third detection pad (SPD3).

[0112] The first crack detection line (CDL1) can be connected to the first pad (PD1) and the third pad (PD3). One end of the first crack detection line (CDL1) is connected to the first pad (PD1), and the other end of the first crack detection line (CDL1) can be connected to the third pad (PD3).

[0113] The second crack detection line (CDL2) can be connected to the second pad (PD2) and the fourth pad (PD4). One end of the second crack detection line (CDL2) is connected to the second pad (PD2), and the other end of the second crack detection line (CDL2) can be connected to the fourth pad (PD4).

[0114] The connection portion (CPT) can be connected to the crack detection pattern (CDP) and extended in a first direction (DR1). The connection portion (CPT) can be extended to the inactive region (NAA) via the first and second sensing electrodes (SE1, SE2) between the hole region (HA) and the inactive region (NAA). The connection portion (CPT) can be insulated from the first and second sensing electrodes (SE1, SE2). The connection portion (CPT) can be connected to the crack detection line (CDL) in the inactive region (NAA).

[0115] A connecting portion (CPT) may include a first connecting portion (CPT1) and a second connecting portion (CPT2) that extend in a first direction (DR1) and are spaced apart from each other in a second direction (DR2). The first connecting portion (CPT1) may be connected to one end of a crack detection pattern (CDP) and a first crack detection line (CDL1). The second connecting portion (CPT2) may be connected to the other end of a crack detection pattern (CDP) and a second crack detection line (CDL2).

[0116] Damage to the display device (DD), such as a crack in the hole area (HA) or inactive area (NAA), can be detected by the crack detection unit (CDT). The first pad (PD1) and the third pad (PD3) are input terminals, and the second pad (PD2) and the fourth pad (PD4) may be output terminals.

[0117] An electrical signal received through the first pad (PD1) can be output to the second pad (PD2) via the first crack detection line (CDL1), the crack detection pattern (CDP), and the second crack detection line (CDL2). Additionally, an electrical signal received through the third pad (PD3) can be output to the fourth pad (PD4) via the first crack detection line (CDL1), the crack detection pattern (CDP), and the second crack detection line (CDL2).

[0118] If the signal detected at each of the second pad (PD2) and the fourth pad (PD4) is detected at a low level or zero (0) level relative to the reference signal, both the first and second crack detection lines (CDL1, CDL2) may be damaged, or the crack detection pattern (CDP) may be damaged. Therefore, whether a crack has occurred within the hole area (HA) can be detected.

[0119] Additionally, if only the signal detected at either the second pad (PD2) or the fourth pad (PD4) is detected as defective, the crack detection line (CDL) may be damaged. Therefore, the occurrence of a crack in the inactive area (NAA) can be detected.

[0120] In an embodiment of the present invention, the presence of a crack in the display device (DD) can be easily detected through the crack detection unit (CDT). Therefore, the defect status of the display device (DD) can be detected without a separate inspection circuit or inspection device. A more detailed configuration of the crack detection unit (CDT) will be described in detail below.

[0121] FIG. 9 is an enlarged view of the first and second sensing units arranged around the hole area. FIG. 10 is a cross-sectional view along line II-II' shown in FIG. 9. FIG. 11 is a cross-sectional view along line III-III' shown in FIG. 9.

[0122] For example, FIGS. 10 and 11 show first and second sensing units (SP1, SP2) disposed on a thin film encapsulation layer (TFE), and the components below the thin film encapsulation layer (TFE) are omitted.

[0123] Referring to FIGS. 9 and 10, each of the first sensing electrodes (SE1) may include a plurality of first sensing parts (SP1), a plurality of first dummy patterns (DPT1), and a plurality of connecting parts (CP). The first dummy patterns (DPT1) may be placed in a plurality of first openings (OP1) defined in each of the first sensing parts (SP1). The connecting parts (CP) may connect the first sensing parts (SP1) to each other.

[0124] For example, in FIG. 9, the boundary (BAL1) between the first sensing parts (SP1) and the first dummy patterns (DPT1), where the first openings (OP1) are defined, is shown as a line. However, as shown in FIG. 10, the first sensing parts (SP1) and the first dummy patterns (DPT1) can be separated and insulated from each other at the boundary (BAL1) between the first sensing parts (SP1) and the first dummy patterns (DPT1).

[0125] A first insulating layer (T_INS1) may be disposed on a thin film encapsulation layer (TFE). Connection portions (CP) may be disposed on the first insulating layer (T_INS1). A second insulating layer (T_INS2) may be disposed on the first insulating layer (T_INS1) to cover the connection portions (CP). First sensing portions (SP1), branching portions (BP), and first dummy patterns (DPT1) may be disposed on the second insulating layer (T_INS2). The first sensing portions (SP1) may be connected to the connection portions (CP) through a plurality of first contact holes (T_CH1) defined in the second insulating layer (T_INS2).

[0126] A third insulating layer (T_INS3) may be disposed on a second insulating layer (T_INS2) to cover the first sensing portions (SP1), branching portions (BP), and first dummy patterns (DPT1). Each of the first, second, and third insulating layers (T_INS1, T_INS2, T_INS3) may comprise an inorganic film and / or an organic film.

[0127] Referring to FIGS. 9 and FIGS. 11, each of the second sensing electrodes (SE2) may include a plurality of second sensing parts (SP2), a plurality of second dummy patterns (DPT2), and a plurality of branching parts (BP). The second dummy patterns (DPT2) may be placed in a plurality of second openings (OP2) defined in each of the second sensing parts (SP2).

[0128] For example, in FIG. 9, the boundary (BAL2) between the second sensing parts (SP2) and the second dummy patterns (DPT2), where the second openings (OP2) are defined, is shown as a line. However, as shown in FIG. 11, the second sensing parts (SP2) and the second dummy patterns (DPT2) can be separated and insulated from each other at the boundary (BAL2) between the second sensing parts (SP2) and the second dummy patterns (DPT2).

[0129] Second sensing parts (SP2), branching parts (BP), and second dummy patterns (DPT2) may be disposed on the second insulating layer (T_INS2). The branching parts (BP) may extend from the second sensing parts (SP2). The branching parts (BP) may be formed integrally with the second sensing parts (SP2). The branching parts (BP) may extend to intersect with the connecting parts (CP). The branching parts (BP) may be insulated from the connecting parts (CP) by the second insulating layer (T_INS2).

[0130] The third insulating layer (T_INS3) may be placed on the second insulating layer (T_INS2) to cover the second sensing parts (SP2), branching parts (BP), and second dummy patterns (DPT2).

[0131] Referring to FIG. 9, the boundary (BAL3) between the first sensing units (SP1) and the second sensing units (SP2) is shown as a line. However, substantially, the first sensing units (SP1) and the second sensing units (SP2) can be separated and insulated from each other at the boundary (BAL3), just as at the boundaries (BAL1, BAL2).

[0132] Each of the first sensing parts (SP1) and the second sensing parts (SP2) may have an approximate rhombus shape. Additionally, a plurality of protruding patterns (PT) may be defined on the edges of each of the first sensing parts (SP1) and the second sensing parts (SP2).

[0133] The first connection part (CPT1) may include an extension line (EXL), a first connection line (CNL1), a first connection pattern (CT1), and a first extension line (EXL1). The second connection part (CPT2) may include a second connection line (CNL2), a second connection pattern (CT2), and a second extension line (EXL2). The first connection pattern (CT1) and the second connection pattern (CT2) may be defined as connection patterns.

[0134] The first and second connection patterns (CT1, CT2) may be insulated from the sensing electrodes (SE1, SE2). For example, some of the first openings (OP1) positioned between the hole area (HA) and the inactive area (NAA) (or non-display area (NDA)) may be opened toward the inactive area (NAA). Some of the openings opened toward the inactive area (NAA) may be defined as a first sub-opening (SOP1) and a second sub-opening (SOP2).

[0135] A first connection pattern (CT1) may be placed in a first sub-opening (SOP1). A second connection pattern (CT2) may be placed in a second sub-opening (SOP2). By being placed in the first and second sub-openings (SOP1, SOP2), the first and second connection patterns (CT1, CT2) may be spaced apart from the first sensing members (SP1) and insulated from the first sensing members (SP1).

[0136] The crack detection pattern (CDP) may be placed on the same floor as the first detection units (SP1), branching units (BP), and second detection units (SP2). The first connection pattern (CT1) may be placed on a different floor from the second connection pattern (CT2). The first connection pattern (CT1) may be placed on the same floor as the crack detection pattern (CDP), and the second connection pattern (CT2) may be placed on a different floor from the crack detection pattern (CDP). The second connection pattern (CT2) may be placed on the same floor as the connection units (CP).

[0137] The first and second connection patterns (CT1, CT2) can be connected to the crack detection pattern (CDP) through the first and second connection lines (CNL1, CNL2) and the extension line (EXL). The first and second connection patterns (CT1, CT2) can be connected to the first and second crack detection lines (CDL1, CDL2) through the first and second extension lines (EXL1, EXL2).

[0138] The first connection pattern (CT1) can be connected to one end of the crack detection pattern (CDP) via an extension line (EXL) and a first connection line (CNL1). Specifically, the extension line (EXL) is placed on the same floor as the crack detection pattern (CDP) and can extend from one end of the crack detection pattern (CDP) toward the first connection pattern (CT1). The first connection line (CNL1) is placed on the same floor as the second connection pattern (CT2) and can connect the first connection pattern (CT1) with the extension line (EXL).

[0139] The first crack detection line (CDL1) may extend from the first connection pattern (CT1). For example, the first extension line (EXL1) may be placed on the same layer as the first connection pattern (CT1) and extend from the first connection pattern (CT1) to the first crack detection line (CDL1). The first extension line (EXL1) may be placed in an inactive area (NAA) (or non-display area (NDA)) and extend in the first direction (DR1). The first crack detection line (CDL1) may be placed on the same layer as the first extension line (EXL1) and extend from the first extension line (EXL1).

[0140] The second connection pattern (CT2) can be connected to the other end of the crack detection pattern (CDP) via the second connection line (CNL2). Specifically, the second connection line (CNL2) is positioned on the same layer as the second connection pattern (CT2) and can extend from the second connection pattern (CT2) to the hole area (HA). The second connection line (CNL2) can be connected to the other end of the crack detection pattern (CDP).

[0141] The second crack detection line (CDL2) may extend from the second connection pattern (CT2). For example, the second extension line (EXL2) may be placed on the same layer as the second connection pattern (CT2) and extend from the second connection pattern (CT2) to the second crack detection line (CDL2). The second extension line (EXL2) may be placed in an inactive area (NAA) (or non-display area (NDA)) and extend in the first direction (DR1). The second crack detection line (CDL2) may be placed on the same layer as the second extension line (EXL2) and extend from the second extension line (EXL2).

[0142] The first connection line (CNL1) and the second connection line (CNL2) may be extended to intersect the branch (BP) located between the hole region (HA) and the inactive region (NAA) among the branch sections (BP). Since the first connection line (CNL1) and the second connection line (CNL2) are located on the same floor as the connection sections (CP), they may be insulated from the branch section (BP).

[0143] A first detection unit (SP1) positioned above the hole area (HA) and a first detection unit (SP1) positioned below the hole area (HA) can be connected via bypass lines (ARL). The bypass lines (ARL) extend along the periphery of the hole (HO) and can be positioned on the same floor as the first detection units (SP1). The bypass lines (ARL) can be positioned outside the crack detection pattern (CDP).

[0144] A first detection unit (SP1) positioned above the hole area (HA) and a first detection unit (SP1) positioned below the hole area (HA) can be connected to bypass lines (ARL) through connection units (CP) positioned between an extension line (EXL) and a second connection line (CNL2). Practically, the bypass lines (ARL) can be connected to the connection units (CP) through contact holes (not shown) defined in the second insulating layer (T_INS2). However, this is described by way of example, and the bypass lines (ARL) can be positioned on the same layer as the connection units (CP) and extend from the connection units (CP).

[0145] FIG. 12 is a diagram exemplarily illustrating the cross-sectional configuration from the hole area and crack detection pattern shown in FIG. 9 to the first connection pattern.

[0146] Referring to FIG. 12, a groove (GV) may be defined between the boundary of the hole (HO) and the hole region (HA). The groove (GV) may be provided in multiple numbers. For example, the groove (GV) may include a first groove (GV1), a second groove (GV2), and a third groove (GV3). The first groove (GV1), the second groove (GV2), and the third groove (GV3) may have a closed line shape surrounding the hole (HO). However, not limited thereto, the first groove (GV1), the second groove (GV2), and the third groove (GV3) may have an intermittent line shape surrounding a portion of the edge of the hole (HO).

[0147] Each of the first groove (GV1), the second groove (GV2), and the third groove (GV3) can be defined by being recessed downward from the upper surface of the substrate (SUB) by a predetermined depth. Each of the first groove (GV1), the second groove (GV2), and the third groove (GV3) can be formed by removing portions of the substrate (SUB). The first groove (GV1) may be adjacent to the boundary between the hole region (HA) and the display region (DA). The third groove (GV3) may be adjacent to the hole (HO). The second groove (GV2) may be positioned between the first groove (GV1) and the third groove (GV3).

[0148] Deposition patterns (ELP) may be disposed in the first groove (GV1), the second groove (GV2), and the third groove (GV3). The deposition patterns (ELP) may contain the same material as the light-emitting layer (EML) and the second electrode (E2) and may be formed together with the light-emitting layer (EML) and the second electrode (E2) during their formation. The deposition patterns (ELP) may be covered by the first encapsulation layer (EN1).

[0149] In an embodiment of the present invention, the deposition patterns (ELP) may not be arranged continuously from the light-emitting layer (EML) by being placed in the first, second, and third grooves (GV1, GV2, GV3). The continuity between the deposition patterns (ELP) and the light-emitting layer (EML) may be blocked by the first, second, and third grooves (GV1, GV2, GV3). Additionally, the deposition patterns (ELP) may not be arranged continuously with each other but may be spaced apart from each other.

[0150] To form a hole (HO), a portion of the display panel (DP) within the hole area (HA) may be cut. During the cutting process, external moisture or oxygen may be introduced into the display panel (DP) through the cut surface via the hole (HO).

[0151] A deposition pattern (ELP) is formed extending from the light-emitting layer (EML), and the deposition pattern (ELP) can be continuously arranged up to the hole (HO). In this case, external moisture or oxygen introduced through the hole (HO) can penetrate into the active region (AA) through the deposition pattern (ELP). The devices placed in the active region (AA) may be damaged by the moisture or oxygen that has penetrated into the active region (AA).

[0152] However, in an embodiment of the present invention, the deposition patterns (ELP) are spaced apart from the light-emitting layer (EML), and the deposition patterns (ELP) are spaced apart from each other, so that external moisture or oxygen introduced through the hole (HO) can be blocked. As a result, damage to the devices placed in the active region (AA) can be prevented.

[0153] For example, three first, second, and third grooves (GV1, GV2, GV3) are shown, but are not limited thereto, and a single groove may be provided around the hole (HO), or the grooves may be omitted.

[0154] A plurality of dams (DAM1, DAM2) may be disposed on a substrate (SUB) between the first groove (GV1), the second groove (GV2), and the third groove (GV3). The dams (DAM1, DAM2) may include a first dam (DAM1) disposed on the substrate (SUB) between the first groove (GV1) and the second groove (GV2), and a second dam (DAM2) disposed on the substrate (SUB) between the second groove (GV2) and the third groove (GV3). Deposition patterns (ELP) may be further disposed on the first and second dams (DAM1, DAM2).

[0155] The first dam (DAM1) may be formed of a barrier layer (BR), a buffer layer (BF), first to fourth insulating layers (IL1~IL4), and a pixel defining film (PDL). The second dam (DAM2) may be formed of a barrier layer (BR), a buffer layer (BF), and first to third insulating layers (IL1~IL3). However, this is illustrated as an example, and the first and second dams (DAM1, DAM2) may have a single-layer structure.

[0156] A barrier layer (BR) may be disposed on a substrate (SUB) between the hole (HO) and the third groove (GV3). A buffer layer (BF) may be disposed on the barrier layer (BR) between the hole (HO) and the third groove (GV3). Deposition patterns (ELP) may be further disposed on the buffer layer (BF) between the hole (HO) and the third groove (GV3).

[0157] The width of each of the first and second dams (DAM1, DAM2) may decrease towards the top. In FIG. 12, the width represents a value measured with respect to the horizontal direction. The widths of the barrier layer (BR) and buffer layer (BF) of the first and second dams (DAM1, DAM2) may be larger than the width of the substrate (SUB) between the first, second, and third grooves (GV1, GV2, GV3). This is because, during the etching process, the amount of etching of the substrate (SUB) and the amount of etching of the barrier layer (BR) and buffer layer (BF) differ depending on the difference in material between the substrate (SUB) and the barrier layer (BR) and buffer layer (BF).

[0158] In the cross-sectional structure, the widths of the first, second, and third insulating layers (IL1, IL2, IL3) may be smaller than the widths of the barrier layer (BR) and the buffer layer (BF). Additionally, the width of the fourth insulating layer (IL4) may be smaller than the widths of the first, second, and third insulating layers (IL1, IL2, IL3). Additionally, the width of the pixel defining film (PDL) may be smaller than the width of the fourth insulating layer (IL4). Deposition patterns (ELP) may be further disposed on the buffer layer (BF) that does not overlap the first, second, and third insulating layers (IL1, IL2, IL3).

[0159] Wiring patterns (LN) may be placed on the second insulating layer (IL2) and the third insulating layer (IL3). The wiring patterns (LN) may be power lines for supplying power to the data lines (DL) or transistor (TR) shown in FIG. 5.

[0160] The first encapsulation layer (EN1) and the third encapsulation layer (EN3) may extend into the hole region (HA). The first and second dams (DAM1, DAM2) may partition the formation region of the second encapsulation layer (EN2) containing organic material. For example, the second encapsulation layer (EN2) may extend into the hole region (HA) and be positioned up to the first dam (DMA1).

[0161] A first encapsulation layer (EN1) may be disposed on a substrate (SUB) and first and second dams (DAM1, DAM2) in a hole region (HA). As previously described, the first encapsulation layer (EN1) may be disposed on the substrate (SUB) to cover deposition patterns (ELP) in the hole region (HA). A third encapsulation layer (EN3) may be disposed on the first encapsulation layer (EN1) in the hole region (HA).

[0162] When manufacturing the display device (DD), a fluid organic material may be cured to form a second encapsulation layer (EN2). Even if the fluid organic material flows into the hole region (HA), it may be blocked at the first dam (DMA1). The second dam (DMA2) may further block the organic material overflowing from the first dam (DAM1).

[0163] Sensing electrodes (SE1, SE2) may be placed on a display area (DA). An insulating layer (INS) may be placed in a hole area (HA) of a display panel (DP). An insulating layer (INS) may be placed on a third encapsulation layer (EN3) in the hole area (HA). The edge of the insulating layer (INS) placed at the boundary between the display area (DA) and the hole area (HA) may have a stepped structure of at least two steps.

[0164] A crack detection pattern (CDP) may be placed in a hole region (HA). A crack detection pattern (CDP) may be placed on an insulating layer (INS) in the hole region (HA). For example, when viewed in a planar view, a crack detection pattern (CDP) having an open curve shape may overlap with a second groove (GV2), but embodiments of the present invention are not limited thereto. For example, when viewed in a planar view, the crack detection pattern (CDP) may overlap with a first groove (GV1) or may overlap with a third groove (GV3). Additionally, when viewed in a planar view, the crack detection pattern (CDP) may be placed between the first groove (GV1) and the second groove (GV2) or between the second groove (GV2) and the third groove (GV3), so as not to overlap with the first, second, and third grooves (GV1, GV2, GV3).

[0165] A first insulating layer (T_INS1) disposed on a thin film encapsulation layer (TFE) of a display area (DA) may extend onto an insulating layer (INS) disposed in a hole area (HA). A second insulating layer (T_INS2) may extend into the hole area (HA) and be disposed on the first insulating layer (T_INS1) in the hole area (HA). A third insulating layer (T_INS3) may extend into the hole area (HA) and be disposed on the second insulating layer (T_INS2) in the hole area (HA).

[0166] A crack detection pattern (CDP), an extension line (EXL) extending from the crack detection pattern (CDP), and a first connection pattern (CT1) may be disposed on a second insulating layer (T_INS2). A first connection line (CNL1) may be disposed on a first insulating layer (T_INS1). A second insulating layer (T_INS2) may be disposed on a first connection line (CNL1).

[0167] The extension line (EXL) and the first connection pattern (CT1) can be connected to the first connection line (CNL1) through a plurality of second contact holes (T_CH2) defined in the second insulating layer (T_INS2). The first connection line (CNL1) can be insulated from the branching section (BP) and the first sensing section (SP1) by the second insulating layer (T_INS2).

[0168] A third insulating layer (T_INS3) may be placed on a second insulating layer (T_INS2) to cover a crack detection pattern (CDP), an extension line (EXL), and a first connection pattern (CT1).

[0169] FIG. 13 is a diagram illustrating an exemplary cross-sectional configuration from the hole area and crack detection pattern shown in FIG. 9 to the second connection pattern. FIG. 14 is a diagram illustrating an exemplary cross-sectional configuration from the hole area and bypass line shown in FIG. 9 to the first detection part adjacent to the hole area.

[0170] Hereinafter, the description of the configuration identical to that described in FIG. 12 will be omitted in FIG. 13 and FIG. 14.

[0171] Referring to FIG. 13, a second connection pattern (CT2) and a second connection line (CNL2) extending from the second connection pattern (CT2) may be placed on a first insulating layer (T_INS1). A second insulating layer (T_INS2) may be placed on the second connection pattern (CT2) and the second connection line (CNL2).

[0172] The crack detection pattern (CDP) can be connected to the second connection line (CNL2) through the third contact hole (T_CH3) defined in the second insulation layer (T_INS2). The second connection line (CNL2) can be insulated from the branch (BP) and the first detection part (SP1) by the second insulation layer (T_INS2).

[0173] Referring to FIG. 14, a bypass line (ARL) may be placed on a second insulating layer (T_INS2). The bypass line (ARL) and the first sensing unit (SP1) may be connected to a connecting unit (CP) through a plurality of fourth contact holes (T_CH4) defined in the second insulating layer (T_INS2). A third insulating layer (T_INS3) may be placed on the second insulating layer (T_INS2) to cover the bypass line (ARL).

[0174] FIG. 15 is a drawing showing the mesh structure of the sensing electrodes and the connection pattern adjacent to the top of the hole area illustrated in FIG. 9.

[0175] Referring to FIG. 15, each of the first and second sensing units (SP1, SP2), first and second dummy patterns (DPT1, DPT2), and first and second connection patterns (CT1, CT2) may have a mesh shape. For example, each of the first and second sensing units (SP1, SP2), first and second dummy patterns (DPT1, DPT2), and first and second connection patterns (CT1, CT2) may include a plurality of first mesh lines (MSL1) extending in a first diagonal direction (DDR1) and a plurality of second mesh lines (MSL2) extending in a second diagonal direction (DDR2).

[0176] The first diagonal direction (DDR1) may intersect the first and second directions (DR1, DR2) on a plane defined by the first and second directions (DR1, DR2). The second diagonal direction (DDR2) may intersect substantially perpendicularly to the first diagonal direction (DDR1) on a plane defined by the first and second directions (DR1, DR2).

[0177] The first mesh lines (MSL1) and the second mesh lines (MSL2) can be formed integrally. Mesh openings (MOP) can be defined by the integrally formed first mesh lines (MSL1) and second mesh lines (MSL2). Pixels (PX) shown in FIG. 5 can be arranged to overlap the mesh openings (MOP). The first and second mesh lines (MSL1, MSL2) can be separated from each other and disconnected at boundaries (BAL1, BAL2, BAL3).

[0178] The first connection line (CNL1) and the second connection line (CNL2) may extend along the first and second mesh lines (MSL1, MSL2) in the active area (AA). The first connection line (CNL1) may be connected to at least one of the intersections of the first mesh lines (MSL1) and the second mesh lines (MSL2). The second connection line (CNL2) may extend from some of the mesh lines of the first and second mesh lines (MSL1, MSL2) of the second connection pattern (CT2).

[0179] The connections (CP) may extend along the first and second mesh lines (MSL1, MSL2) in the active area (AA). The connections (CP) may be connected to at least one of the intersections of the first mesh lines (MSL1) and the second mesh lines (MSL2). The parts indicated by dots represent parts of the connections (CP) and parts of the first connection line (CNL1) connected to the intersections of the first mesh lines (MSL1) and the second mesh lines (MSL2).

[0180] Each of the connections (CP) can extend into at least one line in the hole area (HA). For example, each of the connections (CP) is extended into two lines in the hole area (HA), but the number of extended lines may not be limited to this.

[0181] FIG. 16 is an enlarged view of the first connection pattern, the first extension line, and the first crack detection line shown in FIG. 9. FIG. 17 is a cross-sectional view of the line IV-IV' shown in FIG. 16. FIG. 18 is a cross-sectional view of the line V-V' shown in FIG. 16.

[0182] For example, in FIG. 16, the first connection pattern (CT1) is shown as a mesh shape, and in FIG. 17 and FIG. 18, the components below the thin film encapsulation layer (TFE) are omitted.

[0183] Referring to FIGS. 16 and 17, a first extension line (EXL1) extending from a first connection pattern (CT1) may be placed on a second insulating layer (T_INS2) and extended to an inactive area (NAA) (or non-display area (NDA)). A first crack detection line (CDL1) may be placed on the second insulating layer (T_INS2) and extend from the first extension line (EXL1). That is, the first connection pattern (CT1), the first extension line (EXL1), and the first crack detection line (CDL1) may be formed integrally.

[0184] The third detection lines (SNL3) and the second crack detection line (CDL2) may be disposed on the first insulating layer (T_INS1). The second insulating layer (T_INS2) may be disposed on the first insulating layer (T_INS1) to cover the third detection lines (SNL3) and the second crack detection line (CDL2).

[0185] The first extension line (EXL1) may be extended to intersect the third detection lines (SNL3). The first extension line (EXL1) may be insulated from the third detection lines (SNL3) by the second insulation layer (T_INS2). The third insulation layer (T_INS3) may be placed on the second insulation layer (T_INS2) to cover the first extension line (EXL1) and the first crack detection line (CDL1).

[0186] Referring to FIGS. 16 and 18, the guard ring line (GDR) may be placed in an inactive area (NAA) (or non-marked area (NDA)). The guard ring line (GDR) may be placed between the first and second crack detection lines (CDL1, CDL2) and the active area (AA) (or marked area (DA)). The guard ring line (GDR) may be placed between the first and second crack detection lines (CDL1, CDL2) and the third detection lines (SNL3).

[0187] A guard ring line (GDR) is disposed on a first insulating layer (T_INS1), and a second insulating layer (T_INS2) may be disposed on the first insulating layer (T_INS1) to cover the guard ring line (GDR). The guard ring line (GDR) may be disposed on the same layer as the second connection pattern (CT2). The guard ring line (GDR) may include a conductive material.

[0188] The guard ring line (GDR) can serve to block static electricity entering from the outside from being transmitted to the sensing electrodes (SE1, SE2). The width of the guard ring line (GDR) may be greater than the width of the third sensing lines (SNL3) and the first and second crack sensing lines (CDL1, CDL2), respectively.

[0189] The guard ring line (GDR) may not overlap with the first extension line (EXL1) of the crack detection unit (CDT). For example, when viewed in a planar view, the guard ring line (GDR) may not be placed in the part that overlaps with the first extension line (EXL1). The guard ring line (GDR) may be spaced apart from the first extension line (EXL1).

[0190] If the guard ring line (GDR) is positioned below the first extension line (EXL1) so as to overlap the first extension line (EXL1), the first extension line (EXL1) and the guard ring line (GDR) may short-circuit by penetrating the second insulation layer (T_INS2) during the manufacturing process. In an embodiment of the present invention, the guard ring line (GDR) is spaced apart from the first extension line (EXL1) and does not overlap with the first extension line (EXL1), so that a short circuit between the first extension line (EXL1) and the guard ring line (GDR) can be prevented during the manufacturing process.

[0191] FIG. 19 is an enlarged view of the second connection pattern, the second extension line, and the second crack detection line shown in FIG. 9. FIG. 20 is a cross-sectional view of the line VI-VI' shown in FIG. 19.

[0192] For example, in FIG. 19, the second connection pattern (CT2) is shown as a mesh shape, and in FIG. 20, the components below the thin film encapsulation layer (TFE) are omitted.

[0193] Referring to FIGS. 19 and 20, a second extension line (EXL2) extending from a second connection pattern (CT2) may be placed on a first insulating layer (T_INS1) and extended to an inactive area (NAA) (or non-display area (NDA)). A second crack detection line (CDL2) may be placed on the first insulating layer (T_INS1) and extended from the second extension line (EXL2). That is, the second connection pattern (CT2), the second extension line (EXL2), and the second crack detection line (CDL2) may be formed integrally.

[0194] The second extension line (EXL2) may be extended to intersect with the third sensing lines (SNL3). In the portion overlapping with the second extension line (EXL2), the third sensing lines (SNL3) may be connected via line connectors (LCN). The line connectors (LCN) may be placed on the second insulating layer (T_INS2).

[0195] Although not illustrated, line connections (LCN) may be connected to third sensing lines (SNL3) through contact holes defined in the second insulating layer (T_INS2). The third insulating layer (T_INS3) may be placed on the second insulating layer (T_INS2) to cover the line connections (LCN).

[0196] The guard ring line (GDR) may not overlap with the second extension line (EXL2) of the crack detection unit (CDT). For example, when viewed in a planar view, the guard ring line (GDR) may not be placed in the part that overlaps with the second extension line (EXL2). The guard ring line (GDR) may be spaced apart from the second extension line (EXL2).

[0197] FIG. 21 is an enlarged view of the hole area shown in FIG. 9. FIG. 22 is a cross-sectional view along line VII-VII' shown in FIG. 21. FIG. 23 is a cross-sectional view along line VIII-VIII' shown in FIG. 21. FIG. 24 is a cross-sectional view along line IX-IX' shown in FIG. 21.

[0198] For example, the components below the thin film encapsulation layer (TFE) in FIGS. 22 to 24 have been omitted.

[0199] Referring to FIGS. 21 and 22, a capping layer (CPL) may be disposed at the boundary between an active region (AA) (or a display region (DA)) and a hole region (HA). The capping layer (CPL) may be disposed on an insulating layer (INS) to cover the edge of an insulating layer (INS) having at least two steps, spaced apart from a crack detection pattern (CDP). The capping layer (CPL) may include a conductive material.

[0200] The capping layer (CPL) can be placed on a portion of the insulating layer (INS) adjacent to the boundary of the hole region (HA) and on a portion of the thin film encapsulation layer (TFE) adjacent to the boundary of the hole region (HA). The capping layer (CPL) can be placed outside the bypass line (ARL).

[0201] Referring to FIGS. 21, 22, and 23, a capping layer (CPL) may be disposed on a first insulating layer (T_INS1). The capping layer (CPL) may be disposed on the same layer as a second connecting line (CNL2). That is, the capping layer (CPL) may be disposed on the same layer as a second connecting pattern (CT2). Although not illustrated, the capping layer (CPL) and the connecting portion (CP) may be disposed on the same layer as each other. A second insulating layer (T_INS2) may be disposed on the first insulating layer (T_INS1) to cover the capping layer (CPL). An extension line (EXL) may be disposed on the capping layer (CPL).

[0202] Referring to FIGS. 21 and 23, the capping layer (CPL) may not overlap with the second connection line (CNL2) placed on the same layer. The capping layer (CPL) may be spaced apart from the second connection line (CNL2) by a gap (GAP) greater than 0 and less than 15 micrometers. Similarly, the capping layer (CPL) may not overlap with the connection (CP) passing through the boundary of the hole region (HA). The capping layer (CPL) may be spaced apart from the connection (CP) by a gap (GAP) greater than 0 and less than 15 micrometers.

[0203] Referring to FIG. 24, the second connecting line (CNL2) can be extended over the edge of an insulating layer (INS) formed with at least two steps.

[0204] FIGS. 25 to 30 are drawings for explaining a method of manufacturing the capping layer and the second connecting line shown in FIG. 21.

[0205] For example, FIGS. 25 and 28 are illustrated in cross-sections corresponding to FIG. 22, and FIGS. 26 and 29 are illustrated in cross-sections corresponding to FIG. 23. Additionally, FIGS. 27 and 30 are illustrated in cross-sections corresponding to FIG. 24.

[0206] Referring to FIGS. 25, 26, and 27, a first conductive layer (CON1) may be disposed on a first insulating layer (T_INS1). The first conductive layer (CON1) may be provided on the first insulating layer (T_INS1) to form a capping layer (CPL) and a second connecting line (CNL2). Although not illustrated, a connecting portion (CP) may be formed by the first conductive layer (CON1).

[0207] A photoresist (PR) may be disposed on the first conductive layer (CON1). The photoresist (PR) may be disposed on the area where the capping layer (CPL) is to be formed and the area where the second connecting line (CNL2) is to be formed. Although not illustrated, the photoresist (PR) may be disposed on the area where the connecting portion (CP) is to be formed.

[0208] The photoresist (PR) can act as a mask. Plasma (PLM) used during the dry etching process can be provided to a portion of the first conductive layer (CON1) that is not obscured by the photoresist (PR). Plasma (PLM) provided toward the portion of the first conductive layer (CON1) that is obscured by the photoresist (PR) can be blocked by the photoresist (PR).

[0209] Referring to FIGS. 28, 29, and 30, a portion of the first conductive layer (CON1) that is not covered by the photoresist (PR) can be removed through a dry etching process. The photoresist (PR) can be removed after the etching process. Thus, a capping layer (CPL) and a second connecting line (CNL2) can be formed on the first insulating layer (T_INS1). Although not illustrated, the first conductive layer (CON1) can be patterned to form a connecting portion (CP) on the first insulating layer (T_INS1).

[0210] Subsequently, the second insulating layer (T_INS2) and the third insulating layer (T_INS3) can be sequentially laminated on the capping layer (CPL) and the second connecting line (CNL2).

[0211] FIGS. 31 to 35 are drawings illustrating methods for manufacturing other display devices.

[0212] For example, FIGS. 31 and FIGS. 32 are illustrated in cross-sections corresponding to FIGS. 24, and FIGS. 33 to 35 are illustrated in cross-sections corresponding to FIGS. 22. FIGS. 31 to 35 will be described below together with some of FIGS. 21 to 30 as necessary for the explanation.

[0213] FIGS. 31 and 32 are cross-sectional views corresponding to line IX-IX' and are drawings for explaining the method of manufacturing the second connecting line (CNL2). FIGS. 33 to 35 are cross-sectional views corresponding to line VII-VII' when the capping layer (CPL) is not formed.

[0214] Referring to FIGS. 31 and 32, the insulating layer (INS') may have a stepped structure at its edge. The height of the upper surface of the insulating layer (INS') may be the same as the height of the upper surface of the insulating layer (INS) shown in FIG. 24.

[0215] A first conductive layer (CON1) for forming a second connection line (CNL2) may be provided on a first insulating layer (T_INS1). A photoresist (PR) may be disposed on the first conductive layer (CON1). The photoresist (PR) may be disposed on an area for forming the second connection line (CNL2).

[0216] A photoresist (PR) capable of having fluidity can be placed thinner than the surroundings at the top corner of the insulating layer (INS'). As the step difference at the edge of the insulating layer (INS') increases, the thickness of the photoresist (PR) placed at the top corner of the insulating layer (INS') can be thinner.

[0217] During the dry etching process, the photoresist (PR) may be damaged by the plasma (PLM). If the thickness of the photoresist (PR) is sufficiently thick, the first conductive layer (CON1) may not be exposed even if the photoresist (PR) is damaged. However, if the thickness of the photoresist (PR) is thin, the photoresist (PR) may be damaged by the plasma (PLM) and the first conductive layer (CON1) may be exposed.

[0218] Therefore, an unwanted portion of the first conductive layer (CON1) may be removed. For example, the photoresist (PR) placed on the top edge of the insulating layer (INS') may be damaged, causing the portion of the first conductive layer (CON1) placed on the top edge of the insulating layer (INS') to be removed. In this case, as illustrated in FIG. 32, the second connecting line (CNL2) formed on the insulating layer (INS') may be short-circuited on the top edge of the insulating layer (INS'). That is, the crack detection unit (CDT) may be damaged.

[0219] For example, a second connection line (CNL2) has been described, but the same problem may occur in connection parts (CP) and extension lines (EXL) that extend through a single step of the insulation layer (INS').

[0220] As shown in FIG. 31, the thickness of the photoresist (PR) may be greater at the edge of the insulating layer (INS) having at least two steps, as shown in FIG. 27, than at the edge of the insulating layer (INS) having a single step structure. The photoresist (PR) shown in FIG. 27 may have a thickness sufficient to adequately protect the first conductive layer (CON1) from the plasma (PLM).

[0221] Accordingly, as illustrated in FIG. 30, the second connection line (CNL2) formed by the first conductive layer (CON1) may not be short-circuited on the upper corner of the insulating layer (INS). That is, damage to the crack detection unit (CDT) can be prevented.

[0222] Referring to FIGS. 22 and FIGS. 25, when a capping layer (CPL) is formed, a photoresist (PR) is provided on the area for forming the capping layer (CPL), so that the first conductive layer (CON1) for forming the capping layer (CPL) can be protected. However, when the capping layer (CPL) is not formed, the photoresist (PR) in FIG. 25 may not be used.

[0223] Referring to FIG. 33, if a capping layer (CPL) is not formed on the first insulating layer (T_INS1), the photoresist (PR) is not used, so the first conductive layer (CON1) may be exposed. The first conductive layer (CON1) can be removed by plasma (PLM).

[0224] If the edge of the insulating layer (INS') has a single step, the portion of the first insulating layer (T_INS1) and the portion of the first conductive layer (CON1) provided at the bottom edge of the insulating layer (INS') may have a smaller thickness than the surrounding area. For example, during the deposition process for forming the first insulating layer (T_INS1) and the first conductive layer (CON1), the deposition material may not be sufficiently provided at the bottom edge of the insulating layer (INS').

[0225] Referring to FIGS. 33 and 34, a portion of the first insulating layer (T_INS1) and a portion of the first conductive layer (CON1) provided at the bottom edge of the insulating layer (INS') may be damaged by plasma (PLM) provided in various directions. Thus, as shown in FIG. 34, the bottom edge of the insulating layer (INS') may be exposed. During the cleaning process, a cleaning solution (CLN) may be provided at the bottom edge of the insulating layer (INS').

[0226] Referring to FIG. 35, during the cleaning process, the bottom edge of the insulating layer (INS') can be peeled off by the cleaning solution (CLN) provided at the bottom edge of the insulating layer (INS'). As a result, a defective indicator device can be manufactured.

[0227] Referring to FIG. 25, a photoresist (PR) may be disposed on a portion of the first conductive layer (CON1) for forming a capping layer (CPL). A portion of the first insulating layer (T_INS1) and a portion of the first conductive layer (CON1) provided at the bottom edge of the insulating layer (INS) may be protected by the photoresist (PR) so as not to be damaged by plasma (PLM).

[0228] Referring to FIG. 28, since a capping layer (CPL) is formed on the insulating layer (INS) to cover the edge of the insulating layer (INS), the cleaning solution (CLN) can be blocked by the capping layer (CPL) during the cleaning process. Therefore, the lower edge of the insulating layer (INS) may not peel off.

[0229] According to an embodiment of the present invention, defects in the display device (DD) are reduced, and thus the reliability of the display device (DD) can be improved.

[0230] Although the invention has been described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Furthermore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the invention, and all technical spirits within the scope of the following claims and equivalents should be interpreted as being included within the scope of the rights of the present invention. Explanation of the symbols

[0231] DD: Display device DP: Display panel ISP: Input sensing unit SE1, SE2: First and second sensing electrodes SP1, SP2: 1st and 2nd detection units CP: Connection unit BP: Branching section CDT: Crack detection section HO: Hole HA: Hole area CDP: Crack detection pattern CDL: Crack detection line CT1, CT2: 1st and 2nd connection patterns EXL: Extension line CNL1, CNL2: 1st and 2nd connecting lines EXL1, EXL2: 1st and 2nd extension lines CDL1, CDL2: 1st and 2nd crack detection lines DPT1, DPT2: 1st and 2nd dummy patterns GDR: Guard ring

Claims

Claim 1 A display panel comprising a hole area, a display area around the hole area, and a non-display area around the display area; an insulating layer disposed in the hole area; a plurality of sensing electrodes disposed on the display area; a crack detection pattern disposed on the insulating layer in the hole area; a crack detection line disposed on the non-display area; a connection pattern disposed on the display area, insulated from the sensing electrodes, and connected to the crack detection pattern and the crack detection line; and a connection line extending from the connection pattern to the hole area and connected to the crack detection pattern, wherein the border of the insulating layer disposed at the boundary between the display area and the hole area has at least two steps, and a portion of the connection line is disposed to overlap the at least two steps of the insulating layer, and on the at least two steps of the insulating layer, the display device has at least two steps of the insulating layer corresponding to the at least two steps of the insulating layer. Claim 2 In claim 1, the crack detection pattern comprises one end and the other end and is a display device surrounding a hole defined in the hole area. Claim 3 In claim 2, the connection pattern comprises: a first connection pattern disposed on the same layer as the crack detection pattern and connected to one end of the crack detection pattern; and a second connection pattern disposed on a different layer from the crack detection pattern and connected to the other end of the crack detection pattern, and the crack detection line comprises: a first crack detection line extended from the first connection pattern; and a second crack detection line extended from the second connection pattern. Claim 4 A display device according to claim 3, further comprising a capping layer disposed on the insulating layer to cover the edge of the insulating layer spaced apart from the crack detection pattern. Claim 5 In claim 4, the capping layer is a display device comprising a conductive material. Claim 6 In claim 4, the capping layer is a display device disposed on the same layer as the second connection pattern. Claim 7 A display device according to claim 4, further comprising an extension line extending from one end of the crack detection pattern toward the first connection pattern, wherein the connection line comprises: a first connection line that is disposed on the same layer as the second connection pattern and connects the first connection pattern and the extension line; and a second connection line that extends from the second connection pattern toward the hole area and is connected to the other end of the crack detection pattern. Claim 8 In claim 7, the capping layer is a display device spaced apart from the second connection line. Claim 9 In claim 8, the capping layer is a display device spaced apart from the second connecting line by a distance greater than 0 and less than 15 micrometers. Claim 10 In claim 7, the sensing electrodes comprise: a plurality of first sensing portions arranged in a first direction; a plurality of first dummy patterns disposed in a plurality of first openings defined in each of the first sensing portions; a plurality of connecting portions disposed between the first sensing portions and connecting the first sensing portions; a plurality of second sensing portions arranged in a second direction intersecting the first direction; and a plurality of branching portions disposed between the second sensing portions, formed integrally with the second sensing portions, and extended to intersect while being insulated from the connecting portions. Claim 11 A display device according to claim 10, further comprising a plurality of second dummy patterns disposed in a plurality of second openings defined in each of the second sensing parts. Claim 12 In claim 10, the first connecting line and the second connecting line are a display device that extends to intersect and is insulated from each other by a branching section disposed between the hole area and the non-display area among the branching sections. Claim 13 A display device according to claim 10, wherein the first sensing parts, the branching parts, and the second sensing parts are disposed on the same layer as the crack sensing pattern, and the connecting parts are disposed on the same layer as the second connecting pattern. Claim 14 In claim 10, the first connection pattern and the second connection pattern are a display device disposed respectively in a first sub-opening opened toward the non-display area and a second sub-opening opened toward the non-display area among the first openings disposed between the hole area and the non-display area. Claim 15 A display device according to claim 10, further comprising: a first insulating layer disposed on the display area and extending onto the insulating layer; and a second insulating layer disposed on the first insulating layer, wherein the crack detection pattern is disposed on the second insulating layer, the second connection pattern is disposed on the first insulating layer, and the second insulating layer is disposed on the first insulating layer to cover the second connection pattern. Claim 16 In claim 3, the display device further comprises a guard ring line disposed between the first and second crack detection lines and the display area, wherein the guard ring line is disposed on the same layer as the second connection pattern. Claim 17 A display device according to claim 16, further comprising: a first extension line extending from the first connection pattern to the first crack detection line and disposed on the non-display area; and a second extension line extending from the second connection pattern to the second crack detection line and disposed on the non-display area, wherein the guard ring line does not overlap with the first extension line and the second extension line. Claim 18 In claim 1, the crack detection pattern, the crack detection line, and the connection pattern are a display device comprising a conductive material. Claim 19 A display panel comprising a first region, a second region surrounding the first region, and a third region surrounding the second region; an insulating layer disposed in the first region; a plurality of sensing electrodes disposed on the second region; and a crack detection unit disposed on the insulating layer in the first region and insulated from the sensing electrodes and extending to the second region and the third region, wherein the crack detection unit comprises: a crack detection pattern disposed on the insulating layer in the first region; a crack detection line disposed on the third region; and a connection pattern disposed on the second region, insulated from the sensing electrodes, and connected to the crack detection pattern and the crack detection line. A display device comprising a connection line extending from the connection pattern to the first region and connected to the crack detection pattern, wherein the edge of the insulating layer disposed at the boundary between the first region and the second region has at least two steps, the portion of the connection line is disposed to overlap with the at least two steps of the insulating layer, and on the at least two steps of the insulating layer, the display device has at least two steps of the insulating layer corresponding to the at least two steps of the insulating layer. Claim 20 A display device according to claim 19, further comprising a capping layer disposed on the insulating layer to cover the boundary of the insulating layer. Claim 21 In claim 19, a display device further comprising a guard ring line disposed on the third region, wherein the guard ring line does not overlap with the crack detection part. Claim 22 A display panel comprising: a first region, a second region surrounding the first region, and a third region surrounding the second region; an insulating layer disposed in the first region; a plurality of sensing electrodes disposed on the second region; a crack sensing pattern disposed on the insulating layer in the first region; a crack sensing line disposed on the third region; a connecting pattern disposed on the second region, insulated from the sensing electrodes, and connecting the crack sensing pattern and the crack sensing line; and a capping layer disposed on the insulating layer to cover the boundary of the insulating layer, wherein the edge of the insulating layer disposed at the boundary between the first region and the second region has a step structure of at least two steps, and the capping layer is disposed to overlap the step structure of the insulating layer of at least two steps, and on the step structure of the insulating layer of at least two steps, the display device has a step structure of at least two steps corresponding to the step structure of the insulating layer of at least two steps.

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