Display device

Abstract

A display device is provided. The display device includes a first voltage line, first and second data lines, and a vertical voltage line, a horizontal voltage line, a second voltage line, first and second horizontal connection lines, first to fourth alignment lines, and first and second light-emitting elements, wherein the first voltage line, the horizontal voltage line, and the first alignment line are electrically connected, the first horizontal connection line and the second alignment line are electrically connected, the second horizontal connection line and the third alignment line are electrically connected, and the vertical voltage line, the second voltage line, and the fourth alignment line are electrically connected.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. For example, display devices are being applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions. Display devices may be flat panel display devices such as Liquid Crystal Display Devices, Field Emission Display Devices, and Organic Light Emitting Display Devices. Among these flat panel display devices, light-emitting displays include light-emitting elements in which each pixel of the display panel can emit light independently, thereby enabling the display of images without a backlight unit that provides light to the display panel. The light-emitting elements may be organic light-emitting diodes that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a display device that improves display quality by preventing dark spots through the even distribution of a plurality of light-emitting elements, and ensures redundant connections and prevents voltage drop by electrically connecting all alignment lines to high-potential or low-potential lines having a mesh structure.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device of one embodiment for solving the above problem comprises a first voltage line, first and second data lines, and a vertical voltage line disposed on a substrate and extending parallel in a first direction; a horizontal voltage line, a second voltage line, a first and second horizontal connection line disposed on the first voltage line and extending parallel in a second direction intersecting the first direction; first to fourth alignment lines disposed on the horizontal voltage line and extending parallel in the first direction; a first light-emitting element aligned between the first and second alignment lines; and a second light-emitting element aligned between the third and fourth alignment lines. The first voltage line, the horizontal voltage line, and the first alignment line are electrically connected, the first horizontal connection line and the second alignment line are electrically connected, the second horizontal connection line and the third alignment line are electrically connected, and the vertical voltage line, the second voltage line, and the fourth alignment line are electrically connected.

[0006] The above display device further includes a first upper voltage line extending in the first direction and disposed on the first to fourth alignment lines, and a second upper voltage line extending in the second direction in the same layer as the first upper voltage line, and the first and second upper voltage lines may be formed integrally.

[0007] The first and second upper voltage lines can be electrically connected to the second voltage line and the first and second horizontal connection lines.

[0008] The first upper voltage line can be electrically connected to the second voltage line through a first lower connecting electrode disposed in the layer between the second voltage line and the vertical voltage line.

[0009] In the alignment process of the first and second light-emitting elements, the first horizontal connection line and the second alignment line are electrically connected to the first data line, and the second horizontal connection line and the third alignment line can be electrically connected to the second data line.

[0010] In the first alignment process of the first and second light-emitting elements, the first and second alignment lines receive a first alignment signal, and the third and fourth alignment lines can receive a second alignment signal different from the first alignment signal.

[0011] In the secondary alignment process of the first and second light-emitting elements, the second and third alignment lines receive the first alignment signal, and the first and fourth alignment lines receive the second alignment signal.

[0012] When the alignment of the first and second light-emitting elements is completed, the first horizontal connection line and the first data line can be electrically insulated, and the second horizontal connection line and the second data line can be electrically insulated.

[0013] The above display device may further include an initialization voltage line extending parallel to the first data line in the same layer, a first transistor connected between the first voltage line and the first light-emitting element, a second transistor connected between the first data line and the gate electrode of the first transistor, and a third transistor connected between the initialization voltage line and the first light-emitting element.

[0014] The above display device may further include a first contact electrode connected between the first transistor and the first light-emitting element, a second contact electrode connected between the first light-emitting element and the second light-emitting element, and a third contact electrode connected between the second light-emitting element and the fourth alignment line, which are disposed on the first to fourth alignment lines.

[0015] A display device of one embodiment for solving the above problem comprises: a first voltage line, a data line, and a vertical voltage line disposed on a substrate and extending parallel in a first direction; a horizontal voltage line, a second voltage line, and a horizontal connection line disposed on the first voltage line and extending parallel in a second direction intersecting the first direction; first to third alignment lines disposed on the horizontal voltage line and extending parallel in the first direction; an alignment electrode spaced apart and surrounded by the second alignment line; a first light-emitting element aligned between the first and second alignment lines; and a second light-emitting element aligned between the second and third alignment lines. The first voltage line, the horizontal voltage line, and the third alignment line are electrically connected, the horizontal connection line and the second alignment line are electrically connected, and the vertical voltage line, the second voltage line, and the alignment electrode are electrically connected.

[0016] The above display device further includes a plurality of pixels each comprising the first to third alignment lines, and one of the plurality of pixels' third alignment line may be integrally formed with the first alignment line of another pixel adjacent in the second direction through an alignment connection line extending in the second direction.

[0017] The above display device further includes a first upper voltage line extending in the first direction and disposed on the first to third alignment lines, and a second upper voltage line extending in the second direction in the same layer as the first upper voltage line, and the first and second upper voltage lines may be formed integrally.

[0018] The first and second upper voltage lines can be electrically connected to the second voltage line and the horizontal connection line.

[0019] In the alignment process of the first and second light-emitting elements, the horizontal connection line and the second alignment line can be electrically connected to the data line.

[0020] In the first alignment process of the first and second light-emitting elements, the alignment electrode receives a first alignment signal, and the first to third alignment lines can receive a second alignment signal different from the first alignment signal.

[0021] In the secondary alignment process of the first and second light-emitting elements, the second alignment line receives the first alignment signal, and the first and third alignment lines can receive the second alignment signal.

[0022] When the alignment of the first and second light-emitting elements is completed, the horizontal connection line and the data line can be electrically insulated.

[0023] The display device may further include an initialization voltage line extending parallel to the data line in the same layer, a first transistor connected between the first voltage line and the first light-emitting element, a second transistor connected between the data line and the gate electrode of the first transistor, and a third transistor connected between the initialization voltage line and the first light-emitting element.

[0024] The above display device may further include a first contact electrode connected between the first transistor and the first light-emitting element, a second contact electrode connected between the first light-emitting element and the second light-emitting element, and a third contact electrode connected between the second light-emitting element and the second alignment line, which are disposed on the first to third alignment lines.

[0025] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0026] According to the display device according to the embodiments, by aligning a plurality of light-emitting elements through a first alignment process and a second alignment process, a plurality of light-emitting elements can be evenly distributed to prevent dark spots, and by electrically connecting all alignment lines to a high potential line or a low potential line having a mesh structure, redundant connections can be secured and voltage drop can be prevented.

[0027] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0028] FIG. 1 is a plan view showing a display device according to one embodiment. FIG. 2 is a plan view showing the contact portions of a vertical gate line and a horizontal gate line in a display device according to one embodiment. Figure 3 is an enlarged view of area A1 in Figure 1. FIG. 4 is a drawing showing pixels and lines of a display device according to one embodiment. FIG. 5 is a circuit diagram showing a pixel of a display device according to one embodiment. FIGS. 6 and FIGS. 7 are plan views showing a thin-film transistor layer of a display device according to one embodiment. Figure 8 is a cross-sectional view taken along line I-I' of Figures 6 and 7. FIG. 9 is a plan view showing the connection relationship between the alignment line and the thin-film transistor layer before alignment of the light-emitting element in a display device according to one embodiment. FIG. 10 is a diagram showing the first alignment process of a plurality of light-emitting elements in a display device according to one embodiment. FIG. 11 is a diagram showing a secondary alignment process of a plurality of light-emitting elements in a display device according to one embodiment. FIG. 12 is a plan view showing the connection relationship between the alignment line and the thin-film transistor layer after alignment of the light-emitting element in a display device according to one embodiment. FIG. 13 is a plan view showing a light-emitting element layer of a display device according to one embodiment. Figure 14 is a cross-sectional view taken along line II-II' of Figure 13. FIG. 15 is a plan view showing the connection relationship between the alignment line and the thin-film transistor layer before alignment of the light-emitting element in a display device according to another embodiment. FIG. 16 is a diagram showing the first alignment process of a plurality of light-emitting elements in a display device according to another embodiment. FIG. 17 is a diagram showing the secondary alignment process of a plurality of light-emitting elements in a display device according to another embodiment. FIG. 18 is a plan view showing the connection relationship between the alignment line and the thin-film transistor layer after alignment of the light-emitting element in a display device according to another embodiment. FIG. 19 is a plan view showing a light-emitting element layer of a display device according to another embodiment. Specific details for implementing the invention

[0029] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0030] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0031] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0032] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0033] Specific embodiments will be described below with reference to the attached drawings.

[0034] FIG. 1 is a plan view showing a display device according to one embodiment.

[0035] In this specification, “top,” “top,” and “top surface” refer to the upward direction relative to the display device, i.e., the Z-axis direction, and “bottom,” “bottom,” and “bottom surface” refer to the downward direction relative to the display device, i.e., the direction opposite to the Z-axis. Additionally, “left,” “right,” “up,” and “down” refer to the direction when viewing the display device from a planar perspective. For example, “left” refers to the direction opposite to the X-axis, “right” refers to the X-axis direction, “up” refers to the Y-axis direction, and “down” refers to the direction opposite to the Y-axis.

[0036] Referring to FIG. 1, the display device is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, PMPs (Portable Multimedia Players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0037] The display device may include a display panel (100), a flexible film (210), a display driving unit (220), a circuit board (230), a timing control unit (240), and a power supply unit (250).

[0038] The display panel (100) may be formed in a rectangular shape on a plane. For example, the display panel (100) may have a rectangular planar shape having a long side in the first direction (X-axis direction) and a short side in the second direction (Y-axis direction). The corner where the long side in the first direction (X-axis direction) and the short side in the second direction (Y-axis direction) meet may be formed at a right angle or rounded to have a predetermined curvature. The planar shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. For example, the display panel (100) may be formed flat, but is not limited thereto. As another example, the display panel (100) may be formed to be bent with a predetermined curvature.

[0039] The display panel (100) may include a display area (DA) and a non-display area (NDA).

[0040] The display area (DA) is an area for displaying images and can be defined as the central area of ​​the display panel (100). The display area (DA) may include pixels (SP), a gate line (GL), a data line (DL), an initialization voltage line (VIL), a first voltage line (VDL), a horizontal voltage line (HVDL), a vertical voltage line (VVSL), and a second voltage line (VSL). Pixels (SP) may be formed in each pixel area that intersects the data lines (DL) and the gate lines (GL). The pixels (SP) may include first to third pixels (SP1, SP2, SP3). Each of the first to third pixels (SP1, SP2, SP3) may be connected to one horizontal gate line (HGL) and one data line (DL). Each of the first to third pixels (SP1, SP2, SP3) may be defined as a minimum unit area that outputs light.

[0041] The first pixel (SP1) can emit light of a first color or red light, the second pixel (SP2) can emit light of a second color or green light, and the third pixel (SP3) can emit light of a third color or blue light. The pixel circuit of the first pixel (SP1), the pixel circuit of the third pixel (SP3), and the pixel circuit of the second pixel (SP2) may be arranged in opposite directions to the second direction (Y-axis direction), but the order of the pixel circuits is not limited thereto.

[0042] The gate line (GL) may include a vertical gate line (VGL), a horizontal gate line (HGL), and an auxiliary gate line (BGL).

[0043] The vertical gate lines (VGL) are connected to the display drive unit (220) and can be extended in a second direction (Y-axis direction) and spaced apart from each other in a first direction (X-axis direction). The vertical gate lines (VGL) can be arranged parallel to the data line (DL). The horizontal gate lines (HGL) can be extended in a first direction (X-axis direction) and spaced apart from each other in a second direction (Y-axis direction). Each of the horizontal gate lines (HGL) can intersect with the vertical gate lines (VGL). For example, one horizontal gate line (HGL) can be connected to one of the vertical gate lines (VGL) through a contact unit (MDC). The contact unit (MDC) may correspond to the part where the horizontal gate line (HGL) is inserted into a contact hole and contacts the vertical gate line (VGL). The auxiliary gate line (BGL) extends from the horizontal gate line (HGL) and can supply gate signals to the first to third pixels (SP1, SP2, SP3).

[0044] Data lines (DL) may be extended in a second direction (Y-axis direction) and spaced apart from each other in a first direction (X-axis direction). Data lines (DL) may include first to third data lines (DL1, DL2, DL3). Each of the first to third data lines (DL1, DL2, DL3) may supply data voltage to each of the first to third pixels (SP1, SP2, SP3).

[0045] The initialization voltage lines (VIL) may extend in a second direction (Y-axis direction) and be spaced apart from each other in a first direction (X-axis direction). The initialization voltage lines (VIL) may supply an initialization voltage received from the display driver (220) to the pixel circuits of each of the first to third pixels (SP1, SP2, SP3). The initialization voltage lines (VIL) may receive a sensing signal from the pixel circuits of each of the first to third pixels (SP1, SP2, SP3) and supply it to the display driver (220).

[0046] The first voltage lines (VDL) extend in the second direction (Y-axis direction) and can be spaced apart from each other in the first direction (X-axis direction). The first voltage lines (VDL) can supply a driving voltage or high potential voltage received from the power supply unit (250) to the first to third pixels (SP1, SP2, SP3).

[0047] Horizontal voltage lines (HVDL) extend in a first direction (X-axis direction) and can be spaced apart from each other in a second direction (Y-axis direction). The horizontal voltage lines (HVDL) can be connected to the first voltage line (VDL). The horizontal voltage lines (HVDL) can supply a driving voltage or a high potential voltage to the first voltage line (VDL).

[0048] The vertical voltage lines (VVSL) extend in a second direction (Y-axis direction) and can be spaced apart from each other in a first direction (X-axis direction). The vertical voltage lines (VVSL) can be connected to the second voltage lines (VSL). The vertical voltage lines (VVSL) can supply a low potential voltage received from the power supply unit (250) to the second voltage lines (VSL).

[0049] The second voltage lines (VSL) extend in the first direction (X-axis direction) and can be spaced apart from each other in the second direction (Y-axis direction). The second voltage lines (VSL) can supply low potential voltage to the first to third pixels (SP1, SP2, SP3).

[0050] The connection relationship of the pixel (SP), gate line (GL), data line (DL), initialization voltage line (VIL), first voltage line (VDL), and second voltage line (VSL) can be changed according to the number and arrangement of the pixel (SP).

[0051] The non-display area (NDA) may be defined as the remaining area of ​​the display panel (100) excluding the display area (DA). For example, the non-display area (NDA) may include a vertical gate line (VGL), a data line (DL), an initialization voltage line (VIL), a first voltage line (VDL), and fan-out lines connecting the vertical voltage line (VVSL) and the display driver (220), and a pad portion (not shown) connected to a flexible film (210).

[0052] Input terminals provided on one side of the flexible film (210) can be attached to the circuit board (230) by a film attachment process, and output terminals provided on the other side of the flexible film (210) can be attached to the pad portion by a film attachment process. For example, the flexible film (210) may be a flexible film that can be bent, such as a tape carrier package or a chip on film. The flexible film (210) may be bent to the bottom of the display panel (100) to reduce the bezel area of ​​the display device.

[0053] The display driver (220) can be mounted on a flexible film (210). For example, the display driver (220) can be implemented as an integrated circuit (IC). The display driver (220) receives digital video data and data control signals from the timing control unit (240), and converts the digital video data into an analog data voltage according to the data control signal and supplies it to the data lines (DL) through the fan-out lines. The display driver (220) can generate a gate signal according to the gate control signal supplied from the timing control unit (240) and supply it sequentially to the vertical gate lines (VGL) according to a set order. Thus, the display driver (220) can simultaneously perform the roles of a data driver and a gate driver. The display device (10) can minimize the size of the left, right, and upper sides of the non-display area (NDA) by including the display driver (220) positioned below the non-display area (NDA).

[0054] The circuit board (230) supports the timing control unit (240) and the power supply unit (250) and can supply signals and power to the display driving unit (220). For example, the circuit board (230) can supply signals supplied from the timing control unit (240) and power voltage supplied from the power supply unit (250) to the display driving unit (220) to display an image at each pixel. To this end, signal lines and power lines may be provided on the circuit board (230).

[0055] The timing control unit (240) is mounted on the circuit board (230) and can receive image data and timing synchronization signals supplied from a display driving system or a graphics device through a user connector provided on the circuit board (230). The timing control unit (240) can generate digital video data by aligning the image data to suit the pixel arrangement structure based on the timing synchronization signal, and can supply the generated digital video data to the display driving unit (220). The timing control unit (240) can generate a data control signal and a gate control signal based on the timing synchronization signal. The timing control unit (240) can control the supply timing of the data voltage of the display driving unit (220) based on the data control signal, and can control the supply timing of the gate signal of the display driving unit (220) based on the gate control signal.

[0056] The power supply unit (250) is positioned on the circuit board (230) and can supply power voltage to the display driving unit (220) and the display panel (100). For example, the power supply unit (250) can generate a driving voltage or a high potential voltage and supply it to the first voltage line (VDL), generate a low potential voltage and supply it to the vertical voltage line (VVSL), and generate an initialization voltage and supply it to the initialization voltage line (VIL).

[0057] FIG. 2 is a plan view showing the contact portions of a vertical gate line and a horizontal gate line in a display device according to one embodiment.

[0058] Referring to FIG. 2, the display area (DA) may include first to third display areas (DA1, DA2, DA3).

[0059] Each horizontal gate line (HGL) may intersect with vertical gate lines (VGL). Horizontal gate lines (HGL) may intersect with vertical gate lines (VGL) at contact portions (MDC) and non-contact portions (NMC). For example, one horizontal gate line (HGL) may be connected to one of the vertical gate lines (VGL) through a contact portion (MDC). One horizontal gate line (HGL) may be insulated from the remaining vertical gate lines (VGL) at a non-contact portion (NMC).

[0060] The contact portion (MDC) of the first display area (DA1) may be positioned on an extension line connecting the upper left corner of the first display area (DA1) to the lower right corner of the first display area (DA1). The contact portion (MDC) of the second display area (DA2) may be positioned on an extension line connecting the upper left corner of the second display area (DA2) to the lower right corner of the second display area (DA2). The contact portion (MDC) of the third display area (DA3) may be positioned on an extension line connecting the upper left corner of the third display area (DA3) to the lower right corner of the third display area (DA3). Accordingly, the contact portions (MDC) may be arranged along a diagonal direction between the first direction (X-axis direction) and the opposite direction of the second direction (Y-axis direction) in each of the first to third display areas (DA1, DA2, DA3).

[0061] The display device (10) may include a display driver (220) that performs the roles of a data driver and a gate driver. Accordingly, the data line (DL) receives a data voltage from the display driver (220) positioned below the non-display area (NDA), and the vertical gate line (VGL) receives a gate signal from the display driver (220) positioned below the non-display area (NDA), thereby allowing the display device (10) to minimize the size of the left, right, and upper sides of the non-display area (NDA).

[0062] Figure 3 is an enlarged view of area A1 in Figure 1.

[0063] Referring to FIG. 3, the non-display area (NDA) may include a pad area (PDA) and a fan-out area (FOA). The pad area (PDA) and the fan-out area (FOA) may be positioned on one side of the non-display area (NDA). The pad area (PDA) may include a plurality of pad portions connected to a flexible film (210). The flexible film (210) may mount a display driving unit (220) and may be attached to the pad portions of the pad area (PDA). The flexible film (210) may include a signal line that electrically connects the display driving unit (220) and the pad portions.

[0064] A fan-out area (FOA) may be positioned between a pad area (PDA) and a display area (DA). The fan-out area (FOA) may include a plurality of fan-out lines (FOL). The fan-out lines (FOL) may electrically connect a plurality of data lines (DL) and a display driver (220), and may electrically connect an initialization voltage line (VIL) and a display driver (220). The fan-out lines (FOL) may be positioned on a first metal layer on a substrate in the fan-out area (FOA). For example, the plurality of fan-out lines (FOL) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0065] The first voltage pattern (VDP) may be positioned between the pad area (PDA) and the display area (DA). The first voltage pattern (VDP) may be positioned on the left fan-out lines (FOL) among the fan-out lines (FOL) in the fan-out area (FOA). The first voltage pattern (VDP) may be positioned on a second metal layer on a first metal layer, or on a third metal layer on a second metal layer, but is not limited thereto. For example, the first voltage pattern (VDP) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0066] The first voltage pattern (VDP) may include a first lead portion (LD1), a first plate portion (PLT1), and a first branch portion (BRC1). The first lead portion (LD1) may extend from the pad area (PDA) to the first plate portion (PLT1). The first lead portion (LD1) may be connected to the lower left side of the first plate portion (PLT1).

[0067] The first plate portion (PLT1) can overlap with the fan-out lines (FOL) and may have a plate shape consisting of a long side and a short side. By including the first plate portion (PLT1), the first voltage pattern (VDP) can reduce the size of the fan-out area (FOA) while reducing the internal resistance of the first voltage pattern (VDP). By including the first plate portion (PLT1), the first voltage pattern (VDP) can reduce signal interference caused by the coupling capacitance of the fan-out lines (FOL).

[0068] The first branch section (BRC1) may branch off from the first plate section (PLT1) and extend to the display area (DA). The first branch sections (BRC1) may extend in the second direction (Y-axis direction) and be spaced apart from each other in the first direction (X-axis direction). The first branch sections (BRC1) may be electrically connected to the first voltage line (VDL) of the display area (DA). Thus, the first voltage pattern (VDP) may supply a driving voltage or high potential voltage received from the power supply section (250) to the first voltage line (VDL).

[0069] A second voltage pattern (VSP) may be positioned between a pad area (PDA) and a display area (DA). A second voltage pattern (VSP) may be positioned on the right fan-out lines (FOL) among the fan-out lines (FOL) in a fan-out area (FOA). The first and second voltage patterns (VDP, VSP) may have symmetrical shapes with respect to each other, but are not limited thereto. A second voltage pattern (VSP) may be formed of the same material in the same layer as a first voltage pattern (VDP). Accordingly, a fan-out area (FOA) may include a fan-out line (FOL) composed of two layers, and first and second voltage patterns (VDP, VSP).

[0070] The second voltage pattern (VSP) may include a second lead portion (LD2), a second plate portion (PLT2), and a second branch portion (BRC2). The second lead portion (LD2) may extend from the pad area (PDA) to the second plate portion (PLT2). The second lead portion (LD2) may be connected to the lower right side of the second plate portion (PLT2).

[0071] The second plate portion (PLT2) can overlap with the fan-out lines (FOL) and may have a plate shape consisting of a long side and a short side. By including the second plate portion (PLT2), the second voltage pattern (VSP) can reduce the size of the fan-out area (FOA) while reducing the internal resistance of the second voltage pattern (VSP). By including the second plate portion (PLT2), the second voltage pattern (VSP) can reduce signal interference caused by the coupling capacitance of the fan-out lines (FOL).

[0072] The second branch (BRC2) may branch off from the second plate (PLT2) and extend to the display area (DA). The second branch (BRC2) may extend in the second direction (Y-axis direction) and be spaced apart from each other in the second direction (X-axis direction). The second branch (BRC2) may be electrically connected to the vertical voltage line (VVSL) of the display area (DA). Thus, the second voltage pattern (VSP) can supply a low potential voltage received from the power supply (250) to the vertical voltage line (VVSL).

[0073] FIG. 4 is a drawing showing pixels and lines of a display device according to one embodiment.

[0074] Referring to FIG. 4, the pixel (SP) may include first to third pixels (SP1, SP2, SP3). The pixel circuit of the first pixel (SP1), the pixel circuit of the second pixel (SP2), and the pixel circuit of the third pixel (SP3) may be arranged in opposite directions to the second direction (Y-axis direction), but the order of the pixel circuits is not limited thereto.

[0075] Each of the first to third pixels (SP1, SP2, SP3) can be connected to a first voltage line (VDL), an initialization voltage line (VIL), a gate line (GL), and a data line (DL).

[0076] The first voltage line (VDL) may be extended in a second direction (Y-axis direction). The first voltage line (VDL) may be positioned to the left of the pixel circuit of the first to third pixels (SP1, SP2, SP3). The first voltage line (VDL) may supply a driving voltage or a high potential voltage to each transistor of the first to third pixels (SP1, SP2, SP3).

[0077] The horizontal voltage line (HVDL) may extend in a first direction (X-axis direction). The horizontal voltage line (HVDL) may be placed below the pixel circuit of a third pixel (SP3) located in the k+1 row (ROWk+1, where k is a positive integer). The horizontal voltage line (HVDL) or the second voltage line (VSL) may be placed below the pixel circuit of the third pixel (SP3). The horizontal voltage line (HVDL) may be connected to the first voltage line (VDL). The horizontal voltage line (HVDL) may receive a driving voltage or a high potential voltage from the first voltage line (VDL).

[0078] The initialization voltage line (VIL) may be extended in a second direction (Y-axis direction). The initialization voltage line (VIL) may be positioned to the right of the auxiliary gate line (BGL). The initialization voltage line (VIL) may be positioned between the auxiliary gate line (BGL) and the data line (DL). The initialization voltage line (VIL) may supply an initialization voltage to each pixel circuit of the first to third pixels (SP1, SP2, SP3). The initialization voltage line (VIL) may receive a sensing signal from each pixel circuit of the first to third pixels (SP1, SP2, SP3) and supply it to the display driver (220).

[0079] The gate line (GL) may include a vertical gate line (VGL), a horizontal gate line (HGL), and an auxiliary gate line (BGL).

[0080] The vertical gate lines (VGL) can be extended in a second direction (Y-axis direction). At least one vertical gate line (VGL) can be placed between adjacent pixels (SP). The vertical gate line (VGL) can be connected between the display driver (220) and the horizontal gate line (HGL). Each of the vertical gate lines (VGL) can intersect the horizontal gate lines (HGL). The vertical gate line (VGL) can supply a gate signal received from the display driver (220) to the horizontal gate line (HGL).

[0081] For example, the nth vertical gate line (VGLn, where n is a positive integer) and the n+1th vertical gate line (VGLn+1) may be placed between a pixel (SP) placed in the jth column (COLj, where j is a positive integer) and a pixel (SP) placed in the j+1th column (COLj+1). The vertical gate lines (VGL) may be placed side by side between a data line (DL) connected to pixels (SP) placed on the left and a first voltage line (VDL) connected to pixels (SP) placed on the right. The nth and n+1th vertical gate lines (VGLn, VGLn+1) may be placed between a data line (DL) connected to a pixel (SP) placed in the jth column (COLj) and a first voltage line (VDL) connected to a pixel (SP) placed in the j+1th column (COLj+1). The nth vertical gate line (VGLn) can be connected to the nth horizontal gate line (HGLn) through a contact portion (MDC) and can be isolated from the remaining horizontal gate lines (HGL). The n+1th vertical gate line (VGLn+1) can be connected to the n+1th horizontal gate line (HGLn+1) through a contact portion (MDC) and can be isolated from the remaining horizontal gate lines (HGL).

[0082] At least one vertical gate line (VGL) may be positioned to the left of the pixel (SP). For example, the n+2 vertical gate line (VGLn+2) and the n+3 vertical gate line (VGLn+3) may be positioned to the left of the pixel (SP) located in column j (COLj). The n+2 and n+3 vertical gate lines (VGLn+2, VGLn+3) may be positioned to the left of the first voltage line (VDL) connected to the pixel (SP) located in column j (COLj).

[0083] The horizontal gate line (HGL) can be extended in a first direction (X-axis direction). The horizontal gate line (HGL) can be positioned above the pixel circuit of the first pixel (SP1). The horizontal gate line (HGL) can be connected between the vertical gate line (VGL) and the auxiliary gate line (BGL). The horizontal gate line (HGL) can supply a gate signal received from the vertical gate line (VGL) to the auxiliary gate line (BGL).

[0084] For example, the nth horizontal gate line (HGLn) may be placed above the pixel circuit of the first pixel (SP1) located in the kth row (ROWk, where k is a positive integer). The nth horizontal gate line (HGLn) may be connected to the nth vertical gate line (VGLn) through a contact part (MDC) and may be insulated from the remaining vertical gate lines (VGL). The n+1th horizontal gate line (HGLn+1) may be placed above the pixel circuit of the first pixel (SP1) located in the k+1th row (ROWk+1). The n+1th horizontal gate line (HGLn+1) may be connected to the n+1th vertical gate line (VGLn+1) through a contact part (MDC) and may be insulated from the remaining vertical gate lines (VGL).

[0085] The auxiliary gate line (BGL) may extend from the horizontal gate line (HGL) in the opposite direction of the second direction (Y-axis direction). The auxiliary gate line (BGL) may be positioned to the right of the pixel circuits of the first to third pixels (SP1, SP2, SP3). The auxiliary gate line (BGL) may supply a gate signal received from the horizontal gate line (HGL) to the pixel circuits of the first to third pixels (SP1, SP2, SP3).

[0086] Data lines (DL) can be extended in a second direction (Y-axis direction). Data lines (DL) can supply data voltage to pixels (SP). Data lines (DL) may include first to third data lines (DL1, DL2, DL3).

[0087] The first data line (DL1) may be extended in a second direction (Y-axis direction). The first data line (DL1) may be positioned to the right of the initialization voltage line (VIL). The first data line (DL1) may supply the data voltage received from the display driver (220) to the pixel circuit of the first pixel (SP1).

[0088] The second data line (DL2) can be extended in a second direction (Y-axis direction). The second data line (DL2) can be positioned to the right of the first data line (DL1). The second data line (DL2) can supply data voltage received from the display driver (220) to the pixel circuit of the second pixel (SP2).

[0089] The third data line (DL3) can be extended in the second direction (Y-axis direction). The third data line (DL3) can be positioned to the right of the second data line (DL2). The third data line (DL3) can supply the data voltage received from the display driver (220) to the pixel circuit of the third pixel (SP3).

[0090] The vertical voltage line (VVSL) can be extended in a second direction (Y-axis direction). The vertical voltage line (VVSL) can be positioned to the right of the third data line (DL3). The vertical voltage line (VVSL) can be connected between the power supply unit (250) and the second voltage line (VSL). The vertical voltage line (VVSL) can supply a low potential voltage supplied from the power supply unit (250) to the second voltage line (VSL).

[0091] The second voltage line (VSL) may be extended in the first direction (X-axis direction). The second voltage line (VSL) may be placed below the pixel circuit of the third pixel (SP3) located in the k-th row (ROWk). The second voltage line (VSL) may be connected to the vertical voltage line (VVSL). The second voltage line (VSL) may supply the low potential voltage received from the vertical voltage line (VVSL) to the light-emitting element layer of the first to third pixels (SP1, SP2, SP3).

[0092] FIG. 5 is a circuit diagram showing a pixel of a display device according to one embodiment.

[0093] Referring to FIG. 5, each pixel (SP) can be connected to a first voltage line (VDL), a data line (DL), an initialization voltage line (VIL), an auxiliary gate line (BGL), and a second voltage line (VSL).

[0094] Each of the first to third pixels (SP1, SP2, SP3) may include the first to third transistors (ST1, ST2, ST3), the first capacitor (C1), and a plurality of light-emitting elements (ED).

[0095] The first transistor (ST1) may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor (ST1) may be connected to a first node (N1), the drain electrode may be connected to a first voltage line (VDL), and the source electrode may be connected to a second node (N2). The first transistor (ST1) may control the drain-source current (or driving current) based on the data voltage applied to the gate electrode.

[0096] The light-emitting elements (ED) may include a first light-emitting element (ED1) and a second light-emitting element (ED2). The first and second light-emitting elements (ED1, ED2) may be connected in series. The first and second light-emitting elements (ED1, ED2) may emit light upon receiving a driving current. The amount of light emitted or the brightness of the light-emitting element (ED) may be proportional to the magnitude of the driving current. The light-emitting element (ED) may be an inorganic light-emitting element including an inorganic semiconductor, but is not limited thereto.

[0097] The first electrode of the first light-emitting element (ED1) can be connected to the second node (N2), and the second electrode of the first light-emitting element (ED1) can be connected to the third node (N3). The first electrode of the first light-emitting element (ED1) can be connected to the source electrode of the first transistor (ST1), the drain electrode of the third transistor (ST3), and the second capacitor electrode of the first capacitor (C1) through the second node (N2). The second electrode of the first light-emitting element (ED1) can be connected to the first electrode of the second light-emitting element (ED2) through the third node (N3).

[0098] The first electrode of the second light-emitting element (ED2) can be connected to the third node (N3), and the second electrode of the second light-emitting element (ED2) can be connected to the second voltage line (VSL). The first electrode of the second light-emitting element (ED2) can be connected to the second electrode of the first light-emitting element (ED1) through the third node (N3).

[0099] The second transistor (ST2) can be turned on by a gate signal of the auxiliary gate line (BGL) or the gate line (GL) to electrically connect the data line (DL) and the first node (N1), which is the gate electrode of the first transistor (ST1). By turning on the second transistor (ST2) based on the gate signal, it can supply a data voltage to the first node (N1). The gate electrode of the second transistor (ST2) can be connected to the auxiliary gate line (BGL), the drain electrode can be connected to the data line (DL), and the source electrode can be connected to the first node (N1). The source electrode of the second transistor (ST2) can be connected to the gate electrode of the first transistor (ST1) and the first capacitor electrode of the first capacitor (C1) through the first node (N1).

[0100] The third transistor (ST3) can be turned on by a gate signal of the auxiliary gate line (BGL) or the gate line (GL) to electrically connect the initialization voltage line (VIL) and the second node (N2), which is the source electrode of the first transistor (ST1). By turning on the third transistor (ST3) based on the gate signal, it can supply an initialization voltage to the second node (N2). The gate electrode of the third transistor (ST3) can be connected to the auxiliary gate line (BGL), the drain electrode can be connected to the second node (N2), and the source electrode can be connected to the initialization voltage line (VIL). The drain electrode of the third transistor (ST3) can be connected to the source electrode of the first transistor (ST1), the second capacitor electrode of the first capacitor (C1), and the first electrode of the first light-emitting element (ED1) through the second node (N2).

[0101] FIGS. 6 and 7 are plan views showing a thin-film transistor layer of a display device according to one embodiment, and FIG. 8 is a cross-sectional view taken along line I-I' of FIGS. 6 and 7. FIGS. 7 is a diagram showing the same reference numerals separately.

[0102] Referring to FIGS. 6 through 8, the display area (DA) may include a pixel (SP), a first voltage line (VDL), a horizontal voltage line (HVDL), a vertical gate line (VGL), a horizontal gate line (HGL), an auxiliary gate line (BGL), an initialization voltage line (VIL), a data line (DL), a vertical voltage line (VVSL), and a second voltage line (VSL). The pixel (SP) may include first to third pixels (SP1, SP2, SP3). The pixel circuit of the first pixel (SP1), the pixel circuit of the second pixel (SP2), and the pixel circuit of the third pixel (SP3) may be arranged in the opposite direction of the second direction (Y-axis direction).

[0103] The first voltage line (VDL) can be placed on the first metal layer (MTL1) on the substrate (SUB). The first voltage line (VDL) can be placed to the left of the pixel circuit of the first to third pixels (SP1, SP2, SP3). The first voltage line (VDL) can be connected to the first connection electrode (BE1) of the third metal layer (MTL3) through the tenth contact hole (CNT10), and the first connection electrode (BE1) can be connected to the drain electrode (DE1) of the first transistor (ST1) of the first pixel (SP1) through the eleventh contact hole (CNT11). The first voltage line (VDL) can be connected to the fifth connection electrode (BE5) of the third metal layer (MTL3) through the 20th contact hole (CNT20), and the fifth connection electrode (BE5) can be connected to the drain electrode (DE1) of the first transistor (ST1) of the second pixel (SP2) through the 21st contact hole (CNT21). The first voltage line (VDL) can be connected to the ninth connection electrode (BE9) of the third metal layer (MTL3) through the 30th contact hole (CNT30), and the ninth connection electrode (BE9) can be connected to the drain electrode (DE1) of the first transistor (ST1) of the third pixel (SP3) through the 31st contact hole (CNT31).

[0104] A horizontal voltage line (HVDL) may be placed on a third metal layer (MTL3). The third metal layer (MTL3) may be placed on an interlayer insulating layer (ILD) covering a second metal layer (MTL2). A horizontal voltage line (HVDL) may be placed below the pixel circuit of a third pixel (SP3). A horizontal voltage line (HVDL) may be placed above the n+1 horizontal gate line (HGLn+1). A horizontal voltage line (HVDL) may be connected to a plurality of first voltage lines (VDL) through a seventh contact hole (CNT7) to receive a driving voltage. A horizontal voltage line (HVDL) may stably maintain the driving voltage or high potential voltage of a plurality of first voltage lines (VDL).

[0105] A vertical gate line (VGL) may be placed on a first metal layer (MTL1). The vertical gate line (VGL) may include an n-th vertical gate line (VGLn) and an n+1-th vertical gate line (VGLn+1) placed to the left of a first voltage line (VDL). The n-th vertical gate line (VGLn) may be connected to the n-th horizontal gate line (HGLn) through a contact portion (MDC) and may be insulated from the remaining horizontal gate lines (HGL).

[0106] A horizontal gate line (HGL) can be placed on the third metal layer (MTL3). A horizontal gate line (HGL) can be placed on the upper side of the pixel circuit of the first pixel (SP1). The nth horizontal gate line (HGLn) can be connected to the nth vertical gate line (VGLn) through a contact portion (MDC). The nth horizontal gate line (HGLn) can be connected to an auxiliary gate line (BGL) through a ninth contact hole (CNT9). The nth horizontal gate line (HGLn) can supply a gate signal received from the nth vertical gate line (VGLn) to the auxiliary gate line (BGL).

[0107] An auxiliary gate line (BGL) may be placed on a second metal layer (MTL2). The second metal layer (MTL2) may be placed on a gate insulating layer (GI) covering an active layer (ACTL). The auxiliary gate line (BGL) may extend from a horizontal gate line (HGL) in the opposite direction of a second direction (Y-axis direction). The auxiliary gate line (BGL) may be placed to the right of the pixel circuit of the first to third pixels (SP1, SP2, SP3). The auxiliary gate line (BGL) may supply a gate signal received from the horizontal gate line (HGL) to the first to third pixels (SP1, SP2, SP3).

[0108] The initialization voltage line (VIL) can be placed on the first metal layer (MTL1). The initialization voltage line (VIL) can be placed to the right of the auxiliary gate line (BGL). The initialization voltage line (VIL) can be connected to the third connection electrode (BE3) of the third metal layer (MTL3) through the 17th contact hole (CNT17), and the third connection electrode (BE3) can be connected to the source electrode (SE3) of the third transistor (ST3) of the first pixel (SP1) through the 18th contact hole (CNT18). The initialization voltage line (VIL) can be connected to the seventh connection electrode (BE7) of the third metal layer (MTL3) through the 27th contact hole (CNT27), and the seventh connection electrode (BE7) can be connected to the source electrode (SE3) of the third transistor (ST3) of the second pixel (SP2) through the 28th contact hole (CNT28). The initialization voltage line (VIL) can be connected to the 11th connection electrode (BE11) of the 3rd metal layer (MTL3) through the 37th contact hole (CNT37), and the 11th connection electrode (BE11) can be connected to the source electrode (SE3) of the 3rd transistor (ST3) of the 3rd pixel (SP3) through the 38th contact hole (CNT38). Accordingly, the initialization voltage line (VIL) can supply an initialization voltage to the 3rd transistor (ST3) of each of the 1st to 3rd pixels (SP1, SP2, SP3) and can receive a sensing signal from the 3rd transistor (ST3).

[0109] The first data line (DL1) can be placed on the first metal layer (MTL1). The first data line (DL1) can be placed to the right of the initialization voltage line (VIL). The first data line (DL1) can be connected to the second connection electrode (BE2) of the third metal layer (MTL3) through the 14th contact hole (CNT14), and the second connection electrode (BE2) can be connected to the drain electrode (DE2) of the second transistor (ST2) of the first pixel (SP1) through the 15th contact hole (CNT15). The first data line (DL1) can supply a data voltage to the second transistor (ST2) of the first pixel (SP1).

[0110] The second data line (DL2) can be placed on the first metal layer (MTL1). The second data line (DL2) can be placed to the right of the first data line (DL1). The second data line (DL2) can be connected to the sixth connection electrode (BE6) of the third metal layer (MTL3) through the 24th contact hole (CNT24), and the sixth connection electrode (BE6) can be connected to the drain electrode (DE2) of the second transistor (ST2) of the second pixel (SP2) through the 25th contact hole (CNT25). The second data line (DL2) can supply a data voltage to the second transistor (ST2) of the second pixel (SP2).

[0111] The third data line (DL3) can be placed on the first metal layer (MTL1). The third data line (DL3) can be placed to the right of the second gate line (DL2). The third data line (DL3) can be connected to the 10th connection electrode (BE10) of the third metal layer (MTL3) through the 34th contact hole (CNT34), and the 10th connection electrode (BE10) can be connected to the drain electrode (DE2) of the second transistor (ST2) of the third pixel (SP3) through the 35th contact hole (CNT35). The third data line (DL3) can supply a data voltage to the second transistor (ST2) of the third pixel (SP3).

[0112] The vertical voltage line (VVSL) can be placed on the first metal layer (MTL1). The vertical voltage line (VVSL) can be placed to the right of the third data line (DL3). The vertical voltage line (VVSL) can be connected to the second voltage line (VSL) of the third metal layer (MTL3) through the eighth contact hole (CNT8). The vertical voltage line (VVSL) can supply a low potential voltage to the second voltage line (VSL).

[0113] The second voltage line (VSL) may be placed on the third metal layer (MTL3). The second voltage line (VSL) may be placed above the nth horizontal gate line (HGLn). The second voltage line (VSL) may supply a low potential voltage received from the vertical voltage line (VVSL) to the fourth alignment line (AL4 in FIG. 12) of each of the first to third pixels (SP1, SP2, SP3). Here, the fourth alignment line of each of the first to third pixels (SP1, SP2, SP3) may be placed on the fourth metal layer (MTL4 in FIG. 14) on the third metal layer (MTL3).

[0114] The pixel circuit of the first pixel (SP1) may include first to third transistors (ST1, ST2, ST3). The first transistor (ST1) of the first pixel (SP1) may include an active region (ACT1), a gate electrode (GE1), a drain electrode (DE1), and a source electrode (SE1). The active region (ACT1) of the first transistor (ST1) may be placed on an active layer (ACTL) and may overlap with the gate electrode (GE1) of the first transistor (ST1). The active layer (ACTL) may be placed on a buffer layer (BF) covering a first metal layer (MTL1).

[0115] The gate electrode (GE1) of the first transistor (ST1) may be placed on the second metal layer (MTL2). The gate electrode (GE1) of the first transistor (ST1) may be part of the first capacitor electrode (CPE1) of the first capacitor (C1). The first capacitor electrode (CPE1) may be connected to the source electrode (SE2) of the second transistor (ST2) of the active layer (ACTL) through the 16th contact hole (CNT16).

[0116] The drain electrode (DE1) and source electrode (SE1) of the first transistor (ST1) can be made conductive by heat-treating the active layer (ACTL). The drain electrode (DE1) of the first transistor (ST1) can be connected to the first voltage line (VDL) through the first connection electrode (BE1). The drain electrode (DE1) of the first transistor (ST1) can receive a driving voltage from the first voltage line (VDL).

[0117] The source electrode (SE1) of the first transistor (ST1) can be connected to the fourth connection electrode (BE4) of the third metal layer (MTL3) through the 12th contact hole (CNT12). The fourth connection electrode (BE4) can be connected to the second capacitor electrode (CPE2) of the first metal layer (MTL1) through the 13th contact hole (CNT13). Accordingly, the first capacitor (C1) can be formed in a dual configuration between the first capacitor electrode (CPE1) and the second capacitor electrode (CPE2), and between the first capacitor electrode (CPE1) and the fourth connection electrode (BE4).

[0118] The fourth connecting electrode (BE4) can be connected to the drain electrode (DE3) of the third transistor (ST3) through the 19th contact hole (CNT19). The fourth connecting electrode (BE4) can be connected to the first contact electrode (CTE1 in FIG. 13) of the first pixel (SP1). Here, the first contact electrode (CTE1 in FIG. 13) of the first pixel (SP1) can be placed on the fifth metal layer (MTL5 in FIG. 14).

[0119] The second transistor (ST2) of the first pixel (SP1) may include an active region (ACT2), a gate electrode (GE2), a drain electrode (DE2), and a source electrode (SE2). The active region (ACT2) of the second transistor (ST2) may be placed in the active layer (ACTL) and may overlap with the gate electrode (GE2) of the second transistor (ST2).

[0120] The gate electrode (GE2) of the second transistor (ST2) may be placed on the second metal layer (MTL2). The gate electrode (GE2) of the second transistor (ST2) may be part of an auxiliary gate line (BGL).

[0121] The drain electrode (DE2) and source electrode (SE2) of the second transistor (ST2) can be made conductive by heat-treating the active layer (ACTL). The drain electrode (DE2) of the second transistor (ST2) can be electrically connected to the first data line (DL1) through the second connection electrode (BE2). The drain electrode (DE2) of the second transistor (ST2) can receive the data voltage of the first pixel (SP1) from the first data line (DL1).

[0122] The source electrode (SE2) of the second transistor (ST2) can be electrically connected to the gate electrode (GE1) of the first transistor (ST1) by being connected to the first capacitor electrode (CPE1) through the 16th contact hole (CNT16).

[0123] The third transistor (ST3) of the first pixel (SP1) may include an active region (ACT3), a gate electrode (GE3), a drain electrode (DE3), and a source electrode (SE3). The active region (ACT3) of the third transistor (ST3) may be placed in the active layer (ACTL) and may overlap with the gate electrode (GE3) of the third transistor (ST3).

[0124] The gate electrode (GE3) of the third transistor (ST3) may be placed on the second metal layer (MTL2). The gate electrode (GE3) of the third transistor (ST3) may be part of the auxiliary gate line (BGL).

[0125] The drain electrode (DE3) and source electrode (SE3) of the third transistor (ST3) can be made conductive by heat-treating the active layer (ACTL). The drain electrode (DE3) of the third transistor (ST3) can be connected to the fourth connection electrode (BE4) through the 19th contact hole (CNT19). The fourth connection electrode (BE4) can be connected to the source electrode (SE1) of the first transistor (ST1) through the 12th contact hole (CNT12) and to the second capacitor electrode (CPE2) of the first metal layer (MTL1) through the 13th contact hole (CNT13).

[0126] The source electrode (SE3) of the third transistor (ST3) can be electrically connected to the initialization voltage line (VIL) through the third connection electrode (BE3). The source electrode (SE3) of the third transistor (ST3) can receive an initialization voltage from the initialization voltage line (VIL). The source electrode (SE3) of the third transistor (ST3) can supply a sensing signal to the initialization voltage line (VIL).

[0127] The pixel circuit of the second pixel (SP2) may include first to third transistors (ST1, ST2, ST3). The first transistor (ST1) of the second pixel (SP2) may include an active region (ACT1), a gate electrode (GE1), a drain electrode (DE1), and a source electrode (SE1). The active region (ACT1) of the first transistor (ST1) may be placed in the active layer (ACTL) and may overlap with the gate electrode (GE1) of the first transistor (ST1).

[0128] The gate electrode (GE1) of the first transistor (ST1) may be placed on the second metal layer (MTL2). The gate electrode (GE1) of the first transistor (ST1) may be part of the first capacitor electrode (CPE1) of the first capacitor (C1). The first capacitor electrode (CPE1) may be connected to the source electrode (SE2) of the second transistor (ST2) of the active layer (ACTL) through the 26th contact hole (CNT26).

[0129] The drain electrode (DE1) and source electrode (SE1) of the first transistor (ST1) can be made conductive by heat-treating the active layer. The drain electrode (DE1) of the first transistor (ST1) can be electrically connected to the first voltage line (VDL) through the fifth connection electrode (BE5). The drain electrode (DE1) of the first transistor (ST1) can receive a driving voltage from the first voltage line (VDL).

[0130] The source electrode (SE1) of the first transistor (ST1) can be connected to the eighth connecting electrode (BE8) of the third metal layer (MTL3) through the 22nd contact hole (CNT22). The eighth connecting electrode (BE8) can be connected to the second capacitor electrode (CPE2) of the first metal layer (MTL1) through the 23rd contact hole (CNT23). Accordingly, the first capacitor (C1) can be formed in a dual configuration between the first capacitor electrode (CPE1) and the second capacitor electrode (CPE2), and between the first capacitor electrode (CPE1) and the eighth connecting electrode (BE8).

[0131] The eighth connection electrode (BE8) can be connected to the drain electrode (DE3) of the third transistor (ST3) through the 29th contact hole (CNT29). The eighth connection electrode (BE8) can be connected to the first contact electrode of the second pixel (SP2). Here, the first contact electrode of the second pixel (SP2) can be placed on the fifth metal layer (MTL5 in FIG. 14).

[0132] The second transistor (ST2) of the second pixel (SP2) may include an active region (ACT2), a gate electrode (GE2), a drain electrode (DE2), and a source electrode (SE2). The active region (ACT2) of the second transistor (ST2) may be placed in the active layer (ACTL) and may overlap with the gate electrode (GE2) of the second transistor (ST2).

[0133] The gate electrode (GE2) of the second transistor (ST2) may be placed on the second metal layer (MTL2). The gate electrode (GE2) of the second transistor (ST2) may be part of an auxiliary gate line (BGL).

[0134] The drain electrode (DE2) and source electrode (SE2) of the second transistor (ST2) can be made conductive by heat-treating the active layer (ACTL). The drain electrode (DE2) of the second transistor (ST2) can be electrically connected to the second data line (DL2) through the sixth connection electrode (BE6). The drain electrode (DE2) of the second transistor (ST2) can receive the data voltage of the second pixel (SP2) from the second data line (DL2).

[0135] The source electrode (SE2) of the second transistor (ST2) can be electrically connected to the gate electrode (GE1) of the first transistor (ST1) by being connected to the first capacitor electrode (CPE1) through the 26th contact hole (CNT26).

[0136] The third transistor (ST3) of the second pixel (SP2) may include an active region (ACT3), a gate electrode (GE3), a drain electrode (DE3), and a source electrode (SE3). The active region (ACT3) of the third transistor (ST3) may be placed in the active layer (ACTL) and may overlap with the gate electrode (GE3) of the third transistor (ST3).

[0137] The gate electrode (GE3) of the third transistor (ST3) may be placed on the second metal layer (MTL2). The gate electrode (GE3) of the third transistor (ST3) may be part of the auxiliary gate line (BGL).

[0138] The drain electrode (DE3) and source electrode (SE3) of the third transistor (ST3) can be made conductive by heat-treating the active layer (ACTL). The drain electrode (DE3) of the third transistor (ST3) can be connected to the eighth connecting electrode (BE8) through the 29th contact hole (CNT29). The eighth connecting electrode (BE8) can be connected to the source electrode (SE1) of the first transistor (ST1) through the 22nd contact hole (CNT22) and to the second capacitor electrode (CPE2) of the first metal layer (MTL1) through the 23rd contact hole (CNT23).

[0139] The source electrode (SE3) of the third transistor (ST3) can be electrically connected to the initialization voltage line (VIL) through the seventh connection electrode (BE7). The source electrode (SE3) of the third transistor (ST3) can receive an initialization voltage from the initialization voltage line (VIL). The source electrode (SE3) of the third transistor (ST3) can supply a sensing signal to the initialization voltage line (VIL).

[0140] The pixel circuit of the third pixel (SP3) may include first to third transistors (ST1, ST2, ST3). The first transistor (ST1) of the third pixel (SP3) may include an active region (ACT1), a gate electrode (GE1), a drain electrode (DE1), and a source electrode (SE1). The active region (ACT1) of the first transistor (ST1) may be placed in the active layer (ACTL) and may overlap with the gate electrode (GE1) of the first transistor (ST1).

[0141] The gate electrode (GE1) of the first transistor (ST1) may be placed on the second metal layer (MTL2). The gate electrode (GE1) of the first transistor (ST1) may be part of the first capacitor electrode (CPE1) of the first capacitor (C1). The first capacitor electrode (CPE1) may be connected to the source electrode (SE2) of the second transistor (ST2) of the active layer (ACTL) through the 36th contact hole (CNT36).

[0142] The drain electrode (DE1) and source electrode (SE1) of the first transistor (ST1) can be made conductive by heat-treating the active layer. The drain electrode (DE1) of the first transistor (ST1) can be electrically connected to the first voltage line (VDL) through the ninth connection electrode (BE9). The drain electrode (DE1) of the first transistor (ST1) can receive a driving voltage from the first voltage line (VDL).

[0143] The source electrode (SE1) of the first transistor (ST1) can be connected to the 12th connection electrode (BE12) of the third metal layer (MTL3) through the 32nd contact hole (CNT32). The 12th connection electrode (BE12) can be connected to the second capacitor electrode (CPE2) of the first metal layer (MTL1) through the 33rd contact hole (CNT33). Thus, the first capacitor (C1) can be formed in a dual configuration between the first capacitor electrode (CPE1) and the second capacitor electrode (CPE2), and between the first capacitor electrode (CPE1) and the 12th connection electrode (BE12).

[0144] The 12th connection electrode (BE12) can be connected to the drain electrode (DE3) of the 3rd transistor (ST3) through the 39th contact hole (CNT39). The 12th connection electrode (BE12) can be connected to the first contact electrode of the 3rd pixel (SP3). Here, the first contact electrode of the 3rd pixel (SP3) can be placed on the 5th metal layer (MTL5 in FIG. 14).

[0145] The second transistor (ST2) of the third pixel (SP3) may include an active region (ACT2), a gate electrode (GE2), a drain electrode (DE2), and a source electrode (SE2). The active region (ACT2) of the second transistor (ST2) may be placed in the active layer (ACTL) and may overlap with the gate electrode (GE2) of the second transistor (ST2).

[0146] The gate electrode (GE2) of the second transistor (ST2) may be placed on the second metal layer (MTL2). The gate electrode (GE2) of the second transistor (ST2) may be part of an auxiliary gate line (BGL).

[0147] The drain electrode (DE2) and source electrode (SE2) of the second transistor (ST2) can be made conductive by heat-treating the active layer (ACTL). The drain electrode (DE2) of the second transistor (ST2) can be electrically connected to the third data line (DL3) through the tenth connection electrode (BE10). The drain electrode (DE2) of the second transistor (ST2) can receive the data voltage of the third pixel (SP3) from the third data line (DL3).

[0148] The source electrode (SE2) of the second transistor (ST2) can be electrically connected to the gate electrode (GE1) of the first transistor (ST1) by connecting it to the first capacitor electrode (CPE1) through the 36th contact hole (CNT36).

[0149] The third transistor (ST3) of the third pixel (SP3) may include an active region (ACT3), a gate electrode (GE3), a drain electrode (DE3), and a source electrode (SE3). The active region (ACT3) of the third transistor (ST3) may be placed in the active layer (ACTL) and may overlap with the gate electrode (GE3) of the third transistor (ST3).

[0150] The gate electrode (GE3) of the third transistor (ST3) may be placed on the second metal layer (MTL2). The gate electrode (GE3) of the third transistor (ST3) may be part of the auxiliary gate line (BGL).

[0151] The drain electrode (DE3) and source electrode (SE3) of the third transistor (ST3) can be made conductive by heat-treating the active layer (ACTL). The drain electrode (DE3) of the third transistor (ST3) can be connected to the 12th connection electrode (BE12) through the 39th contact hole (CNT39). The 12th connection electrode (BE12) can be connected to the source electrode (SE1) of the first transistor (ST1) through the 32nd contact hole (CNT32) and to the 2nd capacitor electrode (CPE2) of the first metal layer (MTL1) through the 33rd contact hole (CNT33).

[0152] The source electrode (SE3) of the third transistor (ST3) can be electrically connected to the initialization voltage line (VIL) through the first connection electrode (BE11). The source electrode (SE3) of the third transistor (ST3) can receive an initialization voltage from the initialization voltage line (VIL). The source electrode (SE3) of the third transistor (ST3) can supply a sensing signal to the initialization voltage line (VIL).

[0153] In FIG. 8, the protective layer (PV) is disposed on the third metal layer (MTL3) and the interlayer insulating layer (ILD) to protect the pixel circuits of the first to third pixels (SP1, SP2, SP3). The via layer (VIA) is disposed on the protective layer (PV) to flatten the top of the thin-film transistor layer.

[0154] FIG. 9 is a plan view showing the connection relationship between the alignment line and the thin-film transistor layer before the alignment of the light-emitting elements in a display device according to one embodiment. FIG. 10 is a diagram showing the first alignment process of a plurality of light-emitting elements in a display device according to one embodiment, and FIG. 11 is a diagram showing the second alignment process of a plurality of light-emitting elements in a display device according to one embodiment.

[0155] Referring to FIGS. 9 through 11, each of the first to third pixels (SP1, SP2, SP3) may include an alignment line (AL). The alignment lines (AL) of the first to third pixels (SP1, SP2, SP3) may be spaced apart in a first direction (X-axis direction). The alignment line (AL) may include first to fourth alignment lines (AL1, AL2, AL3, AL4). The first to fourth alignment lines (AL1, AL2, AL3, AL4) may extend in a second direction (Y-axis direction) and be spaced apart from each other in a first direction (X-axis direction). The first to fourth alignment lines (AL1, AL2, AL3, AL4) may be placed on a fourth metal layer (MTL4 in FIG. 14). In FIG. 9, the alignment lines (AL) of the first to third pixels (SP1, SP2, SP3) may not overlap with the first voltage line (VDL), the initialization voltage line (VIL), the first to third data lines (DL1, DL2, DL3), and the vertical voltage line (VVSL), but are not limited thereto. As another example, at least one of the first to fourth alignment lines (AL1, AL2, AL3, AL4) of the first to third pixels (SP1, SP2, SP3) may overlap with at least one of the first voltage line (VDL), the initialization voltage line (VIL), the first to third data lines (DL1, DL2, DL3), and the vertical voltage line (VVSL).

[0156] The fourth alignment line (AL4) of each of the first to third pixels (SP1, SP2, SP3) can be connected to the second voltage line (VSL) of the third metal layer (MTL3) through the fourth contact hole (CNT4). The second voltage line (VSL) can be connected to the vertical voltage line (VVSL) of the first metal layer (MTL1) through the eighth contact hole (CNT8) and to the first lower connecting electrode (MCE1) of the second metal layer (MTL2) through the fifth contact hole (CNT5). Accordingly, the fourth alignment line (AL4) can receive an alignment signal through the vertical voltage line (VVSL).

[0157] The first alignment line (AL1) of each of the first to third pixels (SP1, SP2, SP3) can be connected to the horizontal voltage line (HVDL) of the third metal layer (MTL3) through the first contact hole (CNT1). The horizontal voltage line (HVDL) can be connected to the first voltage line (VDL) of the first metal layer (MTL1) through the seventh contact hole (CNT7). Accordingly, the first alignment line (AL1) can receive an alignment signal through the first voltage line (VDL).

[0158] Each of the first to third pixels (SP1, SP2, SP3) can be connected to the first horizontal connection line (HCL1) of the third metal layer (MTL3) through the second contact hole (CNT2). The first horizontal connection line (HCL1) can be connected to the first upper connection electrode (ACE1) of the fourth metal layer (MTL4 in FIG. 14) through the 40th contact hole (CNT40), and can be connected to the second lower connection electrode (MCE2) of the second metal layer (MTL2) through the fifth contact hole (CNT5). The first upper connecting electrode (ACE1) can be connected to the 13th connecting electrode (BE13) of the third metal layer (MTL3) through the 41st contact hole (CNT41), and the 13th connecting electrode (BE13) can be connected to the first data line (DL1) of the first metal layer (MTL1) through the 42nd contact hole (CNT42). Accordingly, the second alignment line (AL2) can receive an alignment signal through the first data line (DL1). As another example, the second alignment line (AL2) can receive an alignment signal by being electrically connected to the initialization voltage line (VIL) or the third data line (DL3).

[0159] Each of the first to third pixels (SP1, SP2, SP3) can be connected to the second horizontal connection line (HCL2) of the third metal layer (MTL3) through the third contact hole (CNT3). The second horizontal connection line (HCL2) can be connected to the second upper connection electrode (ACE2) of the fourth metal layer (MTL4 in FIG. 14) through the 43rd contact hole (CNT43), and can be connected to the third lower connection electrode (MCE3) of the second metal layer (MTL2) through the fifth contact hole (CNT5). The second upper connecting electrode (ACE2) can be connected to the 14th connecting electrode (BE14) of the third metal layer (MTL3) through the 44th contact hole (CNT44), and the 14th connecting electrode (BE14) can be connected to the second data line (DL2) of the first metal layer (MTL1) through the 45th contact hole (CNT45). Accordingly, the third alignment line (AL3) can receive an alignment signal through the second data line (DL2). As another example, the third alignment line (AL3) can receive an alignment signal by being electrically connected to the initialization voltage line (VIL) or the third data line (DL3).

[0160] In FIG. 10, the first and second alignment lines (AL1, AL2) of each of the first to third pixels (SP1, SP2, SP3) can receive a first alignment signal (AS1), and the third and fourth alignment lines (AL3, AL4) can receive a second alignment signal (AS2). For example, the first alignment signal (AS1) may be an alternating current signal having a predetermined frequency, and the second alignment signal (AS2) may be a ground signal, but is not limited thereto. By the first and second alignment lines (AL1, AL2) receiving the first alignment signal (AS1) and the third and fourth alignment lines (AL3, AL4) receiving the second alignment signal (AS2), an electric field can be formed from the first and second alignment lines (AL1, AL2) toward the third and fourth alignment lines (AL3, AL4). For example, a plurality of light-emitting elements (ED) can be sprayed onto alignment lines (AL) of first to third pixels (SP1, SP2, SP3) through an inkjet printing process, and the plurality of light-emitting elements (ED) dispersed in the ink can be aligned by receiving a dielectrophoresis force due to an electric field. Accordingly, the plurality of light-emitting elements (ED) can be aligned toward the same direction on the first to fourth alignment lines (AL1, AL2, AL3, AL4).

[0161] In FIG. 11, the second and third alignment lines (AL2, AL3) of each of the first to third pixels (SP1, SP2, SP3) can receive a first alignment signal (AS1), and the first and fourth alignment lines (AL1, AL4) can receive a second alignment signal (AS2). By the second alignment line (AL2) receiving the first alignment signal (AS1) and the first alignment line (AL1) receiving the second alignment signal (AS2), an electric field can be formed from the second alignment line (AL2) to the first alignment line (AL1). Accordingly, a plurality of first light-emitting elements (ED1) can be aligned toward a first direction (X-axis direction) between the first and second alignment lines (AL1, AL2). By receiving the first alignment signal (AS1) from the third alignment line (AL3) and the second alignment signal (AS2) from the fourth alignment line (AL4), an electric field can be formed from the third alignment line (AL3) to the fourth alignment line (AL4). Accordingly, a plurality of second light-emitting elements (ED2) can be aligned in the opposite direction of the first direction (X-axis direction) between the third and fourth alignment lines (AL3, AL4).

[0162] The display device (10) can align a plurality of light-emitting elements (ED) through the first alignment process of FIG. 10 and the second alignment process of FIG. 11, thereby preventing the plurality of light-emitting elements (ED) from being partially concentrated and allowing the plurality of light-emitting elements (ED) to be evenly distributed. Accordingly, the display device (10) can prevent dark spots and improve display quality.

[0163] FIG. 12 is a plan view showing the connection relationship between the alignment line and the thin-film transistor layer after alignment of the light-emitting element in a display device according to one embodiment.

[0164] Referring to FIG. 12, the first and second upper voltage lines (RVL, RHL) may be placed on a fifth metal layer (MTL5 in FIG. 14) on a fourth metal layer (MTL4 in FIG. 14). The fifth metal layer (MTL5 in FIG. 14) may be formed after alignment of the light-emitting element (ED).

[0165] A plurality of first upper voltage lines (RVL) may extend in a second direction (Y-axis direction) and be spaced apart in a first direction (X-axis direction). The first upper voltage lines (RVL) may be connected to the first lower connecting electrode (MCE1) of the second metal layer (MTL2) through the sixth contact hole (CNT6). The first lower connecting electrode (MCE1) may be connected to the second voltage line (VSL) of the third metal layer (MTL3) through the fifth contact hole (CNT5). The second voltage line (VSL) may be connected to the vertical voltage line (VVSL) of the first metal layer (MTL1) through the eighth contact hole (CNT8). Thus, the first upper voltage lines (RVL) can receive a low potential voltage from the vertical voltage line (VVSL).

[0166] The first upper voltage line (RVL) can be connected to the second lower connecting electrode (MCE2) of the second metal layer (MTL2) through the sixth contact hole (CNT6). The second lower connecting electrode (MCE2) can be connected to the first horizontal connecting line (HCL1) of the third metal layer (MTL3) through the fifth contact hole (CNT5). The first upper connecting electrode (ACE1) can be cut by the separation part (RMO). Thus, the first horizontal connecting line (HCL1) can be electrically insulated from the first data line (DL1) and can receive a low potential voltage from the first upper voltage line (RVL).

[0167] The first upper voltage line (RVL) can be connected to the third lower connecting electrode (MCE3) of the second metal layer (MTL2) through the sixth contact hole (CNT6). The third lower connecting electrode (MCE3) can be connected to the second horizontal connecting line (HCL2) of the third metal layer (MTL3) through the fifth contact hole (CNT5). The second upper connecting electrode (ACE2) can be cut by the separation part (RMO). Thus, the second horizontal connecting line (HCL2) can be electrically insulated from the second data line (DL2) and can receive a low potential voltage from the first upper voltage line (RVL).

[0168] A plurality of second upper voltage lines (RHL) may be extended in a first direction (X-axis direction) and spaced apart in a second direction (Y-axis direction). A plurality of second upper voltage lines (RHL) may be formed integrally with a plurality of first upper voltage lines (RVL). Accordingly, the second upper voltage lines (RHL) can receive a low potential voltage from the vertical voltage line (VVSL). A plurality of second upper voltage lines (RHL) may intersect with the first to fourth alignment lines (AL1, AL2, AL3, AL4).

[0169] The first alignment line (AL1) of the display device (10) can be electrically connected to a horizontal voltage line (HVDL) and a first voltage line (VDL) to receive a high potential voltage, and the second to fourth alignment lines (AL2, AL3, AL4) can be electrically connected to a vertical voltage line (VVSL), a second voltage line (VSL), first and second horizontal connection lines (HCL1, HCL2), and first and second upper voltage lines (RVL, RHL) to receive a low potential voltage. The first alignment line (AL1) can be electrically connected to a high potential line having a mesh structure (e.g., a horizontal voltage line (HVDL) and a first voltage line (VDL)), and the second to fourth alignment lines (AL2, AL3, AL4) can be electrically connected to a low potential line having a mesh structure (e.g., a vertical voltage line (VVSL) and a second voltage line (VSL) or first and second upper voltage lines (RVL, RHL)). Accordingly, all alignment lines (AL) of the display device (10) are electrically connected to a high potential line or a low potential line having a mesh structure, thereby ensuring redundant connections and preventing voltage drop (IR Drop).

[0170] FIG. 13 is a plan view showing a light-emitting element layer of a display device according to one embodiment, and FIG. 14 is a cross-sectional view taken along line II-II' of FIG. 13. Here, FIG. 13 shows a first pixel (SP1), and the second and third pixels (SP2, SP3) can be designed to be in the same manner as the first pixel (SP1).

[0171] Referring to FIGS. 13 and 14, the light-emitting element layer (EML) of the display device (10) may be disposed on a thin-film transistor layer (TFTL). The light-emitting element layer (EML) may include first to fourth alignment lines (AL1, AL2, AL3, AL4), a first insulating layer (PAS1), a bank layer (BNL), first and second light-emitting elements (ED1, ED2), first to third contact electrodes (CTE1, CTE2, CTE3), a second insulating layer (PAS2), and a third insulating layer (PAS3).

[0172] The fourth metal layer (MTL4) may be disposed on a via layer (VIA). The fourth metal layer (MTL4) may include first to fourth alignment lines (AL1, AL2, AL3, AL4). The first to fourth alignment lines (AL1, AL2, AL3, AL4) may extend in a second direction (Y-axis direction) and be spaced apart from each other in a first direction (X-axis direction).

[0173] The first insulating layer (PAS1) may be placed on the first to fourth alignment lines (AL1, AL2, AL3, AL4). The first insulating layer (PAS1) may insulate the first to fourth alignment lines (AL1, AL2, AL3, AL4) from the first and second light-emitting elements (ED1, ED2).

[0174] A plurality of first light-emitting elements (ED1) can be aligned between first and second alignment lines (AL1, AL2) on the first insulating layer (PAS1). A plurality of second light-emitting elements (ED2) can be aligned between third and fourth alignment lines (AL3, AL4) on the first insulating layer (PAS1).

[0175] The fifth metal layer (MTL5) may be disposed on the first insulating layer (PAS1) and the light-emitting element (ED). The fifth metal layer (MTL5) may include first to third contact electrodes (CTE1, CTE2, CTE3).

[0176] The first contact electrode (CTE1) is placed on the second alignment line (AL2) and can be electrically connected to the pixel circuit of the first pixel (SP1) through the 52nd contact hole (CNT52). For example, the first contact electrode (CTE1) can receive a driving current that has passed through the first transistor (ST1) of FIG. 5. The first contact electrode (CTE1) can be connected between the first transistor (ST1) of the first pixel (SP1) and one end of a plurality of first light-emitting elements (ED1). The first contact electrode (CTE1) may correspond to the anode electrode of the plurality of first light-emitting elements (ED1), but is not limited thereto.

[0177] The second contact electrode (CTE2) is positioned on the first to third alignment lines (AL1, AL2, AL3) and may be insulated from the first to third alignment lines (AL1, AL2, AL3). A first portion of the second contact electrode (CTE2) may be positioned on the first alignment line (AL1) and may extend in a second direction (Y-axis direction). A second portion of the second contact electrode (CTE2) may be bent from the lower side of the first portion and may extend in a first direction (X-axis direction). A third portion of the second contact electrode (CTE2) may be bent from the right side of the second portion and extend in a second direction (Y-axis direction), and may be positioned on the third alignment line (AL3).

[0178] The second contact electrode (CTE2) may be connected between the other end of a plurality of first light-emitting elements (ED1) and one end of a plurality of second light-emitting elements (ED2). The second contact electrode (CTE2) may correspond to the third node (N3) of FIG. 5. The second contact electrode (CTE2) may correspond to the cathode electrode of a plurality of first light-emitting elements (ED1), but is not limited thereto. The second contact electrode (CTE2) may correspond to the anode electrode of a plurality of second light-emitting elements (ED2), but is not limited thereto.

[0179] The third contact electrode (CTE3) is placed on the fourth alignment line (AL4) and can be connected to the fourth alignment line (AL4) through the 53rd contact hole (CNT53). The third contact electrode (CTE3) can be connected between the other end of a plurality of second light-emitting elements (ED2) and the fourth alignment line (AL4). The fourth alignment line (AL4) can receive a low potential voltage from the second voltage line (VSL). The third contact electrode (CTE3) may correspond to the cathode electrode of a plurality of second light-emitting elements (ED2), but is not limited thereto.

[0180] The bank layer (BNL) can separate the light-emitting elements (ED) of the first to third pixels (SP1, SP2, SP3). The second insulating layer (PAS2) can insulate the first and second contact electrodes (CTE1, CTE2) on the first light-emitting element (ED1) and can insulate the second and third contact electrodes (CTE1, CTE2) on the second light-emitting element (ED2). The third insulating layer (PAS3) can be disposed on the first to third contact electrodes (CTE1, CTE2, CTE3) and the second insulating layer (PAS2) to protect the light-emitting element layer (EML).

[0181] The thin film transistor (TFT) of the thin film transistor layer (TFTL) may include an active region (ACT), a gate electrode (GE), a drain electrode (DE), and a source electrode (SE). The drain electrode (DE) of the thin film transistor (TFT) may be electrically connected to a first voltage line (VDL) of the first metal layer (MTL1) through a connection electrode (BE).

[0182] FIG. 15 is a plan view showing the connection relationship between the alignment line and the thin-film transistor layer before the alignment of the light-emitting elements in a display device according to another embodiment. FIG. 16 is a diagram showing the first alignment process of a plurality of light-emitting elements in a display device according to another embodiment, and FIG. 17 is a diagram showing the second alignment process of a plurality of light-emitting elements in a display device according to another embodiment.

[0183] Referring to FIGS. 15 to 17, each of the first to third pixels (SP1, SP2, SP3) may include an alignment line (AL) and an alignment electrode (AE). The alignment line (AL) and the alignment electrode (AE) may be disposed on a fourth metal layer (MTL4). The alignment line (AL) may include first to third alignment lines (AL1, AL2, AL3). The first to third alignment lines (AL1, AL2, AL3) may extend in a second direction (Y-axis direction) and be spaced apart from each other in a first direction (X-axis direction). The first alignment line (AL1) may be formed integrally with the third alignment line (AL3) of an adjacent pixel through an alignment connection line (CAL) extending in the first direction (X-axis direction). For example, the third alignment line (AL3) of the first pixel (SP1) can be connected to the first alignment line (AL1) of the second pixel (SP2) through an alignment connection line (CAL). The third alignment line (AL3) of the second pixel (SP2) can be connected to the first alignment line (AL1) of the third pixel (SP3) through an alignment connection line (CAL).

[0184] In FIG. 15, the alignment lines (AL) of the first to third pixels (SP1, SP2, SP3) may not overlap with the first voltage line (VDL), the initialization voltage line (VIL), the first to third data lines (DL1, DL2, DL3), and the vertical voltage line (VVSL), but are not limited thereto. In another example, at least one of the first to third alignment lines (AL1, AL2, AL3) of the first to third pixels (SP1, SP2, SP3) may overlap with at least one of the first voltage line (VDL), the initialization voltage line (VIL), the first to third data lines (DL1, DL2, DL3), and the vertical voltage line (VVSL).

[0185] The third alignment line (AL3) of each of the first to third pixels (SP1, SP2, SP3) can be connected to the horizontal voltage line (HVDL) of the third metal layer (MTL3) through the 46th contact hole (CNT46). The horizontal voltage line (HVDL) can be connected to the first voltage line (VDL) of the first metal layer (MTL1) through the 7th contact hole (CNT7). Thus, the third alignment line (AL3) can receive an alignment signal through the first voltage line (VDL). The first alignment line (AL1) can receive an alignment signal through the first voltage line (VDL) by being connected to the third alignment line (AL3).

[0186] The second alignment line (AL2) of each of the first to third pixels (SP1, SP2, SP3) can be connected to the horizontal connection line (HCL) of the third metal layer (MTL3) through the 47th contact hole (CNT47). The horizontal connection line (HCL) can be connected to the upper connection electrode (ACE) of the fourth metal layer (MTL4) through the 49th contact hole (CNT49) and to the second lower connection electrode (MCE2) of the second metal layer (MTL2) through the 5th contact hole (CNT5). The upper connection electrode (ACE) can be connected to the 15th connection electrode (BE15) of the third metal layer (MTL3) through the 50th contact hole (CNT50), and the 15th connection electrode (BE15) can be connected to the first data line (DL1) of the first metal layer (MTL1) through the 51st contact hole (CNT51). Accordingly, the second alignment line (AL2) can receive an alignment signal through the first data line (DL1). As another example, the second alignment line (AL2) can receive an alignment signal by being electrically connected to the initialization voltage line (VIL), the second data line (DL2), or the third data line (DL3).

[0187] The alignment electrode (AE) of each of the first to third pixels (SP1, SP2, SP3) may be spaced apart and surrounded by a second alignment line (AL2). The alignment electrode (AE) may be connected to a second voltage line (VSL) of the third metal layer (MTL3) through a 48th contact hole (CNT3). The second voltage line (VSL) may include a first portion extending in a first direction (X-axis direction) and a second portion intersecting the first portion and extending in a second direction (Y-axis direction), and the alignment electrode (AE) may be connected to the second portion of the second voltage line (VSL). The second voltage line (VSL) may be connected to a vertical voltage line (VVSL) of the first metal layer (MTL1) through an 8th contact hole (CNT8) and may be connected to a first lower connecting electrode (MCE1) of the second metal layer (MTL2) through a 5th contact hole (CNT5). Therefore, the alignment electrode (AE) can receive an alignment signal through the vertical voltage line (VVSL).

[0188] In FIG. 16, each alignment electrode (AE) of the first to third pixels (SP1, SP2, SP3) can receive a first alignment signal (AS1), and the first to third alignment lines (AL1, AL2, AL3) can receive a second alignment signal (AS2). For example, the first alignment signal (AS1) may be an AC signal having a predetermined frequency, and the second alignment signal (AS2) may be a ground signal, but is not limited thereto. By the alignment electrode (AE) receiving the first alignment signal (AS1) and the first to third alignment lines (AL1, AL2, AL3) receiving the second alignment signal (AS2), an electric field can be formed from the alignment electrode (AE) toward the first to third alignment lines (AL1, AL2, AL3). For example, a plurality of light-emitting elements (ED) can be sprayed onto alignment lines (AL) of first to third pixels (SP1, SP2, SP3) through an inkjet printing process, and the plurality of light-emitting elements (ED) dispersed in the ink can be aligned by receiving a dielectrophoresis force due to an electric field. Accordingly, the plurality of light-emitting elements (ED) can be aligned toward an alignment electrode (AE) on the first to third alignment lines (AL1, AL2, AL3).

[0189] In FIG. 17, the second alignment line (AL2) of each of the first to third pixels (SP1, SP2, SP3) can receive a first alignment signal (AS1), and the first and third alignment lines (AL1, AL3) can receive a second alignment signal (AS2). The alignment electrode (AE) may not receive a separate alignment signal and may have a floating state. By the second alignment line (AL2) receiving the first alignment signal (AS1) and the first and third alignment lines (AL1, AL3) receiving the second alignment signal (AS2), an electric field can be formed from the second alignment line (AL2) to the first or third alignment line (AL1, AL3). Accordingly, a plurality of first light-emitting elements (ED1) can be aligned toward a first direction (X-axis direction) between first and second alignment lines (AL1, AL2), and a plurality of second light-emitting elements (ED2) can be aligned toward a direction opposite to the first direction (X-axis direction) between second and third alignment lines (AL2, AL3).

[0190] The display device (10) can align a plurality of light-emitting elements (ED) through the first alignment process of FIG. 16 and the second alignment process of FIG. 17, thereby preventing the plurality of light-emitting elements (ED) from being partially concentrated and allowing the plurality of light-emitting elements (ED) to be evenly distributed. Accordingly, the display device (10) can prevent dark spots and improve display quality.

[0191] FIG. 18 is a plan view showing the connection relationship between the alignment line and the thin-film transistor layer after alignment of the light-emitting element in a display device according to another embodiment.

[0192] Referring to FIG. 18, the first and second upper voltage lines (RVL, RHL) may be placed on the fifth metal layer (MTL5) on the fourth metal layer (MTL4). The fifth metal layer (MTL5) may be formed after alignment of the light-emitting element (ED).

[0193] A plurality of first upper voltage lines (RVL) may extend in a second direction (Y-axis direction) and be spaced apart in a first direction (X-axis direction). The first upper voltage lines (RVL) may be connected to the first lower connecting electrode (MCE1) of the second metal layer (MTL2) through the sixth contact hole (CNT6). The first lower connecting electrode (MCE1) may be connected to the second voltage line (VSL) of the third metal layer (MTL3) through the fifth contact hole (CNT5). The second voltage line (VSL) may be connected to the vertical voltage line (VVSL) of the first metal layer (MTL1) through the eighth contact hole (CNT8). Thus, the first upper voltage lines (RVL) can receive a low potential voltage from the vertical voltage line (VVSL).

[0194] The first upper voltage line (RVL) can be connected to the second lower connecting electrode (MCE2) of the second metal layer (MTL2) through the sixth contact hole (CNT6). The second lower connecting electrode (MCE2) can be connected to the horizontal connecting line (HCL) of the third metal layer (MTL3) through the fifth contact hole (CNT5). The upper connecting electrode (ACE) can be cut by the separation part (RMO). Thus, the horizontal connecting line (HCL) can be electrically insulated from the first data line (DL1) and can receive a low potential voltage from the first upper voltage line (RVL).

[0195] A plurality of second upper voltage lines (RHL) may be extended in a first direction (X-axis direction) and spaced apart in a second direction (Y-axis direction). A plurality of second upper voltage lines (RHL) may be formed integrally with a plurality of first upper voltage lines (RVL). Accordingly, the second upper voltage lines (RHL) can receive a low potential voltage from the vertical voltage line (VVSL). A plurality of second upper voltage lines (RHL) may intersect with first to third alignment lines (AL1, AL2, AL3).

[0196] The first and third alignment lines (AL1, AL3) of the display device (10) can be electrically connected to a horizontal voltage line (HVDL) and a first voltage line (VDL) to receive a high potential voltage, and the second alignment line (AL2) can be electrically connected to a vertical voltage line (VVSL), a second voltage line (VSL), a horizontal connection line (HCL), and first and second upper voltage lines (RVL, RHL) to receive a low potential voltage. The first and third alignment lines (AL1, AL3) can be electrically connected to high potential lines having a mesh structure (e.g., horizontal voltage line (HVDL) and first voltage line (VDL)), and the second alignment line (AL2) can be electrically connected to low potential lines having a mesh structure (e.g., vertical voltage line (VVSL) and second voltage line (VSL) or first and second upper voltage lines (RVL, RHL)). Accordingly, all alignment lines (AL) of the display device (10) are electrically connected to a high potential line or a low potential line having a mesh structure, thereby ensuring redundant connections and preventing voltage drop (IR Drop).

[0197] FIG. 19 is a plan view showing a light-emitting element layer of a display device according to another embodiment. Here, FIG. 19 shows a first pixel (SP1), and the second and third pixels (SP2, SP3) can be designed to be in the same manner as the first pixel (SP1).

[0198] Referring to FIG. 19, the light-emitting element layer (EML) may include first to third alignment lines (AL1, AL2, AL3), alignment electrodes (AE), first and second light-emitting elements (ED1, ED2), and first to third contact electrodes (CTE1, CTE2, CTE3).

[0199] The fourth metal layer (MTL4) may include first to third alignment lines (AL1, AL2, AL3). The first to third alignment lines (AL1, AL2, AL3) may extend in a second direction (Y-axis direction) and be spaced apart from each other in a first direction (X-axis direction).

[0200] A plurality of first light-emitting elements (ED1) can be aligned between first and second alignment lines (AL1, AL2). A plurality of second light-emitting elements (ED2) can be aligned between second and third alignment lines (AL2, AL3).

[0201] The fifth metal layer (MTL5) may include first to third contact electrodes (CTE1, CTE2, CTE3). The first contact electrode (CTE1) may be placed on the second alignment line (AL2) and electrically connected to the pixel circuit of the first pixel (SP1) through the 52nd contact hole (CNT52). For example, the first contact electrode (CTE1) may receive a driving current that has passed through the first transistor (ST1) of FIG. 5. The first contact electrode (CTE1) may be connected between the first transistor (ST1) of the first pixel (SP1) and one end of a plurality of first light-emitting elements (ED1). The first contact electrode (CTE1) may correspond to the anode electrode of the plurality of first light-emitting elements (ED1), but is not limited thereto.

[0202] The second contact electrode (CTE2) is positioned on the first and second alignment lines (AL1, AL2) and may be insulated from the first and second alignment lines (AL1, AL2). A first portion of the second contact electrode (CTE2) may be positioned on the first alignment line (AL1) and may extend in a second direction (Y-axis direction). A second portion of the second contact electrode (CTE2) may be bent from the lower side of the first portion and may extend in a first direction (X-axis direction). A third portion of the second contact electrode (CTE2) may be bent from the right side of the second portion and extend in a second direction (Y-axis direction), and may be positioned on the second alignment line (AL2).

[0203] The second contact electrode (CTE2) may be connected between the other end of a plurality of first light-emitting elements (ED1) and one end of a plurality of second light-emitting elements (ED2). The second contact electrode (CTE2) may correspond to the third node (N3) of FIG. 5. The second contact electrode (CTE2) may correspond to the cathode electrode of a plurality of first light-emitting elements (ED1), but is not limited thereto. The second contact electrode (CTE2) may correspond to the anode electrode of a plurality of second light-emitting elements (ED2), but is not limited thereto.

[0204] The third contact electrode (CTE3) is placed on the third alignment line (AL3) and can be connected to the second alignment line (AL2) through the 53rd contact hole (CNT53). The third contact electrode (CTE3) can be connected between the other end of a plurality of second light-emitting elements (ED2) and the second alignment line (AL2). The second alignment line (AL2) can receive a low potential voltage from the second voltage line (VSL). The third contact electrode (CTE3) may correspond to the cathode electrode of a plurality of second light-emitting elements (ED2), but is not limited thereto.

[0205] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0206] SP1, SP2, SP3: 1st to 3rd pixels DL1, DL2, DL3: 1st to 3rd data lines VGL: Vertical Gate Line HGL: Horizontal Gate Line BGL: Auxiliary gate line VDL: First voltage line HVDL: Horizontal voltage line VVSL: Vertical voltage line VSL: Second voltage line VIL: Initial voltage line AL1, AL2, AL3, AL4: 1st to 4th alignment lines HCL1, HCL2: 1st and 2nd horizontal connection lines ED1, ED2: First and second light-emitting elements RVL, RHL: 1st and 2nd upper voltage lines CTE1, CTE2, CTE3: First to third contact electrodes

Claims

Claim 1 A display device comprising: a first voltage line, first and second data lines, and a vertical voltage line disposed on a substrate and extending parallel in a first direction; a horizontal voltage line, a second voltage line, and a first and second horizontal connection line disposed on the first voltage line and extending parallel in a second direction intersecting the first direction; first to fourth alignment lines disposed on the horizontal voltage line and extending parallel in the first direction; a first light-emitting element aligned between the first and second alignment lines; and a second light-emitting element aligned between the third and fourth alignment lines, wherein the first voltage line, the horizontal voltage line, and the first alignment line are electrically connected, the first horizontal connection line and the second alignment line are electrically connected, the second horizontal connection line and the third alignment line are electrically connected, and the vertical voltage line, the second voltage line, and the fourth alignment line are electrically connected. Claim 2 A display device according to claim 1, further comprising: a first upper voltage line extending in the first direction and disposed on the first to fourth alignment lines; and a second upper voltage line extending in the second direction in the same layer as the first upper voltage line, wherein the first and second upper voltage lines are integrally formed. Claim 3 In claim 2, the first and second upper voltage lines are a display device electrically connected to the second voltage line and the first and second horizontal connection lines. Claim 4 In claim 3, the first upper voltage line is electrically connected to the second voltage line through a first lower connecting electrode disposed in a layer between the second voltage line and the vertical voltage line. Claim 5 A display device according to claim 1, wherein in the alignment process of the first and second light-emitting elements, the first horizontal connection line and the second alignment line are electrically connected to the first data line, and the second horizontal connection line and the third alignment line are electrically connected to the second data line. Claim 6 A display device according to claim 5, wherein in the first alignment process of the first and second light-emitting elements, the first and second alignment lines receive a first alignment signal, and the third and fourth alignment lines receive a second alignment signal different from the first alignment signal. Claim 7 In claim 6, a display device wherein, in the secondary alignment process of the first and second light-emitting elements, the second and third alignment lines receive the first alignment signal, and the first and fourth alignment lines receive the second alignment signal. Claim 8 A display device according to claim 5, wherein when the alignment of the first and second light-emitting elements is completed, the first horizontal connection line and the first data line are electrically insulated, and the second horizontal connection line and the second data line are electrically insulated. Claim 9 A display device according to claim 1, further comprising: an initialization voltage line extending parallel to the first data line in the same layer; a first transistor connected between the first voltage line and the first light-emitting element; a second transistor connected between the first data line and the gate electrode of the first transistor; and a third transistor connected between the initialization voltage line and the first light-emitting element. Claim 10 A display device according to claim 9, further comprising: a first contact electrode disposed on the first to fourth alignment lines and connected between the first transistor and the first light-emitting element; a second contact electrode connected between the first light-emitting element and the second light-emitting element; and a third contact electrode connected between the second light-emitting element and the fourth alignment line. Claim 11 A display device comprising: a first voltage line, a data line, and a vertical voltage line disposed on a substrate and extending parallel to a first direction; a horizontal voltage line, a second voltage line, and a horizontal connection line disposed on the first voltage line and extending parallel to a second direction intersecting the first direction; first to third alignment lines disposed on the horizontal voltage line and extending parallel to the first direction; an alignment electrode spaced apart and surrounded by the second alignment line; a first light-emitting element aligned between the first and second alignment lines; and a second light-emitting element aligned between the second and third alignment lines, wherein the first voltage line, the horizontal voltage line, and the third alignment line are electrically connected, the horizontal connection line and the second alignment line are electrically connected, and the vertical voltage line, the second voltage line, and the alignment electrode are electrically connected. Claim 12 A display device according to claim 11, further comprising a plurality of pixels each including the first to third alignment lines, wherein one of the plurality of pixels' third alignment line is integrally formed with the first alignment line of another pixel adjacent in the second direction through an alignment connection line extending in the second direction. Claim 13 A display device according to claim 11, further comprising: a first upper voltage line extending in the first direction and disposed on the first to third alignment lines; and a second upper voltage line extending in the second direction in the same layer as the first upper voltage line, wherein the first and second upper voltage lines are integrally formed. Claim 14 In claim 13, the first and second upper voltage lines are electrically connected to the second voltage line and the horizontal connection line, forming a display device. Claim 15 In claim 11, in the alignment process of the first and second light-emitting elements, the horizontal connection line and the second alignment line are electrically connected to the data line in the display device. Claim 16 A display device according to claim 15, wherein in the first alignment process of the first and second light-emitting elements, the alignment electrode receives a first alignment signal, and the first to third alignment lines receive a second alignment signal different from the first alignment signal. Claim 17 In claim 16, a display device wherein, in the secondary alignment process of the first and second light-emitting elements, the second alignment line receives the first alignment signal, and the first and third alignment lines receive the second alignment signal. Claim 18 In claim 15, when the alignment of the first and second light-emitting elements is completed, the horizontal connection line and the data line are electrically insulated in the display device. Claim 19 A display device according to claim 11, further comprising: an initialization voltage line extending parallel to the data line in the same layer; a first transistor connected between the first voltage line and the first light-emitting element; a second transistor connected between the data line and the gate electrode of the first transistor; and a third transistor connected between the initialization voltage line and the first light-emitting element. Claim 20 A display device according to claim 19, further comprising: a first contact electrode disposed on the first to third alignment lines and connected between the first transistor and the first light-emitting element; a second contact electrode connected between the first light-emitting element and the second light-emitting element; and a third contact electrode connected between the second light-emitting element and the second alignment line.

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