Display device and display driving method

Abstract

Embodiments of the present disclosure relate to a display device and a display driving method, and more specifically, a display device may be provided comprising: a display panel having a plurality of subpixels arranged thereon; a gate driving circuit that supplies a plurality of scan signals to the display panel through a plurality of gate lines; a data driving circuit that supplies a plurality of data voltages to the display panel through a plurality of data lines; a power management circuit that supplies a plurality of driving voltages to the gate driving circuit and the data driving circuit; and a timing controller that controls the power management circuit so that the level of the gate voltage applied to the gate driving circuit is changed according to the output state of the gate driving circuit.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to a display device and a display driving method, and more specifically, to a display device and a display driving method capable of resolving image defects by stably driving a gate driving circuit. Background Technology

[0003] Representative display devices that display images using digital data include Liquid Crystal Displays (LCDs) using liquid crystals and Organic Light Emitting Diodes (OLEDs).

[0004] Among these display devices, organic light-emitting display devices utilize self-emissive light-emitting diodes, offering advantages such as fast response speed, contrast ratio, luminous efficiency, brightness, and viewing angle. In this case, the light-emitting diodes can be implemented using inorganic or organic materials.

[0005] This organic light-emitting display device includes a light-emitting diode placed in each of a plurality of subpixels arranged on a display panel, and can display an image by controlling the brightness represented by each subpixel by emitting light through voltage control flowing through the light-emitting diode.

[0006] In such a display device, a light-emitting element and a subpixel circuit for driving the light-emitting element may be disposed on the display panel. For example, the subpixel circuit includes a driving transistor that controls the driving current flowing through the light-emitting element, and at least one scan transistor that controls the gate-source voltage of the driving transistor according to a scan signal. The scan transistor of the subpixel circuit may be controlled by a scan signal output from a gate driving circuit disposed on the substrate of the display panel.

[0007] However, as the driving time of the display device increases, the transistors constituting the gate driving circuit deteriorate, which may lead to a decrease in image quality. The problem to be solved

[0009] Accordingly, the inventors of the present disclosure can provide a display device and a display driving method capable of stably operating a gate driving circuit by effectively detecting the deterioration state of the gate driving circuit.

[0010] Embodiments of the present disclosure can provide a display device and a display driving method capable of effectively detecting the degradation state of a gate driving circuit using a sensing voltage for a characteristic value of a subpixel circuit.

[0011] In addition, embodiments of the present disclosure can provide a display device and a display driving method capable of stably operating a gate driving circuit by controlling the gate voltage based on the sensing voltage for the characteristic value of the subpixel circuit. means of solving the problem

[0013] Embodiments of the present disclosure may provide a display device comprising: a display panel having a plurality of subpixels arranged thereon; a gate driving circuit that supplies a plurality of scan signals to the display panel through a plurality of gate lines; a data driving circuit that supplies a plurality of data voltages to the display panel through a plurality of data lines; a power management circuit that supplies a plurality of driving voltages to the gate driving circuit and the data driving circuit; and a timing controller that controls the power management circuit so that the level of the gate voltage applied to the gate driving circuit is changed according to the output state of the gate driving circuit.

[0014] Embodiments of the present disclosure may provide a display driving method comprising the steps of: setting a test gate voltage; detecting a sensing voltage for a characteristic value of a subpixel disposed in a display panel; determining whether the sensing voltage corresponds to a multi-output value; if the sensing voltage corresponds to a multi-output value, setting the test gate voltage to an error gate voltage; determining a stable gate voltage; and applying the stable gate voltage to a gate driving circuit. Effects of the invention

[0016] According to the embodiments of the present disclosure, by effectively detecting the deterioration state of the gate driving circuit, the gate driving circuit can be operated stably.

[0017] In addition, according to the embodiments of the present disclosure, the degradation state of the gate driving circuit can be effectively detected by using the sensing voltage for the characteristic value of the subpixel circuit.

[0018] In addition, according to the embodiments of the present disclosure, by controlling the gate voltage based on the sensing voltage for the characteristic value of the subpixel circuit, the gate driving circuit can be operated stably. Brief explanation of the drawing

[0020] FIG. 1 is a diagram showing the schematic configuration of a display device according to embodiments of the present disclosure. FIG. 2 is a system example diagram of a display device according to embodiments of the present disclosure. FIG. 3 is a diagram of one example of a circuit constituting a subpixel in a display device according to embodiments of the present disclosure. FIG. 4 is a diagram illustrating an example of a display panel in which a gate driving circuit is implemented as a GIP type in a display device according to embodiments of the present disclosure. FIG. 5 is a block diagram showing the schematic configuration of a gate driving circuit in a display device according to embodiments of the present disclosure. FIG. 6 is a diagram showing a plurality of stage circuit configurations constituting a gate driving circuit according to embodiments of the present disclosure. FIG. 7 is a diagram showing a gate driving integrated circuit constituting a gate driving circuit in a display driving circuit according to embodiments of the present disclosure. FIG. 8 is a conceptual diagram illustrating the degradation and occurrence of errors in a gate driving circuit according to driving time in a display device according to embodiments of the present disclosure. FIG. 9 is a diagram illustrating, as an example, the waveform of a scan signal output from a gate driving circuit during a display period and a sensing period in a display device according to embodiments of the present disclosure. Figure 10 is a signal waveform diagram showing the case where a multi-output error occurs in which a scan signal is generated on any gate line due to the degradation of the gate driving integrated circuit. FIG. 11 is a flowchart illustrating a display driving method according to embodiments of the present disclosure. FIG. 12 is a diagram illustrating an example of a circuit for sensing the characteristic value of a driving transistor in a display device according to embodiments of the present disclosure. FIG. 13 is a diagram illustrating an example of a driving timing diagram for detecting a threshold voltage among the characteristic values ​​of a driving transistor in a display device according to embodiments of the present disclosure. FIG. 14 is a diagram illustrating an example of a sensing voltage in a display device according to embodiments of the present disclosure, in which a single output or multiple output occurs depending on the gate voltage. FIG. 15 is a diagram illustrating an example of controlling the level of the gate voltage according to the deterioration state of the gate driving circuit in a display device according to embodiments of the present disclosure. Specific details for implementing the invention

[0021] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0022] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0023] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0024] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0025] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0026] FIG. 1 is a diagram showing the schematic configuration of a display device according to embodiments of the present disclosure.

[0027] Referring to FIG. 1, a display device (100) according to one embodiment of the present specification may include a display panel (110) in which a plurality of gate lines (GL) and data lines (DL) are connected and a plurality of subpixels (SP) are arranged in a matrix form, a gate driving circuit (120) for driving a plurality of gate lines (GL), a data driving circuit (130) for supplying a data voltage through a plurality of data lines (DL), a timing controller (140) for controlling the gate driving circuit (120) and the data driving circuit (130), and a power management circuit (Power Management IC, 150).

[0028] The display panel (110) displays an image based on a scan signal transmitted from a gate driving circuit (120) through a plurality of gate lines (GL) and a data voltage transmitted from a data driving circuit (130) through a plurality of data lines (DL).

[0029] In the case of a liquid crystal display, the display panel (110) includes a liquid crystal layer formed between two substrates and may operate in any known mode, such as a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In Plane Switching) mode, or an FFS (Fringe Field Switching) mode. On the other hand, in the case of an organic light-emitting display, the display panel (110) may be implemented in a top emission method, a bottom emission method, or a dual emission method.

[0030] A display panel (110) may have a plurality of pixels arranged in a matrix form, and each pixel may consist of subpixels (SP) of different colors, for example, a white subpixel, a red subpixel, a green subpixel, and a blue subpixel, and each subpixel (SP) may be defined by a plurality of data lines (DL) and a plurality of gate lines (GL).

[0031] A single subpixel (SP) may include a thin film transistor (TFT) formed in the region where a data line (DL) and a gate line (GL) intersect, a light-emitting element such as an organic light-emitting diode that charges the data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0032] For example, if a display device (100) having a resolution of 2,160 X 3,840 is composed of four subpixels (SP) of white (W), red (R), green (G), and blue (B), a total of 3,840 X 4 = 15,360 data lines (DL) may be provided by 2,160 gate lines (GL) and 3,840 data lines (DL) connected to each of the four subpixels (WRGB), and each subpixel (SP) will be placed at the point where the gate lines (GL) and data lines (DL) intersect.

[0033] The gate driving circuit (120) is controlled by a controller (140) and controls the driving timing for a plurality of subpixels (SP) by sequentially outputting scan signals to a plurality of gate lines (GL) arranged on a display panel (110).

[0034] In a display device (100) having a resolution of 2,160 x 3,840, a case in which a scan signal is output sequentially from the first gate line to the 2,160th gate line for 2,160 gate lines (GL) can be called 2,160-phase driving. Alternatively, a case in which a scan signal is output sequentially in units of 4 gate lines (GL), such as sequentially outputting a scan signal from the first gate line to the 4th gate line and then sequentially outputting a scan signal from the 5th gate line to the 8th gate line, is called 4-phase driving. That is, a case in which a scan signal is output sequentially for every N gate lines (GL) can be called N-phase driving.

[0035] At this time, the gate driving circuit (120) may include one or more gate driving integrated circuits (GDICs), and depending on the driving method, it may be located on only one side of the display panel (110) or on both sides. Alternatively, the gate driving circuit (120) may be embedded in the bezel area of ​​the display panel (110) and implemented in the form of a GIP (Gate In Panel).

[0036] The data driving circuit (130) receives image data (DATA) from the timing controller (140) and converts the received image data (DATA) into an analog data voltage. Then, by outputting the data voltage to each data line (DL) in accordance with the timing at which a scan signal is applied through the gate line (GL), each subpixel (SP) connected to the data line (DL) displays a light emission signal of brightness corresponding to the data voltage.

[0037] Likewise, the data driving circuit (130) may include one or more source driving integrated circuits (SDICs), and the source driving integrated circuits (SDICs) may be connected to the bonding pads of the display panel (110) or placed directly on the display panel (110) using a tape-automated bonding (TAB) method or a chip-on-glass (COG) method.

[0038] In some cases, each source driving integrated circuit (SDIC) may be integrated and placed on the display panel (110). Additionally, each source driving integrated circuit (SDIC) may be implemented using a COF (Chip On Film) method, in which case each source driving integrated circuit (SDIC) may be mounted on a circuit film and electrically connected to the data line (DL) of the display panel (110) through the circuit film.

[0039] The timing controller (140) supplies various control signals to the gate driving circuit (120) and the data driving circuit (130) and controls the operation of the gate driving circuit (120) and the data driving circuit (130). That is, the timing controller (140) controls the gate driving circuit (120) to output a scan signal according to the timing implemented in each frame, and on the other hand, transmits image data (DATA) received from the outside to the data driving circuit (130).

[0040] At this time, the timing controller (140) receives various timing signals, including a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable; DE), and a main clock (MCLK), along with video data (DATA) from an external host system (200).

[0041] The host system (200) can be any one of a TV (Television) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, or a wearable device.

[0042] Accordingly, the timing controller (140) generates a control signal using various timing signals received from the host system (200) and transmits it to the gate driving circuit (120) and the data driving circuit (130).

[0043] For example, the timing controller (140) outputs various gate control signals, including a Gate Start Pulse (GSP), a Gate Clock (GCLK), and a Gate Output Enable signal (GOE), to control the gate driving circuit (120). Here, the Gate Start Pulse (GSP) controls the timing at which one or more Gate Driving Integrated Circuits (GDICs) constituting the gate driving circuit (120) begin operation. Additionally, the Gate Clock (GCLK) is a clock signal commonly input to one or more Gate Driving Integrated Circuits (GDICs) and controls the shift timing of the scan signal. Additionally, the Gate Output Enable signal (GOE) specifies the timing information of one or more Gate Driving Integrated Circuits (GDICs).

[0044] Additionally, the timing controller (140) outputs various data control signals, including a Source Start Pulse (SSP), a Source Sampling Clock (SCLK), and a Source Output Enable Signal (SOE), to control the data driving circuit (130). Here, the Source Start Pulse (SSP) controls the timing at which one or more source driving integrated circuits (SDICs) constituting the data driving circuit (130) begin data sampling. The Source Sampling Clock (SCLK) is a clock signal that controls the timing of data sampling by the source driving integrated circuit (SDIC). The Source Output Enable Signal (SOE) controls the output timing of the data driving circuit (130).

[0045] Such a display device (100) may include a power management circuit (150) that supplies various voltages or currents to a display panel (110), a gate driving circuit (120), a data driving circuit (130), etc., or controls various voltages or currents to be supplied.

[0046] The power management circuit (150) adjusts the DC input voltage (Vin) supplied from the host system (200) to generate the power required to drive the display panel (100), the gate driving circuit (120), and the data driving circuit (130).

[0047] Meanwhile, a subpixel (SP) is located at the point where the gate line (GL) and the data line (DL) intersect, and a light-emitting element may be placed in each subpixel (SP). For example, an organic light-emitting display device includes a light-emitting element, such as an organic light-emitting diode, in each subpixel (SP), and can display an image by controlling the current flowing through the light-emitting element according to the data voltage.

[0048] These display devices (100) can be of various types, such as liquid crystal displays, organic light-emitting displays, and plasma display panels.

[0049] FIG. 2 is a system example diagram of a display device according to embodiments of the present disclosure.

[0050] Referring to FIG. 2, the display device (100) according to embodiments of the present disclosure shows a case in which the source driving integrated circuit (SDIC) included in the data driving circuit (130) is implemented in a COF (Chip On Film) manner among various methods (TAB, COG, COF, etc.) and the gate driving circuit (120) is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

[0051] When the gate driving circuit (120) is implemented in the form of a GIP, a plurality of gate driving integrated circuits (GDICs) included in the gate driving circuit (120) can be directly formed in the bezel area of ​​the display panel (110). At this time, the gate driving integrated circuits (GDICs) can receive various signals (clock signal, gate high signal, gate low signal, etc.) required for generating a scan signal through gate driving related signal wiring placed in the bezel area.

[0052] Likewise, one or more source driving integrated circuits (SDICs) included in the data driving circuit (130) may each be mounted on a source film (SF), and one side of the source film (SF) may be electrically connected to a display panel (110). Additionally, wiring for electrically connecting the source driving integrated circuit (SDIC) and the display panel (110) may be arranged on the upper side of the source film (SF).

[0053] The display device (100) may include at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) for mounting control components and various electrical devices for circuit connection between a plurality of source driving integrated circuits (SDIC) and other devices.

[0054] At this time, the other side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted can be connected to at least one source printed circuit board (SPCB). That is, one side of the source film (SF) on which the source driving integrated circuit (SDIC) is mounted can be electrically connected to the display panel (110), and the other side can be electrically connected to the source printed circuit board (SPCB).

[0055] A timing controller (140) and a power management circuit (Power Management IC, 150) may be mounted on a control printed circuit board (CPCB). The timing controller (140) can control the operation of a data driving circuit (130) and a gate driving circuit (120). The power management circuit (150) may supply driving voltage or current to a display panel (110), a data driving circuit (130), and a gate driving circuit (120), and may control the supplied voltage or current.

[0056] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be circuitously connected through at least one connecting member, and the connecting member may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. In addition, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be implemented by integrating them into a single printed circuit board.

[0057] The display device (100) may further include a set board (170) electrically connected to a control printed circuit board (CPCB). In this case, the set board (170) may also be referred to as a power board. The set board (170) may contain a main power management circuit (M-PMC, 160) that manages the total power of the display device (100). The main power management circuit (160) may be linked with a power management circuit (150).

[0058] In the case of a display device (100) configured as above, the driving voltage is generated at the set board (170) and transmitted to the power management circuit (150) within the control printed circuit board (CPCB). The power management circuit (150) transmits the driving voltage required for display driving or characteristic value sensing to the source printed circuit board (SPCB) via the flexible printed circuit (FPC) or flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board (SPCB) is supplied to emit light or sense a specific subpixel (SP) within the display panel (110) via the source driving integrated circuit (SDIC).

[0059] At this time, each subpixel (SP) arranged in the display panel (110) within the display device (100) may be composed of a light-emitting element and a circuit element such as a driving transistor for driving it.

[0060] The types and number of circuit elements constituting each subpixel (SP) can be determined in various ways depending on the provided functions and design methods.

[0061] FIG. 3 is a diagram of one example of a circuit constituting a subpixel in a display device according to embodiments of the present disclosure.

[0062] Referring to FIG. 3, in a display device (100) according to embodiments of the present disclosure, a subpixel (SP) may include one or more transistors and capacitors, and a light-emitting element may be disposed therein.

[0063] For example, a subpixel (SP) may include a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), a storage capacitor (Cst), and a light-emitting diode (ED).

[0064] The driving transistor (DRT) has a first node (N1), a second node (N2), and a third node (N3). The first node (N1) of the driving transistor (DRT) may be a gate node to which a data voltage (Vdata) is applied from the data driving circuit (130) through the data line (DL) when the switching transistor (SWT) is turned on.

[0065] The second node (N2) of the driving transistor (DRT) can be electrically connected to the anode electrode of the light-emitting diode (ED) and can be a source node or a drain node.

[0066] The third node (N3) of the driving transistor (DRT) is electrically connected to the driving voltage line (DVL) to which the subpixel driving voltage (EVDD) is applied, and may be a drain node or a source node.

[0067] At this time, during the display driving period, the subpixel driving voltage (EVDD) required to display the image can be supplied through the driving voltage line (DVL), for example, the subpixel driving voltage (EVDD) required to display the image can be 27V.

[0068] The switching transistor (SWT) is electrically connected between the first node (N1) of the driving transistor (DRT) and the data line (DL), and the gate line (GL) is connected to the gate node and operates according to the first scan signal (SCAN1) supplied through the gate line (GL). In addition, when the switching transistor (SWT) is turned on, the operation of the driving transistor (DRT) is controlled by transmitting the data voltage (Vdata) supplied through the data line (DL) to the gate node of the driving transistor (DRT).

[0069] The sensing transistor (SENT) is electrically connected between the second node (N2) of the driving transistor (DRT) and the reference voltage line (RVL), and operates according to the second scan signal (SCAN2) supplied through the gate line (GL). When the sensing transistor (SENT) is turned on, the reference voltage (Vref) supplied through the reference voltage line (RVL) is delivered to the second node (N2) of the driving transistor (DRT).

[0070] That is, by controlling the switching transistor (SWT) and the sensing transistor (SENT), the voltage at the first node (N1) and the voltage at the second node (N2) of the driving transistor (DRT) are controlled, thereby enabling the supply of current to drive the light-emitting diode (ED).

[0071] The gate nodes of the switching transistor (SWT) and the sensing transistor (SENT) may be connected together to a single gate line (GL) or to different gate lines (GL). Here, a structure in which the switching transistor (SWT) and the sensing transistor (SENT) are connected to different gate lines (GL) is shown as an example, and in this case, the switching transistor (SWT) and the sensing transistor (SENT) can be independently controlled by a first scan signal (SCAN1) and a second scan signal (SCAN2) transmitted through different gate lines (GL).

[0072] On the other hand, when the switching transistor (SWT) and the sensing transistor (SENT) are connected to a single gate line (GL), the switching transistor (SWT) and the sensing transistor (SENT) can be simultaneously controlled by a first scan signal (SCAN1) or a second scan signal (SCAN2) transmitted through the single gate line (GL), and the aperture ratio of the subpixel (SP) can be increased.

[0073] Meanwhile, the transistors placed in the subpixel (SP) can consist of not only n-type transistors but also p-type transistors; however, the case composed of n-type transistors is shown here as an example.

[0074] The storage capacitor (Cst) is electrically connected between the first node (N1) and the second node (N2) of the driving transistor (DRT) and maintains the data voltage (Vdata) for one frame.

[0075] These storage capacitors (Cst) may be connected between the first node (N1) and the third node (N3) of the driving transistor (DRT) depending on the type of driving transistor (DRT). The anode electrode of the light-emitting diode (ED) may be electrically connected to the second node (N2) of the driving transistor (DRT), and a base voltage (EVSS) may be applied to the cathode electrode of the light-emitting diode (ED).

[0076] Here, the base voltage (EVSS) may be a ground voltage or a voltage higher or lower than the ground voltage. Additionally, the electromotive force voltage (EVSS) may vary depending on the driving state, for example, the base voltage (EVSS) at the time of display driving and the base voltage (EVSS) at the time of sensing driving may be set differently from each other.

[0077] The switching transistor (SWT) and the sensing transistor (SENT) can be described as scan transistors controlled by scan signals (SCAN1, SCAN2).

[0078] The structure of these subpixels (SPs) may include one or more additional transistors, or in some cases, one or more additional capacitors.

[0079] The display device (100) of the present disclosure may use a method of measuring the current flowing by the voltage charged to the storage capacitor (Cst) during the characteristic value sensing period of the driving transistor (DRT) in order to effectively sense the characteristic value of the driving transistor (DRT), for example, threshold voltage or mobility, and this is called current sensing.

[0080] That is, by measuring the current flowing due to the voltage charged in the storage capacitor (Cst) during the characteristic value sensing period of the driving transistor (DRT), the characteristic value of the driving transistor (DRT) within the subpixel (SP) or the change in the characteristic value can be determined.

[0081] In this case, since the reference voltage line (RVL) not only serves to transmit the reference voltage (Vref) but also acts as a sensing line to sense the characteristic value of the driving transistor (DRT) within the subpixel, the reference voltage line (RVL) may also be referred to as a sensing line or a sensing channel.

[0082] More specifically, the characteristic value or change in the characteristic value of the driving transistor (DRT) can correspond to the difference between the gate node voltage and the source node voltage of the driving transistor (DRT).

[0083] Compensation of the characteristic value of such driving transistors (DRT) can be performed as internal compensation, which senses and compensates the characteristic value of the driving transistors (DRT) within the subpixel (SP) without using additional external configuration, or as external compensation, which senses and compensates the characteristic value of the driving transistors (DRT) using an external compensation circuit.

[0084] At this time, external compensation may be performed before shipment of the display device (100), and internal compensation may be performed after shipment of the display device (100), but internal compensation and external compensation may also be performed together after shipment of the display device (100).

[0085] FIG. 4 is a diagram illustrating an example of a display panel in which a gate driving circuit is implemented as a GIP type in a display device according to embodiments of the present disclosure.

[0086] Referring to FIG. 4, in a display device (100) according to embodiments of the present disclosure, 2n gate lines (GL(1) ~ GL(2n), n is a natural number) may be arranged in a display area (A / A) that displays an image on a display panel (110).

[0087] At this time, the gate driving circuit (120) is embedded in a non-display area corresponding to the outer edge of the display area (A / A) of the display panel (110) and may include 2n gate lines (GL(1) ~ GL(2n)) and 2n GIP circuits (GIPC: GIP Circuit) corresponding to each other.

[0088] Therefore, 2n GIP circuits (GIPC) can output a scan signal (SCAN) with 2n gate lines (GL(1) to GL(2n)).

[0089] In this way, when the gate driving circuit (120) is implemented as a GIP type, there is no need to manufacture a separate integrated circuit with a gate driving function and bond it to the display panel (110), so the number of integrated circuits can be reduced and the process of connecting the integrated circuits to the display panel (110) can be omitted. In addition, the size of the bezel area for bonding the integrated circuits to the display panel (110) can be reduced.

[0090] 2n GIP circuits (GIPC) can be distinguished from each other and identified as GIPC (1), GIPC (2), … GIPC (2n) in order to identify the correspondence with 2n gate lines (GL (1) ~ GL (2n)).

[0091] Here, a case is illustrated in which 2n GIP circuits (GIPC(1) to GIPC(2n)) are divided and arranged on both sides of a display area (A / A). For example, among the 2n GIP circuits (GIPC(1) to GIPC(2n)), the odd-numbered GIP circuits (GIPC(1), GIPC(3), …, GIPC(2n-1)) can drive the odd-numbered gate lines (GL(1), GL(3), …, GL(2n-1)). Among the 2n GIP circuits (GIPC(1) to GIPC(2n)), the even-numbered GIP circuits (GIPC(2), GIPC(4), …, GIPC(2n)) can drive the even-numbered gate lines (GL(2), GL(4), …, GL(2n)).

[0092] Alternatively, 2n GIP circuits (GIPC (1) to GIPC (2n)) may be placed on only one side of the display area (A / A).

[0093] A plurality of clock signal lines (CL) for transmitting a gate clock required for generating and outputting a scan signal (SCAN) to a gate driving circuit (120) may be arranged in a non-display area corresponding to the outer edge of the display area (A / A) of the display panel (110).

[0094] FIG. 5 is a block diagram showing the schematic configuration of a gate driving integrated circuit in a display device according to embodiments of the present disclosure.

[0095] Referring to FIG. 5, in a display device (100) according to embodiments of the present disclosure, one gate driving integrated circuit may include a shift register (Shift Register, 122) and a buffer circuit (124).

[0096] The gate driver integrated circuit starts operating according to the gate start pulse (GSP) and outputs a scan signal (SCAN) according to the gate clock (GCLK). The scan signal (SCAN) output from the gate driver integrated circuit is sequentially shifted and supplied sequentially through the gate line (GL).

[0097] The buffer circuit (124) has two nodes (Q, QB) important for the gate driving state and may include a pull-up transistor (TU) and a pull-down transistor (TD). Here, the gate node of the pull-up transistor (TU) may correspond to the Q node, and the gate node of the pull-down transistor (TD) may correspond to the QB node.

[0098] The shift register (122) can also be called a shift logic circuit and can be used to generate a scan signal (SCAN) synchronized with the gate clock (GCLK).

[0099] The shift register (122) can control the Q node and QB node connected to the buffer circuit (124) so ​​that the buffer circuit (124) can output a scan signal (SCAN), and for this purpose, it may include a plurality of transistors.

[0100] The shift register (122) starts generating a scan signal (SCAN) and the output of the shift register (122) is turned on sequentially according to the gate clock (GCLK). That is, by controlling the output time of the shift register (122) using the gate clock (GCLK), the logic state determining the on / off of the gate line (GL) can be transmitted to the buffer circuit (124).

[0101] According to this shift register (122), the voltage state of each of the Q node and QB node of the buffer circuit (124) may change. Accordingly, the buffer circuit (124) may output a voltage to turn on the corresponding gate line (GL) (e.g., corresponding to a high level voltage or a low level voltage, and may be a signal having a gate high voltage (VGH), for example) to the corresponding gate line (GL), or output a voltage to turn off the corresponding gate line (GL) (e.g., corresponding to a low level voltage or a high level voltage, and may be a base voltage (VSS) having a gate low voltage (VGL), for example) to the corresponding gate line (GL).

[0102] Meanwhile, a gate driving integrated circuit may further include a level shifter in addition to the shift register (122) and buffer circuit (124).

[0103] At this time, the shift register (122) and buffer circuit (124) constituting the gate driving integrated circuit can be connected in various structures.

[0104] FIG. 6 is a diagram showing a plurality of stage circuit configurations constituting a gate driving circuit according to embodiments of the present disclosure.

[0105] Referring to FIG. 6, a gate driving circuit (120) according to another embodiment of the present specification includes a first to k-th stage circuit (ST(1) to ST(k)) (k is a positive integer), a gate voltage line (131), a clock signal line (132), a line sensing signal line (133), and a reset signal line (134).

[0106] Here, each stage circuit (ST) may correspond to a gate driving integrated circuit (GDIC) or GIP circuit (GIPC) that constitutes the gate driving circuit (120).

[0107] Additionally, the gate driving circuit (120) may further include a front dummy stage circuit (DST1) placed at the front end of the first stage circuit (ST(1)) and a rear dummy stage circuit (DST2) placed at the rear end of the k-th stage circuit (ST(k)).

[0108] The gate voltage line (131) supplies a high potential gate voltage (GVDD) and a low potential gate voltage (GVSS) supplied from the power management circuit (150) to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2), respectively.

[0109] The gate voltage line (131) may include a plurality of high-potential gate voltage lines supplying a plurality of high-potential gate voltages having different voltage levels and a plurality of low-potential gate voltage lines supplying a plurality of low-potential gate voltages having different voltage levels.

[0110] For example, the gate voltage line (131) may include three high-potential gate voltage lines supplying a first high-potential gate voltage (GVDD1), a second high-potential gate voltage (GVDD2), and a third high-potential gate voltage (GVDD3) having different voltage levels, respectively, and three low-potential gate voltage lines supplying a first low-potential gate voltage (GVSS1), a second low-potential gate voltage (GVSS2), and a third low-potential gate voltage (GVSS3) having different voltage levels, respectively. However, this is only one example, and the number of lines included in the gate voltage line (131) may vary depending on the embodiment.

[0111] The clock signal line (132) supplies a plurality of clock signals (CLKs), such as a carry clock or a scan clock, supplied from the timing controller (140) to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2), respectively.

[0112] The line sensing signal line (133) supplies a line sensing signal (LSP) supplied from the timing controller (140) to the first to k-th stage circuits (ST(1) to ST(k)). Optionally, the line sensing signal line (133) may be additionally connected to the front dummy stage circuit (DST1).

[0113] The reset signal line (134) supplies a reset signal (RESET) supplied from the timing controller (140) to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2), respectively.

[0114] The panel on signal line (135) supplies the panel on signal (POS) supplied from the timing controller (140) to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2), respectively.

[0115] In addition, lines for supplying other signals other than the lines (131, 132, 133, 134) shown herein may be additionally connected to the first to k-th stage circuits (ST(1) to ST(k)), the front dummy stage circuit (DST1), and the rear dummy stage circuit (DST2). For example, a line for supplying a gate start pulse (GSP) to the front dummy stage circuit (DST1) may be additionally connected to the front dummy stage circuit (DST1).

[0116] The shear dummy stage circuit (DST1) outputs a shear carry signal (Cd1) in response to the input of a gate start pulse (GSP) supplied from the timing controller (140).

[0117] The front-end carry signal (Cd1) can be supplied to any one of the first to k-th stage circuits (ST(1) to ST(k)).

[0118] The rear dummy stage circuit (DST2) outputs a rear carry signal (Cd2). The rear carry signal (Cd2) can be supplied to any one of the first to k-th stage circuits (ST(1) to ST(k)).

[0119] The first to k-th stage circuits (ST(1) to ST(k)) can be connected to each other in a stepped or cascaded manner.

[0120] The first to k-th stage circuits (ST(1) to ST(k)) each output j scan signals (SCAN) and one carry signal (C) (j is a positive integer). That is, any stage circuit outputs the first to j-th scan signals and one carry signal (C).

[0121] For example, each stage circuit outputs four scan signals (SCAN) and one carry signal (C). For example, the first stage circuit (ST(1)) outputs a first scan signal (SCAN(1)), a second scan signal (SCAN(2)), a third scan signal (SCAN(3)), a fourth scan signal (SCAN(4)), and a first carry signal (C(1)), and the second stage circuit (ST(2)) outputs a fifth scan signal (SCAN(5)), a sixth scan signal (SCAN(6)), a seventh scan signal (SCAN(7)), an eighth scan signal (SCAN(8)), and a second carry signal (C(2)). Thus, in the embodiment here, j is 4.

[0122] The number of scan signals output by the first to k-th stage circuits (ST(1) to ST(k)) corresponds to the number (n) of gate lines (15) arranged on the display panel (10). As described above, each stage circuit outputs j scan signals. Therefore, the relationship j × k = n holds.

[0123] For example, when j=4, the number of stage circuits (k) is 1 / 4 of the number of gate lines (GL) (n). However, the number of scan signals output by each stage circuit is not limited to this. That is, in the embodiments of the present disclosure, each stage circuit may output one, two, or three scan signals, or may output five or more scan signals. The number of stage circuits may vary depending on the number of scan signals output by each stage circuit.

[0124] The scan signal (SCAN) output by the first to k-th stage circuits (ST(1) to ST(k)) may be a scan signal for sensing the threshold voltage of a driving transistor (DRT) or a gate signal for image display. Additionally, the carry signal (C) output by the first to k-th stage circuits (ST(1) to ST(k)) may be supplied to different stage circuits. Here, the carry signal supplied to any stage circuit from the front stage circuit is referred to as the front carry signal, and the carry signal supplied from the rear stage circuit is referred to as the rear carry signal.

[0125] FIG. 7 is a diagram illustrating an example of a stage circuit constituting a gate driving circuit in a display driving circuit according to embodiments of the present disclosure.

[0126] Referring to FIG. 7, the stage circuit according to embodiments of the present disclosure includes an M node, a Q node, and a QB node, and includes a line selection unit (502), a Q node control unit (504), a Q node stabilization unit (506), an inverter unit (508), a QB node stabilization unit (510), a carry signal output unit (512), and a scan signal output unit (514).

[0127] The line selector (502) charges the M node based on the front-end carry signal (C(k-2)) in response to the input of the line sensing signal (LSP). Additionally, the line selector (502) charges the Q node to the level of the first high-potential gate voltage (GVDD1) based on the charging voltage of the M node in response to the input of the reset signal (RESET). Additionally, the line selector (502) discharges or resets the Q node to the level of the third low-potential gate voltage (GVSS3) in response to the input of the panel-on signal (POS).

[0128] The line selection unit (502) includes 11th to 17th transistors (T11 to T17) and a pre-charging capacitor (CA).

[0129] The 11th transistor (T11) and the 12th transistor (T12) are connected between the first high-potential gate voltage line, which carries the first high-potential gate voltage (GVDD1), and the M node. Additionally, the 11th transistor (T11) and the 12th transistor (T12) are connected in series with each other.

[0130] The 11th transistor (T11) outputs a front-end carry signal (C(k-2)) to the first connection node (NC1) in response to the input of the line sensing signal (LSP).

[0131] The 12th transistor (T12) electrically connects the first connection node (NC1) to the M node in response to the input of a line sensing signal (LSP). For example, when a high voltage line sensing signal (LSP) is input to the 11th transistor (T11) and the 12th transistor (T12), the 11th transistor (T11) and the 12th transistor (T12) are turned on simultaneously, and the M node is charged to the level of the first high potential gate voltage (GVDD1).

[0132] The 13th transistor (T13) is turned on when the voltage level of the M node is high, and supplies the first high potential gate voltage (GVDD1) to the first connection node (NC1). When the first high potential gate voltage (GVDD1) is supplied to the first connection node (NC1), the voltage difference between the gate voltage of the 11th transistor (T11) and the first connection node (NC1) increases.

[0133] Accordingly, when a low-level line sensing signal (LSP) is input to the gate node of the 11th transistor (T11) and the 11th transistor (T11) is turned off, the 11th transistor (T11) can be kept in a completely turned-off state due to the voltage difference between the gate voltage of the 11th transistor (T11) and the first connection node (NC1). Accordingly, current leakage of the 11th transistor (T11) and the resulting voltage drop of the M node are prevented, so the voltage of the M node can be maintained stably.

[0134] A pre-charging capacitor (CA) is connected between the first high-potential gate voltage line that delivers the first high-potential gate voltage (GVDD1) and the M node to store the difference between the first high-potential gate voltage (GVDD1) and the voltage charged at the M node.

[0135] When the 11th transistor (T11), the 12th transistor (T12), and the 13th transistor (T13) are turned on, the pre-charging capacitor (CA) stores the high voltage of the front-end carry signal (C(k-2)). When the 11th transistor (T11), the 12th transistor (T12), and the 13th transistor (T13) are turned off, the pre-charging capacitor (CA) maintains the voltage of the M node for a certain period of time with the stored voltage.

[0136] The 14th transistor (T14) and the 15th transistor (T15) are connected between the first high-potential gate voltage line, which carries the first high-potential gate voltage (GVDD1), and the Q node. The 14th transistor (T14) and the 15th transistor (T15) are connected in series with each other.

[0137] The 14th transistor (T14) and the 15th transistor (T15) charge the Q node to the first high potential gate voltage (GVDD1) in response to the voltage of the M node and the input of the reset signal (RESET).

[0138] The 14th transistor (T14) is turned on when the voltage of the M node is at a high level to deliver the first high potential gate voltage (GVDD1) to the shared node of the 14th transistor (T14) and the 15th transistor (T15).

[0139] The 15th transistor (T15) is turned on by a high-level reset signal (RESET) to supply the voltage of the shared node to the Q node. Thus, when the 14th transistor (T14) and the 15th transistor (T15) are turned on simultaneously, the Q node is charged to the first high-potential gate voltage (GVDD1).

[0140] The 16th transistor (T16) and the 17th transistor (T17) are connected between the Q node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3). The 16th transistor (T16) and the 17th transistor (T17) are connected in series with each other.

[0141] The 16th transistor (T16) and the 17th transistor (T17) discharge the Q node to the third low-potential gate voltage (GVSS3) in response to the input of the panel-on signal (POS). Discharging the Q node to the third low-potential gate voltage (GVSS3) can also be expressed as the Q node being reset.

[0142] The 17th transistor (T17) is turned on by the input of a high-level panel-on signal (POS) to supply a third low-potential gate voltage (GVSS3) to the QH node.

[0143] The 16th transistor (T16) is turned on upon input of a high-level panel-on signal (POS) to electrically connect the Q node and the QH node. Thus, when the 16th transistor (T16) and the 17th transistor (T17) are turned on simultaneously, the Q node is discharged or reset to the third low-potential gate voltage (GVSS3).

[0144] The Q node control unit (504) charges the Q node to the level of the first high potential gate voltage (GVDD1) in response to the input of the front carry signal (C(k-2)), and discharges the Q node to the level of the third low potential gate voltage (GVSS3) in response to the input of the rear carry signal (C(k+2)).

[0145] The Q node control unit (504) includes 21 to 28 transistors (T21 to T28).

[0146] The 21st transistor (T21) and the 22nd transistor (T22) are connected between the first high-potential gate voltage line and the Q node, which transmits the first high-potential gate voltage (GVDD1). The 21st transistor (T21) and the 22nd transistor (T22) are connected in series with each other.

[0147] The 21st transistor (T21) and the 22nd transistor (T22) charge the Q node to the first high potential gate voltage (GVDD1) level in response to the input of the front-end carry signal (C(k-2)).

[0148] The 21st transistor (T21) is turned on upon input of the front-end carry signal (C(k-2)) to supply the first high-potential gate voltage (GVDD1) to the second connection node (NC2).

[0149] The 22nd transistor (T22) is turned on upon input of the front-end carry signal (C(k-2)) to electrically connect the 2nd connection node (NC2) and the Q node. Thus, when the 21st transistor (T21) and the 22nd transistor (T22) are turned on simultaneously, the 1st high-potential gate voltage (GVDD1) is supplied to the Q node.

[0150] The 25th transistor (T25) and the 26th transistor (T26) are connected to a third high-potential gate voltage line that delivers a third high-potential gate voltage (GVDD3). The 25th transistor (T25) and the 26th transistor (T26) supply the third high-potential gate voltage (GVDD3) to the second connection node (NC2) in response to the third high-potential gate voltage (GVDD3).

[0151] The 25th transistor (T25) and the 26th transistor (T26) are simultaneously turned on by the third high potential gate voltage (GVDD3) to continuously supply the third high potential gate voltage (GVDD3) to the second connection node (NC2), thereby increasing the voltage difference between the gate voltage of the 21st transistor (T21) and the second connection node (NC2). Therefore, when a low-level front-end carry signal (C(k-2)) is input to the gate node of the 21st transistor (T21) and the 21st transistor (T21) is turned off, the 21st transistor (T21) can be kept in a completely turned-off state due to the voltage difference between the gate voltage of the 21st transistor (T21) and the second connection node (NC2).

[0152] Accordingly, current leakage of the 21st transistor (T21) and the resulting voltage drop of the Q node are prevented, so the voltage of the Q node can be maintained stably.

[0153] For example, when the threshold voltage of the 21st transistor (T21) is negative (-), the gate-source voltage (Vgs) of the 21st transistor (T21) is maintained as negative (-) by the third high potential gate voltage (GVDD3) supplied to the drain electrode.

[0154] Therefore, when a low-level front-end carry signal (C(k-2)) is input to the gate node of the 21st transistor (T21) and the 21st transistor (T21) is turned off, the 21st transistor (T21) remains in a completely turned-off state, thereby preventing the occurrence of leakage current.

[0155] Here, the third high potential gate voltage (GVDD3) is set to a voltage level lower than the first high potential gate voltage (GVDD1).

[0156] The 23rd transistor (T23) and the 24th transistor (T24) are connected between the Q node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3). The 23rd transistor (T23) and the 24th transistor (T24) are connected in series with each other.

[0157] The 23rd transistor (T23) and the 24th transistor (T24) discharge the Q node and QH node to the 3rd low potential gate voltage (GVSS3) level in response to the input of the rear carry signal (C(k+2)).

[0158] The 24th transistor (T24) is turned on upon input of the subsequent carry signal (C(k+2)) to discharge the QH node to the level of the third low potential gate voltage (GVSS3). The 23rd transistor (T23) is turned on upon input of the subsequent carry signal (C(k+2)) to electrically connect the Q node and the QH node. Therefore, when the 23rd transistor (T23) and the 24th transistor (T24) are turned on simultaneously, the Q node and the QH node are discharged or reset to the level of the third low potential gate voltage (GVSS3), respectively.

[0159] The 27th transistor (T27) and the 28th transistor (T28) are connected between the first high-potential gate voltage line carrying the first high-potential gate voltage (GVDD1) and the Q node, and between the first high-potential gate voltage line carrying the first high-potential gate voltage (GVDD1) and the QH node. The 27th transistor (T27) and the 28th transistor (T28) are connected in series with each other.

[0160] The 27th transistor (T27) and the 28th transistor (T28) supply a first high potential gate voltage (GVDD1) to the QH node in response to the voltage of the Q node. The 27th transistor (T27) is turned on when the voltage of the Q node is at a high level and supplies the first high potential gate voltage (GVDD1) to the shared node of the 27th transistor (T27) and the 28th transistor (T28).

[0161] The 28th transistor (T28) is turned on when the voltage of the Q node is at a high level to electrically connect the shared node and the QH node. Thus, the 27th transistor (T27) and the 28th transistor (T28) are turned on simultaneously when the voltage of the Q node is at a high level to supply the first high potential gate voltage (GVDD1) to the QH node.

[0162] When the first high potential gate voltage (GVDD1) is supplied to the QH node, the voltage difference between the gate node of the 23rd transistor (T23) and the QH node increases. Therefore, when a low-level rear carry signal (C(k+2)) is input to the gate node of the 23rd transistor (T23) and the 23rd transistor (T23) is turned off, the 23rd transistor (T23) can be kept in a completely turned-off state due to the voltage difference between the gate voltage of the 23rd transistor (T23) and the QH node. Accordingly, current leakage of the 23rd transistor (T23) and the resulting voltage drop of the Q node are prevented, and the voltage of the Q node can be maintained stably.

[0163] The Q node stabilization unit (506) discharges the Q node and QH node to the level of the third low potential gate voltage (GVSS3) in response to the voltage of the QB node. The Q node stabilization unit (506) includes a 31st transistor (T31) and a 32nd transistor (T32). The 31st transistor (T31) and the 32nd transistor (T32) are connected between the Q node and the third low potential gate voltage line that transmits the third low potential gate voltage (GVSS3). The 31st transistor (T31) and the 32nd transistor (T32) are connected in series with each other.

[0164] The 31st transistor (T31) and the 32nd transistor (T32) discharge the Q node and the QH node to the level of the third low potential gate voltage (GVSS3) in response to the voltage of the QB node. The 32nd transistor (T32) is turned on when the voltage of the QB node is at a high level to supply the third low potential gate voltage (GVSS3) to the shared node of the 31st transistor (T31) and the 32nd transistor (T32).

[0165] The 31st transistor (T31) is turned on when the voltage of the QB node is at a high level, electrically connecting the Q node and the QH node. Thus, when the 31st transistor (T31) and the 32nd transistor (T32) are turned on simultaneously in response to the voltage of the QB node, the Q node and the QH node are discharged or reset to the level of the third low potential gate voltage (GVSS3), respectively.

[0166] The inverter section (508) changes the voltage level of the QB node according to the voltage level of the Q node. The inverter section (508) includes the 41st to 45th transistors (T41 to T45).

[0167] The 42nd transistor (T42) and the 43rd transistor (T43) are connected between the second high-potential gate voltage line, which carries the second high-potential gate voltage (GVDD2), and the third connection node (NC3). The 42nd transistor (T42) and the 43rd transistor (T43) are connected in series with each other.

[0168] The 42nd transistor (T42) and the 43rd transistor (T43) supply the 2nd high-potential gate voltage (GVDD2) to the 3rd connection node (NC3) in response to the 2nd high-potential gate voltage (GVDD2). The 42nd transistor (T42) is turned on by the 2nd high-potential gate voltage (GVDD2) to supply the 2nd high-potential gate voltage (GVDD2) to the shared node of the 42nd transistor (T42) and the 43rd transistor (T43).

[0169] The 43rd transistor (T43) is turned on by the second high potential gate voltage (GVDD2) to electrically connect the shared node of the 42nd transistor (T42) and the 43rd transistor (T43) with the third connection node (NC3). Thus, when the 42nd transistor (T42) and the 43rd transistor (T43) are turned on simultaneously by the second high potential gate voltage (GVDD2), the third connection node (NC3) is charged to the level of the second high potential gate voltage (GVDD2).

[0170] The 44th transistor (T44) is connected between the 3rd connection node (NC3) and the 2nd low-potential gate voltage line that carries the 2nd low-potential gate voltage (GVSS2).

[0171] The 44th transistor (T44) supplies a second low-potential gate voltage (GVSS2) to the third connection node (NC3) in response to the voltage of the Q node. The 44th transistor (T44) is turned on when the voltage of the Q node is at a high level to discharge or reset the third connection node (NC3) to the second low-potential gate voltage (GVSS2).

[0172] The 41st transistor (T41) is connected between the second high-potential gate voltage line, which carries the second high-potential gate voltage (GVDD2), and the QB node.

[0173] The 41st transistor (T41) supplies a second high-potential gate voltage (GVDD2) to the QB node in response to the voltage of the third connection node (NC3). The 41st transistor (T41) is turned on when the voltage of the third connection node (NC3) is at a high level to charge the QB node to the level of the second high-potential gate voltage (GVDD2).

[0174] The 45th transistor (T45) is connected between the QB node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3).

[0175] The 45th transistor (T45) supplies a third low potential voltage (GVSS3) to the QB node in response to the voltage of the Q node. The 45th transistor (T45) is turned on when the voltage of the Q node is at a high level to discharge or reset the QB node to the third low potential gate voltage (GVSS3) level.

[0176] The QB node stabilization unit (510) discharges the QB node to the level of the third low potential gate voltage (GVSS3) in response to the input of the rear carry signal (C(k-2)), the input of the reset signal (RESET), and the charging voltage of the M node. The QB node stabilization unit (510) includes the 51st to 53rd transistors (T51 to T53).

[0177] The 51st transistor (T51) is connected between the QB node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3).

[0178] The 51st transistor (T51) supplies a third low-potential gate voltage (GVSS3) to the QB node in response to the input of the rear carry signal (C(k-2)).

[0179] The 52nd transistor (T52) and the 53rd transistor (T53) are connected between the QB node and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3). The 52nd transistor (T52) and the 53rd transistor (T53) are connected in series with each other.

[0180] The 52nd transistor (T52) and the 53rd transistor (T53) discharge the QB node to the 3rd low potential gate voltage (GVSS3) level in response to the input of the reset signal (RESET) and the charging voltage of the M node.

[0181] The 53rd transistor (T53) is turned on when the voltage of the M node is at a high level and supplies a third low-potential gate voltage (GVSS3) to the shared node of the 52nd transistor (T52) and the 53rd transistor (T53).

[0182] The 52nd transistor (T52) is turned on by the input of a reset signal (RESET) to electrically connect the shared node of the 52nd transistor (T52) and the 53rd transistor (T53) with the QB node. Therefore, when a reset signal (RESET) is input while the voltage of the M node is at a high level, the 52nd transistor (T52) and the 53rd transistor (T53) are turned on simultaneously, and the QB node is discharged or reset to the level of the third low potential gate voltage (GVSS2).

[0183] The carry signal output unit (512) outputs a carry signal (C(k)) based on the voltage level of the carry clock (CRCLK(k)) or the third low potential gate voltage (GVSS3) level according to the voltage level of the Q node or the voltage level of the QB node.

[0184] The carry signal output section (512) includes a 61st transistor (T61), a 62nd transistor (T62), and a boosting capacitor (CC).

[0185] The 61st transistor (T61) is connected between the clock line that carries the carry clock (CRCLK(k)) and the first output node (NO1). A boosting capacitor (CC) is connected between the gate node and the source node of the 61st transistor (T61).

[0186] The 61st transistor (T61) outputs a high-level carry signal (C(k)) through the first output node (NO1) based on the carry clock (CRCLK(k)) in response to the voltage of the Q node. The 61st transistor (T61) is turned on when the voltage of the Q node is at a high level and supplies the high-level carry clock (CRCLK(k)) to the first output node (NO1). Accordingly, a high-level carry signal (C(k)) is output.

[0187] When the carry signal (C(k)) is output, the boosting capacitor (CC) bootstraps the voltage of the Q node to a boosting voltage level higher than the level of the first high potential gate voltage (GVDD1) in synchronization with the high level carry clock (CRCLK(k)). When the voltage of the Q node is bootstrapped, the high level carry clock (CRCLK(k)) can be output as the carry signal (C(k)) quickly and without distortion.

[0188] The 62nd transistor (T62) is connected between the first output node (NO1) and the third low-potential gate voltage line that carries the third low-potential gate voltage (GVSS3).

[0189] The 62nd transistor (T62) outputs a low-level carry signal (C(k)) through the first output node (NO1) based on the third low-potential gate voltage (GVSS3) in response to the voltage of the QB node. The 62nd transistor (T62) is turned on when the voltage of the QB node is at a high level and supplies the third low-potential voltage (GVSS3) to the first output node (NO1). Accordingly, a low-level carry signal (C(k)) is output.

[0190] The scan signal output unit (514) outputs a plurality of scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) based on the voltage levels of a plurality of scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) or the first low potential gate voltage (GVSS1) level, depending on the voltage level of the Q node or the voltage level of the QB node. (i is a positive integer)

[0191] Here, multiple scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) are signals corresponding to the gate clock (GCLK), and may vary depending on the number of scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) output from the gate driving integrated circuit (GDIC).

[0192] The scan signal output unit (514) includes the 71st to 78th transistors (T71 to T78) and boosting capacitors (CS1, CS2, CS3, CS4).

[0193] The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) are each connected between a clock line that transmits a scan clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) and the 2nd to 5th output nodes (NO2 to NO5).

[0194] Boosting capacitors (CS1, CS2, CS3, CS4) are connected between the gate node and the source node of the 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77), respectively.

[0195] The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) each output a high-level scan signal (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) through the 2nd output node (NO2), the 3rd output node (NO3), the 4th output node (NO4), and the 5th output node (NO5) based on the scan clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) in response to the voltage of the Q node.

[0196] The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) are turned on when the voltage of the Q node is at a high level, and supply high-level scan clocks (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) to the 2nd output node (NO2), the 3rd output node (NO3), the 4th output node (NO4), and the 5th output node (NO5), respectively. Accordingly, high-level scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) are output, respectively.

[0197] The 71st transistor (T71), the 73rd transistor (T73), the 75th transistor (T75), and the 77th transistor (T77) each correspond to pull-up transistors.

[0198] When a scan signal (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) is output, the boosting capacitors (CS1, CS2, CS3, CS4) bootstrap or increase the voltage of the Q node to a boosting voltage level higher than the first high potential gate voltage (GVDD1) level in synchronization with the high level scan clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)). When the voltage of the Q node is bootstrapped, the high level scan clock (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) can be output as a scan signal (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) quickly and without distortion.

[0199] The 72nd transistor (T72), the 74th transistor (T74), the 76th transistor (T76), and the 78th transistor (T78) each output a low-level scan signal (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) through the 2nd output node (NO2), the 3rd output node (NO3), the 4th output node (NO4), and the 5th output node (NO5) respectively, based on the 1st low-potential gate voltage (GVSS1) in response to the voltage of the QB node.

[0200] The 72nd transistor (T72), the 74th transistor (T74), the 76th transistor (T76), and the 78th transistor (T78) are turned on when the voltage of the QB node is at a high level, and supply the 1st low potential gate voltage (GVSS1) to the 2nd output node (NO2), the 3rd output node (NO3), the 4th output node (NO4), and the 5th output node (NO5), respectively. Accordingly, low-level scan signals (SCAN(i), SCAN(i+1), SCAN(i+2), SCAN(i+3)) are output.

[0201] The 72nd transistor (T72), the 74th transistor (T74), the 76th transistor (T76), and the 78th transistor (T78) each correspond to a pull-down transistor.

[0202] This describes a case where three high-potential gate voltages (GVDD1, GVDD2, GVDD3) and three low-potential gate voltages (GVSS1, GVSS2, GVSS3) are supplied to each stage circuit at different levels. For example, the first high-potential gate voltage (GVDD1) may be set to 20V, the second high-potential gate voltage (GVDD2) to 16V, and the third high-potential gate voltage (GVDD3) to 14V, and the first low-potential gate voltage (GVSS1) may be set to -6V, the second low-potential gate voltage (GVSS2) to -10V, and the third low-potential gate voltage (GVSS3) to -12V. These figures are merely examples, and the levels of the high-potential gate voltages and low-potential gate voltages may be set differently depending on the embodiment.

[0203] Meanwhile, since a gate driver integrated circuit (GDIC) is composed of multiple transistors, the degradation and lifespan of the gate driver integrated circuit (GDIC) can be determined by the transistor with the greatest degradation among them.

[0204] Generally, the stabilization operation of the Q node plays an important role in the gate driving integrated circuit (GDIC), and as a result, the stress applied to the transistors (T31, T32) constituting the Q node stabilization section (506) and the pull-down transistors (T72, T74, T76, T78) constituting the scan signal output section (514) can be said to be relatively large.

[0205] FIG. 8 is a conceptual diagram illustrating the degradation and occurrence of errors in a gate driving circuit according to driving time in a display device according to embodiments of the present disclosure.

[0206] Referring to FIG. 8, in the display device (100) according to embodiments of the present disclosure, as the driving time increases, the transistor constituting the gate driving integrated circuit (GDIC) deteriorates, and the threshold voltage (Vth) may increase.

[0207] In particular, the transistors (T31, T32) constituting the Q node stabilization section (506) and the pull-down transistors (T72, T74, T76, T78) constituting the scan signal output section (514) have their gate terminals connected to the QB node, so they have a direct effect on the degradation of the gate driving integrated circuit (GDIC).

[0208] Among these, the transistors (T31, T32) constituting the Q node stabilization unit (506) are subjected to stress by a voltage corresponding to the difference between the second high potential gate voltage (GVDD2) and the threshold voltage (Vth).

[0209] Accordingly, when the second high-potential gate voltage (GVDD2) applied to the gate driving integrated circuit (GDIC) is maintained at a constant level, the difference between the second high-potential gate voltage (GVDD2) and the threshold voltage (Vth) becomes large during the initial driving period of the display device (100). Consequently, during the initial driving period of the display device (100), the stress applied to the transistors (T31, T32) constituting the Q node stabilization unit (506) appears large (STRESS1).

[0210] However, as the driving period of the display device (100) increases, the threshold voltage (Vth) of the transistors (T31, T32) constituting the Q node stabilization unit (506) increases, so the difference between the second high potential gate voltage (GVDD2) and the threshold voltage (Vth) gradually decreases (STRESS2).

[0211] Therefore, as the driving period of the display device (100) increases, the stress on the transistors (T31, T32) constituting the Q node stabilization unit (506) can be said to gradually decrease.

[0212] However, as the driving time increases, if the threshold voltage (Vth) of the second high potential gate voltage (GVDD2) and the transistors (T31, T32) constituting the Q node stabilization unit (506) decreases within a certain range, a multi-output error may occur in which a scan signal is generated on any gate line due to an operation error of the transistors (T31, T32) constituting the Q node stabilization unit (506).

[0213] FIG. 9 is a diagram illustrating an example of a waveform of a scan signal output from a gate driving circuit during a display period and a sensing period in a display device according to embodiments of the present disclosure, and FIG. 10 is a signal waveform diagram illustrating a case where a multi-output error occurs in which a scan signal is generated on any gate line due to degradation of the gate driving integrated circuit.

[0214] First, referring to FIG. 9, a display device (100) according to embodiments of the present disclosure can emit light from a subpixel (SP) placed on a display panel (110) during a display driving period and detect a characteristic value of a driving transistor placed on any subpixel (SP) during a sensing period. At this time, the sensing period may correspond to a blank period in which the display panel (110) does not emit light.

[0215] In the case of a 12-phase scan clock structure in which 12 scan clocks are supplied sequentially, 12 scan clocks with different phases can be sequentially applied to the gate driving circuit (120) through 12 scan clock lines. At this time, each of the 12 scan clocks can correspond to 12 scan signals (SCAN(1)-SCAN(12)).

[0216] Accordingly, during the display driving period, the gate driving circuit (120) supplies 12 scan signals (SCAN (1)-SCAN (12)) to the display panel (110) at constant phase intervals.

[0217] Meanwhile, during the sensing period, a scan signal (here, a second scan signal (SCAN (2))) is applied only to the designated gate line, thereby detecting the characteristic value of the subpixel connected to the corresponding line.

[0218] However, as illustrated in FIG. 10, as the driving time of the display device (100) increases, if the second high potential gate voltage (GVDD2) and the threshold voltage (Vth) of the transistors (T31, T32) constituting the Q node stabilization unit (506) decrease within a certain range, a multi-output error may occur in which multiple scan signals are supplied to any gate line due to an operating error of the transistors (T31, T32) constituting the Q node stabilization unit (506).

[0219] For example, in a 12-phase scan clock structure, due to the degradation of the gate driving integrated circuit (GDIC), a multi-output error may occur in which the second scan signal (SCAN (2)) and the tenth scan signal (SCAN (10)) are output simultaneously.

[0220] Accordingly, the display device (100) of the present disclosure controls the gate voltage applied to the gate driving circuit (120) in consideration of cases where a multi-output error occurs in the gate driving circuit (120), thereby reducing the degradation of the gate driving circuit (120) and improving the operating performance.

[0221] At this time, in order to reduce the degradation of the gate driving circuit (120) and improve the operating performance, it is effective to target a second high potential gate voltage (GVDD2) corresponding to the driving voltage of the transistors (T41, T42, T43, T44) that constitute the inverter section (508) so as to relieve stress on the transistors (T31, T32) that constitute the Q node stabilization section (506) in the gate driving integrated circuit.

[0222] FIG. 11 is a flowchart illustrating a display driving method according to embodiments of the present disclosure.

[0223] Referring to FIG. 11, a display driving method according to embodiments of the present disclosure may include the steps of setting a test gate voltage (S100), detecting a sensing voltage for a characteristic value of a subpixel (SP) (S200), determining whether the sensing voltage corresponds to a multi-output value (S300), setting an error gate voltage (S400) when the sensing voltage corresponds to a multi-output value, determining a stable gate voltage (S500), and applying the stable gate voltage to a gate driving circuit (120) (S600).

[0224] The step of setting the test gate voltage (S100) is a process of setting the test gate voltage to be applied to the gate driving circuit (120) in order to check the deterioration state of the gate driving circuit (120) during the sensing period for detecting the characteristic value (threshold voltage or mobility) of the subpixel (SP).

[0225] The test gate voltage may correspond to a second high potential gate voltage (GVDD2) applied to the inverter section (508) of the gate driving integrated circuit (GDIC).

[0226] The test gate voltage may have a value that decreases in constant level increments from the initial set voltage so as to check the deterioration state of the gate driving circuit (120). For example, the initial set voltage of the test gate voltage can be set to 6V, and the deterioration state of the gate driving circuit (120) can be checked by decreasing it by 1V.

[0227] The step (S200) of detecting a sensing voltage for a characteristic value of a subpixel (SP) is a process of detecting a sensing voltage corresponding to a characteristic value of a driving transistor (DRT) according to a scan signal of a gate driving circuit (120) driven by a test gate voltage during the sensing period.

[0228] FIG. 12 is a diagram illustrating an example of a circuit for sensing the characteristic value of a driving transistor in a display device according to embodiments of the present disclosure.

[0229] Referring to FIG. 12, a display device (100) according to embodiments of the present disclosure may include configurations for compensating for a deviation in the characteristic value of a driving transistor (DRT).

[0230] For example, a characteristic value or a change in the characteristic value of the driving transistor (DRT) can be reflected in the second node (N2) voltage of the driving transistor (DRT) (e.g., Vdata - Vth). The second node (N2) voltage of the driving transistor (DRT) can correspond to the voltage of the reference voltage line (RVL) when the sensing transistor (SENT) is turned on. Additionally, the line capacitor (Cline) of the reference voltage line (RVL) can be charged by the second node (N2) voltage of the driving transistor (DRT), and the reference voltage line (RVL) can have a voltage corresponding to the second node (N2) voltage of the driving transistor (DRT) by the sensing voltage (Vsen) charged in the line capacitor (Cline).

[0231] Such a display device (100) may include an analog-to-digital converter (ADC) that measures the voltage of a reference voltage line (RVL) corresponding to the voltage of a second node (N2) of a driving transistor (DRT) and converts it into a digital value, and a switch circuit (SAM, SPRE) for sensing a characteristic value.

[0232] A switch circuit (SAM, SPRE) controlling characteristic value sensing drive may include a sensing reference switch (SPRE) that controls the connection between a reference voltage line (RVL) and a sensing reference voltage supply node (Npres) to which a reference voltage (Vref) is supplied, and a sampling switch (SAM) that controls the connection between a reference voltage line (RVL) and an analog-to-digital converter (ADC). Here, the sensing reference switch (SPRE) is a switch that controls the characteristic value sensing drive, and the reference voltage (Vref) supplied to the reference voltage line (RVL) by the sensing reference switch (SPRE) becomes the sensing reference voltage (VpreS).

[0233] Additionally, the switch circuit for sensing the characteristic value of the driving transistor (DRT) may include a display reference switch (RPRE) that controls the display driving. The display reference switch (RPRE) can control the connection between the reference voltage line (RVL) and the display reference voltage supply node (Nprer) to which the reference voltage (Vref) is supplied. The display reference switch (RPRE) is a switch used for display driving, and the reference voltage (Vref) supplied to the reference voltage line (RVL) by the display reference switch (RPRE) corresponds to the display reference voltage (VpreR).

[0234] In this case, the sensing reference switch (SPRE) and the display reference switch (RPRE) may be provided separately or implemented as a single integrated unit. The sensing reference voltage (VpreS) and the display reference voltage (VpreR) may be the same voltage value or different voltage values.

[0235] The timing controller (140) of the display device (100) may include a memory (MEM) that stores data transmitted from an analog-to-digital converter (ADC) or stores a reference value in advance, and a compensation circuit (COMP) that compensates for deviations in characteristic values ​​by comparing the received data with the reference value stored in the memory (MEM). At this time, the compensation value calculated by the compensation circuit (COMP) may be stored in the memory (MEM).

[0236] Accordingly, the timing controller (140) can compensate the image data (DATA) to be supplied to the data driving circuit (130) using the compensation value calculated by the compensation circuit (COMP), and output the compensated image data (DATA_comp) to the data driving circuit (130). Accordingly, the data driving circuit (130) can convert the compensated image data (DATA_comp) into a compensated data voltage (Vdata_comp) in the form of an analog signal through a digital-to-analog converter (DAC), and output the compensated data voltage (Vdata_comp) to the corresponding data line (DL) through an output buffer (BUF). As a result, the characteristic value deviation (threshold voltage deviation, or mobility deviation) of the driving transistor (DRT) within the corresponding subpixel (SP) can be compensated.

[0237] As described above, the period for sensing the characteristic values ​​(threshold voltage and mobility) of the driving transistor (DRT) can be performed after the generation of a power-on signal and before the display driving begins. For example, when a power-on signal is applied to a display device (100), the timing controller (140) loads the parameters required to drive the display panel (110) and then proceeds with the display driving. At this time, the parameters required to drive the display panel (110) may include information regarding the characteristic value sensing and compensation previously performed on the display panel (110), and sensing of the characteristic values ​​(threshold voltage and mobility) of the driving transistor (DRT) can be performed during this parameter loading process. Thus, the process in which characteristic value sensing is performed after the generation of a power-on signal and before the subpixel emits light is called the On-Sensing Process.

[0238] Alternatively, the period for sensing the characteristic value of the driving transistor (DRT) may proceed after the power-off signal of the display device (100) is generated. For example, when a power-off signal is generated in the display device (100), the timing controller (140) can cut off the data voltage supplied to the display panel (110) and perform sensing of the characteristic value of the driving transistor (DRT) for a certain period of time. In this way, the process of sensing the characteristic value while the light emission of the subpixel has ended due to the data voltage being cut off when a power-off signal is generated is called the Off-Sensing Process.

[0239] In addition, the sensing period for the characteristic value of the driving transistor (DRT) may be performed in real time during display driving. This sensing process is called a Real-Time (RT) sensing process. In the case of a Real-Time sensing process, the sensing process may be performed for one or more subpixels (SP) on one or more subpixel (SP) lines during each blank period of the display driving period.

[0240] That is, during the display driving period in which an image is displayed on the display panel (110), there is a blank section in which data voltage is not supplied to the subpixel (SP) within one frame or between the nth frame and the n+1th frame, and mobility sensing for one or more subpixels (SP) can be performed during this blank section.

[0241] In this way, when a sensing process is performed during a blank period, the subpixel (SP) line where the sensing process is performed can be randomly selected. Additionally, after the sensing process is performed during the blank period, a compensation data voltage (Vdata_comp) can be supplied to the subpixel (SP) where the sensing process was performed during the display driving period. Accordingly, abnormal phenomena in the subpixel (SP) line where the sensing process was completed during the display driving period following the sensing process in the blank period can be mitigated.

[0242] Meanwhile, the data driving circuit (130) may include a data voltage output circuit (136) including a latch circuit, a digital-to-analog converter (DAC), and an output buffer (BUF), and in some cases, may further include an analog-to-digital converter (ADC) and various switches (SAM, SPRE, RPRE). On the other hand, the analog-to-digital converter (ADC) and various switches (SAM, SPRE, RPRE) may be located outside the data driving circuit (130).

[0243] Additionally, the compensation circuit (COMP) may be located outside the timing controller (140) but may also be included inside the timing controller (140), and the memory (MEM) may be located outside the timing controller (140) or may be implemented in the form of a register inside the timing controller (140).

[0244] FIG. 13 is a diagram illustrating an example of a driving timing diagram for detecting a threshold voltage among the characteristic values ​​of a driving transistor in a display device according to embodiments of the present disclosure.

[0245] Referring to FIG. 13, in a display device (100) according to embodiments of the present disclosure, the threshold voltage sensing section (Vth SENSING) may include an initialization section (INITIAL), a tracking section (TRACKING), and a sampling section (SAMPLING).

[0246] In the initialization period (INITIAL), the switching transistor (SWT) is turned on by the first scan signal (SCAN1) of the turn-on level. Accordingly, the first node (N1) of the driving transistor (DRT) is initialized to a sensing data voltage (Vdata_sen) for threshold voltage sensing.

[0247] In addition, during the initialization period (INITIAL), the sensing transistor (SENT) is turned on by the second scan signal (SCAN2) of the turn-on level voltage, and the sensing reference switch (SPRE) is turned on. Accordingly, the second node (N2) of the driving transistor (DRT) is initialized to the sensing reference voltage (VpreS).

[0248] The tracking period is a step of tracking the threshold voltage (Vth) of the driving transistor (DRT). That is, the tracking period tracks the voltage of the second node (N2) of the driving transistor (DRT) that reflects the threshold voltage (Vth) of the driving transistor (DRT).

[0249] During the tracking period, the switching transistor (SWT) and the sensing transistor (SENT) remain in the turned-on state, and the sensing reference switch (SPRE) is turned off. Accordingly, the second node (N2) of the driving transistor (DRT) becomes floating, and the voltage of the second node (N2) of the driving transistor (DRT) begins to rise from the sensing reference voltage (VpreS).

[0250] At this time, since the sensing transistor (SENT) is in the turned-on state, the voltage rise of the second node (N2) of the driving transistor (DRT) leads to a voltage rise of the reference voltage line (RVL).

[0251] The voltage at the second node (N2) of the driving transistor (DRT) rises and then becomes saturated. The saturated voltage at the second node (N2) of the driving transistor (DRT) corresponds to the difference (Vdata_sen - Vth) between the sensing data voltage (Vdata_sen) relative to the threshold voltage and the threshold voltage (Vth) of the driving transistor (DRT).

[0252] Therefore, when the voltage of the second node (N2) of the driving transistor (DRT) is saturated, the voltage of the reference voltage line (RVL) corresponds to the difference between the sensing data voltage (Vdata_sen) and the threshold voltage of the driving transistor (DRT) (Vdata_sen - Vth).

[0253] When the voltage of the second node (N2) of the driving transistor (DRT) reaches saturation, the sampling switch (SAM) is turned on, and the sampling period (SAMPLING) proceeds.

[0254] During the sampling interval, the analog-to-digital converter (ADC) detects the sensing voltage (Vsen) of the reference voltage line (RVL) connected by the sampling switch (SAM) and converts the sensing voltage (Vsen) into sensing data corresponding to a digital value. Here, the sensing voltage (Vsen) transmitted by the analog-to-digital converter (ADC) corresponds to "Vdata_sen - Vth".

[0255] The compensation circuit (COMP) can determine the threshold voltage of the driving transistor (DRT) located at the corresponding subpixel (SP) based on the sensing data output from the analog-to-digital converter (ADC), and accordingly, can compensate the threshold voltage of the driving transistor (DRT).

[0256] That is, the compensation circuit (COMP) can determine the threshold voltage (Vth) of the driving transistor (DRT) from the sensing data (digital data corresponding to Vdata_sen - Vth) measured through the threshold voltage sensing operation and the sensing data for the threshold voltage (digital data corresponding to Vdata_sen).

[0257] The compensation circuit (COMP) can compensate for the threshold voltage deviation between driving transistors (DRTs) by comparing the threshold voltage (Vth) identified for the corresponding driving transistor (DRT) with a reference threshold voltage or the threshold voltage of another driving transistor (DRT). Here, threshold voltage deviation compensation may refer to the process of changing the data voltage (Vdata) to a compensation data voltage (Vdata_comp), that is, the process of multiplying the data voltage (Vdata) by a compensation gain (G). (For example, Vdata_comp = G * Vdata)

[0258] Therefore, if the deviation of the threshold voltage increases, the compensation gain (G) multiplied by the data voltage (Vdata) will increase.

[0259] In this way, while driving the gate driving circuit (120) with the test gate voltage, the sensing voltage (Vsen) for the characteristic value can be detected through the reference voltage line (RVL).

[0260] The gate driving circuit (120) may perform a single output operation that outputs one scan signal within the N-phase scan clock according to the level of the test gate voltage, or a multi-output error that outputs multiple scan signals may occur.

[0261] The step (S300) of determining whether the sensing voltage (Vsen) corresponds to a multi-output value is a process of determining whether a single scan signal is output or multiple scan signals are output within the N-phase scan clock according to the level of the test gate voltage.

[0262] FIG. 14 is a diagram illustrating an example of a sensing voltage in a display device according to embodiments of the present disclosure, in which a single output or multiple output occurs depending on the gate voltage.

[0263] Referring to FIG. 14, the display device (100) according to embodiments of the present disclosure may have a gate driving circuit (120) that outputs a single scan signal within an N-phase scan clock according to the level of the test gate voltage, or a multi-output error that outputs multiple scan signals may occur.

[0264] When the gate driving circuit (120) performs a single output operation that outputs a single scan signal within the N-phase scan clock, the sensing voltage (Vsen) detected through the reference voltage line (RVL) during the sensing period may show a normal output value of a relatively low level.

[0265] On the other hand, when the gate driving circuit (120) outputs multiple scan signals within the N-phase scan clock, a multi-output is achieved, and at least twice the sensing voltage (Vsen) is detected compared to the case of normal operation.

[0266] For example, when two scan signals are output within the N-phase scan clock, a sensing voltage (Vsen) approximately twice that of normal operation is detected, and when three scan signals are output within the N-phase scan clock, a sensing voltage (Vsen) approximately three times that of normal operation is detected.

[0267] In this way, the display device (100) of the present disclosure can determine the deterioration state of the gate driving circuit (120) and the appropriateness of the gate voltage level by detecting the level of the sensing voltage (Vsen) detected through the reference voltage line (RVL) during the sensing period.

[0268] When the sensing voltage (Vsen) corresponds to a multi-output value, the step of setting the error gate voltage (S400) is a process of setting the gate voltage at the point in time when the sensing voltage (Vsen) detected through the reference voltage line (RVL) corresponds to the level of the multi-output as the error gate voltage.

[0269] The display device (100) of the present disclosure can prevent errors in which the gate driving circuit (120) generates multiple outputs by setting the gate voltage to a level greater than a certain value than the error gate voltage, while simultaneously relieving stress on the transistor constituting the gate driving circuit (120).

[0270] The step of determining the stable gate voltage (S500) can determine a voltage higher than the error gate voltage at which a multi-output occurs as the stable gate voltage.

[0271] For example, if a multi-output occurs in the gate driving circuit (120) when the gate voltage is 4V, the error gate voltage becomes 4V, and 10V, which is 6V higher than the error gate voltage, can be determined as the stable gate voltage.

[0272] At this time, the difference between the error gate voltage and the stable gate voltage can be said to be a stable voltage that prevents multiple outputs of the gate driving circuit (120).

[0273] The magnitude of the stabilized voltage may vary depending on the size or structure of the display device (100) and may be stored in the memory (MEM) of the timing controller (140) in the form of a lookup table.

[0274] The step (S600) of applying a stable gate voltage to the gate driving circuit (120) is a process of controlling the level of a second high potential gate voltage (GVDD2) applied to the gate driving circuit (120) to a stable gate voltage according to the output (single output or multi output) state of the gate driving circuit (120).

[0275] FIG. 15 is a diagram illustrating an example of controlling the level of the gate voltage according to the deterioration state of the gate driving circuit in a display device according to embodiments of the present disclosure.

[0276] Referring to FIG. 15, in the display device (100) according to embodiments of the present disclosure, as the driving time increases, the transistor constituting the gate driving integrated circuit (GDIC) deteriorates, and the threshold voltage (Vth) may rise.

[0277] In particular, the transistors (T31, T32) constituting the Q node stabilization section (506) and the pull-down transistors (T72, T74, T76, T78) constituting the scan signal output section (514) have their gate terminals connected to the QB node, so they have a direct effect on the degradation of the gate driving integrated circuit (GDIC).

[0278] Among these, the transistors (T31, T32) constituting the Q node stabilization unit (506) are subjected to stress by a voltage corresponding to the difference between the second high potential gate voltage (GVDD2) and the threshold voltage (Vth).

[0279] Accordingly, it is desirable that the second high potential gate voltage (GVDD2) applied to the gate driving integrated circuit (GDIC) maintains a difference so as not to cause multi-output errors in the gate driving circuit (120), while minimizing stress on the threshold voltage (Vth) of the transistors (T31, T32) constituting the Q node stabilization section (506).

[0280] To this end, the display device (100) of the present disclosure maintains a second high potential gate voltage (GVDD2) that is higher than the stabilization voltage (Vst) than the error gate voltage at which a multi-output error occurs in the gate driving circuit (120), thereby minimizing stress on the transistors (T31, T32) constituting the Q node stabilization unit (506) and preventing a multi-output error from occurring in the gate driving circuit (120).

[0281] That is, the display device (100) of the present disclosure can enable stable operation of the gate driving circuit (120) by controlling the gate voltage to be higher than the threshold voltage (Vth) of the transistor by the stabilization voltage (Vst) when the threshold voltage (Vth) of the transistor changes as the driving time increases.

[0282] The embodiments of the present disclosure described above are briefly explained as follows.

[0283] The display device (100) of the present disclosure may include a display panel (110) having a plurality of subpixels (SP) arranged thereon, a gate driving circuit (120) that supplies a plurality of scan signals (SCAN) to the display panel (110) through a plurality of gate lines (GL), a data driving circuit (130) that supplies a plurality of data voltages to the display panel (110) through a plurality of data lines (DL), a power management circuit (150) that supplies a plurality of driving voltages to the gate driving circuit (120) and the data driving circuit (130), and a timing controller (140) that controls the power management circuit (150) so that the level of the gate voltage applied to the gate driving circuit (120) is changed according to the output state of the gate driving circuit (120).

[0284] The gate driving circuit (120) may include a plurality of gate driving integrated circuits (GDICs) that output N scan signals (SCAN) by N (N is a natural number) scan clocks (SCCLK) supplied sequentially, and output M (M is a natural number smaller than N) scan signals (SCAN).

[0285] The above gate driving integrated circuit (GDIC) comprises a line selector (502) configured to charge an M node based on a carry signal from the preceding stage in response to the input of a line sensing signal, a Q node control unit (504) configured to charge a Q node to the level of a first high potential gate voltage (GVDD1) in response to the carry signal from the preceding stage and discharge the Q node to the level of a third low potential gate voltage (GVSS3) in response to the input of a carry signal from the following stage, a Q node stabilization unit (506) configured to discharge the Q node and QH node to the level of the third low potential gate voltage (GVSS3) in response to the voltage of the QB node, an inverter unit (508) configured to change the voltage level of the QB node to a second high potential gate voltage (GVDD2) according to the voltage level of the Q node, and the QB node to the third low potential gate voltage (GVSS3) in response to the carry signal from the following stage, a reset signal, and the charging voltage of the M node. It may include a QB node stabilization unit (510) configured to discharge at a level, a carry signal output unit (512) configured to output a carry signal based on the voltage level of a carry clock or the level of a third low-potential gate voltage (GVSS3) according to the voltage level of the Q node or the voltage level of the QB node, and a scan signal output unit (514) configured to output a plurality of scan signals (SCAN) based on the voltage level of a plurality of scan clocks (SCCLK) or the level of a first low-potential gate voltage (GVSS1) according to the voltage level of the Q node or the voltage level of the QB node.

[0286] The output state of the gate driving circuit (120) may include a single output state in which one of the N scan signals is output during the sensing period for sensing the characteristic value of the subpixel (SP), and a multi output state in which multiple scan signals among the N scan signals are output during the sensing period for sensing the characteristic value of the subpixel (SP).

[0287] The output state of the gate driving circuit (120) can be determined based on the sensing voltage (Vsen) corresponding to the characteristic value of the subpixel (SP).

[0288] When the above sensing voltage (Vsen) is greater than or equal to a reference value, the output state of the gate driving circuit (120) can be determined as a multi-output state.

[0289] When the output state of the gate driving circuit (120) is a multi-output state, the gate voltage can be changed to a level of stable gate voltage that is higher than the error gate voltage corresponding to the multi-output state by an amount equal to the stabilization voltage (Vst).

[0290] The above gate voltage may correspond to the above second high potential gate voltage (GVDD2).

[0291] Additionally, the display driving method of the present disclosure may include a step of setting a test gate voltage (S100), a step of detecting a sensing voltage (Vsen) for a characteristic value of a subpixel (SP) placed on a display panel (110) (S200), a step of determining whether the sensing voltage (Vsen) corresponds to a multi-output value (S300), a step of setting the test gate voltage to an error gate voltage (S400) when the sensing voltage (Vsen) corresponds to a multi-output value, a step of determining a stable gate voltage (S500), and a step of applying the stable gate voltage to a gate driving circuit (120) (S600).

[0292] The gate driving circuit (120) may include a plurality of gate driving integrated circuits (GDICs) that output N scan signals (SCAN) by N (N is a natural number) scan clocks (SCCLK) supplied sequentially, and output M (M is a natural number smaller than N) scan signals (SCAN).

[0293] The above multi-output value may correspond to a state in which multiple scan signals (SCAN) among the N scan signals (SCAN) are output.

[0294] If the above sensing voltage (Vsen) is greater than or equal to the reference value, it can be determined as a multi-output value.

[0295] The above stable gate voltage may be a voltage level higher than the above error gate voltage by the stabilization voltage (Vst).

[0296] The above gate driving integrated circuit (GDIC) comprises a line selector (502) configured to charge an M node based on a carry signal from the preceding stage in response to the input of a line sensing signal, a Q node control unit (504) configured to charge a Q node to the level of a first high potential gate voltage (GVDD1) in response to the carry signal from the preceding stage and discharge the Q node to the level of a third low potential gate voltage (GVSS3) in response to the input of a carry signal from the following stage, a Q node stabilization unit (506) configured to discharge the Q node and QH node to the level of the third low potential gate voltage (GVSS3) in response to the voltage of the QB node, an inverter unit (508) configured to change the voltage level of the QB node to a second high potential gate voltage (GVDD2) according to the voltage level of the Q node, and the QB node to the third low potential gate voltage (GVSS3) in response to the carry signal from the following stage, a reset signal, and the charging voltage of the M node. It includes a QB node stabilization unit (510) configured to discharge to a level, a carry signal output unit (512) configured to output a carry signal based on the voltage level of a carry clock or the level of a third low-potential gate voltage (GVSS3) according to the voltage level of the Q node or the voltage level of the QB node, and a scan signal output unit (514) configured to output a plurality of scan signals (SCAN) based on the voltage level of a plurality of scan clocks (SCCLK) or the level of a first low-potential gate voltage (GVSS1) according to the voltage level of the Q node or the voltage level of the QB node, wherein the stabilization gate voltage may correspond to the second high-potential gate voltage (GVDD2).

[0297] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, since the embodiments disclosed in the present disclosure are intended to explain, not limit, the scope of the technical concept of the present disclosure is not limited by these embodiments. Explanation of the symbols

[0299] 100: Display device 110: Display panel 120: Gate driving circuit 122: Shift Register 124: Buffer circuit 130: Data driving circuit 131: Gate voltage line 132: Clock signal line 133: Line sensing signal line 134: Reset signal line 140: Timing Controller 150: Power management circuit 160: Main Power Management Circuit 170: Set Board 502: Line selection section 504: Q Node Control Unit 506: Q Node Stabilization Section 508: Inverter section 510: QB Node Stabilization Unit 512: Carry signal output section 514: Scan signal output section

Claims

Claim 1 A display device comprising: a display panel having a plurality of subpixels arranged thereon; a gate driving circuit that supplies a plurality of scan signals to the display panel through a plurality of gate lines; a data driving circuit that supplies a plurality of data voltages to the display panel through a plurality of data lines; a power management circuit that supplies a plurality of driving voltages to the gate driving circuit and the data driving circuit; and a timing controller that controls the power management circuit so that the level of the gate voltage applied to the gate driving circuit is changed according to the output state of the gate driving circuit that outputs a scan signal during a sensing period for sensing a characteristic value of the subpixel. Claim 2 A display device according to claim 1, wherein the gate driving circuit outputs N scan signals by sequentially supplied N (N is a natural number greater than or equal to 2) scan clocks, and comprises a plurality of gate driving integrated circuits that output M (M is a natural number less than N) scan signals. Claim 3 In claim 2, the gate driving integrated circuit comprises: a line selector configured to charge an M node based on a carry signal from the preceding stage in response to the input of a line sensing signal; a Q node control unit configured to charge a Q node to a level of a first high-potential gate voltage in response to the carry signal from the preceding stage and discharge the Q node to a level of a third low-potential gate voltage in response to the input of a carry signal from the following stage; a Q node stabilization unit configured to discharge the Q node and the QH node to a level of the third low-potential gate voltage in response to the voltage of the QB node; an inverter unit configured to change the voltage level of the QB node to a second high-potential gate voltage according to the voltage level of the Q node; a QB node stabilization unit configured to discharge the QB node to a level of the third low-potential gate voltage in response to the carry signal from the following stage, a reset signal, and the charging voltage of the M node; and a unit configured to output a carry signal based on the voltage level of a carry clock or the level of the third low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node. A display device comprising: a carry signal output unit; and a scan signal output unit configured to output a plurality of scan signals based on a voltage level of a plurality of scan clocks or a level of a first low-potential gate voltage, depending on the voltage level of the Q node or the voltage level of the QB node. Claim 4 In claim 3, the output state of the gate driving circuit comprises: a single output state in which one of the N scan signals is output; and a multi output state in which a plurality of the N scan signals are output. Claim 5 In claim 4, a display device in which the output state of the gate driving circuit is determined based on a sensing voltage corresponding to a characteristic value of the subpixel. Claim 6 A display device according to claim 5 that determines the output state of the gate driving circuit as a multi-output state when the sensing voltage is greater than or equal to a reference value. Claim 7 A display device according to claim 4, wherein when the output state of the gate driving circuit is a multi-output state, the gate voltage is changed to a level of a stable gate voltage that is higher than the error gate voltage corresponding to the multi-output state by an amount equal to the stabilization voltage. Claim 8 In claim 7, the gate voltage is a display device corresponding to the second high-potential gate voltage. Claim 9 A display driving method comprising: a step of setting a test gate voltage; a step of detecting a sensing voltage for a characteristic value of a subpixel placed on a display panel; a step of determining whether the sensing voltage corresponds to a multi-output value; a step of setting the test gate voltage to an error gate voltage if the sensing voltage corresponds to a multi-output value; a step of determining a stable gate voltage; and a step of applying the stable gate voltage to a gate driving circuit. Claim 10 A display driving method according to claim 9, wherein the gate driving circuit outputs N scan signals by sequentially supplied N (N is a natural number) scan clocks, and comprises a plurality of gate driving integrated circuits that output M (M is a natural number smaller than N) scan signals. Claim 11 In claim 10, the multi-output value is a display driving method corresponding to a state in which a plurality of scan signals among the N scan signals are output. Claim 12 In claim 9, a display driving method that determines a multi-output value when the sensing voltage is greater than or equal to a reference value. Claim 13 A display driving method according to claim 9, wherein the stabilization gate voltage is a voltage level higher than the error gate voltage by the stabilization voltage. Claim 14 In claim 10, the gate driving integrated circuit comprises: a line selector configured to charge an M node based on a carry signal from the preceding stage in response to the input of a line sensing signal; a Q node control unit configured to charge a Q node to a level of a first high-potential gate voltage in response to the carry signal from the preceding stage and discharge the Q node to a level of a third low-potential gate voltage in response to the input of a carry signal from the following stage; a Q node stabilization unit configured to discharge the Q node and the QH node to a level of the third low-potential gate voltage in response to the voltage of the QB node; an inverter unit configured to change the voltage level of the QB node to a second high-potential gate voltage according to the voltage level of the Q node; a QB node stabilization unit configured to discharge the QB node to a level of the third low-potential gate voltage in response to the carry signal from the following stage, a reset signal, and the charging voltage of the M node; and output a carry signal based on the voltage level of a carry clock or the level of the third low-potential gate voltage according to the voltage level of the Q node or the voltage level of the QB node. A display driving method comprising: a configured carry signal output unit; and a scan signal output unit configured to output a plurality of scan signals based on a voltage level of a plurality of scan clocks or a level of a first low-potential gate voltage according to a voltage level of the Q node or a voltage level of the QB node, wherein the stable gate voltage corresponds to the second high-potential gate voltage.

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