Manufacturing method of semiconductor apparatus and substrate processing apparatus

Abstract

Even in the case of burial into a concave shape that has irregularities on the side of the concave and is prone to void formation, the membrane can be buried within the concave without generating voids. A process of supplying a silicon-containing gas to a substrate having a concave portion provided on its surface to deposit a silicon film within the concave portion, and A process of etching the silicon film within the concave portion by supplying a first etching gas having a first etching profile in which the etching amount differs at the upper and lower portions in the depth direction of the concave portion to the substrate, and A process of etching the silicon film within the concave portion by supplying a second etching gas having a second etching profile different from the first etching profile of the first etching gas to the substrate, and The process involves depositing a new silicon film on the silicon film etched with the second etching gas.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a semiconductor device and a substrate processing device. Background Technology

[0002] Conventionally, a method for manufacturing a semiconductor device is known in which a silicon film is filled into a concave area by repeating the following steps: supplying a silicon-containing film-forming gas to a workpiece having a concave area formed on its surface to form a silicon film within the concave area; supplying a processing gas to the workpiece containing a halogen gas for etching the silicon film and a roughness suppressing gas for suppressing surface roughness of the silicon film after etching by the halogen gas; and further activating the processing gas by applying thermal energy to it to perform etching and widen the opening width of the concave area (see, for example, Patent Document 1). This filling method is called a Deposition Etch Deposition (DED) process in that it involves repeating deposition and etching. Prior art literature

[0003] Japanese Patent Publication No. 2017-228580 The problem to be solved

[0004] The present invention provides a method for manufacturing a semiconductor device and a substrate processing apparatus that can embed a film within a concave portion without generating voids, even in the case of embedding into a concave portion with a shape prone to void formation and irregularities on the side of the concave portion. means of solving the problem

[0005] To achieve the above objective, a method for manufacturing a semiconductor device according to the form of the present disclosure comprises the steps of: supplying a silicon-containing gas to a substrate having a concave portion provided on its surface to deposit a silicon film within the concave portion; and

[0006] A process of etching the silicon film within the concave portion by supplying a first etching gas having a first etching profile in which the etching amount differs at the upper and lower portions in the depth direction of the concave portion to the substrate, and

[0007] A process of etching the silicon film within the concave portion by supplying a second etching gas having a second etching profile different from the first etching profile of the first etching gas to the substrate, and

[0008] The process includes depositing a new silicon film on the silicon film etched with the second etching gas. Effects of the invention

[0009] According to the present disclosure, a membrane can be embedded within a concave portion without generating voids. Brief explanation of the drawing

[0010] FIG. 1 is a drawing illustrating a substrate processing apparatus according to an embodiment of the present disclosure. Figure 2 is a drawing illustrating an example of the shape of a concave portion formed on the surface of wafer W. Figure 3 is a diagram illustrating an example of a general conventional DED process. Figure 4 is a diagram illustrating the DED process when the concave portion has a flat side. Figure 5 is a drawing illustrating an example of the DED process in which the side of the concave portion is not a flat surface. FIG. 6 is a drawing illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. FIG. 7 is a diagram illustrating the etching profile in the depth direction of the first etching gas and the second etching gas. FIG. 8 is a process flowchart illustrating a method for manufacturing a semiconductor device according to a first embodiment. FIG. 9 is a process flowchart showing an example of a method for manufacturing a semiconductor device according to a second embodiment. FIG. 10 is a diagram showing the process flow of a method for manufacturing a semiconductor device according to a third embodiment. Specific details for implementing the invention

[0011] Hereinafter, a description of a form for carrying out the present invention is provided with reference to the drawings.

[0012] FIG. 1 is a drawing illustrating a substrate processing apparatus according to an embodiment of the present disclosure. In this embodiment, an example in which the substrate processing apparatus is configured as a vertical heat treatment apparatus is described. Furthermore, the substrate processing apparatus according to the present disclosure is not limited to a vertical heat treatment apparatus and can be applied to various substrate processing apparatuses capable of alternately performing film deposition and etching. Applicable substrate processing apparatuses include single-wafer substrate processing apparatuses and semi-batch substrate processing apparatuses. In this embodiment, an example in which the substrate processing apparatus is configured as a vertical heat treatment apparatus is described.

[0013] A vertical heat treatment device performs a DED process to form logic elements of a semiconductor device on a wafer W, which is a substrate. That is, it performs film deposition and etching treatments on the wafer W. This film deposition treatment is a process by thermal CVD (Chemical Vapor Deposition), and the etching treatment is a reactive gas etching performed by supplying thermal energy to an etching gas.

[0014] In addition, the logic devices being manufactured include, in addition to conventionally manufactured logic devices, logic devices using, for example, FinFETs, which are next-generation transistors to MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0015] A vertical heat treatment apparatus is provided with a reaction tube (11), which is a roughly cylindrical vacuum vessel with its longitudinal direction oriented vertically. The reaction tube (11) has a double-tube structure composed of an inner tube (12) and an outer tube (13) having a ceiling formed to cover the inner tube (12) and spaced apart from the inner tube (12). The inner tube (12) and the outer tube (13) are formed of a heat-resistant material, for example, quartz. Since the reaction tube (11) forms a closed space for processing substrates, it may be referred to as a processing room.

[0016] Below the outer casing (13), a manifold (14) made of stainless steel (SUS) formed in a tubular shape is disposed. The manifold (14) is hermetically connected to the bottom of the outer casing (13). Additionally, the inner tube (12) protrudes from the inner wall of the manifold (14) and is supported by a support ring (15) formed integrally with the manifold (14).

[0017] A cover (16) is positioned below the manifold (14), and the cover (16) is configured to be able to move up and down between an upward position and a downward position by means of a boat elevator (10). FIG. 1 shows the cover (16) in a state in the upward position, and in this upward position, the cover (16) closes the opening (17) of the reaction tube (11) on the lower side of the manifold (14) to make the inside of the reaction tube (11) airtight. A wafer boat (3), for example made of quartz, is loaded on the cover (16). The wafer boat (3) is configured to hold and support a plurality of wafers W, which are processed as substrates, horizontally at a predetermined distance in the vertical direction. Around the reaction tube (11), an insulating body (18) is provided to surround the reaction tube (11), and on the inner wall surface thereis, a heater (19) consisting of, for example, a resistance heating element, is provided so as to heat the inside of the reaction tube (11).

[0018] In the manifold (14), a processing gas inlet pipe (21) and a purge gas inlet pipe (31) are inserted and penetrated into the lower side of the support ring (15), and the downstream end of each gas inlet pipe (21, 31) is arranged to supply gas to the wafer W inside the inner pipe (12). For example, the upstream side of the processing gas inlet pipe (21) branches out to form branching paths (22A to 22E), and each upstream end of the branching paths (22A to 22E) is connected to a source of diisopropylaminosilane (DIPAS) gas (23A), a source of disilane (Si2H6) gas (23B), a source of monoaminosilane (SiH4) gas (23C), a source of chlorine (Cl2) gas (23D), and a source of nitrogen (N2) gas (23E). And in each branch (22A to 22E), a gas supply mechanism (24A to 24E) is installed. Each gas supply mechanism (24A to 24E) is equipped with a valve or a mass flow controller and is configured to control the flow rate of the treatment gas supplied from the gas supply source (23A to 23E) to the treatment gas inlet pipe (21).

[0019] DIPAS gas is a gas for forming a seed layer to form a first seed layer on the surface of a silicon oxide film formed on the surface of wafer W, and the gas supply source (23A) and the gas supply mechanism (24A) constitute a DIPAS gas supply unit.

[0020] Si2H6 gas is a gas for forming a seed layer to form a second seed layer on the surface of a first seed layer, and the gas supply source (23B) and the gas supply mechanism (24B) constitute a Si2H6 (disilane) gas supply unit.

[0021] Since the DIPAS gas supply unit and the disilane gas supply unit are gas supply units for forming a seed layer, they may also be referred to as seed layer forming gas supply units.

[0022] In addition, in this embodiment, an example is described using two types of gases for forming a seed layer, but any one type of gas may be used for forming a seed layer. Also, when a film is formed on a wafer W on which a seed layer has already been formed, a seed layer forming gas supply unit may not be required. Furthermore, even when a seed layer forming gas supply unit is used, gases other than DIPAS gas and Si2H6 gas may be used. As such, the DIPAS gas supply unit and the disilane gas supply unit given as examples, and additionally the seed layer forming gas supply unit, may be provided as needed.

[0023] SiH4 gas is a film-forming gas for forming a silicon (Si) film on wafer W, and the gas supply source (23C) and the gas supply mechanism (24C) constitute a silicon-containing gas supply unit. Additionally, since the silicon-containing gas is a gas used for film formation, the silicon-containing gas supply unit may be referred to as a film-forming gas supply unit.

[0024] Cl2 gas is an etching gas for etching a Si film, and the gas source (23D) and gas supply mechanism (24D) constitute a chlorine gas supply unit. N2 gas is a dilution gas for changing the etching profile in the depth method of the concave portion (142) of the etching gas, and the gas source (23E) and gas supply mechanism (24E) constitute a nitrogen gas supply unit. In addition, since chlorine gas and nitrogen gas are supplied simultaneously as etching gases, the chlorine gas supply unit and the nitrogen gas supply unit may be collectively referred to as an etching gas supply unit.

[0025] Additionally, the upstream side of the purge gas inlet pipe (31) is connected to a supply source (32) of nitrogen (N2) gas, which is the purge gas. A gas supply mechanism (33) is installed in the purge gas inlet pipe (31). The gas supply mechanism (33) is configured in the same way as the gas supply mechanisms (24A to 24E) and controls the flow rate of the purge gas to the downstream side of the inlet pipe (31).

[0026] Additionally, an exhaust port (25) is opened on the side above the support ring (15) of the manifold (14), and exhaust gas generated in the inner tube (12) is exhausted to the exhaust port (25) through the space formed between the inner tube (12) and the outer tube (13). An exhaust pipe (26) is hermetically connected to the exhaust port (25). A valve (27) and a vacuum pump (28) are installed in this order on the upstream side of the exhaust pipe (26). By adjusting the opening of the valve (27), the pressure inside the reaction tube (11) is controlled to a desired pressure.

[0027] A control unit (30) configured by a computer is provided in the vertical heat treatment device, and the control unit (30) is equipped with a program. This program is configured with a set of steps to output control signals to each part of the vertical heat treatment device (1) and to control the operation of each part so as to perform a series of processing operations described later on the wafer W. Specifically, control signals are output so as to control the lifting and lowering of the cover (16) by the boat elevator (10), the output of the heater (19) (i.e., the temperature of the wafer W), the opening of the valve (27), and the flow rate of each gas supplied into the reaction tube (11) by the gas supply mechanism (24A to 24C, 33). This program is stored in the control unit (30) in a state stored on a storage medium such as, for example, a hard disk, a flexible disk, a compact disk, a magnetic optical disk (MO), or a memory card.

[0028] FIG. 2 is a drawing illustrating an example of the shape of a concave portion formed on the surface of a wafer W. As shown in FIG. 2, a silicon (Si) layer (41) is provided on the surface of the wafer W. The surface layer of the Si layer (41) is oxidized, and a silicon oxide film (43) is formed. Additionally, a concave portion (42) with a depth D and an opening width S is formed. The concave portion (42) is formed, for example, as a trench or a through hole, but the shape is not particularly specific as long as it is a recessed shape.

[0029] In FIG. 2, the aspect ratio of the concave portion (42) is D / S. The aspect ratio of the concave portion is, for example, 2 or more.

[0030] First, a general method for embedding a silicon film in a concave portion (42) by applying a DED process to a concave portion (42) as shown in FIG. 2 will be explained.

[0031] Figure 3 is a diagram illustrating an example of a general conventional DED process.

[0032] FIG. 3(a) is a diagram illustrating a seed layer formation process for forming a seed layer (44) on the surface of a wafer W having a concave portion (42) on the surface. In the seed layer formation process, a thin silicon film is formed as a seed layer (44) on the surface of a silicon oxide film (43). For the formation of the seed layer (44), for example, Si2H6 is used as a film deposition gas.

[0033] FIG. 3(b) is a diagram illustrating the first film deposition process. In the first film deposition process, for example, SiH4 gas is used as the film deposition gas, and a silicon film (45) is deposited in the concave portion (42) and formed on the surface of the wafer W.

[0034] FIG. 3(c) is a diagram illustrating an example of an etching process. In the etching process, the formed silicon film (45) is etched to widen the opening width so that the upper part is not blocked. Then, a V-shaped cross-section is formed on the silicon film (45).

[0035] Figure 3 (d) is the second film formation process. In the second film formation process, a new silicon film (45a) is deposited on a V-shaped silicon film (45) to fill the entire concave portion (42) with silicon films (45, 45a).

[0036] This filling method is a DED process, and even for the high aspect ratio concave portion (42), the filling of the silicon film (45, 45a) can be performed without voids.

[0037] FIG. 4 is a drawing illustrating the DED process when the concave portion (42) has a flat side.

[0038] FIG. 4(a) is a drawing illustrating an example of the shape of a concave portion (42). As shown in FIG. 4(a), the concave portion (42) has a flat side and a seed layer (44) is formed on the surface.

[0039] FIG. 4(b) is a diagram illustrating an example of a first film formation process. A silicon-containing gas is supplied to deposit a silicon film (45) within the concave portion (42). As a result, the opening of the concave portion (42) is narrowed.

[0040] FIG. 4(c) is a diagram illustrating an example of an etching process. In the etching process, the cross-section of the silicon film (45) deposited within the concave portion (42) is made into a V-shape. By doing so, the opening is widened.

[0041] FIG. 4(d) is a drawing illustrating an example of a second film formation process. The opening is widened, and the opening of the silicon film (45) is filled with a silicon film (45a) without forming a void, and the entire concave portion (42) can be filled with a silicon film (45, 45a) without a void.

[0042] FIG. 5 is a drawing illustrating an example of a DED process in which the side of the concave portion (42a) has a convex portion (42b) and is not a flat surface.

[0043] FIG. 5(a) is a drawing illustrating an example of the shape of a concave portion (42a). As shown in FIG. 5(a), the concave portion (42a) has a convex portion (42b) on its side, and the side is an uneven surface.

[0044] FIG. 5(b) is a drawing illustrating an example of a film formation process. In the film formation process, since the silicon film is basically formed conformally, the silicon film (45) is formed in a shape in which the convex portion (42b) protrudes inward along the shape of the concave portion (42a).

[0045] Figure 5(c) is a diagram illustrating an example of an etching process. In the etching process, the upper part is widely open because it is etched to form a V shape, but other parts are not etched much.

[0046] FIG. 5(d) is a diagram illustrating an example of a second film formation process. In the second film formation process, since the opening of the convex portion (42b) is narrowed, the silicon-containing gas does not reach the hollow portion (42c) below the concave portion (42a), and the hollow portion (42c), which is shaped like a hollow due to the presence of the convex portion (42b), is not filled, and a void remains.

[0047] That is, even if the DED process illustrated in FIGS. 3 and 4 is executed, in the case of a concave portion (42a) having irregularities, the silicon film (45, 45a) cannot be filled.

[0048] The convex portion (42b) may be formed due to issues with processing precision, or it may be formed in such a shape. In either case, since there is an uneven concave portion (42a) in the actual process, it becomes difficult to fill in this concave portion (42a) as well.

[0049] Therefore, the present disclosure proposes a method for burying a silicon film without generating voids, even in a concave portion (42a) with irregularities.

[0050] FIG. 6 is a drawing illustrating an example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. With reference to FIG. 1 and FIG. 6, a method for manufacturing a semiconductor device according to the present embodiment will be described.

[0051] First, the wafer W described in FIG. 2 is transported to and supported by a wafer boat (3) by a transport mechanism not shown. Then, the wafer boat (3) is placed on a cover (16) located in a lowered position. Then, the cover (16) is raised toward a rising position, the wafer boat (3) is brought into the reaction tube (11), and the opening (17) of the reaction tube (11) is closed by the cover (16), thereby sealing the inside of the reaction tube (11). Subsequently, as purge gas is supplied into the reaction tube (11), the inside of the reaction tube (11) is exhausted to a vacuum atmosphere of a predetermined pressure, and the wafer W is heated by a heater (19) to a predetermined temperature. At this time, the temperature is set to a predetermined film deposition temperature suitable for depositing a silicon film on the wafer W. Additionally, the temperature control of the heater (19) may be performed by a control unit (30).

[0052] For example, when using SiH4 gas as a film-forming gas, it is set to a predetermined temperature within the range of 440 to 530°C and controllable with chlorine etching gas.

[0053] Figure 6 (a) is a diagram illustrating an example of a seed layer formation process.

[0054] After heating the wafer W, the supply of purge gas is stopped, and DIPAS gas is supplied into the reaction tube (11). This DIPAS gas is deposited on the surface of the silicon oxide film (43) of the wafer W, and a seed layer (44) is formed to cover the silicon oxide film (43) (see FIG. 6 (a)).

[0055] After that, the supply of DIPAS gas is stopped, and purge gas is supplied into the reaction tube (11). After the DIPAS gas is purged from the reaction tube (11), Si2H6 gas is supplied into the reaction tube (11). This Si2H6 gas is deposited on the first seed layer, and a second seed layer is formed to cover the first seed layer. After that, the supply of Si2H6 gas is stopped, and purge gas is supplied into the reaction tube (11), and Si2H6 gas is purged from the reaction tube (11).

[0056] Figure 6(b) is a diagram illustrating an example of the first tabernacle process.

[0057] After the seed layer formation process, the supply of purge gas is stopped, and SiH4 gas is supplied into the reaction tube (11). As shown in FIG. 6(b), SiH4 gas is deposited on the second seed layer, and a Si film (44) is formed over the entire surface of the wafer W to cover the second seed layer. Then, the deposition of SiH4 gas continues, and the Si film (45) grows. That is, the film thickness of the Si film (45) increases. Then, for example, as shown in FIG. 6(b), the supply of SiH4 gas is stopped before the upper side within the concave portion (42a) is blocked by this Si film (45). At this stage, the opposing gap of the silicon film (45) in the convex portion (42b) becomes very narrow.

[0058] After the supply of the above SiH4 gas is stopped, a purge gas is supplied into the reaction tube (11), and the SiH4 gas is purged from the reaction tube (11).

[0059] FIG. 6(c) is a diagram illustrating an example of a first etching process. In the first etching process, Cl2 gas from a gas source (23D) and N2 gas from a gas source (23E) are supplied to a processing gas inlet pipe (21), mixed within the processing gas inlet pipe (21), and supplied to a wafer W within a reaction pipe (11) (Fig. 1).

[0060] Cl2 gas is an etching gas for the Si film (45), and by heating it within the reaction tube (11) and supplying thermal energy, it generates active species such as Cl radicals. Since these active species have relatively high reactivity to Si, they react with Si on the outer side of the concave portion (42) and the upper side of the concave portion (42) until they reach the lower side of the concave portion (42) of the wafer W, generating SiCl4 (silicon tetrachloride) and etching the Si film (45). Accordingly, etching is performed such that the reduction in the thickness of the Si film (45) on the upper side of the concave portion (42) is greater than the reduction in the thickness of the Si film (45) on the lower side of the concave portion (42), thereby expanding the opening width on the upper side of the concave portion (42). Additionally, 2 moles of Cl radicals are generated from 1 mole of Cl2. In other words, because a relatively large number of active species are generated, the expansion of this opening width can proceed at a relatively large speed.

[0061] At this time, the amount of nitrogen gas supplied is reduced, and etching is performed to widen the V-shaped opening. That is, etching is performed in a state close to the conventional V-shape formation.

[0062] The flow rate ratio of chlorine gas to nitrogen gas may be set such that, for example, the flow rate of chlorine gas is greater than the flow rate of nitrogen gas. For example, the flow rate ratio of chlorine gas to nitrogen gas may be set to 10:1 to 9, 10:4 to 8, or 10:6 to 7.

[0063] For example, if the flow rate of chlorine gas is 1 slm, the flow rate of nitrogen gas may be set to 0.65 slm. Etching can be performed without significantly changing the etching profile in the depth direction of the chlorine gas, in which the upper part is cut more and the lower part is cut less in the depth direction within the concave part (42a), and the opening of the silicon film (45) in the concave part (42a) can be greatly widened.

[0064] FIG. 6(d) is a diagram illustrating an example of a second etching process. In the second etching process, a V-shaped etching is performed that is close to conformal. By doing so, the opening near the convex portion (45b) within the concave portion (42a) and the hollow portion (42c) below it can be widened. By widening the opening of the convex portion (42b) and the hollow portion (42c) below it, the silicon film (45) can reach the portion of the hollow portion (42c) in the next film formation, and the film can be filled without generating voids.

[0065] In the second etching process as well, Cl2 gas from the gas source (23D) and N2 gas from the gas source (23E) are supplied to the processing gas inlet pipe (21), mixed within the processing gas inlet pipe (21), and supplied to the wafer W in the reaction pipe (11) (Fig. 1).

[0066] However, the mixing ratio of chlorine gas and nitrogen gas is different from that of the first etching gas. The second etching gas is set to weaken the effect of increasing the opening width on the upper side of the chlorine and to ensure that the etching is close to a conformal state. That is, even within the V-shape, it is adjusted to have an etching profile that has a narrow opening width and reaches deep into the surface. Specifically, the flow rate ratio of nitrogen gas is increased. The flow rate ratio of chlorine gas to nitrogen gas may be set, for example, such that the chlorine gas:nitrogen gas ratio is 1:2 to 10, 1:3 to 8, or 1:4 to 7. For example, when the flow rate of chlorine gas is 1 slm, the flow rate of nitrogen gas may be set to 5.75 slm.

[0067] By performing etching with a second etching gas having such a conformal-like etching profile, the opening width below the convex portion (42b) is widened, creating a condition where the silicon-containing gas can penetrate deep inside.

[0068] After that, the supply of Cl2 gas and N2 gas into the reaction tube (11) is stopped to end the etching process.

[0069] Next, purge gas is supplied to remove the mixed gas from the reaction tube (11). Then, after a predetermined time has elapsed, the supply of purge gas is stopped.

[0070] FIG. 6(e) is a diagram illustrating an example of a second film deposition process. In the second film deposition process, a silicon-containing gas, for example, SiH4 gas, is supplied to deposit a new silicon film (45a) on the etched silicon film (45). At that time, since the opening in the concave portion (42a) is opened with a sufficient opening width to the bottom, the silicon film (45a) can be embedded in the concave portion (42a) without generating voids.

[0071] When the filling of all the concave portions (42a) is finished, the temperature inside the reaction tube (11) is lowered. During the process, the temperature was maintained at a constant film-forming temperature, but when the processing is finished, the temperature inside the reaction tube (11) is lowered to extract the wafer W. As a result, the wafer W is cooled down.

[0072] Subsequently, the cover (16) is lowered so that the wafer boat (3) is removed from the reaction tube (11), and then the wafer W is removed from the wafer boat (3) by a conveying mechanism not shown, and the processing of one batch of wafer W is completed. Since the processing temperature can be kept constant during processing, the burial process can be performed in a short time.

[0073] In this way, according to the method for manufacturing a semiconductor device according to the present embodiment, by performing etching in two stages using two types of etching gases having different etching profiles in the depth direction, even a concave portion (42a) with irregularities can be filled into the concave portion (42a) without generating voids by widening the opening width through etching.

[0074] In addition, in FIG. 6, an example was described in which the upper opening width is widened first with a first etching gas having a strong V-shaped etching profile, and then the deep opening width is widened with a second etching gas having a weak V-shaped etching profile close to conformal; however, depending on the shape of the concave portion (42a), it may be better to reverse the order.

[0075] Therefore, in such cases, a two-stage etching process may be performed in which a narrow opening is formed to a depth in the first etching and the upper opening is widened in the second stage. Additionally, a two-stage etching process may be carried out by introducing an etching gas having another etching profile or a dilution gas having a different profile.

[0076] Thus, according to the method for manufacturing a semiconductor device according to the present embodiment, depending on the shape of the unevenness of the concave portion (42a), it is possible to determine in what order to form an opening, and accordingly, perform two stages of etching, and if necessary, three stages of etching, to form an opening that does not generate voids.

[0077] Next, the etching characteristics of the first etching gas and the second etching gas will be explained.

[0078] FIG. 7 is a diagram illustrating the etching profile in the depth direction of the first etching gas and the second etching gas.

[0079] FIG. 7(a) is a diagram illustrating an example of the first etching gas in FIG. 6. The first etching gas is a gas with a low dilution amount of nitrogen gas. In FIG. 7(a), an example is shown where the chlorine / nitrogen ratio is 1 slm / 0.65 slm. In this way, the first etching gas may be composed by mixing such that the flow rate of chlorine is higher than the flow rate of nitrogen. By doing so, the etching profile of the chlorine gas and chlorine radicals, which widens the upper opening width, is preserved, and a strong V-shaped opening can be formed.

[0080] In FIG. 7(a), data is shown for the case where the first etching is performed under conditions of 375°C and 3 Torr. Specifically, if the thickness of the silicon film at the wafer surface between the concave parts is denoted as top, the thickness of the film on the side of the concave part as side, and the thickness of the film on the bottom surface of the concave part as bottom, then side / top is 106.4%, while bottom / top is 146.0%, and the etching profile has a strong V-shape, with a large opening at the top and not much etched at the bottom. This etching profile is effective for greatly widening the opening at the top of the concave part.

[0081] FIG. 7(b) is a diagram illustrating an example of the second etching gas in FIG. 6. The first etching gas is a gas with a low dilution amount of nitrogen gas. In FIG. 7(b), an example is shown where the chlorine / nitrogen ratio is 1 slm / 5.75 slm. In this way, the first etching gas may be composed by mixing such that the flow rate of chlorine is higher than the flow rate of nitrogen. As a result, the upper etching amount of the chlorine gas and chlorine radicals is significantly greater than the lower etching amount, and the etching profile that widens the opening width is preserved, allowing a strong V-shaped opening to be formed.

[0082] In FIG. 7(b), data is shown for a second etching performed under conditions of 375°C and 3 Torr, similar to FIG. 7(a). Specifically, if the thickness of the silicon film at the wafer surface between the concave parts is denoted as top, the thickness of the film on the side of the concave part as side, and the thickness of the film on the bottom surface of the concave part as bottom, then side / top is 104.1%, while bottom / top is 125.1%, resulting in a conformal etching profile with a weak V-shape and little difference between the etching amount of the upper part and the etching amount of the lower part. This etching profile is effective for widening the openings of the upper and lower parts of the concave part with the same level of etching amount.

[0083] In this way, by performing two-stage etching using two types of etching gases having different etching profiles in the depth direction of the concave portion, an opening with an appropriate opening width can be formed even if there are irregularities within the concave portion.

[0084] Next, various embodiments of the DED process using the first etching and the second etching will be described.

[0085] FIG. 8 is a process flowchart illustrating a method for manufacturing a semiconductor device according to a first embodiment. This is the simplest process, similar to that described in FIG. 6.

[0086] In step S10, a first film formation process is performed. This corresponds to the process illustrated in FIG. 6 (b). That is, a silicon film (45) is deposited within a concave portion (42a) formed on the surface of the seed layer (44). The silicon film (45) is formed conformally along the shape of the concave portion (42a).

[0087] In step S20, a first etching process is performed. This is a process corresponding to (c) of FIG. 6. In the first etching process, a first etching gas having the characteristic that the upper side has a greater amount of etching than the lower side is used to widen the upper opening of the silicon film (45).

[0088] In step S30, a second etching process is performed. This is a process corresponding to (d) of FIG. 6. In the second etching process, a second etching gas having a conformal etching profile with little difference in the amount of etching between the upper and lower parts is used to perform etching that widens the opening of the convex part (42b) and the concave part (42c) below it.

[0089] In step S40, a second film formation process is performed. This is a process corresponding to (e) of FIG. 6. In the second film formation process, a film is formed to fill the opening widened by the second etching and the opening widened by the first etching.

[0090] In step S50, a determination is made as to whether the concave portion (42a) has been filled. In FIG. 6, an example is described in which the concave portion (42a) can be completely filled in two stages. However, in cases where the aspect ratio is high or the shape of the concave portion (42a) is complex, the concave portion (42a) may not be completely filled in two stages.

[0091] Accordingly, in step S50, a determination is made as to whether the silicon film (45a) is completely filled in the concave portion (42a). If it is filled, the processing flow is terminated. On the other hand, if it is not filled, the process returns to step S20 and repeats the second film formation process from the first etching process. In step S50, when it is determined that the concave portion (42a) is filled with silicon films (45, 45a), the processing flow is terminated.

[0092] The processing flow of Fig. 8 is a process that repeats DE1E2D as one cycle when the first etching process is E1, the second etching process is E2, and the film deposition process is D.

[0093] For example, with this processing flow, the inside of the concave portion (42a) can be filled without creating a void within the concave portion (42a).

[0094] In addition, the supply of purge gas may be appropriately performed when switching between the film deposition process and the etching process.

[0095] FIG. 9 is a process flowchart illustrating an example of a method for manufacturing a semiconductor device according to a second embodiment. In FIG. 9, for processing contents identical to the method for manufacturing a semiconductor device according to a first embodiment, the same step number is assigned, and the description of the contents of each individual step is omitted.

[0096] In step S10, a first film formation process is performed so that a silicon film (45) is formed on the seed layer (44).

[0097] In step S20, a first etching process is performed so that the upper opening of the silicon film (45) is widened.

[0098] In step S40, a second film deposition process is performed. This is different from the method of manufacturing a semiconductor device according to the first embodiment. That is, the first etching process and the second etching process do not necessarily have to be performed in succession, and a film deposition process may be inserted in between. Since the upper opening is enlarged in the first etching process and the silicon film (45) in the film deposition process is deposited conformally, the film deposition is performed while maintaining the state of the upper opening being large.

[0099] In step S30, a second etching process is performed. After the film is formed, the opening below the convex portion (42b) is widened.

[0100] In step S41, a third film deposition process is performed. In the third film deposition process, a new silicon film (45a) is deposited on the silicon film (45) on which the second etching was performed.

[0101] In step S50, it is determined whether the concave portion (42a) is completely filled with the silicon film (45, 45a). When the concave portion (42a) can be completely filled and the state shown in (e) of FIG. 6 is reached, the processing flow is terminated.

[0102] However, if the concave portion (42a) is not yet filled, return to step S20 and perform the first etching process. Repeat the first etching process of step S20 up to the third film formation process, and at step S50, when the concave portion (42a) is completely filled with silicon film (45, 45a), the processing flow is terminated.

[0103] The method for manufacturing a semiconductor device according to the second embodiment is a process of DE1DE2D, and after the first D, E1DE2D is one cycle, and this cycle is repeated until the concave portion (42a) is filled. In this way, a film deposition process may be inserted between the first etching process and the second etching process. Also, since the film deposition process is performed under the same conditions without changing the conditions, all are represented as D.

[0104] FIG. 10 is a diagram showing the processing flow of a method for manufacturing a semiconductor device according to a third embodiment. As with FIG. 9, in the case of process contents identical to the processing flow of FIG. 8, the same step number is used and the description is omitted.

[0105] In step S10, a first film formation process is performed to form a silicon film (45) on the seed layer (44).

[0106] In step S20, a first etching process is performed to widen the upper opening of the silicon film (45).

[0107] In step S60, it is determined whether the thickness of the silicon film (45) formed in the first film deposition process and the upper opening formed in the first etching process are appropriate. If the film thickness is insufficient or the size of the opening is insufficient, the process returns to the first film deposition process of step S10 and repeats the first film deposition process S10 and the first etching process of step S20.

[0108] In step S60, if it is determined that the film thickness and upper opening of the silicon film (45) are sufficient, the process proceeds to the second film formation process of step S40.

[0109] In step S30, a second etching process is performed. In the second etching process, the silicon film (45) above the convex portion (42b) and below the convex portion (42b) is etched to widen the opening of the silicon film (45) above the convex portion (42b) and below the convex portion (42b).

[0110] In step S41, a third film deposition process is performed. In the third film deposition process, a new silicon film (45a) is deposited on the silicon film (45) etched in the second etching process.

[0111] In step S50, it is determined whether the concave portion (42a) is filled with a silicon film (45, 45a). If it is filled, the processing flow is terminated.

[0112] Meanwhile, if the concave portion (42a) is not filled with silicon film (45, 45a), return to step S30 and perform the second etching process again. The second etching process of step S30 and the third film formation process of step S41 are repeated until the concave portion (42a) is filled with silicon film (45, 45a).

[0113] And, if it is determined in step S50 that the concave portion (42a) is filled with a silicon film (45, 45a), the processing flow is terminated.

[0114] In this way, it may be a sequence that repeats the cycle of DE1, then performs D, and then repeats the cycle of E2D.

[0115] As described above in the first to third embodiments, the film formation process, the first etching process, and the second etching process can be carried out in various combinations.

[0116] In the first to third embodiments, a judgment location is provided, but the configuration may also involve determining the appropriate number of DE repetitions in advance and performing a preset number of DE cycles.

[0117] In addition, the order of the first etching process and the second etching process may be reversed in terms of the shape of the concave portion (42a), or a combination of etching processes of another profile may be used.

[0118] In this way, by performing two different types of etching in the DED process, even if irregularities are formed on the side of the concave portion (42a), the silicon film (45, 45a) can be filled without voids.

[0119] In this embodiment, although an example was described using a vertical heat treatment device as a substrate processing device, it is also possible to configure the substrate processing device as a single-wafer type film deposition device or a semi-batch type film deposition device that performs ALD (Atomic Layer Deposition) on about 5 to 6 wafers W using a rotary table.

[0120] In addition, it is also possible to apply the same principle to a substrate processing device using plasma. That is, the method for manufacturing a semiconductor device and the substrate processing device according to the present embodiment can be widely applied to a process for embedding a silicon film in a recess using a DED process and to a substrate processing device.

[0121] Although preferred embodiments of the present disclosure have been described in detail above, the present disclosure is not limited to the embodiments described above, and various modifications and substitutions can be made to the embodiments described above without departing from the scope of the present invention.

Claims

Claim 1 A method for manufacturing a semiconductor device comprising: a process of supplying a silicon-containing gas to a substrate having a concave portion provided on its surface to deposit a silicon film within the concave portion; a process of supplying a first etching gas having a first etching profile having different etching amounts at the top and bottom in the depth direction of the concave portion to the substrate to etch the silicon film within the concave portion; a process of supplying a second etching gas having a second etching profile different from the first etching profile of the first etching gas to the substrate to etch the silicon film within the concave portion; and a process of newly depositing the silicon film on the silicon film etched by the second etching gas. Claim 2 A method for manufacturing a semiconductor device according to claim 1, wherein the first etching profile of the first etching gas has an upper etching amount greater than the lower etching amount in the depth direction of the concave portion, and the second etching profile of the second etching gas has a ratio in which the upper etching amount is greater than the lower etching amount that is less than the first etching profile, or the upper etching amount and the lower etching amount are the same. Claim 3 A method for manufacturing a semiconductor device according to claim 2, wherein the first etching profile is a profile that widens the opening of the silicon film on the upper side to form a shallow V-shaped opening, and the second etching profile is a profile that forms a deep V-shape in the silicon film on the lower side. Claim 4 A method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the first etching gas and the second etching gas are produced by adding a diluent gas of a different flow rate to the same etching gas. Claim 5 A method for manufacturing a semiconductor device according to claim 4, wherein the same etching gas is chlorine. Claim 6 A method for manufacturing a semiconductor device, wherein, in paragraph 4, the diluting gas is an inert gas. Claim 7 A method for manufacturing a semiconductor device according to claim 4, wherein the flow rate of the dilution gas is such that the second etching gas is greater than the first etching gas. Claim 8 A method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the concave portion has a shape including irregularities on the side. Claim 9 A method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the process of supplying the first etching gas to etch the silicon film within the concave portion, the process of supplying the second etching gas to the substrate to etch the silicon film within the concave portion, and the process of depositing a new electrical silicon film on the silicon film are repeated. Claim 10 A method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein, between the process of supplying the first etching gas to etch the silicon film within the concave portion and the process of supplying the second etching gas to the substrate to etch the silicon film within the concave portion, the method further comprises the process of depositing a new silicon film on the silicon film etched by the first etching gas. Claim 11 A process comprising: supplying a silicon-containing gas to a substrate having a concave portion provided on its surface to deposit a silicon film within the concave portion; supplying a first etching gas having a first etching profile having different etching amounts at the top and bottom in the depth direction of the concave portion to the substrate to etch the silicon film within the concave portion; and performing a cycle at least once comprising a process of newly depositing the silicon film on the silicon film etched by the first etching gas; a process comprising supplying the first etching gas to etch the silicon film within the concave portion; and performing a first cycle at least once comprising a process of supplying the first etching gas to etch the silicon film within the concave portion and a process of newly depositing the silicon film on the silicon film; a process comprising supplying a second etching gas having a second etching profile different from the first etching profile of the first etching gas to the substrate to etch the silicon film within the concave portion; and the silicon film etched by the second etching gas A method for manufacturing a semiconductor device having a process of performing a second cycle at least once, the process of newly depositing the silicon film on the silicon film, the process of supplying the second etching gas to etch the silicon film within the concave portion, and the process of newly depositing the silicon film on the silicon film. Claim 12 A method for manufacturing a semiconductor device according to claim 11, wherein the first etching profile of the first etching gas has an upper etching amount greater than the lower etching amount in the depth direction of the concave portion, and the second etching profile of the second etching gas has a ratio in which the upper etching amount is greater than the lower etching amount that is less than the first etching profile, or the upper etching amount and the lower etching amount are the same. Claim 13 A method for manufacturing a semiconductor device according to claim 12, wherein the first etching profile is a profile that widens the opening of the silicon film on the upper side to form a shallow V-shaped opening, and the second etching profile is a profile that forms a deep V-shape in the silicon film on the lower side. Claim 14 A method for manufacturing a semiconductor device according to any one of claims 11 to 13, wherein the first etching gas and the second etching gas are produced by adding a diluent gas of a different flow rate to the same etching gas. Claim 15 A method for manufacturing a semiconductor device according to claim 14, wherein the same etching gas is chlorine. Claim 16 A method for manufacturing a semiconductor device, wherein, in paragraph 14, the diluting gas is an inert gas. Claim 17 A method for manufacturing a semiconductor device according to claim 14, wherein the flow rate of the dilution gas is such that the second etching gas is greater than the first etching gas. Claim 18 A method for manufacturing a semiconductor device according to any one of claims 11 to 13, wherein the concave portion has a shape including irregularities on its side. Claim 19 A method for manufacturing a semiconductor device according to any one of claims 11 to 13, wherein the process of supplying the first etching gas to etch the silicon film within the concave portion, the process of supplying the second etching gas to the substrate to etch the silicon film within the concave portion, and the process of depositing a new electrical silicon film on the silicon film are repeated. Claim 20 A substrate processing apparatus comprising: a processing chamber; a substrate holding support member provided in the processing chamber and capable of holding and supporting a substrate having a concave portion formed on its surface; a silicon-containing gas supply unit that supplies a silicon-containing gas to the substrate to deposit a silicon film within the concave portion; a first etching gas supply unit that supplies a first etching gas having a first etching profile having different etching amounts at the top and bottom in the depth direction of the concave portion to the substrate to etch the silicon film within the concave portion; a second etching gas supply unit that supplies a second etching gas having a second etching profile different from the first etching profile of the first etching gas to the substrate to etch the silicon film within the concave portion; and a control unit that supplies the silicon-containing gas from the silicon-containing gas supply unit to deposit a new silicon film on the silicon film etched by the second etching gas.

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