Stretchable display device

Abstract

The present invention relates to a display device capable of reducing the width of a non-display area of ​​a display panel. A display device according to an embodiment comprises a display area and a dummy area disposed on one side of the display area. Each of the display area and the dummy area includes a first island pattern and a second island pattern disposed apart from each other, and a connecting pattern connecting the first island pattern and the second island pattern. The dummy area includes, in each of the first island pattern and the second island pattern, a dummy common electrode and a common connecting electrode electrically connected to the dummy common electrode.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to show images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may be a flat panel display device such as a Liquid Crystal Display Device, a Field Emission Display Device, or a Light Emitting Display Device. The Light Emitting Display Device includes an Organic Light Emitting Display Device comprising an Organic Light Emitting Element, an Inorganic Light Emitting Display Device comprising an Inorganic Light Emitting Element such as an Inorganic Semiconductor, and a Micro Light Emitting Display Device comprising a Micro Light Emitting Element. Recently, Light Emitting Display Devices are being developed as display devices capable of stretching vertically and / or horizontally. The problem to be solved

[0004] The problem that the present invention aims to solve is to provide a display device capable of reducing the width of the non-display area of ​​a display panel.

[0005] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A display device according to one embodiment for solving the above problem comprises a display area and a dummy area disposed on one side of the display area. Each of the display area and the dummy area includes a first island pattern and a second island pattern disposed apart from each other, and a connecting pattern connecting the first island pattern and the second island pattern. The dummy area includes, in each of the first island pattern and the second island pattern, a dummy common electrode and a common connecting electrode electrically connected to the dummy common electrode.

[0007] A display device according to another embodiment for solving the above problem comprises a display area and a dummy area disposed on one side of the display area. Each of the display area and the dummy area includes a first island pattern and a second island pattern disposed apart from each other, and a connecting pattern connecting the first island pattern and the second island pattern. The display area includes a light-emitting element comprising, in each of the first island pattern and the second island pattern, a pixel electrode, a display light-emitting layer disposed on the pixel electrode, and an island common electrode disposed on the display light-emitting layer. The dummy area includes a dummy light-emitting layer comprising the same material as the display light-emitting layer in each of the first island pattern and the second island pattern. The connecting pattern is bent or unfolded.

[0008] A display device according to another embodiment for solving the above problem comprises a display area including display pixels, a scan driver that outputs scan signals to scan lines connected to the display pixels, and a dummy area disposed between the display area and the scan driver. Each of the display area, the dummy area, and the scan driver includes a first island pattern and a second island pattern disposed apart from each other, and a connection pattern connecting the first island pattern and the second island pattern. The scan driver includes a plurality of scan transistors disposed in each of the first island pattern and the second island pattern.

[0009] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0010] According to the display device of the embodiments, the first power wiring may not be placed at the edge of the display panel but may be placed in a dummy area where dummy light-emitting layers are placed. That is, the first power wiring may be placed in the dummy area overlapping with the dummy light-emitting layers. Therefore, the first power wiring placed to the left of the first scan driving unit and to the right of the second scan driving unit can be omitted, thereby reducing the width of the non-display area.

[0011] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0012] FIG. 1 is a plan view showing a display device according to one embodiment. FIG. 2 is a circuit diagram showing a display pixel of a display area according to one embodiment. FIG. 3 is an example drawing showing a first scan driving unit according to one embodiment. FIGS. 4 and FIGS. 5 are layout diagrams showing a display area in detail according to one embodiment. Figure 6 is a layout diagram showing the first island pattern of Figure 4 in detail. FIGS. 7 and FIGS. 8 are perspective views showing first and second island patterns and a second connection pattern according to one embodiment. FIGS. 9 and FIGS. 10 are layout diagrams showing a first dummy region in detail according to one embodiment. Figure 11 is a layout diagram showing the first island pattern of Figure 9 in detail. FIGS. 12 and FIGS. 13 are layout diagrams showing in detail a first scan driving unit according to one embodiment. FIG. 14 is a cross-sectional view showing an example of a display panel cut along A-A' of FIG. 6. FIG. 15 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 11. FIG. 16 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 12. Figure 17 is a layout diagram showing in detail an example of area A of Figure 11. FIG. 18 is a cross-sectional view showing an example of a display panel cut along D-D' of FIG. 17. Figure 19 is a layout diagram showing in detail another example of area A of Figure 11. FIG. 20 is a cross-sectional view showing an example of a display panel cut along E-E' of FIG. 19. FIG. 21 is a layout diagram showing in detail the first island pattern of the first dummy area according to another embodiment. FIG. 22 is a cross-sectional view showing an example of a display panel cut along F-F' of FIG. 21. FIG. 23 is a layout diagram showing in detail the first island pattern of the first dummy area according to another embodiment. FIG. 24 is a cross-sectional view showing an example of a display panel cut along G-G' of FIG. 23. FIG. 25 is a layout diagram showing a display area in detail according to another embodiment. FIG. 26 is a layout diagram showing a first dummy region in detail according to another embodiment. FIG. 27 is a layout diagram showing in detail a first scan driving unit according to another embodiment. Specific details for implementing the invention

[0013] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0014] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0015] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0016] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0017] Specific embodiments will be described below with reference to the attached drawings.

[0018] FIG. 1 is a plan view showing a display device according to one embodiment.

[0019] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0020] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Although the following description focuses on the display device (10) being an organic light-emitting display device, the present invention is not limited thereto.

[0021] The display device (10) includes a display panel (100), a display driving circuit (200), and a circuit board (300).

[0022] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed at a right angle or rounded to have a predetermined curvature. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0023] The display panel (100) may include a display area (DA) for displaying images and a non-display area (NDA) for not displaying images.

[0024] The display area (DA) may include display pixels (SPX in FIG. 2) that display an image. The display area (DA) may occupy most of the area of ​​the display panel (100). The display area (DA) may be placed in the center of the display panel (100).

[0025] The non-display area (NDA) may be positioned adjacent to the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0026] The non-display area (NDA) may include a first dummy area (DMA1) and a second dummy area (DMA2), a first scan drive unit (SDC1), a second scan drive unit (SDC2), and a pad area (PDA).

[0027] A first dummy region (DMA1) may be placed on one side (e.g., the left) of the display region (DA), and a second dummy region (DMA2) may be placed on the other side (e.g., the right) of the display region (DA). The first dummy region (DMA1) and the second dummy region (DMA2) may be regions designed with consideration for the deposition quality of the display light-emitting layers (ELs) of the display pixels (SPXs in FIG. 2) placed at the edges of the fine metal mask when forming the display light-emitting layers (ELs) of the display pixels (SPXs in FIG. 2) of the display region (DA) using a fine metal mask. Therefore, dummy light-emitting layers (DELs) containing substantially the same material as the display light-emitting layers (ELs) of the display pixels (SPXs in FIG. 2) may be placed in the first dummy region (DMA1) and the second dummy region (DMA2).

[0028] The first scan drive unit (SDC1) may be positioned adjacent to the first dummy area (DMA1). The first scan drive unit (SDC1) may be positioned to the left of the first dummy area (DMA1).

[0029] The second scan drive unit (SDC2) may be positioned adjacent to the second dummy area (DMA2). The second scan drive unit (SDC2) may be positioned to the right of the second dummy area (DMA2).

[0030] Each of the first scan driver (SDC1) and the second scan driver (SDC2) may include a scan signal output unit connected to scan wiring of the display area (DA). The scan wiring may include scan write wiring (GWLk in FIG. 2) and scan initialization wiring (GILk in FIG. 2). Additionally, each of the first scan driver (SDC1) and the second scan driver (SDC2) may include a light emission signal output unit connected to light emission wiring (EMLk in FIG. 2) of the display area (DA).

[0031] The first scan driver (SDC1) can be connected to the display pads (PDs) of the pad area (PDA) through the first scan control wires (GCL1). The second scan driver (SDC2) can be connected to the display pads (PDs) of the pad area (PDA) through the second scan control wires (GCL2). As a result, the first scan driver (SDC1) and the second scan driver (SDC2) can each be electrically connected to the display pads (PDs) of the pad area (PDA) and to the display driving circuit (200) through the circuit board (300).

[0032] The scan signal output units of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) respectively receive a scan control signal from the display driving circuit (200) and can generate scan signals according to the scan control signal and output them to the scan wires. Additionally, the light emission signal output units of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) respectively receive a light emission control signal from the display driving circuit (200) and can generate light emission signals according to the light emission control signal and output them to the light emission wires.

[0033] The first power line (VSL) may be placed in the non-display area (NDA). The first power line (VSL) may be placed to surround the display area (DA). The first power line (VSL) may be placed in the lower and upper sides of the display area (DA), the first dummy area (DMA1), and the second dummy area (DMA2). The first power line (VSL) may be connected to the display pads (PD) of the pad area (PDA). That is, the first power line (VSL) may be electrically connected to the circuit board (300) through the display pads (PD) of the pad area (PDA). Therefore, the first power line (VSL) may receive a first power voltage from the circuit board (300).

[0034] The first power connection wires (VSCL) can be placed in the display area (DA), the first dummy area (DMA1), and the second dummy area (DMA2). The first power connection wires (VSCL) can be extended in the first direction (DR1). The first power connection wires (VSCL) can be connected to the first power wire (VSL) in each of the first dummy area (DMA1) and the second dummy area (DMA2). As a result, the first power voltage of the first power wire (VSL) can be supplied to the first power connection wires (VSCL).

[0035] A pad area (PDA) may be placed on one side (e.g., the lower side) of a display panel (100). The pad area (PDA) may include a plurality of display pads (PDs).

[0036] The display driving circuit (200) can generate signals and voltages to drive the display panel (100). The display driving circuit (200) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a chip-on-film (COF) manner.

[0037] The circuit board (300) can be attached to a pad area (PDA) located at one end of the display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100). The display panel (100) can receive power voltages through the circuit board (300) and receive scan control signals and data voltages of the display driving circuit (200). The circuit board (300) may be a flexible film, such as a chip-on-film.

[0038] As shown in FIG. 1, the first power wiring (VSL) is not placed at the edge of the display panel (100) but can be placed in the first dummy area (DMA1) and the second dummy area (DMA2) where dummy light-emitting layers (DEL) are placed. Therefore, the first power wiring placed to the left of the first scan drive unit (SDC1) and to the right of the second scan drive unit (SDC2) can be omitted, thereby reducing the width of the non-display area.

[0039] FIG. 2 is a circuit diagram showing a display pixel of a display area according to one embodiment.

[0040] Referring to FIG. 2, a display pixel (SPX) according to one embodiment may be connected to a k-th (k is a positive integer) scan initialization wire (GILk), a k-th scan write wire (GWLk), and a k-th light-emitting wire (EMLk). Additionally, the display pixel (SPX) may be connected to a first power wire (VSL) to which a first power voltage is supplied, a second power wire (VDL) to which a second power voltage is applied, and an initialization voltage wire (VIL) to which an initialization voltage is supplied.

[0041] A display pixel (SPX) may include an emitting unit (ELU) and a pixel driving unit (DDU). The emitting unit (ELU) may include a light-emitting element (LE). The pixel driving unit (DDU) may supply a driving voltage to drive the light-emitting element (LE) to the pixel electrode of the light-emitting element (LE). The pixel driving unit (DDU) may include a driving transistor (DT), switching elements, and a capacitor (CST1). The switching elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0042] The driving transistor (DT) may include a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls the drain-source current (Ids, hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0043] The light-emitting element (LE) emits light according to the driving current (Ids). The greater the driving current (Ids), the greater the amount of light emitted by the light-emitting element (LE).

[0044] The light-emitting element (LE) may be an organic light-emitting diode comprising an organic light-emitting layer disposed between an anode electrode and a cathode electrode. Alternatively, the light-emitting element (LE) may be an inorganic light-emitting element comprising an inorganic semiconductor disposed between an anode electrode and a cathode electrode. Alternatively, the light-emitting element (LE) may be a quantum dot light-emitting element comprising a quantum dot light-emitting layer disposed between an anode electrode and a cathode electrode. Alternatively, the light-emitting element (LE) may be a micro light-emitting element comprising a micro light-emitting diode disposed between an anode electrode and a cathode electrode.

[0045] The anode electrode of the light-emitting element (LE) is connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode can be connected to the first power wiring (VSL). A parasitic capacitance (Cel) may be formed between the anode electrode and the cathode electrode of the light-emitting element (LE).

[0046] The anode electrode of the light-emitting element (LE) may be the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) shown in FIGS. 4 and 5. Additionally, the cathode electrode of the light-emitting element (LE) may be the common island electrode (ICE) shown in FIGS. 4 and 5.

[0047] The first transistor (ST1) is turned on by a scan initialization signal of the k-th scan initialization wire (GILk) to connect the gate electrode of the driving transistor (DT) to the initialization voltage wire (VIL). As a result, the third power supply voltage of the initialization voltage wire (VIL) can be applied to the gate electrode of the driving transistor (DT). The gate electrode of the first transistor (ST1) is connected to the k-th scan initialization wire (GILk), the first electrode is connected to the gate electrode of the driving transistor (DT), and the second electrode can be connected to the initialization voltage wire (VIL).

[0048] The second transistor (ST2) is turned on by a scan write signal of the k-th scan write line (GWLk) to connect the first electrode of the driving transistor (DT) to the j-th (j is a positive integer) data line (Dj). As a result, the data voltage of the j-th data line (Dj) can be applied to the first electrode of the driving transistor (DT). The gate electrode of the second transistor (ST2) is connected to the k-th scan write line (GWLk), the first electrode is connected to the first electrode of the driving transistor (DT), and the second electrode can be connected to the j-th data line (Dj). The j-th data line (Dj) can be connected to a display pad (PD).

[0049] The third transistor (ST3) is turned on by the scan write signal of the k-th scan write wire (GWLk) to connect the gate electrode of the driving transistor (DT) and the second electrode. When the gate electrode of the driving transistor (DT) and the second electrode are connected, the driving transistor (DT) is driven by a diode. The gate electrode of the third transistor (ST3) is connected to the k-th scan write wire (GWLk), the first electrode is connected to the second electrode of the driving transistor (DT), and the second electrode can be connected to the gate electrode of the driving transistor (DT).

[0050] The fourth transistor (ST4) is turned on by a scan write signal of the k-th scan write wire (GWLk) to connect the anode electrode of the light-emitting element (LE) to the initialization voltage wire (VIL). The third power supply voltage of the initialization voltage wire (VIL) can be applied to the anode electrode of the light-emitting element (LE). The gate electrode of the fourth transistor (ST4) is connected to the k-th scan write wire (GWLk), the first electrode is connected to the anode electrode of the light-emitting element (LE), and the second electrode is connected to the initialization voltage wire (VIL).

[0051] Alternatively, the third transistor (ST3) may be turned on by a scan initialization signal of the k-th scan initialization wire (GILk). In this case, the gate electrode of the third transistor (ST3) may be connected to the k-th scan initialization wire (GILk).

[0052] The fifth transistor (ST5) is turned on by the light emission signal of the k-th light emission wiring (EMLk) to connect the first electrode of the driving transistor (DT) to the second power supply wiring (VDL). The gate electrode of the fifth transistor (ST5) is connected to the k-th light emission wiring (EMLk), the first electrode is connected to the second power supply wiring (VDL), and the second electrode is connected to the first electrode of the driving transistor (DT).

[0053] The sixth transistor (ST6) is positioned between the second electrode of the driving transistor (DT) and the anode electrode of the light-emitting element (LE). The sixth transistor (ST6) is turned on by a light-emitting control signal of the k-th light-emitting wiring (EMLk) to connect the second electrode of the driving transistor (DT) to the anode electrode of the light-emitting element (LE). The gate electrode of the sixth transistor (ST6) is connected to the k-th light-emitting wiring (EMLk), the first electrode is connected to the second electrode of the driving transistor (DT), and the second electrode is connected to the anode electrode of the light-emitting element (LE).

[0054] When both the fifth transistor (ST5) and the sixth transistor (ST6) are turned on, the driving current (Ids) of the driving transistor (DT), according to the data voltage applied to the gate electrode of the driving transistor (DT), can flow to the light-emitting element (LE).

[0055] A capacitor (CST1) is formed between the gate electrode of the driving transistor (DT) and the second power line (VDL). The first capacitor electrode of the capacitor (CST1) is connected to the gate electrode of the driving transistor (DT), and the second capacitor electrode can be connected to the second power line (VDL).

[0056] If the first electrode of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) is a source electrode, the second electrode may be a drain electrode. Alternatively, if the first electrode of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) is a drain electrode, the second electrode may be a source electrode.

[0057] The active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may be formed from any one of polysilicon, amorphous silicon, and oxide semiconductor. In FIG. 2, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) are described primarily as being formed as P-type MOSFETs, but are not limited thereto. For example, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may be formed as N-type MOSFETs. Alternatively, at least one of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) may be formed as an N-type MOSFET.

[0058] FIG. 3 is an example drawing showing a scan signal output section of a first scan driving unit according to one embodiment.

[0059] Referring to FIG. 3, the scan signal output unit (SOU) of the first scan driving unit (SDC1) may include a plurality of stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1, where m is a positive integer). Each of the plurality of stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1) may include a start signal input unit (ST), a reset signal input unit (RT), a clock signal input unit (CKT), a scan signal output unit (SOUT), and a carry signal output unit (COUT).

[0060] Each start signal input (ST) of a plurality of stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1) may be connected to a start wiring (STRL) or a carry signal output (COUT) of a previous stage. For example, the start signal input (ST) of the first stage (STA1) may be connected to a scan start wiring (STRL) into which a scan start signal is input. Additionally, each start signal input (ST) of a plurality of stages (STA2, STA3, STA4, …, STAm-1, STAm, STAm+1), excluding the first stage (STA1), may be connected to a carry signal output (COUT) of a previous stage. For example, the start signal input (ST) of the second stage (STA2) can be connected to the carry signal output (COUT) of the first stage (STA1), and the start signal input (ST) of the third stage (STA3) can be connected to the carry signal output (COUT) of the second stage (STA2).

[0061] Multiple stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1) and their respective reset signal inputs (RT) can be connected to the carry signal outputs (COUT) of subsequent stages. For example, the reset signal input (RT) of the first stage (STA1) can be connected to the carry signal output (COUT) of the fifth stage (STA5).

[0062] Each clock signal input (CKT) of a plurality of stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1) can be connected to any one of the clock wires (CKL1, CKL2, CKL3, CKL4).

[0063] Multiple stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1) may be alternately connected to clock wires (CKL1, CKL2, CKL3, CKL4). For example, the clock signal input (CKT) of the first stage (STA1) may be connected to the first clock wire (CKL1), and the clock signal input (CKT) of the second stage (STA2) may be connected to the second clock wire (CKL2). The clock signal input (CKT) of the third stage (STA3) may be connected to the third clock wire (CKL3), and the clock signal input (CKT) of the fourth stage (STA4) may be connected to the fourth clock wire (CKL4).

[0064] Each scan signal output (SOUT) of a plurality of stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1) can be connected to a corresponding scan write wire and scan initialization wire. For example, the first stage (STA1) can be connected to the first scan initialization wire (GIL1). Additionally, the second stage (STA2) can be connected to the second scan initialization wire (GIL2) and the first scan write wire (GWL1). Additionally, the third stage (STA3) can be connected to the third scan initialization wire (GIL3) and the second scan write wire (GWL2). Additionally, the fourth stage (STA4) can be connected to the fourth scan initialization wire (GIL4) and the third scan write wire (GWL3). Additionally, the m-1 stage (STAm-1) can be connected to the m-1 scan initialization wiring (GILm-1) and the m-2 scan write wiring (GWLm-2). Additionally, the m stage (STAm) can be connected to the m scan initialization wiring (GILm) and the m-1 scan write wiring (GWLm-1). Furthermore, the m+1 stage (STAm+1) can be connected to the m scan write wiring (GWLm).

[0065] Each carry signal output (COUT) of a plurality of stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1) can be connected to the reset signal input (RT) of the previous stage and the start signal input (ST) of the subsequent stage. However, each carry signal output (COUT) of the first stage (STA1), the second stage (STA2), the third stage (STA3), and the fourth stage (STA4) can be connected only to the start signal input (ST) of the subsequent stage.

[0066] Meanwhile, the scan signal output section of the second scan drive unit (SDC2) may be substantially the same as the scan signal output section of the first scan drive unit (SDC1) described in conjunction with Fig. 3, so a description thereof is omitted.

[0067] FIGS. 4 and FIGS. 5 are layout diagrams showing a display area in detail according to one embodiment. FIG. 6 is a layout diagram showing a first island pattern of FIG. 4 in detail.

[0068] FIG. 4 shows island patterns (ISP1~ISP4), incision patterns (CNP1~CNP8), and incisions (CUP1~CUP4) of the display area (DA) when the display device (10) is contracted. FIG. 5 shows island patterns (ISP1~ISP4), incision patterns (CNP1~CNP8), and incisions (CUP1~CUP4) of the display area (DA) when the display device (10) is extended.

[0069] Referring to FIGS. 4 to 6, the substrate (SUB) may include island patterns (ISP) and connection patterns (CNP) cut by cut portions (CUP1 to CUP4) in the display area (DA). The cut portions (CUP1 to CUP4) may be areas where the substrate (SUB) is removed by a patterning process such as a laser process or a dry etching process.

[0070] The display area (DA) may include first to fourth island patterns (ISP1~ISP4), first to eighth connection patterns (CNP1~CNP8), and first to fourth incisions (CUP1~CUP4).

[0071] The first to fourth island patterns (ISP1~ISP4) may be spaced apart from each other. The first island patterns (ISP1) and the second island patterns (ISP2) may be arranged alternately in the first direction (DR1). The third island patterns (ISP3) and the fourth island patterns (ISP4) may be arranged alternately in the first direction (DR1). The first island patterns (ISP1) and the third island patterns (ISP3) may be arranged alternately in the second direction (DR2). The second island patterns (ISP2) and the fourth island patterns (ISP4) may be arranged alternately in the second direction (DR2).

[0072] The first connection pattern (CNP1) can connect the first island pattern (ISP1) and the second island pattern (ISP2) positioned to the left of the first island pattern (ISP1). The first connection pattern (CNP1) can be connected to the upper side of the first island pattern (ISP1). The first connection pattern (CNP1) can be extended in the first direction (DR1).

[0073] The second connection pattern (CNP2) can connect the first island pattern (ISP1) and the second island pattern (ISP2) positioned to the right of the first island pattern (ISP1). The first connection pattern (CNP1) can be connected to the lower side of the first island pattern (ISP1). The second connection pattern (CNP2) can be extended in the first direction (DR1).

[0074] The third connection pattern (CNP3) can connect the first island pattern (ISP1) and the third island pattern (ISP3) positioned above the first island pattern (ISP1). The third connection pattern (CNP3) can be connected to the right side of the first island pattern (ISP1). The third connection pattern (CNP3) can be extended in the second direction (DR2).

[0075] The fourth connection pattern (CNP4) can connect the first island pattern (ISP1) and the third island pattern (ISP3) positioned below the first island pattern (ISP1). The fourth connection pattern (CNP4) can be connected to the left side of the first island pattern (ISP1). The fourth connection pattern (CNP4) can be extended in the second direction (DR2).

[0076] The fifth connection pattern (CNP5) can connect the second island pattern (IPS2) and the fourth island pattern (IPS4) positioned above the second island pattern (IPS2). The fifth connection pattern (CNP5) can be connected to the left side of the second island pattern (ISP2). The fifth connection pattern (CNP5) can be extended in the second direction (DR2).

[0077] The sixth connection pattern (CNP6) can connect the second island pattern (IPS2) and the fourth island pattern (IPS4) positioned below the second island pattern (IPS2). The sixth connection pattern (CNP6) can be connected to the right side of the second island pattern (ISP2). The sixth connection pattern (CNP6) can be extended in the second direction (DR2).

[0078] The seventh connection pattern (CNP7) can connect the third island pattern (IPS3) and the fourth island pattern (IPS4) positioned to the left of the third island pattern (IPS3). The seventh connection pattern (CNP7) can be connected to the lower side of the third island pattern (ISP3). The seventh connection pattern (CNP7) can be extended in the first direction (DR1).

[0079] The 8th connection pattern (CNP8) can connect the 3rd island pattern (IPS3) and the 4th island pattern (IPS4) positioned to the right of the 3rd island pattern (IPS3). The 8th connection pattern (CNP8) can be connected to the upper side of the 4th island pattern (ISP4). The 8th connection pattern (CNP8) can be extended in the 1st direction (DR1).

[0080] The first incision (CUP1) may be positioned between the first island pattern (ISP1) and the second island pattern (ISP2), between the third connection pattern (CNP3) and the fifth connection pattern (CNP5), between the first island pattern (CNP1) and the second connection pattern (CNP2), and between the second island pattern (CNP2) and the second connection pattern (CNP2). Additionally, the first incision (CUP1) may be positioned between the third island pattern (ISP3) and the fourth island pattern (ISP4), between the third island pattern (CNP3) and the eighth connection pattern (CNP8), and between the fourth island pattern (CNP4) and the eighth connection pattern (CNP8).

[0081] The second incision (CUP2) may be positioned between the first island pattern (ISP1) and the third island pattern (ISP3), between the first island pattern (ISP1) and the fourth connection pattern (CNP4), between the third island pattern (ISP3) and the fourth connection pattern (CNP4), and between the second connection pattern (CNP2) and the eighth connection pattern (CNP8). Additionally, the second incision (CUP2) may be positioned between the second island pattern (ISP2) and the fourth island pattern (ISP4), between the second island pattern (ISP2) and the sixth connection pattern (CNP6), and between the fourth island pattern (ISP4) and the sixth connection pattern (CNP6).

[0082] The third incision (CUP3) may be positioned between the first island pattern (ISP1) and the third island pattern (ISP3), between the first island pattern (ISP1) and the third connection pattern (CNP3), between the third island pattern (ISP3) and the third connection pattern (CNP3), and between the first connection pattern (CNP1) and the seventh connection pattern (CNP7). Additionally, the third incision (CUP3) may be positioned between the second island pattern (ISP2) and the fourth island pattern (ISP4), between the second island pattern (ISP2) and the fifth connection pattern (CNP5), and between the fourth island pattern (ISP4) and the fifth connection pattern (CNP5).

[0083] The fourth incision (CUP4) may be positioned between the first island pattern (ISP1) and the second island pattern (ISP2), between the first island pattern (ISP1) and the first connection pattern (CNP1), between the second island pattern (ISP2) and the first connection pattern (CNP1), and between the fourth connection pattern (CNP4) and the sixth connection pattern (CNP6). Additionally, the fourth incision (CUP4) may be positioned between the third island pattern (ISP3) and the fourth island pattern (ISP4), between the third island pattern (ISP3) and the seventh connection pattern (CNP7), and between the fourth island pattern (ISP4) and the seventh connection pattern (CNP7).

[0084] As shown in FIG. 7, when the display device (10) is contracted, the second connection pattern (CNP2) can be bent in the third direction (DR3). As shown in FIG. 8, when the display device (10) is stretched, the second connection pattern (CNP2) can be unfolded. Therefore, when the display device (10) is stretched in the first direction (DR1), the length of the second connection pattern (CNP2) in the first direction (DR1) can be increased compared to when the display device (10) is contracted.

[0085] Similarly, when the display device (10) is contracted, each of the first and third to eighth connection patterns (CNP1, CNP3 to CNP8) may be bent in the third direction (DR3). When the display device (10) is stretched, each of the first and third to eighth connection patterns (CNP1, CNP3 to CNP8) may be unfolded. Therefore, when the display device (10) is stretched in the second direction (DR2), the length of the third connection pattern (CNP3) in the second direction (DR2), the length of the fourth connection pattern (CNP4) in the second direction (DR2), the length of the fifth connection pattern (CNP5) in the second direction (DR2), and the length of the sixth connection pattern (CNP6) in the second direction (DR2) may be increased compared to when the display device (10) is contracted. Additionally, when the display device (10) is stretched in the first direction (DR1), the length of the first direction (DR1) of the first connection pattern (CNP1), the length of the first direction (DR1) of the seventh connection pattern (CNP7), and the length of the first direction (DR1) of the eighth connection pattern (CNP8) may be increased compared to when the display device (10) is contracted. Therefore, when the display device (10) is stretched, the width of each of the cut sections (CUP1~CUP4) may be larger than the width of each of the cut sections (CUP1~CUP4) when the display device (10) is contracted.

[0086] In each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the display area (DA), a scan initialization wire (GILk / GILk+1), a scan write wire (GWLk / GWLk+1), a light emission wire (EMLk / EMLk+1), a red data wire (RDLj / RDLj+1 / RDLj+2 / RDLj+3), a blue data wire (BDLj / BDLj+1 / BDLj+2 / BDLj+3), a green data wire (GDLj / GDLj+1 / GDLj+2 / GDLj+3), a first power connection wire (VSCL), and a second power wire (VDL) may be arranged.

[0087] The k-th scan initialization wiring (GILk), the k-th scan write wiring (GWLk), the k-th light emission wiring (EMLk), and the first power connection wiring (VSCL) may sequentially pass through the first connection pattern (CNP1), the first island pattern (ISP1), the second connection pattern (CNP2), and the second island pattern (ISP2). Additionally, the k+1-th scan initialization wiring (GIL), the k+1-th scan write wiring (GWLk+1), the k+1-th light emission wiring (EMLk+1), and the first power connection wiring (VSCL) may sequentially pass through the seventh connection pattern (CNP7), the third island pattern (ISP3), the eighth connection pattern (CNP8), and the fourth island pattern (ISP4).

[0088] That is, in the display area (DA), the scan initialization wiring (GILk / GILk+1), the scan write wiring (GWLk / GWLk+1), and the light emission wiring (EMLk / EMLk+1) may be extended in a zigzag or winding manner along the first direction (DR1) and connected to the first scan driver (SDC1) and the second scan driver (SDC2). Additionally, in the display area (DA), the first power connection wiring (VSCL) may be extended in a zigzag or winding manner along the first direction (DR1) and connected to the first power wiring (VSL) in the first dummy area (DMA1) and the second dummy area (DMA2), respectively. Therefore, the first power voltage of the first power wiring (VSL) may be applied to the first power connection wiring (VSCL).

[0089] The j-th red data wire (RDLj), the j-th blue data wire (BDLj), and the j-th green data wire (GDLj), the j-+2 red data wire (RDLj+2), the j-+2 blue data wire (BDLj+2), and the j-+2 green data wire (GDLj+2) can sequentially pass through the third connection pattern (CNP3), the first island pattern (ISP1), the fourth connection pattern (CNP4), and the third island pattern (ISP3). Additionally, the j+1 red data wire (RDLj+1), the j+1 blue data wire (BDLj+1), the j+1 green data wire (GDLj+1), the j+3 red data wire (RDLj+3), the j+3 blue data wire (BDLj+3), and the j+3 green data wire (GDLj+3) can sequentially pass through the 5th connection pattern (CNP5), the 2nd island pattern (ISP2), the 6th connection pattern (CNP6), and the 4th island pattern (ISP4).

[0090] The second power line (VDL) can receive the second power voltage. The second power line (VDL) can sequentially pass through the third connection pattern (CNP3), the first island pattern (ISP1), the fourth connection pattern (CNP4), and the third island pattern (ISP3). Additionally, the second power line (VDL) can sequentially pass through the fifth connection pattern (CNP5), the second island pattern (ISP2), the sixth connection pattern (CNP6), and the fourth island pattern (ISP4). That is, in the display area (DA), the red data wiring (RDLj / RDLj+1 / RDLj+2 / RDLj+3), the blue data wiring (BDLj / BDLj+1 / BDLj+2 / BDLj+3), the green data wiring (GDLj / GDLj+1 / GDLj+2 / GDLj+3), and the second power wiring (VDL) may be extended in a zigzag or meandering manner along the second direction (DR2).

[0091] In each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the display area (DA), a first light-emitting part (ELU1) of the first display pixel (SPX1), a second light-emitting part (ELU2) of the second display pixel (SPX2), and a third light-emitting part (ELU3) of the third display pixel (SPX3) may be disposed. The first light-emitting part (ELU1) may be an area that emits light of a first color, for example, light in the red wavelength band. The second light-emitting part (ELU2) may be an area that emits light of a second color, for example, light in the blue wavelength band. The third light-emitting part (ELU3) may be an area that emits light of a third color, for example, light in the green wavelength band.

[0092] The first light-emitting part (ELU1), the second light-emitting part (ELU2), and the third light-emitting part (ELU3) may be arranged in a first direction (DR1). The first light-emitting part (ELU1) may be positioned on one side of the second light-emitting part (ELU2), and the third light-emitting part (ELU3) may be positioned on the other side of the second light-emitting part (ELU2). The area of ​​the second light-emitting part (ELU2) may be larger than the area of ​​the first light-emitting part (ELU1) and the area of ​​the third light-emitting part (ELU3).

[0093] The first pixel electrode (PXE1) of the first light-emitting unit (ELU1), the second pixel electrode (PXE2) of the second light-emitting unit (ELU2), and the third pixel electrode (PXE3) of the third light-emitting unit (ELU3) may be arranged in a first direction (DR1). The first pixel electrode (PXE1) may be placed on one side of the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may be placed on the other side of the second pixel electrode (PXE2). The area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1) and the area of ​​the third pixel electrode (PXE3). Additionally, the area of ​​the first pixel electrode (PXE1) is larger than the area of ​​the first light-emitting part (ELU1), the area of ​​the second pixel electrode (PXE2) is larger than the area of ​​the second light-emitting part (ELU2), and the area of ​​the third pixel electrode (PXE3) may be larger than the area of ​​the third light-emitting part (ELU3).

[0094] The first pixel electrode (PXE1) is connected to the first pixel driver through the first pixel contact hole (PCNT1), thereby receiving the driving voltage of the first pixel driver. The second pixel electrode (PXE2) is connected to the second pixel driver through the second pixel contact hole (PCNT2), thereby receiving the driving voltage of the second pixel driver. The third pixel electrode (PXE3) is connected to the third pixel driver through the third pixel contact hole (PCNT3), thereby receiving the driving voltage of the third pixel driver.

[0095] In FIGS. 4 and 5, the second pixel electrode (PXE2) of the second light-emitting unit (LEU2) is superimposed on the scan initialization wiring (GILk / GILk+1), scan write wiring (GWLk / GWLk+1), light-emitting wiring (EMLk / EMLk+1), and the first power connection wiring (VSCL), and the first pixel electrode (PXE1) of the first light-emitting unit (LEU1), the second pixel electrode (PXE2) of the second light-emitting unit (LEU2), and the third pixel electrode (PXE3) of the third light-emitting unit (LEU3) are superimposed on the red data wiring (RDLj / RDLj+1 / RDLj+2 / RDLj+3), blue data wiring (BDLj / BDLj+1 / BDLj+2 / BDLj+3), green data wiring (GDLj / GDLj+1 / GDLj+2 / GDLj+3), and the second power wiring (VDL), but the embodiments of this specification do not... At least one of the first pixel electrode (PXE1) of the first light-emitting unit (LEU1), the second pixel electrode (PXE2) of the second light-emitting unit (LEU2), and the third pixel electrode (PXE3) of the third light-emitting unit (LEU3) may overlap with at least one of the scan initialization wiring (GILk / GILk+1), scan write wiring (GWLk / GWLk+1), light-emitting wiring (EMLk / EMLk+1), first power connection wiring (VSCL), red data wiring (RDLj / RDLj+1 / RDLj+2 / RDLj+3), blue data wiring (BDLj / BDLj+1 / BDLj+2 / BDLj+3), green data wiring (GDLj / GDLj+1 / GDLj+2 / GDLj+3), and second power wiring (VDL).

[0096] An island common electrode (ICE) may be disposed in each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the display area (DA). In each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4), the island common electrode (ICE) may be connected to the first common connection electrode (CCU1) through the first common contact hole (CCNT1). To prevent damage due to changes in the length of each of the first to eighth connection patterns (CNP1~CNP8), the island common electrode (ICE) may not be disposed in the first to eighth connection patterns (CNP1~CNP8).

[0097] A first common connection electrode (CCU1) may be disposed in each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the display area (DA). The first common connection electrode (CCU1) may be connected to the first power connection wiring (VSCL) through the second common contact hole (CCNT2). Although not shown in FIGS. 4 through 6, the first power connection wiring (VSCL) may overlap with the first common connection electrode (CCU1) and the second common contact hole (CCNT2) in the third direction (DR3). Therefore, the first power voltage of the first power wiring (VSL) may be supplied to the island common electrode (ICE) through the first power connection wiring (VSCL) and the first common connection electrode (CCU1).

[0098] The first common connection electrode (CCU1) may be placed in the same layer as the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3). Therefore, the first common connection electrode (CCU1) may not overlap with the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3).

[0099] As shown in FIGS. 4 to 6, the first to fourth island patterns (ISP1 to ISP4), partitioned by the cut sections (CUP1 to CUP4), are connected by the first to eighth connecting patterns (CNP1 to CNP8), and the first to eighth connecting patterns (CNP1 to CNP8) may have a bent state when the display device (10) is contracted, whereas they may have an unfolded state when the display device (10) is extended. Therefore, the shape of the first to fourth island patterns (ISP1 to ISP4) does not change, and the lengths of the first to eighth connecting patterns (CNP1 to CNP8) change, so that the width of each of the cut sections (CUP1 to CUP4) can be widened or reduced. Thus, the display area (DA) can be extended and contracted.

[0100] FIGS. 9 and FIGS. 10 are layout diagrams showing a first dummy region in detail according to one embodiment. FIG. 11 is a layout diagram showing a first island pattern of FIG. 9 in detail.

[0101] FIG. 9 shows the island patterns (ISP1~ISP4), connection patterns (CNP1~CNP8), and cut sections (CUP1~CUP4) of the first dummy region (DMA1) when the display device (10) is contracted. FIG. 10 shows the island patterns (ISP1~ISP4), connection patterns (CNP1~CNP8), and cut sections (CUP1~CUP4) of the first dummy region (DMA1) when the display device (10) is extended.

[0102] Referring to FIGS. 9 through 11, the substrate (SUB) may include island patterns (ISP) and connection patterns (CNP) cut by cut sections (CUP1 through CUP4) in the first dummy region (DMA1). The island patterns (ISP) and connection patterns (CNP) of the first dummy region (DMA1) may be substantially identical to the island patterns (ISP) and connection patterns (CNP) of the display region (DA) described in conjunction with FIGS. 4 through 6. Therefore, the description of the island patterns (ISP) and connection patterns (CNP) of the first dummy region (DMA1) is omitted.

[0103] In each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the first dummy area (DMA1), a scan initialization wiring (GILk / GILk+1), a scan write wiring (GWLk / GWLk+1), an emission wiring (EMLk / EMLk+1), a first power connection wiring (VSCL), and a first power wiring (VSL) may be arranged.

[0104] The k-th scan initialization wiring (GILk), the k-th scan write wiring (GWLk), and the k-th light emission wiring (EMLk) can sequentially pass through the first connection pattern (CNP1), the first island pattern (ISP1), the second connection pattern (CNP2), and the second island pattern (ISP2). Additionally, the k+1-th scan initialization wiring (GIL), the k+1-th scan write wiring (GWLk+1), and the k+1-th light emission wiring (EMLk+1) can sequentially pass through the seventh connection pattern (CNP7), the third island pattern (ISP3), the eighth connection pattern (CNP8), and the fourth island pattern (ISP4). That is, in the first dummy area (DMA1), the scan initialization wiring (GILk / GILk+1), the scan write wiring (GWLk / GWLk+1), and the light emission wiring (EMLk / EMLk+1) are extended in a zigzag or meandering manner along the first direction (DR1) and can be connected to the first scan drive unit (SDC1) and the second scan drive unit (SDC2).

[0105] The first power line (VSL) may sequentially pass through the third connection pattern (CNP3), the first island pattern (ISP1), the fourth connection pattern (CNP4), and the second island pattern (ISP2). Additionally, the first power line (VSL) may sequentially pass through the fifth connection pattern (CNP5), the second island pattern (ISP2), the sixth connection pattern (CNP6), and the fourth island pattern (ISP4). The first power line (VSL) may be connected to the second common connection electrode (CCU2) through the fourth common contact hole (CCNT4) at each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4). That is, in the first dummy area (DMA1), the first power line (VSL) may be extended in a zigzag or meandering manner along the second direction (DR2).

[0106] In each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4), the first power connection wiring (VSCL) may be branched from the first power wiring (VSL). In the first dummy area (DMA1), the first power connection wiring (VSCL) may be extended in a zigzag or meandering manner along the first direction (DR1).

[0107] For example, as shown in FIG. 9, a first power connection wire (VSCL) branched from a first power wire (VSL) in a first island pattern (ISP1) can be extended to a second connection pattern (CNP2), a second island pattern (ISP2), and a first connection pattern (CNP1). In this case, the first power connection wire (VSCL) branched from a first power wire (VSL) in a first island pattern (ISP1) and extended to a second island pattern (ISP2) can be connected to the first power wire (VSL) in the second island pattern (ISP2).

[0108] Additionally, as shown in FIG. 9, the first power connection wire (VSCL) branched from the first power wire (VSL) in the third island pattern (ISP3) can be extended to the eighth connection pattern (CNP8), the fourth island pattern (ISP4), and the seventh connection pattern (CNP7). In this case, the first power connection wire (VSCL) branched from the first power wire (VSL) in the third island pattern (ISP3) and extended to the fourth island pattern (ISP4) can be connected to the first power wire (VSL) in the fourth island pattern (ISP4).

[0109] In the first dummy region (DMA1), a first dummy light-emitting layer (DEL1), a second dummy light-emitting layer (DEL2), and a third dummy light-emitting layer (DEL3) may be disposed in each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4).

[0110] The first dummy light-emitting layer (DEL1) may include a material substantially identical to the first display light-emitting layer (EL1) of the first light-emitting part (LEU1). The second dummy light-emitting layer (DEL2) may include a material substantially identical to the second display light-emitting layer of the second light-emitting part (LEU2). The third dummy light-emitting layer (DEL3) may include a material substantially identical to the third display light-emitting layer of the third light-emitting part (LEU3).

[0111] The first dummy light-emitting layer (DEL1), the second dummy light-emitting layer (DEL2), and the third dummy light-emitting layer (DEL3) may be arranged in a first direction (DR1). The first dummy light-emitting layer (DEL1) may be placed on one side of the second dummy light-emitting layer (DEL2), and the third dummy light-emitting layer (DEL3) may be placed on the other side of the second dummy light-emitting layer (DEL2). The area of ​​the second dummy light-emitting layer (DEL2) may be larger than the area of ​​the first dummy light-emitting layer (DEL1) and the area of ​​the third dummy light-emitting layer (DEL3).

[0112] FIGS. 9 and 10 illustrate that the second dummy light-emitting layer (DEL2) overlaps the scan initialization wiring (GILk / GILk+1), scan write wiring (GWLk / GWLk+1), light-emitting wiring (EMLk / EMLk+1), and the first power connection wiring (VSCL), and the first dummy light-emitting layer (DEL1), the second dummy light-emitting layer (DEL2), and the third dummy light-emitting layer (DEL3) overlap the first power wiring (VSL), but the embodiments of the present specification are not limited thereto. At least one of the first dummy light-emitting layer (DEL1), the second dummy light-emitting layer (DEL2), and the third dummy light-emitting layer (DEL3) can be superimposed on at least one of the scan initialization wiring (GILk / GILk+1), scan write wiring (GWLk / GWLk+1), light-emitting wiring (EMLk / EMLk+1), the first power connection wiring (VSCL), red data wiring (RDLj / RDLj+1 / RDLj+2 / RDLj+3), blue data wiring (BDLj / BDLj+1 / BDLj+2 / BDLj+3), and green data wiring (GDLj / GDLj+1 / GDLj+2 / GDLj+3).

[0113] A second common connection electrode (CCU2) may be disposed in each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the first dummy area (DMA1). The dummy common electrode (DCE) of each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the first dummy area (DMA1) may be connected to the second common connection electrode (CCU2) through a third common contact hole (CCNT3). The second common connection electrode (CCU2) of each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the first dummy area (DMA1) may be connected to the first power wiring (VSL) through a fourth common contact hole (CCNT4). Although not illustrated in FIGS. 9 to 11, the first power connection wiring (VSCL) may overlap with the second common connection electrode (CCU2) and the fourth common contact hole (CCNT4) in the third direction (DR3). Therefore, the first power voltage of the first power wiring (VSL) can be supplied to the dummy common electrode (DCE) through the first power connection wiring (VSCL) and the second common connection electrode (CCU2).

[0114] The second common connection electrode (CCU2) may be placed in the same layer as the first pixel electrode (PXE1), the second pixel electrode (PXE2), the third pixel electrode (PXE3), and the first common connection electrode (CCU1). The second common connection electrode (CCU2) may not overlap with the first dummy light-emitting layer (DEL1), the second dummy light-emitting layer (DEL2), and the third dummy light-emitting layer (DEL3).

[0115] As shown in FIGS. 9 to 11, the width of each of the cut sections (CUP1 to CUP4) can be adjusted by changing the lengths of the first to eighth connection patterns (CNP1 to CNP8) without changing the shape of the first to fourth island patterns (ISP1 to ISP4) in the first dummy area (DMA1) as well as in the display area (DA). Therefore, stretching and contraction of the first dummy area (DMA1) may be possible.

[0116] Additionally, as shown in FIGS. 9 to 11, the first power wiring (VSL) overlaps with the first dummy light-emitting layer (DEL1), the second dummy light-emitting layer (DEL2), and the third dummy light-emitting layer (DEL3) in the first dummy area (DMA1), and may be extended in a zigzag or serpentine manner along the second direction (DR2). Since the first power wiring (VSL) is not placed at the edge of the display panel (100), the width of the non-display area (NDA) may be reduced compared to when the first power wiring (VSL) is placed at the edge of the display panel (100).

[0117] Meanwhile, since the second dummy region (DMA2) is substantially identical to the first dummy region (DMA1) described in conjunction with FIGS. 9 to 11, the description of the second dummy region (DMA2) is omitted.

[0118] FIGS. 12 and FIGS. 13 are layout diagrams showing in detail a first scan driving unit according to one embodiment.

[0119] FIG. 12 shows the island patterns (ISP1~ISP4), connection patterns (CNP1~CNP8), and cut sections (CUP1~CUP4) of the first scan drive unit (SDC1) when the display device (10) is contracted. FIG. 13 shows the island patterns (ISP1~ISP4), connection patterns (CNP1~CNP8), and cut sections (CUP1~CUP4) of the first scan drive unit (SDC1) when the display device (10) is extended.

[0120] Referring to FIGS. 12 and 13, the substrate (SUB) may include island patterns (ISP) and connection patterns (CNP) cut by the cut sections (CUP1 to CUP4) in the first scan drive unit (SDC1). The island patterns (ISP) and connection patterns (CNP) of the first scan drive unit (SDC1) may be substantially identical to the island patterns (ISP) and connection patterns (CNP) of the display area (DA) described in conjunction with FIGS. 4 and 5. Therefore, the description of the island patterns (ISP) and connection patterns (CNP) of the first scan drive unit (SDC1) is omitted.

[0121] A scan stage circuit (STC) may be disposed in each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the first scan driving unit (SDC1). The scan stage circuit (STC) may include at least one of a plurality of thin-film transistors in each of the plurality of stages (STA1, STA2, STA3, STA4, …, STAm-1, STAm, STAm+1) of the scan signal output unit (SOU).

[0122] In each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4) in the first scan drive unit (SDC1), a first drive voltage wire (VGHL), a second drive voltage wire (VGLL), a first clock wire (CKL1), a second clock wire (CKL2), stage connection wires (STCL1, STCL2), etc. may be arranged. The first scan control wires (GCL1 in FIG. 2) and the second scan control wires (GCL2 in FIG. 2) may include the first drive voltage wire (VGHL), the second drive voltage wire (VGLL), the first clock wire (CKL1), and the second clock wire (CKL2).

[0123] The first driving voltage wiring (VGHL), the second driving voltage wiring (VGLL), the first clock wiring (CKL1), and the second clock wiring (CKL2) can be connected to the stage circuit (STC) at each of the first to fourth island patterns (ISP1, ISP2, ISP3, ISP4). The first driving voltage wiring (VGHL), the second driving voltage wiring (VGLL), the first clock wiring (CKL1), and the second clock wiring (CKL2) can sequentially pass through the third connection pattern (CNP1), the first island pattern (ISP1), the fourth connection pattern (CNP2), and the third island pattern (ISP3). The first driving voltage wiring (VGHL), the second driving voltage wiring (VGLL), the first clock wiring (CKL1), and the second clock wiring (CKL2) may sequentially pass through the fifth connection pattern (CNP5), the second island pattern (ISP2), the sixth connection pattern (CNP6), and the fourth island pattern (ISP4). That is, the first driving voltage wiring (VGHL), the second driving voltage wiring (VGLL), the first clock wiring (CKL1), and the second clock wiring (CKL2) may be extended in a zigzag or meandering manner along the second direction (DR2).

[0124] Stage connection wires (STCL1, STCL2) can connect adjacent stage circuit sections (STC) in the first direction (DR1). The stage connection wires (STCL1, STCL2) can sequentially pass through the first connection pattern (CNP1), the first island pattern (ISP1), the second connection pattern (CNP2), and the second island pattern (ISP2). Additionally, the stage connection wires (STCL1, STCL2) can sequentially pass through the seventh connection pattern (CNP7), the third island pattern (ISP3), the eighth connection pattern (CNP8), and the fourth island pattern (ISP4). That is, the stage connection wires (STCL1, STCL2) can be extended in a zigzag or meandering manner along the first direction (DR1).

[0125] In addition, at least one of the stage connection wires (STCL1, STCL2), as well as the scan initialization wire (GILk / GILk+1), scan write wire (GWLk / GWLk+1), and light emission wire (EMLk / EMLk+1), may sequentially pass through the first connection pattern (CNP1), the first island pattern (ISP1), the second connection pattern (CNP2), and the second island pattern (ISP2), and sequentially pass through the seventh connection pattern (CNP7), the third island pattern (ISP3), the eighth connection pattern (CNP8), and the fourth island pattern (ISP4). That is, at least one of the scan initialization wire (GILk / GILk+1), scan write wire (GWLk / GWLk+1), and light emission wire (EMLk / EMLk+1) may be extended in a zigzag or meandering manner along the first direction (DR1).

[0126] As shown in FIGS. 12 and 13, the width of each of the cut sections (CUP1 to CUP4) can be adjusted by changing the lengths of the first to eighth connection patterns (CNP1 to CNP8) without changing the shape of the first to fourth island patterns (ISP1 to ISP4) in the display area (DA) and the first dummy area (DMA1), as well as in the first scan drive unit (SDC1). Therefore, the first scan drive unit (SDC1) can be stretched and contracted.

[0127] Meanwhile, since the second scan drive unit (SDC2) is substantially the same as the first scan drive unit (SDC1) described in conjunction with FIG. 12 and FIG. 13, the description of the second scan drive unit (SDC2) is omitted.

[0128] FIG. 14 is a cross-sectional view showing an example of a display panel cut along A-A' of FIG. 6. FIG. 15 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 11. FIG. 16 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 12.

[0129] Referring to FIGS. 14 to 16, the substrate (SUB) may be made of an insulating material such as a polymer resin. For example, the substrate (SUB) may be made of polyimide. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc.

[0130] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film intended to protect the transistors of the thin-film transistor layer (TFTL) and the light-emitting layer (EL1) of the light-emitting device layer (EML) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability. For example, the barrier film (BR) may be silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). X It may include inorganic insulating materials such as zinc oxide (ZnO X ) may be zinc oxide (ZnO) and / or zinc peroxide (ZnO2). The barrier film (BR) may include a plurality of inorganic films.

[0131] A first thin-film transistor (TFT1) and a second thin-film transistor (TFT2) may be disposed on the barrier film (BR). The first thin-film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) shown in FIG. 2. The second thin-film transistor (TFT2) may be any one of the plurality of thin-film transistors of the stage circuit (STC) shown in FIG. 3. The first thin-film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1). The second thin-film transistor (TFT2) may include a second active layer (ACT2) and a second gate electrode (G2).

[0132] A first active layer (ACT1) of a first thin-film transistor (TFT1) and a second active layer (ACT2) of a second thin-film transistor (ACT2) may be disposed on the barrier film (BR). The first active layer (ACT1) and the second active layer (ACT2) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor.

[0133] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region that overlaps with the first gate electrode (G1) in the third direction (DR3), which is the thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap with the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions that have conductivity by doping ions or impurities into a silicon semiconductor or an oxide semiconductor.

[0134] The second active layer (ACT2) may include a second channel region (CHA2), a second source region (S2), and a second drain region (D2). The second channel region (CHA2) may be a region that overlaps with the second gate electrode (G2) in the third direction (DR3), which is the thickness direction of the substrate (SUB). The second source region (S2) may be disposed on one side of the second channel region (CHA2), and the second drain region (D2) may be disposed on the other side of the second channel region (CHA2). The second source region (S2) and the second drain region (D2) may be regions that do not overlap with the second gate electrode (G2) in the third direction (DR3). The second source region (S2) and the second drain region (D2) may be regions that have conductivity by doping ions or impurities into a silicon semiconductor or an oxide semiconductor.

[0135] A gate insulating film (130) may be disposed on the first active layer (ACT1) of the first thin-film transistor (TFT1) and the second active layer (ACT2) of the second thin-film transistor (ACT2). The gate insulating film (130) may be silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). X It may include inorganic insulating materials such as ).

[0136] A first gate electrode (G1) of a first thin-film transistor (TFT1), a second gate electrode (G2) of a second thin-film transistor (TFT2), and a first capacitor electrode (CAE1) may be disposed on the gate insulating film (130). The first gate electrode (G1) may overlap with the first active layer (ACT1) in the third direction (DR3). The second gate electrode (G2) may overlap with the second active layer (ACT2) in the third direction (DR3). Although the first gate electrode (G1) and the first capacitor electrode (CAE1) are shown as being disposed apart from each other in FIG. 11, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other. The first gate electrode (G1), the second gate electrode (G2), and the first capacitor electrode (CAE1) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0137] A first interlayer insulating film (141) may be disposed on the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1). The first interlayer insulating film (141) may be silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). X It may include inorganic insulating materials such as ). The first interlayer insulating film (141) may include a plurality of inorganic films.

[0138] A second capacitor electrode (CAE2) may be disposed on the first interlayer insulating film (141). The second capacitor electrode (CAE2) may overlap with the first capacitor electrode (CAE1) in the third direction (DR3). When the first capacitor electrode (CAE1) is connected to the first gate electrode (G1), the second capacitor electrode (CAE2) may overlap with the first gate electrode (G1) in the third direction (DR3). Since the first interlayer insulating film (141) has a predetermined dielectric constant, a capacitor may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the first interlayer insulating film (141) disposed between them. The second capacitor electrode (CAE2) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. A second interlayer insulating film (142) may be disposed on the second capacitor electrode (CAE2). The second interlayer insulating film (142) may be silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). X It may include inorganic insulating materials such as ). The second interlayer insulating film (142) may include a plurality of inorganic films.

[0139] A first anode connection electrode (ANDE1), data lines (RDLj, BDLj, GDLj), a first power line (VSL), a first power connection line (VSCL), a first driving voltage line (VGHL), a second driving voltage line (VGLL), and a first clock line (CKL1) and a second clock line (CKL2) may be disposed on the second interlayer insulating film (142). The first anode connection electrode (ANDE1) may be connected to a first drain region (D1) of the first thin-film transistor (TFT1) through a first connection contact hole (ANCT1) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The first anode connection electrode (ANDE1), data lines (RDLj, BDLj, GDLj), first power line (VSL), first driving voltage line (VGHL), second driving voltage line (VGLL), first clock line (CKL1), and second clock line (CKL2) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0140] A first flattening film (160) for flattening the step difference caused by the first thin-film transistor (TFT1) and the second thin-film transistor (TFT2) may be disposed on the first anode connection electrode (ANDE1), data lines (RDLj, BDLj, GDLj), first power line (VSL), first power connection line (VSCL), first driving voltage line (VGHL), second driving voltage line (VGLL), first clock line (CKL1), and second clock line (CKL2). The first flattening film (160) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0141] First light-emitting elements (LEL1), a first common connection electrode (CCU1), a second common connection electrode (CCU2), and a bank (190) may be disposed on the first planarization film (160). The first light-emitting element (LEL1) includes a first pixel electrode (PXE1), a first light-emitting layer (EL1), and an island common electrode (ICE).

[0142] A first pixel electrode (PXE1), a first common connection electrode (CCU1), and a second common connection electrode (CCU2) may be disposed on a first planarization film (160). The first pixel electrode (PXE1) may be connected to a first anode connection electrode (ANDE1) through a first pixel contact hole (PCT1) penetrating the first planarization film (160). The first common connection electrode (CCU1) may be connected to a first power connection wiring (VSCL) through a second common contact hole (CCNT2) penetrating the first planarization film (160). The second common connection electrode (CCU2) may be connected to a first power wiring (VSL) through a fourth common contact hole (CCNT4) penetrating the first planarization film (160).

[0143] Each of the first pixel electrode (PXE1), the first common connection electrode (CCU1), and the second common connection electrode (CCU2) can be formed from a highly reflective metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (Indium Tin Oxide) (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0144] A bank (190) may be formed to partition pixel electrodes (PXE1) on a first planarization film (160) to define a first light-emitting part (ELU1), a second light-emitting part (ELU2), and a third light-emitting part (ELU3). A bank (190) may be positioned to cover the edges of each pixel electrode (PXE1). A bank (190) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0145] The first light-emitting part (ELU1) represents a region in which a first pixel electrode (PXE1), a first display light-emitting layer (EL1), and an island common electrode (ICE) are sequentially stacked, and light is emitted by holes from the first pixel electrode (PXE1) and electrons from the island common electrode (ICE) recombining in the first display light-emitting layer (EL1).

[0146] A first display light-emitting layer (EL1) may be disposed on the first pixel electrode (PXE1). The first display light-emitting layer (EL1) may include an organic material and emit a predetermined color. For example, the first display light-emitting layer (EL1) includes a hole transporting layer, an organic material layer, and an electron transporting layer.

[0147] The second light-emitting part (ELU2) may be an area in which the second pixel electrode, the second display light-emitting layer, and the island common electrode are sequentially stacked, and the third light-emitting part (ELU3) may be an area in which the third pixel electrode, the third display light-emitting layer, and the island common electrode are sequentially stacked. The second light-emitting part (ELU2) and the third light-emitting part (ELU3) may be formed substantially identically to the first light-emitting part (ELU1).

[0148] A second dummy light-emitting layer (DEL2) may be disposed on the first flattening film (180) which is exposed and not covered by the bank (190). A first dummy light-emitting layer (DEL1) and a third dummy light-emitting layer (DEL3) may also be disposed on the first flattening film (180) which is exposed and not covered by the bank (190). The first dummy light-emitting layer (DEL1) may contain a material substantially identical to the first display light-emitting layer (EL1) of the first light-emitting part (LEU1). The second dummy light-emitting layer (DEL2) may contain a material substantially identical to the second display light-emitting layer of the second light-emitting part (LEU2). The third dummy light-emitting layer (DEL3) may contain a material substantially identical to the third display light-emitting layer of the third light-emitting part (LEU3). An island common electrode (ICE) may be disposed on the first display light-emitting layer (EL1), the second display light-emitting layer, and the third display light-emitting layer. The island common electrode (ICE) may be positioned to cover the first display light-emitting layer (EL1), the second display light-emitting layer, and the third display light-emitting layer. The island common electrode (ICE) may be a common layer formed commonly on the first display light-emitting layer (EL1), the second display light-emitting layer, and the third display light-emitting layer. A capping layer may be formed on the island common electrode (ICE). The island common electrode (ICE) may be connected to the first common connection electrode (CCU1) through a first common contact hole (CCNT1) penetrating the bank (190). As a result, a first power supply voltage may be applied to the island common electrode (ICE).

[0149] A dummy common electrode (DCE) may be placed on a first dummy light-emitting layer (DEL1), a second dummy light-emitting layer (DEL2), and a third dummy light-emitting layer (DEL3). The dummy common electrode (DCE) may be placed to cover the first dummy light-emitting layer (DEL1), the second dummy light-emitting layer (DEL2), and the third dummy light-emitting layer (DEL3). The dummy common electrode (DCE) may be a common layer formed commonly on the first dummy light-emitting layer (DEL1), the second dummy light-emitting layer (DEL2), and the third dummy light-emitting layer (DEL3). A capping layer may be formed on the dummy common electrode (DCE). The dummy common electrode (DCE) may be connected to a second common connection electrode (CCU2) through a second common contact hole (CCNT2) penetrating the bank (190). As a result, a first power supply voltage may be applied to the dummy common electrode (DCE).

[0150] The common island electrode (ICE) and the dummy common electrode (DCE) can be formed from transparent conductive materials (TCO) such as ITO or IZO that can transmit light, or semi-transmissive conductive materials such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common island electrode (ICE) is formed from a semi-transmissive conductive material, the light emission efficiency can be increased by the microcavity.

[0151] An encapsulation layer (TFEL) may be disposed on the common island electrode (ICE) and the dummy common electrode (DCE). The encapsulation layer (TFEL) includes at least one inorganic film to prevent oxygen or moisture from penetrating the light-emitting element layer (EML). Additionally, the encapsulation layer (TFEL) includes at least one organic film to protect the light-emitting element layer (EML) from foreign substances such as dust. For example, the encapsulation layer (TFEL) includes a first encapsulation inorganic film (TFE1), an encapsulation organic film (TFE2), and a second encapsulation inorganic film (TFE3).

[0152] A first encapsulating inorganic film (TFE1) may be disposed on a common electrode (173), an encapsulating organic film (TFE2) may be disposed on the first encapsulating inorganic film (TFE1), and a second encapsulating inorganic film (TFE3) may be disposed on the encapsulating organic film (TFE2). The first encapsulating inorganic film (TFE1) and the second encapsulating inorganic film (TFE3) may be silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2). X It may include inorganic insulating materials such as ). The encapsulating organic film (TFE2) may be an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0153] Meanwhile, although not shown in FIGS. 14 to 16, when the display device (10) is contracted, the first to eighth connection patterns (CNP1 to CNP8) can each be bent in the third direction (DR3) as in FIG. 7. Therefore, the scan initialization wiring (GILk / GILk+1), scan write wiring (GWLk / GWLk+1), light emission wiring (EMLk / EMLk+1), first power connection wiring (VSCL), red data wiring (RDLj / RDLj+1 / RDLj+2 / RDLj+3), blue data wiring (BDLj / BDLj+1 / BDLj+2 / BDLj+3), green data wiring (GDLj / GDLj+1 / GDLj+2 / GDLj+3), and second power wiring (VDL) disposed on each of the first to eighth connection patterns (CNP1~CNP8) may be disposed on the same layer, for example, the second interlayer insulating film (142), to prevent damage when the first to eighth connection patterns (CNP1~CNP8) are bent. That is, the upper surface of the second interlayer insulating film (142) on which the scan initialization wiring (GILk / GILk+1), scan write wiring (GWLk / GWLk+1), light emission wiring (EMLk / EMLk+1), first power connection wiring (VSCL), red data wiring (RDLj / RDLj+1 / RDLj+2 / RDLj+3), blue data wiring (BDLj / BDLj+1 / BDLj+2 / BDLj+3), green data wiring (GDLj / GDLj+1 / GDLj+2 / GDLj+3), and second power wiring (VDL) are arranged can be designed as a neutral plane.

[0154] FIG. 17 is a layout diagram showing in detail an example of area A of FIG. 11. FIG. 18 is a cross-sectional view showing an example of a display panel cut along D-D' of FIG. 17.

[0155] Referring to FIGS. 17 and FIG. 18, the first power connection wiring (VSCL) may include a first sub-power connection wiring (VSCL1) and a second sub-power connection wiring (VSCL2). The first sub-power connection wiring (VSCL1) may be placed in the first island pattern (ISP1) and the first connection pattern (CNP1), and the second sub-power connection wiring (VSCL2) may be placed in the first island pattern (ISP1).

[0156] The first sub-power connection wiring (VSCL1) can be placed on the second interlayer insulating film (142). That is, the first sub-power connection wiring (VSCL1) can be placed on the same layer as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), first power wiring (VSL), first power connection wiring (VSCL), first driving voltage wiring (VGHL), second driving voltage wiring (VGLL), first clock wiring (CKL1), and second clock wiring (CKL2). Additionally, the first sub-power connection wiring (VSCL1) may include the same material as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), first power wiring (VSL), first power connection wiring (VSCL), first driving voltage wiring (VGHL), second driving voltage wiring (VGLL), first clock wiring (CKL1), and second clock wiring (CKL2).

[0157] The second sub-power connection wiring (VSCL2) may be placed on the gate insulating film (130). That is, the second sub-power connection wiring (VSCL2) may be placed on the same layer as the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1). Additionally, the second sub-power connection wiring (VSCL2) may include the same material as the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1).

[0158] The first sub-power connection wiring (VSCL1) can be connected to the second sub-power connection wiring (VSCL2) through a first contact hole (CNT1) that penetrates the first interlayer insulating film (141) and the second interlayer insulating film (142) in the first island pattern (ISP1). Since the second sub-power connection wiring (VSCL2) is placed on the gate insulating film (130) and the first power wiring (VSL) is placed on the second interlayer insulating film (142), the second sub-power connection wiring (VSCL2) and the first power wiring (VSL) can intersect. Because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the width of the second sub-power connection wiring (VSCL2) can be greater than the width of the first sub-power connection wiring (VSCL1).

[0159] The k-th light-emitting wiring (EMLk) may include the k-1 light-emitting wiring (EMLk_1) and the k-2 light-emitting wiring (EMLk_2). The k-1 light-emitting wiring (EMLk_1) may be placed in the first island pattern (ISP1) and the first connection pattern (CNP1), and the k-2 light-emitting wiring (EMLk_2) may be placed in the first island pattern (ISP1).

[0160] The k-1 light-emitting wiring (EMLk_1) can be placed on the second interlayer insulating film (142). That is, the k-1 light-emitting wiring (EMLk_1) can be placed on the same layer as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), first power wiring (VSL), first power connection wiring (VSCL), first driving voltage wiring (VGHL), second driving voltage wiring (VGLL), first clock wiring (CKL1), and second clock wiring (CKL2). Additionally, the k-1 light-emitting wiring (EMLk_1) may include the same material as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), first power wiring (VSL), first power connection wiring (VSCL), first driving voltage wiring (VGHL), second driving voltage wiring (VGLL), first clock wiring (CKL1), and second clock wiring (CKL2).

[0161] The k-2 light-emitting wiring (EMLk_2) may be placed on the gate insulating film (130). That is, the k-2 light-emitting wiring (EMLk_2) may be placed on the same layer as the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1). Additionally, the k-2 light-emitting wiring (EMLk_2) may include the same material as the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1).

[0162] The k-1 light-emitting wire (EMLk_1) can be connected to the k-2 light-emitting wire (EMLk_2) through a second contact hole (CNT2) that penetrates the first interlayer insulating film (141) and the second interlayer insulating film (142) in the first island pattern (ISP1). Since the k-2 light-emitting wire (EMLk_2) is placed on the gate insulating film (130) and the first power wire (VSL) is placed on the second interlayer insulating film (142), the k-2 light-emitting wire (EMLk_2) and the first power wire (VSL) can intersect. Because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the width of the k-2 light-emitting wire (EMLk_2) can be greater than the width of the k-1 light-emitting wire (EMLk_1).

[0163] The k-th scan write wiring (GWLk) may include the k-1 scan write wiring (GWLk_1) and the k-2 scan write wiring (GWLk_2). The k-1 scan write wiring (GWLk_1) is placed in the first island pattern (ISP1) and the first connection pattern (CNP1), and the k-2 scan write wiring (GWLk_2) may be placed in the first island pattern (ISP1).

[0164] The k-1 scan write wiring (GWLk_1) can be placed on the second interlayer insulating film (142). That is, the k-1 scan write wiring (GWLk_1) can be placed on the same layer as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), first power wiring (VSL), first power connection wiring (VSCL), first driving voltage wiring (VGHL), second driving voltage wiring (VGLL), first clock wiring (CKL1), and second clock wiring (CKL2). Additionally, the k-1 scan writing wiring (GWLk_1) may include the same material as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), first power wiring (VSL), first power connection wiring (VSCL), first driving voltage wiring (VGHL), second driving voltage wiring (VGLL), first clock wiring (CKL1), and second clock wiring (CKL2).

[0165] The k-2 scan write wiring (GWLk_2) can be placed on the gate insulating film (130). That is, the k-2 scan write wiring (GWLk_2) can be placed on the same layer as the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1). Additionally, the k-2 scan write wiring (GWLk_2) may include the same material as the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1).

[0166] The k-1 scan write wiring (GWLk_1) can be connected to the k-2 scan write wiring (GWLk_2) through a second contact hole (CNT2) that penetrates the first interlayer insulating film (141) and the second interlayer insulating film (142) in the first island pattern (ISP1). Since the k-2 scan write wiring (GWLk_2) is placed on the gate insulating film (130) and the first power wiring (VSL) is placed on the second interlayer insulating film (142), the k-2 scan write wiring (GWLk_2) and the first power wiring (VSL) can intersect. Because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the width of the k-2 scan write wiring (GWLk_2) can be greater than the width of the k-1 scan write wiring (GWLk_1).

[0167] The k-th scan initialization wiring (GILk) may include the k-1st scan initialization wiring (GILk_1) and the k-2nd scan initialization wiring (GILk_2). The k-1st scan initialization wiring (GILk_1) is placed on the first island pattern (ISP1) and the first connection pattern (CNP1), and the k-2nd scan initialization wiring (GILk_2) may be placed on the first island pattern (ISP1).

[0168] The k-1 scan initialization wiring (GILk_1) may be placed on the second interlayer insulating film (142). That is, the k-1 scan initialization wiring (GILk_1) may be placed on the same layer as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), first power wiring (VSL), first power connection wiring (VSCL), first driving voltage wiring (VGHL), second driving voltage wiring (VGLL), first clock wiring (CKL1), and second clock wiring (CKL2). Additionally, the k-1 scan initialization wiring (GILk_1) may include the same material as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), first power wiring (VSL), first power connection wiring (VSCL), first driving voltage wiring (VGHL), second driving voltage wiring (VGLL), first clock wiring (CKL1), and second clock wiring (CKL2).

[0169] The k-2 scan initialization wiring (GILk_2) may be placed on the gate insulating film (130). That is, the k-2 scan initialization wiring (GILk_2) may be placed on the same layer as the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1). Additionally, the k-2 scan initialization wiring (GILk_2) may include the same material as the first gate electrode (G1) of the first thin-film transistor (TFT1), the second gate electrode (G2) of the second thin-film transistor (TFT2), and the first capacitor electrode (CAE1).

[0170] The k-1 scan initialization wiring (GILk_1) can be connected to the k-2 scan initialization wiring (GILk_2) through a second contact hole (CNT2) that penetrates the first interlayer insulating film (141) and the second interlayer insulating film (142) in the first island pattern (ISP1). Since the k-2 scan initialization wiring (GILk_2) is placed on the gate insulating film (130) and the first power wiring (VSL) is placed on the second interlayer insulating film (142), the k-2 scan initialization wiring (GILk_2) and the first power wiring (VSL) can intersect. Because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the width of the k-2 scan initialization wiring (GILk_2) can be greater than the width of the k-1 scan initialization wiring (GILk_1).

[0171] Meanwhile, each of the stage connection wires (STCL1, STCL2) can be formed substantially identically to the first power connection wire (VSCL), the k-th light emission wire (EMLk), the k-th scan write wire (GWLk), and the k-th scan initialization wire (GILk) described in conjunction with FIGS. 17 and 18. Therefore, the description of the stage connection wires (STCL1, STCL2) is omitted.

[0172] FIG. 19 is a layout diagram showing in detail another example of area A of FIG. 11. FIG. 20 is a cross-sectional view showing an example of a display panel cut along E-E' of FIG. 19.

[0173] The embodiments of FIGS. 19 and 20 differ from the embodiments of FIGS. 17 and 18 in that the first power connection wiring (VSCL) further includes a third sub-power connection wiring (VSCL3), the k-th light-emitting wiring (EMLk) further includes a k-3 light-emitting wiring (EMLk_3), the k-th scan write wiring (GWLk) further includes a k-3 scan write wiring (GWLk_3), and the k-th scan initialization wiring (GILk) further includes a k-3 scan initialization wiring (GILk_3).

[0174] Referring to FIGS. 19 and 20, the third sub-power connection wiring (VSCL3), the k-3 light-emitting wiring (EMLk_3), the k-3 scan write wiring (GWLk_3), and the k-3 scan initialization wiring (GILk_3) may be placed on the first island pattern (ISP1). The third sub-power connection wiring (VSCL3), the k-3 light-emitting wiring (EMLk_3), the k-3 scan write wiring (GWLk_3), and the k-3 scan initialization wiring (GILk_3) may be placed on the first interlayer insulating film (141). That is, the third sub-power connection wiring (VSCL3), the k-3 light-emitting wiring (EMLk_3), the k-3 scan write wiring (GWLk_3), and the k-3 scan initialization wiring (GILk_3) may be placed on the same layer as the second capacitor electrode (CAE2). Additionally, the third sub-power connection wiring (VSCL3), the k-3 light-emitting wiring (EMLk_3), the k-3 scan writing wiring (GWLk_3), and the k-3 scan initialization wiring (GILk_3) may contain the same material as the second capacitor electrode (CAE2).

[0175] The first sub-power connection wiring (VSCL1) can be connected to the third sub-power connection wiring (VSCL3) through a fifth contact hole (CNT5) that penetrates the second interlayer insulating film (142) in the first island pattern (ISP1). Since the third sub-power connection wiring (VSCL3) is placed on the first interlayer insulating film (141) and the first power wiring (VSL) is placed on the second interlayer insulating film (142), the third sub-power connection wiring (VSCL3) and the first power wiring (VSL) can intersect.

[0176] Because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the width of the third sub-power connection wire (VSCL3) may be greater than the width of the first sub-power connection wire (VSCL1). Additionally, because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the first sub-power connection wire (VSCL1) can be divided from the first island pattern (ISP1) into two wires, namely the second sub-power connection wire (VSCL2) and the third sub-power connection wire (VSCL3), and intersect with the first power wire (VSL). As a result, the resistance of the first power connection wire (VSCL) can be lowered.

[0177] The k-1 light-emitting wire (EMLk_1) can be connected to the k-3 light-emitting wire (EMLk_3) through a sixth contact hole (CNT6) that penetrates the second interlayer insulating film (142) in the first island pattern (ISP1). Since the k-3 light-emitting wire (EMLk_3) is placed on the first interlayer insulating film (141) and the first power wire (VSL) is placed on the second interlayer insulating film (142), the k-3 light-emitting wire (EMLk_3) and the first power wire (VSL) can intersect.

[0178] Because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the width of the k-3 light-emitting wire (EMLk_3) can be greater than the width of the k-1 light-emitting wire (EMLk_1). Additionally, because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the k-1 light-emitting wire (EMLk_1) can be divided from the first island pattern (ISP1) into two wires, namely the k-2 light-emitting wire (EMLk_2) and the k-3 light-emitting wire (EMLk_3), and intersect with the first power wire (VSL). As a result, the resistance of the k-th light-emitting wire (EMLk) can be lowered.

[0179] The k-1 scan write wiring (GWLk_1) can be connected to the k-3 scan write wiring (GWLk_3) through a seventh contact hole (CNT7) that penetrates the second interlayer insulating film (142) in the first island pattern (ISP1). Since the k-3 scan write wiring (GWLk_3) is placed on the first interlayer insulating film (141) and the first power wiring (VSL) is placed on the second interlayer insulating film (142), the k-3 scan write wiring (GWLk_3) and the first power wiring (VSL) can intersect.

[0180] Because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the width of the k-3 scan write wire (GWLk_3) can be greater than the width of the k-1 scan write wire (GWLk_1). Additionally, because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the k-1 scan write wire (GWLk_1) can be divided from the first island pattern (ISP1) into two wires, namely the k-2 scan write wire (GWLk_2) and the k-3 scan write wire (GWLk_3), and intersect with the first power wire (VSL). As a result, the resistance of the k scan write wire (GWLk) can be lowered.

[0181] The k-1 scan initialization wiring (GILk_1) can be connected to the k-3 scan initialization wiring (GILk_3) through an eighth contact hole (CNT8) that penetrates the second interlayer insulating film (142) in the first island pattern (ISP1). Since the k-3 scan initialization wiring (GILk_3) is placed on the first interlayer insulating film (141) and the first power wiring (VSL) is placed on the second interlayer insulating film (142), the k-3 scan initialization wiring (GILk_3) and the first power wiring (VSL) can intersect.

[0182] Because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the width of the k-3 scan initialization wire (GILk_3) can be greater than the width of the k-1 scan initialization wire (GILk_1). Additionally, because the space of the first island pattern (ISP1) is wider than the space of the first connection pattern (CNP1), the k-1 scan initialization wire (GILk_1) can be divided from the first island pattern (ISP1) into two wires, namely the k-2 scan initialization wire (GILk_2) and the k-3 scan initialization wire (GILk_3), and intersect with the first power wire (VSL). As a result, the resistance of the k scan initialization wire (GILk) can be lowered.

[0183] Meanwhile, each of the stage connection wires (STCL1, STCL2) can be formed substantially identically to the first power connection wire (VSCL), the k-th light emission wire (EMLk), the k-th scan write wire (GWLk), and the k-th scan initialization wire (GILk) described in conjunction with FIG. 19 and FIG. 20. Therefore, the description of the stage connection wires (STCL1, STCL2) is omitted.

[0184] FIG. 21 is a layout diagram showing in detail the first island pattern of a first dummy area according to another embodiment. FIG. 22 is a cross-sectional view showing an example of a display panel cut along F-F' of FIG. 21.

[0185] The embodiments of FIGS. 21 and 22 differ from the embodiments of FIGS. 11 and 15 in that the first power wiring (VSL) in the first dummy region (DMA1) includes the first sub-power wiring (VSL1) and the second sub-power wiring (VSL2).

[0186] Referring to FIGS. 21 and 22, the first sub-power wiring (VSL1) may be placed on the second interlayer insulating film (142). That is, the first sub-power wiring (VSL1) may be placed on the same layer as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), the first power wiring (VSL), and the first power connection wiring (VSCL). Additionally, the first sub-power wiring (VSL1) may include the same material as the first anode connection electrode (ANDE1), data wirings (RDLj, BDLj, GDLj), the first power wiring (VSL), and the first power connection wiring (VSCL).

[0187] The second sub-power wiring (VSL2) may be placed on the first flattening film (160). The second sub-power wiring (VSL2) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0188] A second flattening film (180) may be disposed on the second sub-power wiring (VSL2). The second sub-power wiring (VSL2) may be connected to the first sub-power wiring (VSL1) through a first power contact hole (VCNT1) that penetrates the first flattening film (160) in the first island pattern (ISP1). The second flattening film (180) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0189] In this case, the first light-emitting element (LEL1), the first common connection electrode (CCU1), the second common connection electrode (CCU2), and the bank (190) illustrated in FIG. 14 may be placed on the second planarization film (180). Additionally, the second anode connection electrode may be placed on the first planarization film (160) and connected to the first anode connection electrode (ANDE1) through a second connection contact hole penetrating the first planarization film (160). Furthermore, the first pixel electrode (PXE1) of the first light-emitting element (LEL1) may be connected to the second anode connection electrode (ANDE2) through a third connection contact hole penetrating the second planarization film (180).

[0190] FIGS. 21 and 22 illustrate that the second sub-power wiring (VSL2) is placed on the first island pattern (ISP1), the first connection pattern (CNP1), and the second connection pattern (CNP2), but embodiments of the present specification are not limited thereto. For example, in the first connection pattern (CNP1) and the second connection pattern (CNP2), the second sub-power wiring (VSL2) is placed on a surface other than the neutral surface, so that if the first connection pattern (CNP1) and the second connection pattern (CNP2) are bent, a crack may occur in the second sub-power wiring (VSL2). Therefore, the second sub-power wiring (VSL2) may be placed on the first island pattern (ISP1), where there is no change in shape or the change in shape is minimized despite the shrinkage and stretching of the display device (10), and may not be placed on the first connection pattern (CNP1) and the second connection pattern (CNP2).

[0191] As shown in FIGS. 21 and 22, by including a first sub-power line (VSL1) and a second sub-power line (VSL2) that overlap each other in the third direction (DR3) in the first power line (VSL), the area relative to the length of the first power line (VSL) can be increased, and thus the resistance of the first power line (VSL) can be reduced.

[0192] Meanwhile, since the first power wiring (VSL) of the second dummy area (DMA2) may be substantially the same as the first power wiring (VSL) shown in FIGS. 21 and FIGS. 22, the description of the first power wiring (VSL) of the second dummy area (DMA2) is omitted.

[0193] FIG. 23 is a layout diagram showing in detail the first island pattern of a first dummy area according to another embodiment. FIG. 24 is a cross-sectional view showing an example of a display panel cut along G-G' of FIG. 23.

[0194] The embodiments of FIGS. 23 and 24 differ from the embodiments of FIGS. 21 and 22 in that the first power line (VSL) in the first dummy region (DMA1) further includes a third sub-power line (VSL3).

[0195] Referring to FIGS. 23 and 24, the third sub-power wiring (VSL3) may be placed on the second flattening film (180). The third sub-power wiring (VSL3) may be formed as a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0196] A third flattening film (181) may be disposed on the third sub-power wiring (VSL3). The third sub-power wiring (VSL3) may be connected to the second sub-power wiring (VSL2) through a second power contact hole (VCNT2) that penetrates the second flattening film (180) in the first island pattern (ISP1). The third flattening film (181) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0197] In this case, the first light-emitting element (LEL1), the first common connection electrode (CCU1), the second common connection electrode (CCU2), and the bank (190) illustrated in FIG. 14 may be placed on the third planarization film (181). Additionally, the third anode connection electrode may be placed on the second planarization film (180) and connected to the second anode connection electrode through a third connection contact hole penetrating the second planarization film (180). Additionally, the first pixel electrode (PXE1) of the first light-emitting element (LEL1) may be connected to the third anode connection electrode through a fourth connection contact hole penetrating the third planarization film (181).

[0198] FIGS. 23 and 24 illustrate that the second sub-power wiring (VSL2) and the third sub-power wiring (VSL3) are placed in the first island pattern (ISP1), the first connection pattern (CNP1), and the second connection pattern (CNP2), but the embodiments of this specification are not limited thereto. Since the second sub-power wiring (VSL2) and the third sub-power wiring (VSL3) are placed on a surface other than the neutral surface in the first connection pattern (CNP1) and the second connection pattern (CNP2), cracks may occur in the second sub-power wiring (VSL2) and the third sub-power wiring (VSL3) when the first connection pattern (CNP1) and the second connection pattern (CNP2) are bent. Therefore, the second sub-power wiring (VSL2) and the third sub-power wiring (VSL3) are placed on the first island pattern (ISP1) where the change in length is minimized despite the shrinkage and stretching of the display device (10), and may not be placed on the first connection pattern (CNP1) and the second connection pattern (CNP2).

[0199] As shown in FIGS. 23 and 24, by including a first sub-power line (VSL1), a second sub-power line (VSL2), and a third sub-power line (VSL3) that overlap each other in the third direction (DR3), the area relative to the length of the first power line (VSL) can be increased, and thus the resistance of the first power line (VSL) can be reduced.

[0200] Meanwhile, since the first power wiring (VSL) of the second dummy area (DMA2) may be substantially the same as the first power wiring (VSL) shown in FIGS. 23 and 24, the description of the first power wiring (VSL) of the second dummy area (DMA2) is omitted.

[0201] FIG. 25 is a layout diagram showing a display area in detail according to another embodiment. FIG. 26 is a layout diagram showing a first dummy area in detail according to another embodiment. FIG. 27 is a layout diagram showing a first scan drive unit in detail according to another embodiment.

[0202] FIG. 25 shows island patterns (ISP1~ISP4), cut patterns (CNP1~CNP8), and cut sections (CUP1~CUP4) of the display area (DA) when the display device (10) is stretched. FIG. 26 shows island patterns (ISP1~ISP4), cut patterns (CNP1~CNP8), and cut sections (CUP1~CUP4) of the first dummy area (DMA1) when the display device (10) is stretched. FIG. 27 shows island patterns (ISP1~ISP4), cut patterns (CNP1~CNP8), and cut sections (CUP1~CUP4) of the first scan drive unit (SDC1) when the display device (10) is stretched.

[0203] The embodiments of FIGS. 25 to 27 differ from the embodiments of FIGS. 5, 10, and 13 in that when the display device (10) contracts and stretches, the first to eighth incision patterns (CNP1 to CNP8) do not bend or unfold, and the incision portions (CUP1 to CUP4) widen. In FIGS. 25 to 27, descriptions that overlap with the embodiments of FIGS. 5, 10, and 13 are omitted.

[0204] Referring to FIGS. 25 to 27, the width of the first direction (DR1) of the first cut portion (CUP1) during the stretching of the display device (10) may be wider than during the contraction of the display device (10). During the stretching of the display device (10), the width of the first cut portion (CUP1) may increase toward the center of the first cut portion (CUP1). That is, during the stretching of the display device (10), the width of the center of the first cut portion (CUP1) may be wider than the width of the edge of the first cut portion (CUP1).

[0205] When the display device (10) is extended, the width of the second direction (DR2) of the second incision (CUP2) may be wider than when the display device (10) is contracted. When the display device (10) is extended, the width of the second incision (CUP2) may increase towards the center of the second incision (CUP2). That is, when the display device (10) is extended, the width of the center of the second incision (CUP2) may be wider than the width of the edge of the second incision (CUP2).

[0206] When the display device (10) is extended, the width of the first direction (DR1) of the third incision (CUP3) may be wider than when the display device (10) is contracted. When the display device (10) is extended, the width of the third incision (CUP1) may increase towards the center of the third incision (CUP3). That is, when the display device (10) is extended, the width of the center of the third incision (CUP3) may be wider than the width of the edge of the third incision (CUP3).

[0207] When the display device (10) is extended, the width of the second direction (DR2) of the fourth cut portion (CUP4) may be wider than when the display device (10) is contracted. When the display device (10) is extended, the width of the fourth cut portion (CUP4) may increase towards the center of the fourth cut portion (CUP4). That is, when the display device (10) is extended, the width of the center of the fourth cut portion (CUP4) may be wider than the width of the edge of the fourth cut portion (CUP4).

[0208] Since at least a portion of the thin-film transistor layer (TFTL) is removed by a laser in the cut sections (CUP1~CUP4), the stretchability of the cut sections (CUP) may be higher than that of the cut patterns (CP'). The shapes of the island patterns (ISP) and connection patterns (CNP) remain unchanged, and the first cut sections (CUP1), second cut sections (CUP2), and third cut sections (CUP3) may be widened.

[0209] As shown in FIGS. 25 to 27, the first to fourth island patterns (ISP1 to ISP4), which are partitioned by the cut sections (CUP1 to CUP4), are connected by the first to eighth connecting patterns (CNP1 to CNP8). Therefore, when the display device (10) is stretched, the width of the cut sections (CUP1 to CUP4) can be wider than when the display device (10) is contracted. Thus, the width of each of the cut sections (CUP1 to CUP4) can be widened or reduced without changing the shape of the first to fourth island patterns (ISP1 to ISP4) and the first to eighth connecting patterns (CNP1 to CNP8). Accordingly, the display area (DA) can be stretched and contracted.

[0210] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0211] 10: Display device 100: Display panel 200: Display driving circuit 300: Circuit board

Claims

Claim 1 A display device comprising: a display area; and a dummy area disposed on one side of the display area, wherein each of the display area and the dummy area comprises: a first island pattern and a second island pattern disposed apart from each other; and a connecting pattern connecting the first island pattern and the second island pattern, wherein the dummy area comprises, in each of the first island pattern and the second island pattern, a dummy common electrode and a common connecting electrode electrically connected to the dummy common electrode, and wherein the display area comprises, in each of the first island pattern and the second island pattern, a light-emitting element having a pixel electrode, a display light-emitting layer disposed on the pixel electrode, and an island common electrode disposed on the display light-emitting layer, wherein the dummy area is a display device in which the pixel electrode is not disposed. Claim 2 delete Claim 3 A display device according to claim 1, wherein the dummy region comprises a dummy light-emitting layer having the same material as the display light-emitting layer in each of the first island pattern and the second island pattern. Claim 4 In claim 3, the display device wherein the island common electrode is connected to the common connecting electrode through a common contact hole penetrating at least one insulating film interposed between the island common electrode and the common connecting electrode. Claim 5 In claim 4, the common contact hole is a display device that does not overlap with the dummy light-emitting layer. Claim 6 In claim 3, the dummy region comprises a first power wiring connected to the common connection electrode, to which a first power voltage is applied in each of the first island pattern and the second island pattern. Claim 7 delete Claim 8 In claim 6, the first power wiring is a display device that overlaps with the dummy light-emitting layer. Claim 9 In claim 6, the first power wiring comprises a first sub-power wiring and a second sub-power wiring that overlap each other, forming a display device. Claim 10 delete Claim 11 A display device according to claim 9, wherein the first sub-power wiring is placed in the first island pattern, the second island pattern, and the connection pattern in the dummy area, and the second sub-power wiring is placed in the first island pattern and the second island pattern. Claim 12 In claim 6, the display area includes a pixel driving unit for driving the light-emitting element, and the pixel driving unit comprises: a driving transistor; a first transistor that initializes the gate electrode of the driving transistor to the initial voltage of the initial voltage wiring according to a scan initialization signal of the scan initialization wiring; a second transistor that applies a data voltage to the gate electrode of the driving transistor according to a scan write signal of the scan write wiring; and a third transistor that connects the first electrode of the driving transistor to the pixel electrode according to a light-emitting signal of the light-emitting wiring. Claim 13 In claim 12, in each of the first island pattern and the second island pattern of the dummy area, the scan initialization wiring, the scan write wiring, and the light-emitting wiring are a display device that intersects the first power wiring. Claim 14 In claim 13, the scan initialization wiring, the scan writing wiring, and the light-emitting wiring are a display device that overlaps with the dummy light-emitting layer. Claim 15 A display device comprising: a display area; and a dummy area disposed on one side of the display area, wherein each of the display area and the dummy area comprises: a first island pattern and a second island pattern disposed apart from each other; and a connecting pattern connecting the first island pattern and the second island pattern, wherein the display area comprises a light-emitting element comprising, in each of the first island pattern and the second island pattern, a pixel electrode, a display light-emitting layer disposed on the pixel electrode, and an island common electrode disposed on the display light-emitting layer, and wherein the dummy area comprises a dummy light-emitting layer comprising the same material as the display light-emitting layer in each of the first island pattern and the second island pattern, wherein the pixel electrode is not disposed therein and the connecting pattern is bent or unfolded. Claim 16 In claim 15, the dummy area is a display device comprising a first power wiring to which a first power voltage is applied in each of the first island pattern and the second island pattern. Claim 17 In claim 16, the dummy area further comprises a first power connection wiring connected to the first power wiring, wherein the first power connection wiring comprises a first sub-power connection wiring disposed in the connection pattern; and a second sub-power connection wiring disposed in the first island pattern, and the first sub-power connection wiring is connected to the second sub-power connection wiring through a first contact hole penetrating at least one insulating film interposed between the first sub-power connection wiring and the second sub-power connection wiring. Claim 18 In claim 17, the second sub-power connection wiring is a display device that overlaps with the dummy light-emitting layer. Claim 19 In claim 17, the first power connection wiring further comprises a third sub-power connection wiring disposed in the first island pattern, and the first sub-power connection wiring is connected to the third sub-power connection wiring through a second contact hole penetrating at least one insulating film interposed between the first sub-power connection wiring and the third sub-power connection wiring. Claim 20 A display device comprising: a display area including display pixels; a scan driving unit that outputs scan signals to scan lines connected to the display pixels; and a dummy area disposed between the display area and the scan driving unit, wherein each of the display area, the dummy area, and the scan driving unit includes a first island pattern and a second island pattern disposed apart from each other; and a connecting pattern connecting the first island pattern and the second island pattern, wherein the scan driving unit includes a plurality of scan transistors disposed in each of the first island pattern and the second island pattern, wherein the display area includes a light-emitting element comprising a pixel electrode, a display light-emitting layer disposed on the pixel electrode, and an island common electrode disposed on the display light-emitting layer, wherein the dummy area is a display device in which the pixel electrode is not disposed.

Images