Circuit board and package substrate having the same

Abstract

A circuit board according to an embodiment includes an insulating layer; and a circuit pattern layer disposed on the insulating layer, wherein the insulating layer includes a surface layer containing fluorine (F), and the circuit pattern layer is disposed on the surface layer of the insulating layer. Additionally, a circuit board according to another embodiment includes an insulating layer having a through hole; and a through electrode disposed within the through hole of the insulating layer, wherein the insulating layer includes a surface layer having fluorine (F) corresponding to the inner wall of the through hole, and the through electrode includes a first metal layer disposed on the surface layer; and a second metal layer disposed on the first metal layer and filling the through hole.

Description

Technology Field

[0001] An embodiment relates to a circuit board and a package board including the same. Background Technology

[0002] A Printed Circuit Board (PCB) is formed by printing circuit line patterns using a conductive material, such as copper, onto an electrically insulating substrate; it refers to a board immediately prior to mounting electronic components. In other words, it signifies a circuit board in which the mounting positions of various electronic components are determined and circuit patterns connecting the components are printed and fixed onto the flat surface to densely mount many different types of electronic components.

[0003] The components mounted on the above printed circuit board can transmit signals generated from the components through circuit patterns connected to each component.

[0004] Meanwhile, with the recent increase in functionality of portable electronic devices, signal frequencies are becoming higher to enable high-speed processing of large amounts of information, and circuit patterns for printed circuit boards suitable for high-frequency applications are required.

[0005] The circuit patterns of such printed circuit boards must minimize signal transmission loss, enabling signal transmission without degrading the quality of high-frequency signals.

[0006] The transmission loss of circuit patterns on a printed circuit board consists mainly of conductor loss caused by metal thin films such as copper and dielectric loss caused by insulators such as insulating layers.

[0007] Conductor loss attributable to metal thin films is related to the surface roughness of the circuit pattern. In other words, as the surface roughness of the circuit pattern increases, transmission loss may increase due to the skin effect.

[0008] Therefore, reducing the surface roughness of the circuit pattern has the effect of preventing transmission loss, but there is a problem in that the adhesion between the circuit pattern and the insulating layer is reduced.

[0009] In addition, to reduce the dielectric, a material with a low dielectric constant can be used as an insulating layer for the circuit board.

[0010] However, for circuit boards used in high-frequency applications, the insulating layer requires chemical and mechanical properties for use in the circuit board in addition to a low dielectric constant.

[0011] Specifically, the insulating layer used in circuit boards for high-frequency applications must possess isotropy in electrical properties for ease of circuit pattern design and processing, low reactivity with metal wiring materials, low ion transferability, sufficient mechanical strength to withstand processes such as chemical mechanical polishing (CMP), low moisture absorption to prevent delamination or increase in dielectric constant, heat resistance to withstand processing temperatures, and a low coefficient of thermal expansion to eliminate cracking due to temperature changes.

[0012] In addition, the insulating layer used in circuit boards for high-frequency applications must satisfy various conditions, such as adhesion, crack resistance, low stress, and low high-temperature gas generation, to minimize various stresses and delamination that may occur at the interface with other materials (e.g., metal thin films).

[0013] Accordingly, the insulating layer used in circuit boards for high-frequency applications must primarily possess low dielectric constant and low coefficient of thermal expansion characteristics, thereby enabling the overall thickness of the circuit board to be slimmed down.

[0014] However, when manufacturing circuit boards using insulating layers of low dielectric material that are thinner than the limit point, reliability problems such as warping, cracking, and delamination occur, and as the number of insulating layers of low dielectric material increases, the severity of reliability problems such as warping, cracking, and delamination increases.

[0015] Therefore, there is a need for a solution that enables the implementation of fine circuit patterns while slimming down circuit boards by using an insulating layer of low dielectric material, and also solves reliability issues such as warping, cracking, and delamination. The problem to be solved

[0016] In an embodiment, a circuit board capable of being slimmed down and a package board including the same are provided.

[0017] In addition, the embodiment provides a circuit board capable of minimizing signal transmission loss and a package board including the same.

[0018] In addition, the embodiment provides a circuit board with improved adhesion between an insulating layer and a circuit pattern layer, and a package board including the same.

[0019] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the proposed embodiments belong from the description below. means of solving the problem

[0020] A circuit board according to an embodiment includes an insulating layer; and a circuit pattern layer disposed on the insulating layer, wherein the insulating layer includes a surface layer containing fluorine (F), and the circuit pattern layer is disposed on the surface layer of the insulating layer.

[0021] In addition, the surface layer is a region with a depth range of 10 nm to 100 nm from the surface of the insulating layer.

[0022] In addition, the surface layer includes a first portion adjacent to the upper surface of the insulating layer and a second portion adjacent to the lower surface of the insulating layer.

[0023] In addition, the circuit pattern layer comprises a first metal layer disposed on the surface layer of the insulating layer and a second metal layer disposed on the first metal layer.

[0024] In addition, the first metal layer is an electroless plating layer, and the second metal layer is an electrolytic plating layer formed by the first metal layer as a seed layer.

[0025] In addition, the first metal layer has a thickness in the range of 1 μm to 2.5 μm.

[0026] In addition, the centerline average roughness value (Ra) of at least one of the surface layers of the first metal layer and the insulating layer satisfies a range between 200 nm and 600 nm.

[0027] In addition, the maximum cross-sectional height value (Rt) of at least one of the first metal layer and the surface layer of the insulating layer satisfies a range between 2㎛ and 6㎛.

[0028] Additionally, the circuit board comprises a through electrode disposed within a through hole penetrating the insulating layer, the surface layer of the insulating layer comprises a third portion formed on the inner wall of the through hole, and the through electrode comprises a third metal layer disposed on the third portion of the surface layer; and a fourth metal layer disposed on the third metal layer and filling the through hole.

[0029] Meanwhile, a circuit board according to another embodiment includes an insulating layer having a through hole; and a through electrode disposed within the through hole of the insulating layer, wherein the insulating layer includes a surface layer corresponding to the inner wall of the through hole and including fluorine (F), and the through electrode includes a first metal layer disposed on the surface layer; and a second metal layer disposed on the first metal layer and filling the through hole.

[0030] In addition, the surface layer is an area with a depth range of 10 nm to 100 nm in the horizontal direction from the inner wall of the through hole of the insulating layer.

[0031] In addition, the atomic ratio of the fluorine (F) in the surface layer satisfies the range of 10% to 50%.

[0032] In addition, the first metal layer has a thickness in the range of 1 μm to 2.5 μm, the centerline average roughness value (Ra) of at least one of the first metal layer and the surface layer satisfies the range of 200 nm to 600 nm, and the maximum cross-sectional height value (Rt) of at least one of the first metal layer and the surface layer satisfies the range of 2 μm to 6 μm.

[0033] Meanwhile, a package substrate according to an embodiment includes an insulating layer having a through hole; a circuit pattern layer disposed on the insulating layer; a through electrode disposed within the through hole of the insulating layer; and a chip mounted on the circuit pattern layer, wherein the insulating layer includes a first portion adjacent to the circuit pattern layer and a second portion adjacent to the through electrode, and includes a surface layer containing fluorine (F), wherein the circuit pattern layer includes a first metal layer disposed on the first portion of the surface layer and a second metal layer disposed on the first metal layer, and the through electrode includes a third metal layer disposed on the second portion of the surface layer; and a fourth metal layer disposed on the third metal layer to fill the through hole, and wherein the surface layer is an area with a depth range of 10 nm to 100 nm from the surface of the insulating layer, and the atomic ratio of the fluorine (F) in the surface layer satisfies a range of 10% to 50%. Effects of the invention

[0034] The circuit board in the embodiment includes an insulating layer comprising a surface layer and a circuit pattern layer disposed on the insulating layer. The surface layer may refer to a depth range of 10 nm to 100 nm from the surface of the insulating layer. The surface layer of the insulating layer contains fluorine. That is, the surface layer of the insulating layer contains carbon (C)-fluorine (F). In this case, the fluorine (F) can lower the polarity of the surface of the insulating layer.

[0035] That is, in the embodiment, plasma treatment is performed on the insulating layer using CF4. At this time, the surface layer of the insulating layer before the plasma treatment includes CH bond portions. Then, the CH bond portions of the surface layer of the insulating layer after the plasma treatment are replaced with CF bonds. Furthermore, the CF has lower electronic polarizability compared to CH, and accordingly, the polarity of the surface of the insulating layer can be reduced. At this time, as the operating frequency of the application to which the circuit board is applied increases, the signal flow moves to the surface of the conductor due to the skin effect, and thus the polarity of the dielectric surface in contact with the conductor is important. At this time, in the embodiment, by including fluorine (F), which has low electrical polarity, in the surface layer within a certain depth range from the surface of the insulating layer, signal transmission loss due to the skin effect can be minimized, and communication performance can be improved accordingly.

[0036] In addition, as the dielectric constant or surface polarity of the insulating layer increases, signal loss increases, and the signal transmission speed decreases accordingly. At this time, the coefficient of thermal expansion and the dielectric constant of the insulating layer have a mutual trade-off relationship; accordingly, if the polarity of the insulating layer is lowered, the coefficient of thermal expansion of the insulating layer increases, and the warpage characteristics are degraded accordingly. In this embodiment, instead of modifying the polarity of the entire area of ​​the insulating layer, polarity modification is performed only on the surface layer up to a certain depth from the surface of the insulating layer through plasma treatment. Through this, in the embodiment, by modifying only the polarity of the surface layer of the insulating layer while maintaining the coefficient of thermal expansion of the insulating layer, it is possible to minimize signal loss and increase the signal transmission speed while maintaining the warpage characteristics of the circuit board.

[0037] In addition, in the embodiment, fluorine (F) with high electronegativity is present in the surface layer of the insulating layer. At this time, the fluorine (F) can lower the overall polarity of the polymer by delocalizing the distribution of electrons within the molecules of the insulating layer. Through this, in the embodiment, the packing density of the polymer is lowered and the free volume is increased, thereby lowering the dielectric constant of the insulating layer, and thus high reliability can be maintained even in products using high frequency.

[0038] Meanwhile, the circuit pattern layer in the embodiment includes a first metal layer and a second metal layer. The first metal layer may satisfy a thickness in the range of 1 μm to 2.5 μm. Preferably, the first metal layer may satisfy a thickness in the range of 1.2 μm to 2.3 μm. Preferably, the first metal layer may satisfy a thickness in the range of 1.4 μm to 2.2 μm. Through this, in the embodiment, the adhesion between the first metal layer and the insulating layer can be further improved, and furthermore, the adhesion between the insulating layer and the circuit pattern layer can be improved. Through this, in the embodiment, the electrical reliability of the circuit pattern layer can be improved, and product satisfaction can be improved accordingly. In addition, in the embodiment, by improving the adhesion between the insulating layer and the circuit pattern layer, the line width of the trace constituting the circuit pattern layer can be miniaturized, thereby increasing the circuit integration density or reducing the overall volume of the circuit board.

[0039] In addition, the centerline average roughness value (Ra) of the first metal layer in the embodiment may have a range between 200 nm and 600 nm. The centerline average roughness value (Ra) of the first metal layer may be between 300 nm and 500 nm. In addition, the maximum cross-sectional height value (Rt) of the first metal layer may be between 2 μm and 6 μm. For example, the maximum cross-sectional height value (Rt) of the first metal layer may be between 3 μm and 5 μm. In the embodiment, by controlling the centerline average roughness value (Ra) or the maximum cross-sectional height value (Rt) in correspondence with the thickness of the first metal layer, the anchoring effect can be further enhanced with increasing thickness of the first metal layer. Furthermore, in the embodiment, the plating thickness uniformity of the first metal layer can be improved by controlling the centerline average roughness value (Ra) and the maximum cross-sectional height value (Rt), and furthermore, when etching the first metal layer, a portion of the first metal layer is prevented from remaining on the surface of the insulating layer, thereby improving the electrical reliability of the circuit board and improving the yield of the circuit board. Brief explanation of the drawing

[0040] Figure 1 is a drawing for explaining a circuit board according to a first comparative example. Figure 2 is a drawing for explaining a circuit board according to a second comparative example. FIG. 3 is a drawing showing a circuit board according to an embodiment. Figure 4 is a drawing for explaining the characteristics of the surface layer of an insulating layer according to an embodiment. Figure 5 is a diagram illustrating the signal transmission flow according to frequency. Figure 6 is a drawing for comparing the adhesion force between the insulating layer and the circuit pattern layer according to a comparative example and an embodiment. FIGS. 7 to 15 are drawings showing a method for manufacturing a circuit board according to an embodiment in process order. FIG. 16 is a drawing showing a multilayer circuit board according to the first embodiment. FIG. 17 is a drawing showing a multilayer circuit board according to a second embodiment. FIG. 18 is a drawing showing a multilayer circuit board according to a third embodiment. FIG. 19 is a drawing showing a package substrate according to an embodiment. Specific details for implementing the invention

[0041] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0042] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a sense that is generally understood by those skilled in the art to which the present invention belongs, unless explicitly and specifically defined otherwise. Terms that are commonly used, such as terms defined in advance, may be interpreted in consideration of their meaning in the context of the relevant technology.

[0043] Furthermore, the terms used in the embodiments of the present invention are for the purpose of describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as “and at least one of B and C (or more than one),” it may include one or more of all combinations that can be formed from A, B, and C.

[0044] In addition, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention. These terms are used merely to distinguish the components from other components and are not intended to limit the essence, order, or sequence of the components.

[0045] And, where it is stated that a component is 'connected', 'combined', or 'joined' to another component, this may include not only cases where the component is directly connected, combined, or joined to the other component, but also cases where it is 'connected', 'combined', or 'joined' due to another component located between the component and the other component.

[0046] Additionally, where described as being formed or placed on the "top or bottom" of each component, the top or bottom includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components.

[0047] In addition, when expressed as “up” or “down,” it can include the meaning of a downward direction as well as an upward direction relative to a single component.

[0049] Before describing the present embodiment, we will first describe the circuit board according to the comparative example.

[0050] FIG. 1 is a drawing for explaining a circuit board according to a first comparative example, and FIG. 2 is a drawing for explaining a circuit board according to a second comparative example.

[0052] Referring to FIG. 1, the circuit board of the first comparative example is manufactured using prepreg as an insulating layer.

[0053] For example, the circuit board of the first comparative example includes an insulating layer (10) containing prepreg. In this case, the prepreg has a structure in which glass fibers are dispersed inside.

[0054] At this time, the base member for manufacturing the circuit board of the first comparative example has a structure in which a primer layer (20) is disposed on an insulating layer (10) and a copper foil layer (30) is laminated on the primer layer (20).

[0055] Meanwhile, the manufacturing method for the circuit board includes the MSAP (Modified Semi Additive Process) and SAP (Semi Additive Process) methods. The MSAP method involves performing a process of forming a circuit pattern layer while the copper foil layer (30) is laminated, and the SAP method involves performing a process of forming a circuit pattern layer after removing the copper foil layer (30).

[0056] At this time, the above MSAP method includes a portion of the circuit pattern layer, which is the copper foil layer (30). Accordingly, the MSAP method has limitations in reducing the width or spacing of the wiring in the circuit pattern layer, and thus limits the increase in circuit integration density.

[0057] Meanwhile, in the case where the circuit pattern layer is manufactured using the SAP method in the first comparative example, a primer layer (20) for securing adhesion must be included on the insulating layer (10), and there is a problem that the manufacturing cost increases or the overall thickness of the circuit board increases accordingly.

[0058] Furthermore, in the first comparative example, the prepreg used as the insulating layer (10) contains glass fibers inside, and it is difficult to reduce the thickness of the glass fibers. This is because if the thickness of the prepreg is reduced, the glass fibers contained in the prepreg may come into contact with the circuit pattern layer placed on the surface of the prepreg, and a crack list may occur as a result. Accordingly, in the first comparative example, if the thickness of the prepreg is reduced, dielectric breakdown and damage to the circuit pattern layer may occur. Accordingly, the circuit board in the comparative example had a limit in reducing the overall thickness due to the thickness of the glass fibers constituting the prepreg.

[0060] Meanwhile, in the second comparative example, RCC (Resin coated copper) is used to solve the problem of the first comparative example.

[0061] As shown in FIG. 2(a), the circuit board of the second comparative example is manufactured using an insulating layer (40) composed of RCC. The insulating layer (40) has a structure in which fillers (41) are dispersed. Additionally, the insulating layer (40) has a structure in which a copper foil layer (50) is attached thereto.

[0062] At this time, as shown in Fig. 2(b), in the second comparative example, in order to manufacture a circuit board using the RCC, a process of removing the copper foil layer (50) placed on the insulating layer (40) is performed first.

[0063] In addition, in the second comparative example, a chemical copper plating layer (60) is formed on an insulating layer (40) from which the copper foil layer (50) has been removed, and an electroplating layer is formed on the chemical copper plating layer (60) as a seed layer to form a circuit pattern layer.

[0064] At this time, the chemical copper plating layer (60) in the second comparative example is placed on the insulating layer (40) from which the copper foil layer (50) has been removed. That is, the lower surface of the chemical copper plating layer (60) is in direct contact with the upper surface of the insulating layer (40). The adhesion force between the chemical copper plating layer (60) and the insulating layer (40) is affected by the line width of the trace of the circuit pattern formed using the chemical copper plating layer (60). At this time, if the line width of the trace is 10 μm or less, there is a problem in that the trace separates from the insulating layer (40) as the adhesion force between the chemical copper plating layer (60) and the insulating layer (40) is not secured.

[0065] In addition, the chemical copper plating layer (60) in the second comparative example has a thickness of less than 0.9 μm. However, as in the second comparative example, if the thickness of the chemical copper plating layer (60) is less than 0.9 μm, the adhesion between the insulating layer (40) and the chemical copper plating layer (60) is not secured, and accordingly, when a certain force is applied in the trace shear direction, there is a problem that the circuit pattern layer placed on the insulating layer (40) is separated or peeled off from the insulating layer (40).

[0067] Accordingly, in the embodiment, the polarity of the surface of the insulating layer is lowered to increase the signal transmission speed while minimizing signal transmission loss. Additionally, in the embodiment, the thickness of the chemical copper plating layer is increased to improve the adhesion between the chemical copper plating layer and the insulating layer. Furthermore, in the embodiment, the surface roughness of the insulating layer is lowered to minimize signal transmission loss. Moreover, in the embodiment, one value is determined based on at least one of the surface roughness value of the insulating layer and the thickness of the chemical copper plating layer to improve the overall reliability of the circuit board.

[0069] -Electronic Devices-

[0070] Before describing the embodiment, an electronic device including the package substrate of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the package substrate of the embodiment. Various chips may be mounted on the package substrate. Broadly, the package substrate may be mounted with memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), an antenna chip, a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; and logic chips such as an analog-to-digital converter and an ASIC (application-specific IC).

[0071] In addition, the embodiment provides a circuit board and a package board capable of mounting at least two chips of different types on a single substrate according to the pitch reduction. Furthermore, the embodiment provides a circuit board and a package board capable of placing more traces between mounting pads having a smaller pitch than the comparative example.

[0072] At this time, the electronic device may be a smartphone, personal digital assistant, digital video camera, digital still camera, network system, computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, etc. However, it is not limited to these, and it is obvious that it may be any other electronic device that processes data in addition to these.

[0074] - Example of Implementation -

[0075] FIG. 3 is a diagram showing a circuit board according to an embodiment, FIG. 4 is a diagram explaining the characteristics of the surface layer of an insulating layer according to an embodiment, and FIG. 5 is a diagram explaining the signal transmission flow according to frequency.

[0076] Referring to FIGS. 3 to 5, the circuit board provides a mounting space that allows at least one chip to be mounted. The chip mounted on the circuit board may be one, or alternatively, two, or alternatively, three or more. For example, one processor chip may be mounted on the circuit board, or alternatively, at least two processor chips with different functions may be mounted, or alternatively, one memory chip may be mounted together with one processor chip, or alternatively, at least two processor chips with different functions and at least one memory chip may be mounted.

[0078] The circuit board includes an insulating layer (110).

[0079] The above insulating layer (110) may be RCC (Resin coated copper).

[0080] Accordingly, the insulating layer (110) may include a resin and a filler (111) dispersed within the resin. The insulating layer (110) may be a resin for semiconductor packages. In the embodiment, the dielectric constant of the insulating layer (110) can be lowered to 3.2 Dk or less by changing the content of the composition within the insulating layer (110) constituting the resin for semiconductor packages. Preferably, in the embodiment, the dielectric constant of the insulating layer (110) can be lowered to 3.0 Dk or less by changing the content of the composition within the insulating layer (110) constituting the resin for semiconductor packages. More preferably, in the embodiment, the dielectric constant of the insulating layer (110) can satisfy the range of 2.9 Dk to 3.2 Dk by changing the content of the composition within the insulating layer (110) constituting the resin for semiconductor packages.

[0081] The insulating layer (110) described above is a composite of resin and filler (111). The insulating layer (110) may have a specific third dielectric constant resulting from a combination of the first dielectric constant of the resin and the second dielectric constant of the filler (111). Furthermore, the third dielectric constant may satisfy a range between 2.9 Dk and 3.2 Dk. Accordingly, the insulating layer (110) in the embodiment can be applied to a circuit board suitable for high-frequency applications. Accordingly, the insulating layer (110) in the embodiment can minimize signal loss and solve the problem of the filler (111) being exposed to the surface of the resin, thereby improving reliability.

[0082] The above resin may have a low dielectric constant. At this time, the general types of resin and the dielectric constant according to the types of resin are shown in Table 1.

[0084] material Phenolic Epoxy Maleimide or modified epoxy Cyanate PTFE Permittivity (Dk) 4.5~6.5 3.5~5.0 2.3~2.5 2.6~3.0 2.2

[0085] As described above, the resin can contain various materials. In this case, resins containing phenolic, general epoxy, and cyanate exhibit a dielectric constant of 2.6 Dk or higher. Additionally, the resin containing PTFE has a low dielectric constant of approximately 2.2 Dk, but requires high process temperature conditions. For example, the required process temperature for general resin is 250°C, whereas PTFE requires a process temperature of 300°C or higher. Furthermore, for the manufacture of a multilayer circuit board, a bonding sheet is essential during the lamination process for PTFE, which increases the overall thickness of the circuit board and poses a problem for making the circuit board slim. Accordingly, in the embodiment, a modified epoxy or maleimide series is used to lower the dielectric constant of the resin constituting the insulating layer (110). However, the embodiments are not limited thereto, and the dielectric constant may include general epoxy or cyanate. Additionally, the filler (111) may have a dielectric constant of a certain level. For example, the filler (111) may be formed of a ceramic filler. At this time, the dielectric constant according to the type of ceramic filler is as shown in Table 2 below.

[0087] material SiO2 Al2O3 ZrO3 HfO2 TiO2 Permittivity (Dk) 3.7~4.2 9.0 3.7~4.2 3.7~4.2 3.7~4.2

[0088] As described above, when the filler (111) is formed of Al2O3, the dielectric constant of the filler (111) itself is at the level of 9.0 Dk, and accordingly, there is a limit to lowering the dielectric constant of the insulating layer (110), which is a composite thereof, to 3.2 Dk or less using only the dielectric constant of the resin. Therefore, in the embodiment, SiO2, ZrO3, HfO2, and TiO2 The filler (111) is configured using any one of the ceramic materials. Accordingly, the filler (111) may have a dielectric constant in the range of 3.7 to 4.2 Dk. Meanwhile, the filler (111) may be divided into multiple groups based on diameter. For example, the filler (111) may be divided into at least three groups based on diameter. For example, the filler (111) may include a first filler group having a first diameter range, a second filler group having a second diameter range smaller than the first diameter range, and a third filler group having a third diameter range smaller than the second diameter range. Specifically, the filler (111) may include a first filler group having a first diameter, a second filler group having a second diameter smaller than the first diameter, and a third filler group having a third diameter smaller than the second diameter. And, the first diameter of the first filler group may satisfy the first diameter range. Additionally, the second diameter of the second filler group may satisfy the second diameter range. Additionally, the third diameter of the third filler group may satisfy the third diameter range. In the embodiment, when dispersing the filler (111) within the resin, the filler (111) is divided into at least three filler groups based on different diameter ranges, and the at least three filler groups are dispersed within the resin. Accordingly, in the embodiment, the insulating layer (110) is made to have a low dielectric constant of 2.9 to 3.2 Dk, and the insulating layer (110) is made to have a strength above a certain level. Furthermore, in the embodiment, under conditions where the insulating layer (110) has the dielectric constant and strength of the above range, the exposure of the filler (111) after desmearing is minimized, thereby minimizing migration growth.

[0089] In addition, the insulating layer (110) in the embodiment is configured to have a thermal expansion coefficient of 30 to 42 ppm.

[0090] To this end, the filler (111) in the insulating layer (110) may have a high content. For example, the content of the filler (111) in the insulating layer (110) in the embodiment may be 68% by weight to 76% by weight. If the content of the filler (111) in the insulating layer (110) is lower than 68% by weight, the insulating layer (110) may not have a strength above a certain level and may not have a coefficient of thermal expansion within the above range. Also, if the content of the filler (111) in the insulating layer (110) is greater than 76% by weight, the insulating layer (110) may not have a low dielectric constant. Therefore, in the embodiment, the filler (111) in the insulating layer (110) is configured to satisfy a range of 65% by weight to 76% by weight. Meanwhile, in the embodiment, the filler (111) may be divided into a plurality of groups having different diameter ranges. In addition, multiple groups of the filler (111) may have different contents.

[0091] For example, the filler (111) may be divided into at least three groups of fillers having different diameter ranges. Specifically, the filler (111) may include a first group of fillers having a first diameter range. The first diameter range of the first group of fillers may be 2 μm to 3.5 μm. The first group of fillers may have a larger diameter than the other groups of fillers constituting the filler (111). For example, the first group of fillers may have the largest diameter range among the diameter ranges of each of the at least three groups of fillers included in the filler (111). The filler (111) may include a second group of fillers having a second diameter range. The second diameter range of the second group of fillers may be 1 μm to 2 μm. The second group of fillers may be the group of fillers having the highest content among the groups of fillers constituting the filler (111). For example, the second filler group may consist of fillers having an intermediate diameter range among the plurality of filler groups constituting the filler (111). And, among the respective contents of the plurality of filler groups constituting the filler (111), the content of the second filler group having the intermediate diameter range may be the largest. The filler (111) may include a third filler group having a third diameter range. The third diameter range of the third filler group may be 0.5 μm to 1 μm. In the first embodiment, the third filler group may consist of fillers having the smallest diameter range among the plurality of filler groups constituting the filler (111). The third filler group enables the direction of resin flow within the insulating layer (110) to be controlled while maintaining the dielectric constant that the insulating layer (110) must have within the content range of the filler (111).

[0092] For example, the filler (111) described above includes a first group of fillers, a second group of fillers, and a third group of fillers. In this case, the flow of resin between the fillers (111) comprising such a plurality of filler groups may be regular. For example, in the embodiment, the first group of fillers has the largest diameter range. Accordingly, a second group of fillers and a third group of fillers having a smaller diameter may be arranged between the fillers constituting the first group of fillers. Therefore, in the embodiment, with the presence of the filler (111) comprising such a plurality of filler groups, the flow of resin may occur along the second group of fillers and the third group of fillers between the first group of fillers having the largest diameter.

[0093] In the embodiment, the first filler group is included in the filler (111) in a range of 5% to 20% by weight. If the content of the first filler group is less than 5% by weight, the insulating layer (110) may not have a certain level of rigidity. Additionally, if the content of the first filler group is greater than 20% by weight, a problem may occur in which the filler is exposed to the surface of the insulating layer (110) during the desmearing process as the content of the first filler group increases. This may lead to migration growth.

[0094] Additionally, in the embodiment, the second filler group may be included in the filler (111) in a range between 60% and 80% by weight. If the second filler group has a content less than 60% by weight, the insulating layer (110) may not have a certain level of rigidity. Also, if the second filler group has a content greater than 80% by weight, the insulating layer (110) may not satisfy the required low dielectric constant. Additionally, if the second filler group has a content greater than 80% by weight, a problem may occur in which the filler is exposed to the surface of the insulating layer (110) during the desmear process.

[0095] In addition, in the embodiment, the third filler group in the filler (111) may have a content of 10% to 30% by weight. If the third filler group has a content less than 10% by weight, the content of the first filler group or the second filler group must be increased as the content of the third filler group decreases, and reliability issues may arise as a result. In addition, if the third filler group has a content greater than 30% by weight, resin flowability may decrease as the content of the third filler group increases.

[0096] Meanwhile, although it has been described above that the filler (111) included in the insulating layer (110) is divided into at least three groups according to its diameter, it is not limited thereto. For example, the diameters of the filler (111) included in the insulating layer (110) may all be the same, or they may be divided into two groups according to their diameter.

[0097] The insulating layer (110) may have a thickness in the range of 10 µm to 30 µm. For example, the insulating layer (110) may have a thickness in the range of 15 µm to 25 µm.

[0098] Meanwhile, although it has been described above that the filler (111) within the insulating layer (110) is divided into at least three groups according to its diameter, it is not limited thereto. For example, the diameters of the filler (111) included within the insulating layer (110) may all be the same, or they may be divided into two groups according to their diameter.

[0099] The insulating layer (110) includes a surface layer (110S). At this time, the surface layer (110S) does not mean a layer separately laminated on the insulating layer (110), but may mean an area adjacent to the surface in the entire area of ​​the insulating layer (110).

[0100] For example, the surface layer (110S) of the insulating layer (110) may refer to a certain depth region on the surface of the insulating layer (110). For example, the surface layer (110S) of the insulating layer (110) may refer to a depth region in the range of 10 nm to 100 nm on the surface of the insulating layer (110). For example, the surface layer (110S) of the insulating layer (110) may refer to a depth region in the range of 12 nm to 70 nm on the surface of the insulating layer (110). For example, the surface layer (110S) of the insulating layer (110) may refer to a depth region in the range of 15 nm to 50 nm on the surface of the insulating layer (110).

[0101] The surface layer (110S) of the insulating layer (110) may include a plurality of portions.

[0102] For example, the surface layer (110S) of the insulating layer (110) may include a first portion (110TS) adjacent to the upper surface of the insulating layer (110). For example, the surface layer (110S) of the insulating layer (110) may include a second portion (110BS) adjacent to the lower surface of the insulating layer (110). For example, the surface layer (110S) of the insulating layer (110) may include a third portion (110WS) adjacent to the inner wall of a through hole (not shown) of the insulating layer (110).

[0103] The first part (110TS), the second part (110BS), and the third part (110WS) of the surface layer (110S) of the insulating layer (110) may each contain fluorine (F). The first part (110TS), the second part (110BS), and the third part (110WS) may have substantially the same characteristics, and accordingly, they will be described below as the surface layer (110S).

[0104] The surface layer (110S) of the insulating layer (110) contains fluorine (F). That is, in the embodiment, plasma treatment is performed on the surface layer (110S) corresponding to a certain depth region on the surface of the insulating layer (110). That is, in the embodiment, plasma treatment is performed on the physical properties on the surface of the insulating layer (110) to modify the physical properties.

[0105] For example, as in FIG. 4(a), the surface layer (110S) of the insulating layer (110) before plasma treatment includes CH bond portions.

[0106] And, in the embodiment, plasma treatment is performed on the surface of the insulating layer (110) as shown in Fig. 4(b). Preferably, in the embodiment, plasma treatment is performed on the surface of the insulating layer (110) using CF4.

[0107] In addition, in the embodiment, if plasma treatment is performed using CF4 on the surface of the insulating layer (110), the surface layer (110S) of the insulating layer (110) can be modified.

[0108] Specifically, when plasma treatment is performed using the above CF4, CH in the surface layer (110S) of the insulating layer (110) can be replaced with CF. Through this, in the embodiment, fluorine (F) can be included in the surface layer (110S) of the insulating layer (110).

[0109] That is, the surface layer (110S) in the depth range of 10 nm to 100 nm from the surface of the insulating layer (110) includes carbon (C)-fluorine (F) bonding portions. At this time, the fluorine (F) can lower the polarity of the surface of the insulating layer.

[0110] At this time, the CF bond has a lower electronic polarizability compared to the CH bond, and accordingly, the polarity of the surface of the insulating layer (110) can be reduced.

[0111] Specifically, as the operating frequency of the application to which the circuit board is applied increases, the signal flow moves to the surface of the conductor (circuit pattern layer) due to the skin effect.

[0112] Accordingly, the polarity at the surface layer (110S) of the insulating layer (110) in contact with the conductor determines the overall communication performance of the circuit board.

[0113] That is, as shown in Fig. 5(a), in the first frequency range (e.g., 0 to 3 GHz), the signal has the characteristic of flowing in an area away from the surface of the conductor.

[0114] And, as shown in Fig. 5(b), in the second frequency range (e.g., 3 to 7 GHz), the signal has the characteristic of flowing in the area adjacent to the surface of the conductor.

[0115] In addition, as shown in Fig. 5(c), in a third frequency range (e.g., 10 GHz or higher), the signal has the characteristic of flowing on the surface of the conductor.

[0116] Accordingly, as the frequency of the above signal increases, the signal has the characteristic of flowing toward the surface of the conductor, and the polarity at the surface of the conductor is important.

[0117] In addition, the polarity on the surface of the conductor corresponds substantially to the polarity on the surface layer (110S) of the insulating layer (110) in contact with the conductor.

[0118] At this time, the polarity of the surface layer (110S) of the insulating layer (110) containing the fluorine (F) in the embodiment has a lower polarity than CH prior to the plasma treatment. Accordingly, in the embodiment, plasma treatment is performed using CF4 to include fluorine (F) with low polarity in the surface layer (110S) of the insulating layer (110). Through this, in the embodiment, by lowering the polarity of the surface layer (110S) of the insulating layer (110), the polarity of the surface of the circuit pattern layer can be lowered compared to the existing one, thereby lowering the signal transmission loss of the circuit pattern layer and improving the signal transmission speed.

[0119] For example, the surface layer (110S) includes a first part (110TS), a second part (110BS), and a third part (110WS), and accordingly, the transmission loss of a signal flowing through the first circuit pattern layer (120), the second circuit pattern layer (130), and the through electrode (140) described below can be minimized, and the signal transmission speed can be improved.

[0120] Meanwhile, the surface layer (110S) in the embodiment may contain a plurality of elements. For example, the surface layer of the insulating layer (110) in the embodiment may contain carbon (C), oxygen (O), nitrogen (N), silicon (Si), and fluorine (F).

[0121] At this time, the atomic ratio of multiple elements in the surface layer (110S) in the embodiment may differ from the atomic ratio of the existing surface layer prior to plasma treatment.

[0122] Here, the atomic ratio may refer to the ratio between the number of each metal element included in the surface layer (110S).

[0123] The ratio of each element in the surface layer in the examples and comparative examples may be as shown in Table 3 below.

[0125] C 1s O 1s N 1s F 1s Si op Example 1 25.6 38.1 1.2 16.1 11.5 Example 2 23.7 27 1.1 33.2 - Comparison Example 1 35.2 39.2 1.2 - 1.9 Comparison Example 2 34.1 40.6 1.0 - 1.6

[0127] Meanwhile, Table 3 does not include element ratios for some elements, and accordingly, the surface layer in the examples and comparative examples may contain elements other than those in Table 3. For example, the surface layer in the examples and comparative examples may additionally contain at least one of chromium (Cr), nickel (Ni), and zinc (Zn).

[0128] Referring to Table 3, it was confirmed that fluorine (F) was not detected in the surface layer of the insulating layer in the existing comparative examples 1 and 2.

[0129] In contrast, in the example, plasma treatment was performed on the surface layer of the insulating layer using CF4, and it was confirmed that fluorine (F) was detected in the surface layer.

[0130] At this time, the atomic ratio of fluorine (F) in the surface layer (110S) in the embodiment may satisfy a range of 8% to 50%. Preferably, the atomic ratio of fluorine (F) in the surface layer (110S) may satisfy a range of 9% to 40%. More preferably, the atomic ratio of fluorine (F) in the surface layer (110S) may satisfy a range of 10% to 30%.

[0131] If the atomic ratio of fluorine (F) in the surface layer (110S) is less than 8%, the effect of reducing signal transmission loss in the circuit pattern layer due to the fluorine (F) may be negligible. This may make it difficult to apply to products using high frequencies. Also, if the atomic ratio of fluorine (F) in the surface layer (110S) exceeds 50%, the adhesion between the insulating layer (110) and the circuit pattern layers or through electrodes due to the fluorine (F) may be reduced, and this may result in a reliability problem where the circuit pattern layers or through electrodes are separated from the insulating layer.

[0132] As described above, in the embodiment, fluorine (F) with low electrical polarity is included in the surface layer (110S) at a certain depth from the surface of the insulating layer (110), thereby minimizing signal transmission loss due to the skin effect and improving communication performance.

[0133] Meanwhile, as the dielectric constant or polarity of the insulating layer (110) increases, signal loss increases and the signal transmission speed decreases accordingly. However, if the dielectric constant or polarity of the insulating layer (110) is lowered without a standard, the bending characteristics of the insulating layer may be degraded accordingly.

[0134] Specifically, the coefficient of thermal expansion and the dielectric constant of the insulating layer (110) have a mutual trade-off relationship. Accordingly, if the polarity of the insulating layer (110) is lowered, the coefficient of thermal expansion of the insulating layer (110) increases, and the warpage characteristic is reduced. In this embodiment, the polarity is not modified for the entire area of ​​the insulating layer (110), but rather the polarity is modified only for the surface layer (110S) at a certain depth from the surface of the insulating layer (110) through plasma treatment. Through this, in the embodiment, the polarity of only the surface layer (110S) of the insulating layer (110) is modified while maintaining the coefficient of thermal expansion of the insulating layer (110), thereby allowing for the minimization of signal loss and an increase in signal transmission speed while maintaining the warpage characteristic of the circuit board.

[0135] In addition, the fluorine (F) can delocalize the distribution of electrons within the molecules of the insulating layer, thereby lowering the overall polarity of the polymer. Through this, in the embodiment, the packing density of the polymer is lowered and the free volume is increased, thereby lowering the dielectric constant of the insulating layer (110), and thus, high reliability can be maintained even in products using high frequency.

[0137] At this time, the signal transmission loss in the case where the surface layer of the insulating layer (110) in the embodiment includes fluorine (F) and the case where the fluorine (F) is not included is as shown in Table 4 below.

[0139] Signal transmission loss (dB / in), strip line 10GHz 20GHz 30GHz 60GHz Example 1 -0.37 -0.60 -0.80 -1.44 Example 2 -0.37 -0.63 -0.88 -1.67 Comparison Example 1 -0.44 -0.78 -1.21 -1.81 Comparison Example 2 -0.49 -0.88 -1.15 -2.35

[0141] Referring to Table 4, it was confirmed that the signal transmission loss in the case where fluorine (F) is included in the surface layer (110S) of the insulating layer (110) through plasma treatment as in the example is lower than the signal transmission loss before conventional plasma treatment.

[0143] Meanwhile, a circuit pattern layer may be disposed on the surface of the insulating layer (110) of the embodiment.

[0144] For example, a first circuit pattern layer (120) may be disposed on the upper surface of the insulating layer (110) (preferably, a first portion of the surface layer of the insulating layer). Additionally, a second circuit pattern layer (130) may be disposed on the lower surface of the insulating layer (110) (preferably, a second portion of the surface layer of the insulating layer).

[0145] The first circuit pattern layer (120) and the second circuit pattern layer (130) can be formed using the SAP (Semi Additive Process) method.

[0146] The first circuit pattern layer (120) and the second circuit pattern layer (130) may each include a trace and a pad.

[0147] At this time, the line width of each trace of the first circuit pattern layer (120) and the second circuit pattern layer (130) may have a range of 2 μm to 15 μm. For example, the line width of each trace of the first circuit pattern layer (120) and the second circuit pattern layer (130) may satisfy a range of 2.2 μm to 12 μm. For example, the line width of each trace of the first circuit pattern layer (120) and the second circuit pattern layer (130) may satisfy a range of 2.5 μm to 10 μm.

[0148] Preferably, the traces of the first circuit pattern layer (120) and the second circuit pattern layer (130) may be fine patterns having a line width in the range of 2.5 μm to 10 μm.

[0149] Accordingly, in the embodiment, fluorine (F) is included between the insulating layer (110) and the first circuit pattern layer (120), and between the insulating layer (110) and the second circuit pattern layer (130), thereby reducing signal transmission loss transmitted through the first circuit pattern layer (120) and the second circuit pattern layer (130).

[0150] In addition, in the embodiment, the adhesion between the insulating layer (110) and the first circuit pattern layer (120) and the second circuit pattern layer (130) can be improved by controlling the thickness of the first metal layer and the surface roughness value of each of the first circuit pattern layer (120) and the second circuit pattern layer (130) described below.

[0151] The first circuit pattern layer (120) and the second circuit pattern layer (130) described above may be formed from at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Additionally, the first circuit pattern layer (120) and the second circuit pattern layer (130) may be formed from a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit pattern layer (120) and the second circuit pattern layer (130) may be formed from copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0152] The first circuit pattern layer (120) and the second circuit pattern layer (130) may have a thickness in the range of 5 μm to 20 μm. For example, the first circuit pattern layer (120) and the second circuit pattern layer (130) may have a thickness in the range of 6 μm to 17 μm. The first circuit pattern layer (120) and the second circuit pattern layer (130) may have a thickness in the range of 7 μm to 13 μm. If the thickness of the first circuit pattern layer (120) and the second circuit pattern layer (130) is less than 5 μm, the resistance may increase. If the thickness of the first circuit pattern layer (120) and the second circuit pattern layer (130) exceeds 20 μm, it may be difficult to miniaturize the trace.

[0153] Meanwhile, the first circuit pattern layer (120) and the second circuit pattern layer (130) may each have a plurality of layer structures.

[0154] For example, the first circuit pattern layer (120) may include a first metal layer (121) and a second metal layer (122). Correspondingly, the second circuit pattern layer (130) may include a first metal layer (131) and a second metal layer (132). At this time, the layer structure of the first circuit pattern layer (120) and the second circuit pattern layer (130) has substantially the same structure, and below, the explanation will focus on the layer structure of the first circuit pattern layer (120).

[0155] The first circuit pattern layer (120) may include a first metal layer (121) disposed on the upper surface of the insulating layer (110). The first metal layer (121) may be an electroless plating layer. Preferably, the first metal layer (121) may be a chemical copper plating layer.

[0156] The first circuit pattern layer (120) may include a second metal layer (122) disposed on the first metal layer (121). The second metal layer (122) may be an electroplated layer. For example, the second metal layer (122) may be a layer formed by electroplating the first metal layer (121) as a seed layer.

[0157] The thickness of the first metal layer (121) may satisfy a range of 10% to 100% of the line width of the trace of the first circuit pattern layer (120). For example, the ratio of the line width of the trace of the first circuit pattern layer (120) to the thickness of the first metal layer (121) may satisfy a range of 1 to 10 times. The thickness of the first metal layer (121) may satisfy a range of 5% to 50% of the total thickness of the first circuit pattern layer (120). For example, the ratio of the total thickness of the first circuit pattern layer (120) to the thickness of the first metal layer (121) may satisfy a range of 2 to 20 times. The thickness of the first metal layer (121) may satisfy a range of 6% to 100% of the thickness of the second metal layer (122). For example, the ratio of the thickness of the second metal layer (122) to the thickness of the first metal layer (121) can satisfy a range between 1 and 19 times.

[0158] Specifically, the first metal layer (121) may satisfy a thickness in the range of 1 μm to 2.5 μm. Preferably, the first metal layer (121) may satisfy a thickness in the range of 1.2 μm to 2.3 μm. Preferably, the first metal layer (121) may satisfy a thickness in the range of 1.4 μm to 2.2 μm.

[0159] If the thickness of the first metal layer (121) is less than 1 μm, the size of the plating particles constituting the first metal layer (121) is small, and accordingly, the adhesion between the insulating layer (110) and the first metal layer (121) may be reduced. And, due to the decrease in adhesion between the first metal layer (121) and the insulating layer (110), a problem may occur in which the first circuit pattern layer (120) is separated into the insulating layer (110).

[0160] If the thickness of the first metal layer (121) is greater than 2.5 μm, it may be difficult to miniaturize the first circuit pattern layer (120). For example, if the thickness of the first metal layer (121) is greater than 2.5 μm, it may be difficult to form the line width of the trace of the first circuit pattern layer (120) to be 10 μm or less.

[0161] In the embodiment, the thickness of the first metal layer (121) is increased compared to the comparative example, and the adhesion between the insulating layer (110) and the first metal layer (121) can be improved accordingly.

[0163] Below, the difference in adhesion strength according to the difference in plating thickness of the first metal layer between the comparative example and the example is shown in Table 5.

[0165] Trace shear (gf) Trace line width 5㎛ 7㎛ 9㎛ 11㎛ 13㎛ 15㎛ 17㎛ Comparison Example 6.06 7.92 10.59 13.40 14.84 17.26 19.32 Example 1 (1.1㎛) 6.9 8.5 11.4 14.3 15.95 18.99 21.01 Example 2 (1.5㎛) 7.25 9.5 12.05 14.87 17.30 20.22 22.30 Improvement % of Example 2 19.8% 17.3% 12.3% 10.6% 14.2% 14.9% 14.1% Example 3 (1.9㎛) 8.46 10.65 13.20 16.26 19.05 22.40 24.77 Improvement (%) of Example 3 39.6% 34.5% 24.6% 21.3% 28.4% 29.8% 28.2%

[0166] Referring to Table 5, it was confirmed that in the embodiment, as the thickness of the first metal layer (121) corresponding to the chemical copper plating layer increased compared to the comparative example, the adhesion between the first metal layer (121) and the insulating layer (110) increased. In particular, in the embodiment, when the line width of the trace of the first circuit pattern layer (120) was 10 μm or less, it was confirmed that the adhesion between the first metal layer (121) and the insulating layer (110) was further improved compared to the comparative example.

[0167] Meanwhile, in order to further improve the adhesion between the first metal layer (121) and the upper surface of the insulating layer (110), it is preferable that the surface roughness value of the upper surface of the insulating layer (110) be determined based on the thickness of the first metal layer (121).

[0168] Here, the surface roughness value described below may refer to the surface roughness value of the surface layer (110S) of the insulating layer (110) or the surface roughness value of the first metal layer.

[0169] For example, the centerline average roughness value (Ra) of the insulating layer (110) may be 12% to 50% of the thickness of the first metal layer (121).

[0170] For example, the centerline average roughness value (Ra) of the upper surface of the insulating layer (110) may have a range between 200 nm and 600 nm. For example, the centerline average roughness value (Ra) of the upper surface of the insulating layer (110) may be between 300 nm and 500 nm.

[0171] If the centerline average roughness value (Ra) of the upper surface of the insulating layer (110) is less than 200 nm, the anchoring effect that can be expected when plating the first metal layer (121) on the insulating layer (110) may be reduced.

[0172] Additionally, if the centerline average roughness value (Ra) of the upper surface of the insulating layer (110) exceeds 600 nm, the first metal layer (121) cannot be formed with a uniform thickness on the upper surface of the insulating layer (110) as the centerline average roughness value (Ra) of the upper surface of the insulating layer (110) is large, and consequently, the adhesion between the insulating layer (110) and the first metal layer (121) may be reduced. Furthermore, if the centerline average roughness value (Ra) of the upper surface of the insulating layer (110) is greater than 600 nm, a problem may occur in which the first metal layer (121) remains between the roughness of the upper surface of the insulating layer (110) during the process of etching the first metal layer (121) on the insulating layer (110), and electrical reliability problems such as circuit shorts may occur due to the remaining metal. Furthermore, if the centerline average roughness value (Ra) of the upper surface of the insulating layer (110) is greater than 600 nm, signal transmission loss may increase due to the skin effect.

[0173] Preferably, the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) can satisfy a range between 80% and 600% of the thickness of the first metal layer (121).

[0174] For example, the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) may be 2 μm to 6 μm. For example, the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) may be 3 μm to 5 μm.

[0175] For example, if the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) is less than 2 μm, the anchoring effect that can be expected when plating the first metal layer (121) on the insulating layer (110) may be reduced.

[0176] Additionally, if the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) exceeds 6 μm, the first metal layer (121) cannot be formed with a uniform thickness on the upper surface of the insulating layer (110) as the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) is large, and consequently, the adhesion between the insulating layer (110) and the first metal layer (121) may be reduced. Furthermore, if the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) is greater than 6 μm, a problem may occur in which the first metal layer (121) remains between the roughness of the upper surface of the insulating layer (110) during the process of etching the first metal layer (121) on the insulating layer (110), and electrical reliability problems such as circuit shorts may occur due to the remaining metal. Furthermore, if the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) is greater than 6㎛, the signal transmission loss may increase due to the skin effect.

[0177] Meanwhile, the first metal layer (131) of the second circuit pattern layer (130) may also have a thickness within the same range as the first metal layer (121) of the first circuit pattern layer (120). Additionally, the lower surface of the insulating layer (110) may have the same centerline average roughness value (Ra) and / or maximum cross-sectional height value (Rt) as the upper surface of the insulating layer (110).

[0179] Meanwhile, the centerline average roughness value (Ra) and the maximum cross-sectional height value (Rt) of the upper surface of the insulating layer (110) can each correspond to the centerline average roughness value (Ra) and the maximum cross-sectional height value (Rt) of the lower surface of the first metal layer (121) in contact with the upper surface of the insulating layer (110).

[0180] And, the adhesion force between the insulating layer and the first metal layer (121) according to the centerline average roughness value (Ra) and maximum cross-sectional height value (Rt) as described above is as shown in Table 6 below.

[0182] Trace line width (9㎛) Trace shear (gf) / Ra: 300nm Rt: 3㎛ Ra: 400nm Rt: 4㎛ Ra: 500nm Rt: 5㎛ First metal layer thickness: 1.0㎛ 9.10 10.60 12.30 First metal layer thickness: 1.5㎛ 10.90 12.10 13.50 First metal layer thickness: 1.9㎛ 11.80 13.20 14.80

[0183] As shown in Table 6 above, in the embodiment, it was confirmed that the adhesion force is further enhanced by controlling the centerline average roughness value (Ra) and the maximum cross-sectional height value (Rt) of the surface of the insulating layer (110) or the first metal layer (121) in correspondence with the thickness of the first metal layer (121). Meanwhile, a through electrode (140) may be formed within the insulating layer (110). The through electrode (140) may penetrate the insulating layer (110). For example, the through electrode (140) may electrically connect the first circuit pattern layer (120) and the second circuit pattern layer (130). For example, the upper surface of the through electrode (140) may be connected to the first circuit pattern layer (120), and the lower surface of the through electrode (140) may be connected to the second circuit pattern layer (130).

[0184] The above-mentioned penetrating electrode (140) can be formed by forming a penetrating hole (not shown) that penetrates the insulating layer (110) and filling the inside of the formed penetrating hole with a conductive material.

[0185] The through hole may be formed by any one of the processing methods of mechanical, laser, and chemical processing. When the through hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used; when it is formed by laser processing, UV or CO2 laser methods may be used; and when it is formed by chemical processing, at least one of the plurality of insulating layers may be opened using a chemical agent including aminosilanes, ketones, etc.

[0186] Meanwhile, the above-mentioned laser processing is a cutting method that concentrates optical energy on a surface to melt and evaporate a portion of the material to form a desired shape, and can easily process complex shapes created by computer programs and can also process composite materials that are difficult to cut by other methods.

[0187] In addition, the above laser processing has the advantage of a cutting diameter of up to 0.005 mm and a wide range of processable thicknesses.

[0188] It is preferable to use a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser for the above-mentioned laser processing drill. A YAG laser is capable of processing both the copper foil layer and the insulating layer, while a CO2 laser is capable of processing only the insulating layer.

[0189] When the through hole is formed, the inside of the through hole can be filled with a conductive material to form the through electrode (140). The metal material forming the through electrode (140) may be any one of copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the filling of the conductive material may be performed using any one of electroless plating, electroplating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0190] Meanwhile, the penetrating electrode (140) may include a first metal layer (141) and a second metal layer (142).

[0191] The first metal layer (141) of the through electrode (140) may correspond to the first metal layer (121) of the first circuit pattern layer (120), and the second metal layer (142) of the through electrode (140) may correspond to the second metal layer (122) of the first circuit pattern layer (120).

[0192] Accordingly, the first metal layer (141) of the through electrode (140) may satisfy a thickness in the range of 1 μm to 2.5 μm. Preferably, the first metal layer (141) of the through electrode (140) may satisfy a thickness in the range of 1.2 μm to 2.3 μm. Preferably, the first metal layer (141) of the through electrode (140) may satisfy a thickness in the range of 1.4 μm to 2.2 μm.

[0193] Additionally, the centerline average roughness value (Ra) of the inner wall of the through hole of the insulating layer (110) (clearly, the third part of the surface layer of the insulating layer) may have a range between 200 nm and 600 nm. For example, the centerline average roughness value (Ra) of the inner wall of the through hole of the insulating layer (110) may be between 300 nm and 500 nm.

[0194] Additionally, the maximum cross-sectional height value (Rt) of the inner wall of the through hole of the insulating layer (110) may be 2 μm to 6 μm. For example, the maximum cross-sectional height value (Rt) of the inner wall of the through hole of the insulating layer (110) may be 3 μm to 5 μm.

[0196] In the embodiment, by controlling the surface roughness value of the surface layer (110S) of the insulating layer (110) while including fluorine (F) in the surface layer (110S) of the insulating layer (110) as described above, and further controlling the thickness of the first metal layer in contact with the surface layer (110S) of the insulating layer (110), the signal transmission loss of the circuit pattern layer or the through electrode can be lowered, and the adhesion with the insulating layer can be improved.

[0198] Figure 6 is a drawing for comparing the adhesion force between the insulating layer and the circuit pattern layer according to a comparative example and an embodiment.

[0199] As shown in FIG. 6(a), in the comparative example, it was confirmed that as the line width of the trace decreases, reliability problems such as separation of the trace occur in some areas as the adhesion between the trace and the insulating layer decreases. In FIG. 9, W1 means that the line width of the trace is 17 μm, W2 means that the line width of the trace is 15 μm, W3 means that the line width of the trace is 13 μm, W4 means that the line width of the trace is 11 μm, W5 means that the line width of the trace is 9 μm, W6 means that the line width of the trace is 7 μm, and W7 means that the line width of the trace is 5 μm.

[0200] For example, in a comparative example, at a line width of 7 μm (W6), it was confirmed that traces in some regions were separated and did not remain on the insulating layer.

[0201] In contrast, in the embodiment, the thickness of the first metal layer constituting the circuit pattern layer is increased compared to the comparative example, thereby ensuring adhesion between the insulating layer (110) and the circuit pattern layers. Through this, as shown in FIG. 6 (b), in the embodiment, it was confirmed that even if the line width of the trace of the circuit pattern layer is reduced to 10 μm or less, it is stably placed on the insulating layer.

[0203] The circuit board in the embodiment includes an insulating layer comprising a surface layer and a circuit pattern layer disposed on the insulating layer. The surface layer may refer to a depth range of 10 nm to 100 nm from the surface of the insulating layer. The surface layer of the insulating layer contains fluorine. That is, the surface layer of the insulating layer contains carbon (C)-fluorine (F). In this case, the fluorine (F) can lower the polarity of the surface of the insulating layer.

[0204] That is, in the embodiment, plasma treatment is performed on the insulating layer using CF4. At this time, the surface layer of the insulating layer before the plasma treatment includes CH bond portions. Then, the CH bond portions of the surface layer of the insulating layer after the plasma treatment are replaced with CF bonds. Furthermore, the CF has lower electronic polarizability compared to CH, and accordingly, the polarity of the surface of the insulating layer can be reduced. At this time, as the operating frequency of the application to which the circuit board is applied increases, the signal flow moves to the surface of the conductor due to the skin effect, and thus the polarity of the dielectric surface in contact with the conductor is important. At this time, in the embodiment, by including fluorine (F), which has low electrical polarity, in the surface layer within a certain depth range from the surface of the insulating layer, signal transmission loss due to the skin effect can be minimized, and communication performance can be improved accordingly.

[0205] In addition, as the dielectric constant or surface polarity of the insulating layer increases, signal loss increases, and the signal transmission speed decreases accordingly. At this time, the coefficient of thermal expansion and the dielectric constant of the insulating layer have a mutual trade-off relationship; accordingly, if the polarity of the insulating layer is lowered, the coefficient of thermal expansion of the insulating layer increases, and the warpage characteristics are degraded accordingly. In this embodiment, instead of modifying the polarity of the entire area of ​​the insulating layer, polarity modification is performed only on the surface layer up to a certain depth from the surface of the insulating layer through plasma treatment. Through this, in the embodiment, by modifying only the polarity of the surface layer of the insulating layer while maintaining the coefficient of thermal expansion of the insulating layer, it is possible to minimize signal loss and increase the signal transmission speed while maintaining the warpage characteristics of the circuit board.

[0206] In addition, in the embodiment, fluorine (F) with high electronegativity is present in the surface layer of the insulating layer. At this time, the fluorine (F) can lower the overall polarity of the polymer by delocalizing the distribution of electrons within the molecules of the insulating layer. Through this, in the embodiment, the packing density of the polymer is lowered and the free volume is increased, thereby lowering the dielectric constant of the insulating layer, and thus high reliability can be maintained even in products using high frequency.

[0207] Meanwhile, the circuit pattern layer in the embodiment includes a first metal layer and a second metal layer. The first metal layer may satisfy a thickness in the range of 1 μm to 2.5 μm. Preferably, the first metal layer may satisfy a thickness in the range of 1.2 μm to 2.3 μm. Preferably, the first metal layer may satisfy a thickness in the range of 1.4 μm to 2.2 μm. Through this, in the embodiment, the adhesion between the first metal layer and the insulating layer can be further improved, and furthermore, the adhesion between the insulating layer and the circuit pattern layer can be improved. Through this, in the embodiment, the electrical reliability of the circuit pattern layer can be improved, and product satisfaction can be improved accordingly. In addition, in the embodiment, by improving the adhesion between the insulating layer and the circuit pattern layer, the line width of the trace constituting the circuit pattern layer can be miniaturized, thereby increasing the circuit integration density or reducing the overall volume of the circuit board.

[0208] In addition, the centerline average roughness value (Ra) of the first metal layer in the embodiment may have a range between 200 nm and 600 nm. The centerline average roughness value (Ra) of the first metal layer may be between 300 nm and 500 nm. In addition, the maximum cross-sectional height value (Rt) of the first metal layer may be between 2 μm and 6 μm. For example, the maximum cross-sectional height value (Rt) of the first metal layer may be between 3 μm and 5 μm. In the embodiment, by controlling the centerline average roughness value (Ra) or the maximum cross-sectional height value (Rt) in correspondence with the thickness of the first metal layer, the anchoring effect can be further enhanced with increasing thickness of the first metal layer. Furthermore, in the embodiment, the plating thickness uniformity of the first metal layer can be improved by controlling the centerline average roughness value (Ra) and the maximum cross-sectional height value (Rt), and furthermore, when etching the first metal layer, a portion of the first metal layer is prevented from remaining on the surface of the insulating layer, thereby improving the electrical reliability of the circuit board and improving the yield of the circuit board.

[0210] - Manufacturing Method -

[0211] Hereinafter, a method for manufacturing a circuit board according to an embodiment will be described.

[0212] FIGS. 7 to 15 are drawings showing a method for manufacturing a circuit board according to an embodiment in process order.

[0213] Referring to FIG. 7, in the embodiment, an insulating member is prepared to form the basis for manufacturing a circuit board. Preferably, in the embodiment, resin-coated copper (RCC) may be prepared. For example, the insulating member may include an insulating layer (110) comprising resin and a filler (111) and a copper foil layer (200) attached to the insulating layer (110).

[0214] Next, referring to FIG. 8, in the embodiment, the insulating member can be processed to form a through hole (TH) that penetrates the insulating member.

[0215] Next, referring to FIG. 9, in the embodiment, a process of removing the copper foil layer (200) can be performed to form a circuit pattern layer using the SAP method. In addition, in the embodiment, plasma treatment is performed on the surface of the insulating layer (110) using CF4.

[0216] Next, referring to FIG. 10, in the embodiment, the surface layer (110S) of the insulating layer (110) may be modified as the plasma treatment is performed. For example, in the embodiment, fluorine (F) may be included in the surface layer (110S) of the insulating layer (110). For example, in the embodiment, the surface layer (110S) of the insulating layer (110) includes a first part (110TS), a second part (110BS), and a third part (110WS). And, the first part (110TS), the second part (110BS), and the third part (110WS) may each include fluorine (F). Through this, the polarity in the surface layer (110S) of the insulating layer (110) can be lowered in the embodiment.

[0217] Next, referring to FIG. 11, in the embodiment, a process of forming a first metal layer can be carried out. For example, in the embodiment, a process of forming a first metal layer (121, 131, 141) on each of the first part (110TS), the second part (110BS), and the third part (110WS) of the surface layer (110S) of the insulating layer (110) can be carried out.

[0218] At this time, the first metal layer (121, 131, 141) may satisfy a thickness in the range of 1 μm to 2.5 μm. Preferably, the first metal layer (121, 131, 141) may satisfy a thickness in the range of 1.2 μm to 2.3 μm. Preferably, the first metal layer (121, 131, 141) may satisfy a thickness in the range of 1.4 μm to 2.2 μm.

[0219] Next, referring to FIG. 12, in the embodiment, a process of forming a dry film on the first metal layer (121, 131, 141) can be carried out.

[0220] For example, in an embodiment, a process of laminating a first dry film (DF1) having a first opening (OR1) that overlaps vertically with an area where a first circuit pattern layer (120) is to be placed, and a second dry film (DF2) having a second opening (OR2) that overlaps vertically with an area where a second circuit pattern layer (130) is to be placed can be performed.

[0221] Next, referring to FIG. 13, in the embodiment, electroplating can be performed on the first metal layer (121, 131, 141) as a seed layer to form a second metal layer (122, 132, 142) that fills the opening (OR1, OR2) of the dry film (DF1, DF2).

[0222] Next, referring to FIG. 14, in the embodiment, a process of removing dry films (DF1, DF2) can be carried out.

[0223] Next, referring to FIG. 15, in the embodiment, a process of removing the first metal layer (121, 131, 141) that is not vertically overlapped with the second metal layer (122, 132, 142) can be carried out to form a first circuit pattern layer (120), a second circuit pattern layer (130), and a through electrode (140) each comprising the first metal layer and the second metal layer.

[0225] - Multilayer Substrate -

[0226] FIG. 16 is a drawing showing a multilayer circuit board according to the first embodiment.

[0227] Referring to FIG. 16, the circuit board may include an insulating substrate including first to third insulating portions (310, 320, 330), a circuit pattern layer (340), and a through electrode (350).

[0228] The insulating substrate including the first to third insulating portions (310, 320, 330) may have a flat structure. The insulating substrate may be a PCB. Here, the insulating substrate may be implemented as a single substrate, or alternatively, as a multilayer substrate in which a plurality of insulating layers are stacked continuously.

[0229] Accordingly, the insulating substrate may include a plurality of insulating portions (310, 320, 330). As shown in FIG. 16, the plurality of insulating portions includes a first insulating portion (310), a second insulating portion (320) disposed above the first insulating portion (310), and a third insulating portion (330) disposed below the first insulating portion (310).

[0230] The first insulating part (310), the second insulating part (320), and the third insulating part (330) may include different insulating materials. Preferably, the first insulating part (310) may include glass fiber. Also, the second insulating part (320) and the third insulating part (330) may not include glass fiber, unlike the first insulating part (310). Preferably, the second insulating part (320) and the third insulating part (330) may include RCC as shown in FIG. 3.

[0231] Accordingly, the thickness of each insulating layer constituting the first insulating part (310) may differ from the thickness of each insulating layer constituting the second insulating part (320) and the third insulating part (330). In other words, the thickness of each insulating layer constituting the first insulating part (310) may be greater than the thickness of each insulating layer constituting the second insulating part (320) and the third insulating part (330).

[0232] That is, the first insulating part (310) includes glass fibers, and the glass fibers generally have a thickness of 12 μm. Accordingly, the thickness of each insulating layer constituting the first insulating part (310) includes the glass fibers and can have a range between 19 μm and 23 μm.

[0233] In contrast, the second insulating part (320) does not contain glass fibers. Preferably, each insulating layer constituting the second insulating part (320) may be composed of RCC.

[0234] Additionally, the third insulating part (330) does not contain glass fibers. Preferably, each insulating layer constituting the third insulating part (330) may be RCC.

[0236] In other words, the insulating portion constituting the circuit board in the comparative example includes a plurality of insulating layers, and all of the plurality of insulating layers are composed of prepreg containing glass fibers. In this case, it is difficult to reduce the thickness of the glass fibers relative to the prepreg in the circuit board of the comparative example. This is because if the thickness of the prepreg is reduced, the glass fibers contained in the prepreg may come into contact with the circuit pattern placed on the surface of the prepreg, resulting in cracking. Consequently, in the circuit board of the comparative example, reducing the thickness of the PPG could lead to dielectric breakdown and damage to the circuit pattern. Accordingly, the circuit board of the comparative example had a limit in reducing its overall thickness due to the thickness of the glass fibers constituting the prepreg.

[0238] Furthermore, the circuit board in the comparative example has a high dielectric constant because it consists solely of an insulating layer of prepreg containing glass fibers. However, dielectrics with high dielectric constants present a problem in that they are difficult to approach as high-frequency alternatives. In other words, due to the high dielectric constant of the glass fibers in the circuit board of the comparative example, a phenomenon occurs where the dielectric constant breaks down in the high-frequency band.

[0239] Accordingly, in the embodiment, at least some of the layers in the multilayer circuit board include the RCC shown in FIG. 3, thereby making the thickness of the circuit board slim while minimizing signal loss even in the high-frequency band, and furthermore, providing a highly reliable circuit board with improved adhesion between the circuit pattern layer and the insulating layer.

[0240] The first insulating portion (310) may include a first insulating layer (311), a second insulating layer (312), a third insulating layer (313), and a fourth insulating layer (314) from the bottom. Additionally, glass fibers may be included in each of the first insulating layer (311), the second insulating layer (312), the third insulating layer (313), and the fourth insulating layer (314). For example, the first insulating layer (311), the second insulating layer (312), the third insulating layer (313), and the fourth insulating layer (314) may each include prepreg.

[0242] Meanwhile, the insulating substrate in the embodiment of the present invention may be composed of 8 layers based on the insulating layer. However, the embodiment is not limited thereto, and the total number of layers of the insulating layer may increase or decrease.

[0243] In addition, in the first embodiment, the first insulating part (310) may be composed of four layers. For example, in the first embodiment, the first insulating part (310) may be composed of four layers of prepreg.

[0244] Additionally, the second insulating part (320) may include a fifth insulating layer (321) and a sixth insulating layer (322) from the bottom. The fifth insulating layer (321) and the sixth insulating layer (322) constituting the second insulating part (320) may include RCC.

[0245] Additionally, the third insulating part (330) may include a seventh insulating layer (331) and an eighth insulating layer (332) from the top. The seventh insulating layer (331) and the eighth insulating layer (332) constituting the third insulating part (330) may include RCC.

[0246] Accordingly, the circuit pattern layers disposed on the second insulating part (320) and the third insulating part (330) may have a structure corresponding to the first and second circuit pattern layers shown in FIG. 3.

[0247] That is, a circuit pattern layer (340) may be disposed on the surface of the insulating layer constituting each of the first insulating part (310), the second insulating part (320), and the third insulating part (330).

[0248] Preferably, a circuit pattern layer (340) may be disposed on at least one surface of the first insulating layer (311), the second insulating layer (312), the third insulating layer (313), the fourth insulating layer (314), the fifth insulating layer (321), the sixth insulating layer (322), the seventh insulating layer (331) and the eighth insulating layer (332).

[0249] At least one through electrode (350) is formed in at least one of the plurality of insulating layers constituting the first insulating part (310), the second insulating part (320), and the third insulating part (330). The through electrode (350) is positioned to penetrate at least one of the plurality of insulating layers. The through electrode (350) may penetrate only one of the plurality of insulating layers, or it may be formed to penetrate at least two of the plurality of insulating layers in common. Accordingly, the through electrode (350) electrically connects circuit patterns placed on the surfaces of different insulating layers.

[0251] FIG. 17 is a drawing showing a multilayer circuit board according to a second embodiment, and FIG. 18 is a drawing showing a multilayer circuit board according to a third embodiment.

[0252] Referring to FIGS. 17 and 18, in the overall laminated structure of the insulating substrate, the circuit board has a difference in the number of layers of the first insulating part composed of PPG, the second insulating part composed of RCC, and the third insulating part, respectively.

[0253] Referring to FIG. 17, the circuit board in the second embodiment includes a first insulating part (310a), a second insulating part (320a), and a third insulating part (330a).

[0254] Also, the first insulating part (310a) may include two layers of prepreg (311a, 312a).

[0255] Additionally, the second insulating part (320a) may include three layers of RCC (321a, 322a, 323a).

[0256] Additionally, the third insulating part (330a) may include three layers of RCC (331a, 332a, 333a).

[0258] Referring to FIG. 18, the circuit board in the third embodiment may include only one insulating part (310b). And, the insulating part (310b) may have an 8-layer structure.

[0259] In addition, the insulating portion (310b) may all include RCC (311b, 312b, 313b, 314b, 315b, 316b, 317b, 318b).

[0261] - Package Substrate -

[0262] FIG. 19 is a drawing showing a package substrate according to an embodiment.

[0263] Referring to FIG. 19, the package substrate may include at least one multilayer substrate among FIGS. 16 to 18.

[0264] To this end, the multilayer circuit board constituting the package substrate may include a first insulating part (410) including a plurality of insulating layers (411, 412, 413, 414), a second insulating part (420) including a plurality of insulating layers (421, 422), and a third insulating part (430) including a plurality of insulating layers (431, 432). In addition, the second insulating part (420) and the third insulating part (430) may include RCC, and first and second circuit pattern layers as shown in FIG. 3 may be disposed on their surfaces.

[0265] Meanwhile, the package substrate includes a first protective layer (SR1) disposed on an insulating layer disposed at the uppermost side and a second protective layer (SR2) disposed on an insulating layer disposed at the lowermost side.

[0266] Additionally, the package substrate includes a connection portion (500) disposed on a circuit pattern layer disposed on the uppermost side. The connection portion (500) may be a solder ball, but is not limited thereto.

[0267] Additionally, the package substrate may include a chip (600) attached to the connection portion (500).

[0268] The above chip (600) may be a processor chip. For example, the above chip (600) may be an application processor (AP) chip among a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller.

[0269] Additionally, although not shown in the drawings, the package substrate of the embodiment may include additional chips. For example, in the embodiment, at least two chips among a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller may each be placed on the circuit board at a certain interval. For example, the chip (600) in the embodiment may include a central processor chip and a graphics processor chip, but is not limited thereto.

[0270] Meanwhile, the plurality of chips may be spaced apart from each other at a certain distance on the circuit board. For example, the spacing between the plurality of chips may be 150 μm or less. For example, the spacing between the plurality of chips may be 120 μm or less. For example, the spacing between the plurality of chips may be 100 μm or less.

[0271] Preferably, the spacing between the plurality of chips may range from 60 µm to 150 µm. Preferably, the spacing between the plurality of chips may range from 70 µm to 120 µm. Preferably, the spacing between the plurality of chips may range from 80 µm to 110 µm. If the spacing between the plurality of chips is less than 60 µm, problems with operational reliability may occur due to mutual interference between the plurality of chips. If the spacing between the plurality of chips is greater than 150 µm, signal transmission loss may increase as the distance between the plurality of chips increases. If the spacing between the plurality of chips is greater than 150 µm, the volume of the package substrate may increase.

[0273] The circuit board in the embodiment includes an insulating layer comprising a surface layer and a circuit pattern layer disposed on the insulating layer. The surface layer may refer to a depth range of 10 nm to 100 nm from the surface of the insulating layer. The surface layer of the insulating layer contains fluorine. That is, the surface layer of the insulating layer contains carbon (C)-fluorine (F). In this case, the fluorine (F) can lower the polarity of the surface of the insulating layer.

[0274] That is, in the embodiment, plasma treatment is performed on the insulating layer using CF4. At this time, the surface layer of the insulating layer before the plasma treatment includes CH bond portions. Then, the CH bond portions of the surface layer of the insulating layer after the plasma treatment are replaced with CF bonds. Furthermore, the CF has lower electronic polarizability compared to CH, and accordingly, the polarity of the surface of the insulating layer can be reduced. At this time, as the operating frequency of the application to which the circuit board is applied increases, the signal flow moves to the surface of the conductor due to the skin effect, and thus the polarity of the dielectric surface in contact with the conductor is important. At this time, in the embodiment, by including fluorine (F), which has low electrical polarity, in the surface layer within a certain depth range from the surface of the insulating layer, signal transmission loss due to the skin effect can be minimized, and communication performance can be improved accordingly.

[0275] In addition, as the dielectric constant or surface polarity of the insulating layer increases, signal loss increases, and the signal transmission speed decreases accordingly. At this time, the coefficient of thermal expansion and the dielectric constant of the insulating layer have a mutual trade-off relationship; accordingly, if the polarity of the insulating layer is lowered, the coefficient of thermal expansion of the insulating layer increases, and the warpage characteristics are degraded accordingly. In this embodiment, instead of modifying the polarity of the entire area of ​​the insulating layer, polarity modification is performed only on the surface layer up to a certain depth from the surface of the insulating layer through plasma treatment. Through this, in the embodiment, by modifying only the polarity of the surface layer of the insulating layer while maintaining the coefficient of thermal expansion of the insulating layer, it is possible to minimize signal loss and increase the signal transmission speed while maintaining the warpage characteristics of the circuit board.

[0276] In addition, in the embodiment, fluorine (F) with high electronegativity is present in the surface layer of the insulating layer. At this time, the fluorine (F) can lower the overall polarity of the polymer by delocalizing the distribution of electrons within the molecules of the insulating layer. Through this, in the embodiment, the packing density of the polymer is lowered and the free volume is increased, thereby lowering the dielectric constant of the insulating layer, and thus high reliability can be maintained even in products using high frequency.

[0278] Meanwhile, the circuit pattern layer in the embodiment includes a first metal layer and a second metal layer. The first metal layer may satisfy a thickness in the range of 1 μm to 2.5 μm. Preferably, the first metal layer may satisfy a thickness in the range of 1.2 μm to 2.3 μm. Preferably, the first metal layer may satisfy a thickness in the range of 1.4 μm to 2.2 μm. Through this, in the embodiment, the adhesion between the first metal layer and the insulating layer can be further improved, and furthermore, the adhesion between the insulating layer and the circuit pattern layer can be improved. Through this, in the embodiment, the electrical reliability of the circuit pattern layer can be improved, and product satisfaction can be improved accordingly. In addition, in the embodiment, by improving the adhesion between the insulating layer and the circuit pattern layer, the line width of the trace constituting the circuit pattern layer can be miniaturized, thereby increasing the circuit integration density or reducing the overall volume of the circuit board.

[0279] In addition, the centerline average roughness value (Ra) of the first metal layer in the embodiment may have a range between 200 nm and 600 nm. The centerline average roughness value (Ra) of the first metal layer may be between 300 nm and 500 nm. In addition, the maximum cross-sectional height value (Rt) of the first metal layer may be between 2 μm and 6 μm. For example, the maximum cross-sectional height value (Rt) of the first metal layer may be between 3 μm and 5 μm. In the embodiment, by controlling the centerline average roughness value (Ra) or the maximum cross-sectional height value (Rt) in correspondence with the thickness of the first metal layer, the anchoring effect can be further enhanced with increasing thickness of the first metal layer. Furthermore, in the embodiment, the plating thickness uniformity of the first metal layer can be improved by controlling the centerline average roughness value (Ra) and the maximum cross-sectional height value (Rt), and furthermore, when etching the first metal layer, a portion of the first metal layer is prevented from remaining on the surface of the insulating layer, thereby improving the electrical reliability of the circuit board and improving the yield of the circuit board.

[0281] The features, structures, effects, etc. described in the above-described embodiments are included in at least one embodiment of the present invention and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the present invention.

[0282] Furthermore, although the above description has focused on the embodiments, this is merely illustrative and does not limit the invention. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically shown in the embodiments may be modified and implemented. Differences related to such modifications and applications should be interpreted as being included within the scope of the invention as defined in the appended claims.

Claims

Claim 1 A circuit board comprising: an insulating layer comprising a modified epoxy or maleimide-based resin and a filler disposed within the resin; and a circuit pattern layer disposed on the insulating layer, wherein the insulating layer comprises a surface layer comprising fluorine (F) defined as an area of ​​a certain depth range on the upper and lower surfaces of the insulating layer, and the circuit pattern layer is disposed on the surface layer of the insulating layer, wherein the surface layer is formed by plasma treating the surface of the insulating layer with CF4, wherein the ratio of the element occupied by fluorine in the surface layer of the insulating layer before plasma treatment is 0%, and the ratio of the element occupied by fluorine in the surface layer of the insulating layer after plasma treatment is 10% to 50%. Claim 2 A circuit board according to claim 1, wherein the surface layer is a region with a depth range of 10 nm to 100 nm from the surface of the insulating layer. Claim 3 delete Claim 4 A circuit board according to claim 1 or 2, wherein the surface layer comprises a first portion adjacent to the upper surface of the insulating layer and a second portion adjacent to the lower surface of the insulating layer. Claim 5 A circuit board according to claim 1, wherein the circuit pattern layer comprises a first metal layer disposed on the surface layer of the insulating layer and a second metal layer disposed on the first metal layer. Claim 6 A circuit board according to claim 5, wherein the first metal layer is an electroless plating layer and the second metal layer is an electrolytic plating layer formed by the first metal layer as a seed layer. Claim 7 A circuit board according to claim 5 or 6, wherein the first metal layer has a thickness in the range of 1 μm to 2.5 μm. Claim 8 A circuit board according to claim 7, wherein at least one of the surface layers of the first metal layer and the insulating layer has a centerline average roughness value (Ra) satisfying a range between 200 nm and 600 nm. Claim 9 A circuit board according to claim 7, wherein at least one of the surface layer of the first metal layer and the insulating layer has a maximum cross-sectional height value (Rt) satisfying a range between 2㎛ and 6㎛. Claim 10 A circuit board according to claim 4, comprising a through electrode disposed within a through hole penetrating the insulating layer, wherein the surface layer of the insulating layer comprises a third portion formed on the inner wall of the through hole, and the through electrode comprises a third metal layer disposed on the third portion of the surface layer; and a fourth metal layer disposed on the third metal layer and filling the through hole. Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 A circuit board described in claim 10; and a package board comprising a chip mounted on a circuit pattern layer of said circuit board.

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