Circuit board

Abstract

A printed circuit board according to an embodiment comprises: an insulating layer; a first circuit pattern disposed on a first surface of the insulating layer; and a first solder resist disposed on the first surface of the insulating layer; The first barrier layer comprises a first-1 portion disposed between the first solder resist and the first circuit pattern, and a first-2 portion disposed between the insulating layer and the first circuit pattern, wherein the first-1 portion of the first barrier layer comprises a first-1 gold (Au) layer disposed on the lower surface of the first circuit pattern and a first-1 palladium (Pd) layer disposed on the lower surface of the first-1 gold (Au) layer, and the first-2 portion of the first barrier layer comprises a first-2 gold (Au) layer disposed surrounding the side and upper surfaces of the first circuit pattern and a first-2 palladium (Pd) layer disposed surrounding the first-2 gold (Au) layer, and the first circuit pattern does not come into contact with the first solder resist and the insulating layer by the first-1 portion and the first-2 portion of the first barrier layer.

Description

Technology Field

[0001] The embodiment relates to a printed circuit board and a method for manufacturing the same. Background Technology

[0002] As the miniaturization, lightweighting, and integration of electronic components accelerate, circuit linewidths are becoming finer. In particular, as semiconductor chip design rules are integrated to the nanometer scale, the circuit linewidths of package substrates or printed circuit boards on which semiconductor chips are mounted are being reduced to a few micrometers or less.

[0003] Various processes have been proposed to increase the circuit integration density of printed circuit boards, that is, to miniaturize the circuit line width. For the purpose of preventing loss of circuit line width during the etching step to form a pattern after copper plating, the semi-additive process (SAP) and modified semi-additive process (MSAP) have been proposed.

[0004] Subsequently, the Embedded Trace Substrate (hereinafter referred to as 'ETS') method, in which copper foil is embedded within an insulating layer to implement finer circuit patterns, is being used in the industry. The ETS method is advantageous for miniaturizing circuit pitch because, instead of forming the copper foil circuit on the surface of the insulating layer, it is manufactured in an embedded form within the insulating layer, thereby eliminating circuit loss due to etching.

[0005] Meanwhile, to meet the recent demand for wireless data traffic, improved 5G (5 th Efforts are being made to develop a 5G communication system or a pre-5G communication system. Here, 5G communication systems use ultra-high frequency (mmWave) bands (sub 6 GHz, 28 GHz, 38 GHz, or higher frequencies) to achieve high data transmission rates.

[0006] In addition, to mitigate path loss and increase the transmission distance of radio waves in the ultra-high frequency band, aggregation technologies such as beamforming, massive MIMO, and array antennas are being developed in 5G communication systems. Considering that these frequency bands can consist of hundreds of active antennas, the antenna system becomes relatively large.

[0007] Since these antennas and AP modules are patterned or mounted on printed circuit boards, low loss of the board is critical. This means that the multiple boards constituting the active antenna system—namely, the antenna board, antenna feed board, transceiver board, and baseband board—must be integrated into a single compact unit.

[0008] In addition, printed circuit boards applied to 5G communication systems as described above are manufactured according to the trend of miniaturization, and accordingly, circuit patterns are becoming increasingly finer.

[0009] However, in conventional printed circuit boards containing fine circuit patterns, the pitch between patterns becomes increasingly smaller, causing the spacing between patterns to narrow, and consequently, reliability problems arise. Specifically, in conventional printed circuit boards, migration of copper, a metallic material constituting the circuit pattern, occurs during reliability evaluation, and reliability problems arise as a result. The problem to be solved

[0010] In the embodiments, a printed circuit board of a new structure and a method for manufacturing the same are provided.

[0011] In addition, the embodiment provides a printed circuit board capable of suppressing the phenomenon in which a metal material constituting a circuit pattern migrates to an insulating layer, and a method for manufacturing the same.

[0012] In addition, the embodiment provides a printed circuit board capable of suppressing the phenomenon in which a metal material constituting a circuit pattern migrates to a solder resist, and a method for manufacturing the same.

[0013] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the proposed embodiments belong from the description below. means of solving the problem

[0014] A circuit board according to an embodiment comprises an insulating layer having via holes penetrating the upper and lower surfaces; a first penetrating via disposed within the via holes of the insulating layer; and a second penetrating via disposed between the inner wall of the via holes of the insulating layer and the side of the penetrating via, wherein the second penetrating via has a width in a different horizontal direction from the upper surface of the insulating layer toward the lower surface of the insulating layer.

[0015] In addition, the insulating layer includes glass.

[0016] In addition, the first penetrating via and the second penetrating via contain different materials.

[0017] In addition, the first through-via contains copper.

[0018] In addition, the width of the second through-via in the horizontal direction decreases toward the lower surface of the insulating layer.

[0019] Additionally, the second through-via includes a first part disposed on the inner wall of the via hole, and a second part disposed between the first part and the side of the first through-via.

[0020] In addition, the width of the first through-via in the horizontal direction decreases toward the lower surface of the insulating layer.

[0021] In addition, the width of each of the first and second parts of the second through-via in the horizontal direction decreases toward the lower surface of the insulating layer.

[0022] In addition, the second through via has a slope in which the width in the horizontal direction gradually decreases from the upper surface of the insulating layer toward the lower surface of the insulating layer.

[0023] In addition, the first through via has a slope in which the width in the horizontal direction gradually decreases from the upper surface of the insulating layer toward the lower surface of the insulating layer.

[0024] In addition, the side of the first penetrating via and the side of the second penetrating via have the same slope.

[0025] Additionally, it further includes an upper circuit layer disposed on the upper surface of the first through-via and the second through-via; and a lower circuit layer disposed on the lower surface of the first through-via and the second through-via. Effects of the invention

[0026] In an embodiment, a printed circuit board comprising an insulating layer and a circuit pattern is provided. In this case, the circuit pattern is formed from a metallic material containing copper. In this case, the circuit pattern formed from the metallic material containing copper does not come into direct contact with the insulating layer. To this end, a barrier layer is disposed around the circuit pattern. For example, in an embodiment, a gold metal layer containing gold (Au) is disposed surrounding the circuit pattern, and a palladium metal layer containing palladium (Pd) is disposed surrounding the gold metal layer. The palladium metal layer can prevent copper constituting the circuit pattern from penetrating toward the insulating layer, thereby suppressing copper migration and improving reliability. Additionally, the gold metal layer is disposed between the palladium metal layer and the circuit pattern to form the palladium metal layer. In this case, the gold metal layer contains gold (Au) with a grain size larger than that of other layers, which has the effect of stably forming the palladium metal layer.

[0027] In addition, in the embodiment, a barrier layer as described above is formed for the circuit pattern disposed on the outermost layer among the circuit patterns. This can prevent the copper constituting the circuit pattern on the outermost layer from migrating to the solder resist.

[0028] In addition, in the embodiment, a portion of the barrier layer is disposed over the surface of the embedded pattern in the ETS structure. At this time, the barrier layer is disposed protruding over the surface of the embedded pattern, and this can function as a mounting pad on which a solder layer for device mounting is disposed. That is, in the ETS structure, conventionally, since the embedded pattern is formed as a fine pattern, a simple pattern alone could not function as a mounting pad; consequently, a separate mounting pad had to be formed with a structure that is embedded inside the insulating layer or protrudes over the surface of the insulating layer. In this case, when the mounting pad is embedded inside the insulating layer, the spacing of the fine pattern due to the width of the mounting pad widens, and consequently, there were problems with circuit integration density. Furthermore, in the case where the mounting pad is structured to protrude outside the insulating layer, a separate process had to be performed to form it. In contrast, in the embodiment, when forming the barrier layer on the embedded pattern, a portion of the barrier layer has a structure that protrudes over the surface of the insulating layer, and accordingly, the barrier layer can be utilized as a mounting pad, thereby simplifying the manufacturing process. Brief explanation of the drawing

[0029] FIG. 1 is a drawing showing a printed circuit board according to an embodiment. FIG. 2 is a drawing showing a printed circuit board including vias according to an embodiment. FIGS. 3 to 15 are drawings showing the manufacturing method of the printed circuit board illustrated in FIG. 1 in process order. Specific details for implementing the invention

[0030] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0031] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0032] Furthermore, terms used in the embodiments of the present invention (including technical and scientific terms) may be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Terms commonly used, such as those defined in advance, may be interpreted by considering their meaning in the context of the relevant technology. Additionally, the terms used in the embodiments of the present invention are intended to describe the embodiments and are not intended to limit the present invention.

[0033] In this specification, the singular form may include the plural form unless specifically stated otherwise in the text, and when described as "at least one of A and B and C (or more than one)," it may include one or more of all combinations that can be formed from A, B, and C. Additionally, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the embodiments of the present invention.

[0034] These terms are intended only to distinguish a component from another component and are not limited by the nature, order, or sequence of the component. Furthermore, where it is stated that a component is 'connected,' 'combined,' or 'connected' to another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component.

[0035] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0036] FIG. 1 is a drawing showing a printed circuit board according to an embodiment.

[0037] Prior to describing the present invention, with the recent advancement of 5G technology, interest in printed circuit boards capable of reflecting this technology is increasing. At this time, for 5G technology to be applied, the printed circuit board must have a high multilayer structure, and the circuit patterns must be miniaturized accordingly. However, in comparative examples, while it is possible to form fine patterns, there is a problem in that they cannot be reliably protected. For example, the circuit patterns applied to printed circuit boards for 5G are becoming narrower in line width, and consequently, the spacing between patterns is becoming narrower. However, in the conventional method, although it is possible to form fine patterns, the migration of copper, a metallic material constituting the fine patterns, cannot be suppressed, and thus there are reliability issues. Accordingly, the embodiment provides a printed circuit board with a new structure capable of solving these reliability problems.

[0038] Specifically, referring to FIG. 1, the printed circuit board includes an insulating layer (140), a first circuit pattern (130), a first barrier layer (120, 130), a second circuit pattern (160), a second barrier layer (150, 170), a first protective layer (180), and a second protective layer (185).

[0039] Prior to the description of FIG. 1, the printed circuit board according to the embodiment may have a multilayer structure based on the insulating layer. That is, although the printed circuit board in FIG. 1 is illustrated as including a single insulating layer, the embodiment is not limited thereto. For example, the printed circuit board in the embodiment may include a plurality of insulating layers. In this case, the first circuit pattern (130) shown in FIG. 1 may represent a first outer layer circuit pattern embedded within the first outermost insulating layer among the plurality of insulating layers. Additionally, the second circuit pattern (160) shown in FIG. 1 may represent a second outer layer circuit pattern protruding above the surface of the second outermost insulating layer among the plurality of insulating layers.

[0040] The insulating layer (140) may represent a specific layer of any one of the multiple laminated structures. The insulating layer (140) may include a substrate on which an electrical circuit capable of changing wiring is organized, and may include a printed circuit board and an insulating substrate made of an insulating material capable of forming circuit patterns on its surface.

[0041] For example, the insulating layer (140) may be rigid or flexible. For example, the insulating layer (140) may include glass or plastic. Specifically, the insulating layer (140) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or sapphire.

[0042] Additionally, the insulating layer (140) may include an optically isotropic film. For example, the insulating layer (140) may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0043] Additionally, the insulating layer (140) may be partially curved. That is, the insulating layer (140) may be partially flat and partially curved. Specifically, the insulating layer (140) may be bent or bent with a curved end or a surface including random curvature.

[0044] Additionally, the insulating layer (140) may be a flexible substrate having flexible properties. Additionally, the insulating layer (140) may be a curved or bent substrate. In this case, the insulating layer (140) may represent electrical wiring connecting circuit components based on a circuit design as a wiring pattern and reproduce an electrical conductor on the insulating material. Additionally, the insulating layer (140) may mount electrical components and form wiring that connects them circuitously, and may mechanically fix components other than the electrical connection function of the components.

[0045] A circuit pattern can be placed on the surface of the insulating layer (140).

[0046] For example, a first circuit pattern (130) may be placed on the lower surface of the insulating layer (140).

[0047] Additionally, a second circuit pattern (160) may be disposed on the upper surface of the insulating layer (140).

[0048] The first circuit pattern (130) may be formed by being embedded in the lower part of the insulating layer (140). The side of the first circuit pattern (130) may be surrounded by the insulating layer (140). However, the side of the first circuit pattern (130) may not come into contact with the insulating layer (140). That is, the first-2 portion (120) of the first barrier layer may be located between the side of the first circuit pattern (130) and the insulating layer (140). Accordingly, the side of the first circuit pattern (130) may be spaced apart from the insulating layer (140) by the thickness of the first-2 portion (120) of the first barrier layer.

[0049] Additionally, the upper surface of the first circuit pattern (130) may be located within the insulating layer (140). Clearly, the upper surface of the first circuit pattern (130) may be located higher than the lower surface of the insulating layer (140). Meanwhile, the upper surface of the first circuit pattern (130) may not be in contact with the insulating layer (140). That is, the first-second portion (120) of the first barrier layer may be located between the upper surface of the first circuit pattern (130) and the insulating layer (140). Accordingly, the upper surface of the first circuit pattern (130) may be spaced apart from the insulating layer (140) by the thickness of the first-second portion (120) of the first barrier layer.

[0050] The lower surface of the first circuit pattern (130) may be located on the same plane as the lower surface of the insulating layer (140).

[0051] As described above, the upper surface, lower surface, and side surface of the first circuit pattern (130) do not come into contact with the insulating layer (140). Accordingly, in the embodiment, the problem of the metal material constituting the first circuit pattern (130) migrating to the insulating layer (140) can be solved.

[0052] That is, the first circuit pattern (130) is embedded and disposed in the lower part of the insulating layer (140), but may not come into direct contact with the insulating layer (140) by the first-second portion (120) of the first barrier layer. That is, the first-second portion (120) of the first barrier layer may be located between the side and top surfaces of the first circuit pattern (130) and the insulating layer (140). Accordingly, the side and top surfaces of the first circuit pattern (130) may be spaced apart from the insulating layer (140) by the thickness of the first-second portion (120) of the first barrier layer.

[0053] The second circuit pattern (160) is positioned protruding above the upper surface of the insulating layer (140). At this time, the second circuit pattern (160) may not come into contact with the insulating layer (140). That is, the lower surface of the second circuit pattern (160) may be positioned at a certain distance from the upper surface of the insulating layer (140). That is, the lower surface of the second circuit pattern (160) may be positioned higher than the upper surface of the insulating layer (140). Specifically, the second-1 portion (150) of the second barrier layer may be positioned between the lower surface of the first circuit pattern (130) and the upper surface of the insulating layer (140). Accordingly, the lower surface of the second circuit pattern (160) may be spaced apart from the insulating layer (140) by the thickness of the second-1 portion (150) of the second barrier layer.

[0054] That is, the second circuit pattern (160) is positioned on the upper surface of the insulating layer (140), but may not come into direct contact with the insulating layer (140) due to the second-1 portion (150) of the second barrier layer. That is, the second-1 portion (150) of the second barrier layer may be located between the lower surface of the second circuit pattern (160) and the upper surface of the insulating layer (140). Accordingly, the lower surface of the second circuit pattern (160) may be spaced apart from the insulating layer (140) by the thickness of the first portion of the second barrier layer.

[0055] The first circuit pattern (130) and the second circuit pattern (160) described above are wirings that transmit electrical signals and can be formed from a metal material with high electrical conductivity. Preferably, the first circuit pattern (130) and the second circuit pattern (160) can be formed from copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0056] In addition, as the first circuit pattern (130) and the second circuit pattern (160) are formed of copper, migration of copper ions into the insulating layer (140) may occur. At this time, a first barrier layer is disposed between the first circuit pattern (130) and the insulating layer (140) in the embodiment. Additionally, a second barrier layer is disposed between the second circuit pattern (160) and the insulating layer (140) in the embodiment. Accordingly, in the embodiment, migration of copper ions into the insulating layer (140) can be prevented, and the reliability of the fine pattern can be improved.

[0057] Meanwhile, a first protective layer (180) is disposed on the lower surface of the insulating layer (140). Additionally, a second protective layer (185) is disposed on the upper surface of the insulating layer (140).

[0058] The first protective layer (180) and the second protective layer (182) may be formed into at least one layer using one or more of SR (Solder Resist), oxide, and Au. Preferably, the first protective layer (180) and the second protective layer (185) may be solder resist.

[0059] The first protective layer (180) is disposed on the lower surface of the insulating layer (140) to protect the first circuit pattern (130).

[0060] For example, the first protective layer (180) can protect the lower surface of the first circuit pattern (130). In this case, the first circuit pattern (130) may not come into direct contact with the first circuit pattern (130).

[0061] The second protective layer (185) may be positioned to cover the second circuit pattern (160). That is, the side of the second circuit pattern (160) may be surrounded by the second protective layer (185). However, the side of the second circuit pattern (160) may not come into contact with the second protective layer (185). That is, a second-2 portion (170) of the second barrier layer may be located between the side of the second circuit pattern (160) and the second protective layer (185). Accordingly, the side of the second circuit pattern (160) may be spaced apart from the second protective layer (185) by the thickness of the second-2 portion (170) of the second barrier layer.

[0062] Additionally, at least a portion of the upper side of the second circuit pattern (160) may be covered by the second protective layer (185). That is, the upper surface of the second circuit pattern (160) may be positioned lower than the upper surface of the second protective layer (185). In this case, the upper surface of the second circuit pattern (160) may not come into contact with the second protective layer (185). That is, the second-2 portion (170) of the second barrier layer may be located between the upper surface of the second circuit pattern (160) and the second protective layer (185). Accordingly, the upper surface of the second circuit pattern (160) may be spaced apart from the second protective layer (185) by the thickness of the second-2 portion (170) of the second barrier layer.

[0063] The lower surface of the second circuit pattern (160) may be positioned higher than the upper surface of the insulating layer (140) and higher than the lower surface of the second protective layer (185).

[0064] As described above, the upper, lower, and side surfaces of the second circuit pattern (160) do not come into contact with the insulating layer (140) and the second protective layer (185). Accordingly, in the embodiment, the problem of copper ions constituting the second circuit pattern (160) migrating to the second protective layer (185) can be resolved.

[0065] That is, the second circuit pattern (160) protrudes over the upper surface of the insulating layer (140) and is covered by the second protective layer (185), but may not come into direct contact with the second protective layer (185) by the second-2 portion (170) of the second barrier layer. That is, the second-2 portion (170) of the second barrier layer may be located between the side and upper surface of the second circuit pattern (160) and the second protective layer (185). Accordingly, the side and upper surface of the second circuit pattern (160) may be spaced apart from the second protective layer (185) by the thickness of the second-2 portion (170) of the second barrier layer.

[0067] Below, the first barrier layer and the second barrier layer will be described.

[0068] The first barrier layer may be disposed between the first circuit pattern (130) and the insulating layer (140). Additionally, the first barrier layer may be disposed between the first circuit pattern (130) and the first protective layer (180).

[0069] Specifically, the first barrier layer includes a first-1 portion (110) disposed between the first circuit pattern (130) and the first protection layer (180). Additionally, the first barrier layer includes a first-2 portion (120) disposed between the first circuit pattern (130) and the insulating layer (140).

[0070] The first-1 portion (110) and the first-2 portion (120) of the first barrier layer may each be composed of a plurality of layers.

[0071] That is, the first-1 portion (110) of the first barrier layer includes a first-1 metal layer (111). The first-1 metal layer (111) may be formed of a metallic material including palladium (Pd). The first-1 metal layer (111) may function to prevent copper ions constituting the first circuit pattern (130) from migrating to the first protective layer (180).

[0072] Additionally, the first-1 portion (110) of the first barrier layer includes a first-2 metal layer (112) disposed between the lower surface of the first circuit pattern (130) and the first-1 metal layer (111). The first-2 metal layer (112) may be a seed layer of the first-1 metal layer (111). Furthermore, the first-2 metal layer (112) may function to primarily block the migration of copper ions constituting the first circuit pattern (130). Accordingly, in the embodiment, the first-2 metal layer (112) is formed between the first circuit pattern (130) and the first-1 metal layer (111) using gold (Au) with a relatively large grain size. At this time, the first-1 metal layer (111) may be referred to as the first-1 palladium layer. In addition, the first-2 metal layer (112) can be called the first-1 gold layer.

[0073] The first-second metal layer (112) may be disposed with a first width below the lower surface of the first circuit pattern (130). At this time, the first width of the first-second metal layer (112) may be larger than the second width of the lower surface of the first circuit pattern (130). Accordingly, the first circuit pattern (130) may not come into contact with the first protective layer (180).

[0074] The first-1 metal layer (111) can be disposed below the lower surface of the first-2 metal layer (112) having a first width equal to that of the first-2 metal layer (112).

[0075] That is, the first-2 portion (120) of the first barrier layer includes a second-1 metal layer (121). The second-1 metal layer (121) may be formed from a metallic material including palladium (Pd). The second-1 metal layer (111) may function to prevent copper ions constituting the first circuit pattern (130) from migrating to the insulating layer (140).

[0076] Additionally, the first-2 portion (120) of the first barrier layer includes a second-2 metal layer (122) disposed between the side and top surfaces of the first circuit pattern (130) and the second-1 metal layer (121). The second-2 metal layer (122) may be a seed layer of the second-1 metal layer (121).

[0077] Accordingly, in the embodiment, a second-2 metal layer (122) composed of a metal including gold (Au) with a relatively large grain size is formed on the side and top surfaces of the first circuit pattern (130). Then, the second-1 metal layer (121) can be formed by plating the second-2 metal layer (122) as a seed layer. At this time, the second-1 metal layer (121) can be referred to as a first-2 palladium layer. Also, the second-2 metal layer (122) can be referred to as a first-2 gold layer.

[0078] The second-2 metal layer (122) may be arranged to surround the side and top surfaces of the first circuit pattern (130). Additionally, the second-1 metal layer (121) may be arranged to surround the second-2 metal layer (122).

[0079] Meanwhile, the upper surface of the first-2 metal layer (112) may include a first region that contacts the lower surface of the first circuit pattern (130). Additionally, the upper surface of the first-2 metal layer (112) may include a second region that contacts the second-1 metal layer (121). Furthermore, the upper surface of the first-2 metal layer (112) may include a third region that contacts the second-2 metal layer (122). Accordingly, the first-1 metal layer (111) in the embodiment may not contact the first circuit pattern (130), the second-1 metal layer (121), and the second-2 metal layer (122).

[0080] The second barrier layer may be disposed between the second circuit pattern (160) and the insulating layer (140). Additionally, the second barrier layer may be disposed between the second circuit pattern (160) and the second protection layer (185).

[0081] Specifically, the second barrier layer includes a second-1 portion (150) disposed between the second circuit pattern (160) and the insulating layer (140). Additionally, the second barrier layer includes a second-2 portion (170) disposed between the second circuit pattern (160) and the second protective layer (185).

[0082] The 2-1 portion (150) and 2-2 portion (170) of the second barrier layer may each be composed of a plurality of layers.

[0083] That is, the second-1 portion (150) of the second barrier layer includes a third-1 metal layer (151). The third-1 metal layer (151) may be formed from a metallic material including palladium (Pd). The third-1 metal layer (151) may function to prevent copper ions constituting the second circuit pattern (160) from migrating to the insulating layer (140).

[0084] Additionally, the second-1 portion (150) of the second barrier layer includes a third-2 metal layer (152) disposed between the lower surface of the second circuit pattern (160) and the third-1 metal layer (151). The third-2 metal layer (152) may be a seed layer of the third-1 metal layer (151). Accordingly, in the embodiment, a third-2 metal layer (152) containing gold (Au) with a relatively large grain size is formed on the lower surface of the second circuit pattern (160). Furthermore, the third-1 metal layer (151) may be formed by plating the third-2 metal layer (152) as a seed layer. At this time, the third-1 metal layer (151) may be referred to as a second-1 palladium layer. Additionally, the third-2 metal layer (152) may be referred to as a second-1 gold layer.

[0085] The above third-2 metal layer (152) may be disposed with a first width below the lower surface of the second circuit pattern (160). At this time, the first width of the third-2 metal layer (152) may be larger than the second width of the lower surface of the second circuit pattern (160). Accordingly, the second circuit pattern (160) may not come into contact with the insulating layer (140).

[0086] The above 3-1 metal layer (151) can be disposed below the lower surface of the above 3-2 metal layer (152) having a first width equal to that of the above 3-2 metal layer (152).

[0087] That is, the second-2 portion (170) of the second barrier layer includes a fourth-1 metal layer (171). The fourth-1 metal layer (171) may be formed from a metallic material including palladium (Pd). The second-1 metal layer (111) may function to prevent copper ions constituting the second circuit pattern (160) from migrating to the second protective layer (185).

[0088] Additionally, the second-2 portion (170) of the second barrier layer includes a fourth-2 metal layer (172) disposed between the side and top surfaces of the second circuit pattern (160) and the fourth-1 metal layer (171). The fourth-2 metal layer (172) may be a seed layer of the fourth-1 metal layer (171). In an embodiment, a fourth-2 metal layer (172) containing gold (Au) with a relatively large grain size is formed on the side and top surfaces of the second circuit pattern (160). Furthermore, the fourth-1 metal layer (171) may be formed by plating the fourth-2 metal layer (172) as a seed layer. At this time, the fourth-1 metal layer (171) may be referred to as a second-2 palladium layer. Additionally, the fourth-2 metal layer (172) may be referred to as a second-2 gold layer.

[0089] The above 4-2 metal layer (172) may be arranged to surround the side and top surfaces of the above 2 circuit pattern (160). Additionally, the above 4-1 metal layer (171) may be arranged to surround the above 4-2 metal layer (172).

[0090] Meanwhile, the upper surface of the third-2 metal layer (152) may include a first region that contacts the lower surface of the second circuit pattern (160). Additionally, the upper surface of the third-2 metal layer (152) may include a second region that contacts the fourth-1 metal layer (171). Furthermore, the upper surface of the third-2 metal layer (152) may include a third region that contacts the fourth-2 metal layer (172). Accordingly, the third-1 metal layer (151) in the embodiment may not contact the second circuit pattern (160), the fourth-1 metal layer (171), and the fourth-2 metal layer (172).

[0091] In the above embodiment, a printed circuit board comprising an insulating layer and a circuit pattern is provided. At this time, the circuit pattern is formed from a metallic material containing copper. At this time, the circuit pattern formed from the metallic material containing copper does not come into direct contact with the insulating layer. To this end, a barrier layer is disposed around the circuit pattern. For example, in the embodiment, a gold metal layer containing gold (Au) is disposed surrounding the circuit pattern, and a palladium metal layer containing palladium (Pd) is disposed surrounding the gold metal layer. The palladium metal layer can prevent copper constituting the circuit pattern from penetrating toward the insulating layer, thereby suppressing copper migration and improving reliability. Additionally, the gold metal layer is disposed between the palladium metal layer and the circuit pattern to form the palladium metal layer. At this time, the gold metal layer contains gold (Au) with a grain size larger than that of other layers, and accordingly, this brings about the effect of stably forming the palladium metal layer.

[0092] In addition, in the embodiment, a barrier layer as described above is formed for the circuit pattern disposed on the outermost layer among the circuit patterns. This can prevent the copper constituting the circuit pattern on the outermost layer from migrating to the solder resist.

[0093] In addition, in the embodiment, a portion of the barrier layer is disposed over the surface of the embedded pattern in the ETS structure. At this time, the barrier layer is disposed protruding over the surface of the embedded pattern, and this can function as a mounting pad on which a solder layer for device mounting is disposed. That is, in the ETS structure, conventionally, since the embedded pattern is formed as a fine pattern, a simple pattern alone could not function as a mounting pad; consequently, a separate mounting pad had to be formed with a structure that is embedded inside the insulating layer or protrudes over the surface of the insulating layer. In this case, when the mounting pad is embedded inside the insulating layer, the spacing of the fine pattern due to the width of the mounting pad widens, and consequently, there were problems with circuit integration density. Furthermore, in the case where the mounting pad is structured to protrude outside the insulating layer, a separate process had to be performed to form it. In contrast, in the embodiment, when forming the barrier layer on the embedded pattern, a portion of the barrier layer has a structure that protrudes over the surface of the insulating layer, and accordingly, the barrier layer can be utilized as a mounting pad, thereby simplifying the manufacturing process.

[0095] FIG. 2 is a drawing showing a printed circuit board including vias according to an embodiment.

[0096] Meanwhile, although only the circuit pattern is described in FIG. 1, the printed circuit board (100A) in the embodiment may include vias (190) disposed within the insulating layer (140).

[0097] Referring to FIG. 2, the via (190) can be formed by penetrating the insulating layer (140). Specifically, the via (190) can electrically connect the first circuit pattern (130) and the second circuit pattern (160). At this time, the via (190) can be formed from a metallic material including copper. Accordingly, copper ions constituting the via (190) can migrate to the insulating layer (140). Thus, the via (190) in the embodiment can have a three-layer structure in the horizontal direction. That is, the via (190) can be formed by plating a metallic material within a via hole (not shown) penetrating the insulating layer (140).

[0098] At this time, in the embodiment, when a via hole is formed, a 5-1 metal layer (191) is preferentially formed on the inner wall of the via hole. The 5-1 metal layer (191) may be formed of a metal including palladium.

[0099] Additionally, the via (190) may include a 5-2 metal layer (192) formed on the inner surface of the 5-1 metal layer (191). The 5-2 metal layer (192) may include gold.

[0100] Additionally, the via (190) may include a fifth-third metal layer (193). The fifth-third metal layer (193) may include copper. The fifth-third metal layer (193) may be formed to fill the interior of the via hole. That is, in the embodiment, the interior of the via hole is not filled using only the fifth-third metal layer (193), but the fifth-third metal layer (193) is formed after the fifth-first metal layer (191) and the fifth-second metal layer (192) are formed. Accordingly, copper ions constituting the fifth-third metal layer (193) can be prevented from migrating to the insulating layer (140).

[0102] Hereinafter, a method for manufacturing a printed circuit board according to an embodiment will be described. FIGS. 3 to 15 are drawings showing the method for manufacturing a printed circuit board illustrated in FIG. 1 in the order of processes.

[0103] Referring to FIG. 3, a carrier board (210), which is a base material, is prepared for manufacturing a printed circuit board. The carrier board (210) may include an insulating member (211) and a metal layer (212) disposed on the insulating member (211).

[0104] At this time, although the drawing shows the metal layer (212) being disposed on only one side of the insulating member (211), it is not limited thereto. That is, the metal layer (212) can be disposed on both sides of the insulating member (211), and accordingly, a plurality of printed circuit boards can be manufactured simultaneously on both sides of the insulating member (211).

[0105] Next, referring to FIG. 4, a first-1 portion (110) constituting a first barrier layer is formed on the carrier board (210).

[0106] That is, the first-1 portion (110) of the first barrier layer comprises a first-1 metal layer (111) disposed on the carrier board (210) and a first-2 metal layer (112) disposed on the first-1 metal layer (111).

[0107] The first-1 metal layer (111) may contain palladium. Additionally, the first-2 metal layer (112) may contain gold. The first-1 metal layer (111) and the first-2 metal layer (112) may be formed through a chemical copper plating process.

[0108] Next, referring to FIG. 5, in the embodiment, a first mask (M1) is formed on the first-1 portion (110) of the first barrier layer. The first mask (M1) may include an opening (not shown) that exposes an area where a first circuit pattern (130) is to be formed.

[0109] In addition, in the embodiment, the first portion of the first barrier layer is plated as a seed layer to form a first circuit pattern (130) that fills the opening of the first mask (M1).

[0110] Next, referring to FIG. 6, in the embodiment, the first mask (M1) is removed and a second mask (M2) is formed on the first-1 portion (110) of the first barrier layer. The second mask (M2) may include an opening (not shown) that exposes an area where a second-2 metal layer (122) is to be formed in the first-2 portion (120) of the first barrier layer.

[0111] In addition, in the embodiment, the first-1 portion (110) of the first barrier layer is plated as a seed layer to form a second-2 metal layer (122) that fills the opening of the second mask (M2).

[0112] Next, referring to FIG. 7, in the embodiment, the second mask (M2) is removed and a third mask (M3) is formed on the first-1 portion (110) of the first barrier layer. The third mask (M3) may include an opening (not shown) that exposes the area where the second-1 metal layer (121) is to be formed in the first-2 portion (120) of the first barrier layer.

[0113] In addition, in the embodiment, the first-1 portion (110) of the first barrier layer is plated as a seed layer to form a second-1 metal layer (121) that fills the opening of the third mask (M3).

[0114] Next, referring to FIG. 8, in the embodiment, an insulating layer (140) covering the first circuit pattern (130) is formed on the first barrier layer.

[0115] The insulating layer (140) may be rigid or flexible. For example, the insulating layer (140) may include glass or plastic. Specifically, the insulating layer (140) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or sapphire.

[0116] Additionally, the insulating layer (140) may include an optically isotropic film. For example, the insulating layer (140) may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0117] Additionally, the insulating layer (140) may be partially curved. That is, the insulating layer (140) may be partially flat and partially curved. Specifically, the insulating layer (140) may be bent or bent with a curved end or a surface including random curvature.

[0118] Additionally, the insulating layer (140) may be a flexible substrate having flexible properties. Additionally, the insulating layer (140) may be a curved or bent substrate. In this case, the insulating layer (140) may represent electrical wiring connecting circuit components based on a circuit design as a wiring pattern and reproduce an electrical conductor on the insulating material. Additionally, the insulating layer (140) may mount electrical components and form wiring that connects them circuitously, and may mechanically fix components other than the electrical connection function of the components.

[0119] Next, referring to FIG. 9, a second-1 portion (150) constituting a second barrier layer is formed on the insulating layer (140).

[0120] That is, the second-1 portion (150) of the second barrier layer comprises a third-1 metal layer (151) disposed on the insulating layer (140) and a third-2 metal layer (152) disposed on the third-1 metal layer (151).

[0121] The above 3-1 metal layer (151) may include palladium. Additionally, the 3-2 metal layer (152) may include gold. The 3-1 metal layer (151) and the 3-2 metal layer (152) may be formed through a chemical copper plating process.

[0122] Next, referring to FIG. 10, the process of FIG. 5 to FIG. 7 is sequentially repeated to form a second circuit pattern (160) on the second-1 portion (150) of the second barrier layer and to form a second-2 portion (170) of the second barrier layer on the second circuit pattern (160). The second-2 portion (170) of the second barrier layer includes a fourth-1 metal layer (171) and a fourth-2 metal layer (172).

[0123] Next, referring to FIG. 11, in the embodiment, a process of removing a portion of the 2-1 portion (150) of the second barrier layer can be performed.

[0124] Next, referring to FIG. 12, in the embodiment, the process of removing the carrier board (210) can be carried out.

[0125] Next, referring to FIG. 13, in the embodiment, a process of removing a portion of the first-1 portion (110) of the first barrier layer can be performed.

[0126] Next, referring to FIG. 14, in the embodiment, a process of forming a first protective layer (180) on the lower surface of an insulating layer (140) and forming a second protective layer (185) on the upper surface of the insulating layer (140) can be carried out.

[0127] That is, a first protective layer (180) is disposed on the lower surface of the insulating layer (140). In addition, a second protective layer (185) is disposed on the upper surface of the insulating layer (140).

[0128] The first protective layer (180) and the second protective layer (182) may be formed into at least one layer using one or more of SR (Solder Resist), oxide, and Au. Preferably, the first protective layer (180) and the second protective layer (185) may be solder resist.

[0129] The first protective layer (180) is disposed on the lower surface of the insulating layer (140) to protect the first circuit pattern (130).

[0130] For example, the first protective layer (180) can protect the lower surface of the first circuit pattern (130). In this case, the first circuit pattern (130) may not be in direct contact with the first circuit pattern (130). The second protective layer (185) may be placed to cover the second circuit pattern (160). That is, the side of the second circuit pattern (160) may be surrounded by the second protective layer (185). However, the side of the second circuit pattern (160) may not be in contact with the second protective layer (185). That is, the second-2 portion (170) of the second barrier layer may be located between the side of the second circuit pattern (160) and the second protective layer (185). Accordingly, the side of the second circuit pattern (160) can be spaced apart from the second protective layer (185) by the thickness of the second-2 portion (170) of the second barrier layer.

[0131] Additionally, at least a portion of the upper side of the second circuit pattern (160) may be covered by the second protective layer (185). That is, the upper surface of the second circuit pattern (160) may be positioned lower than the upper surface of the second protective layer (185). In this case, the upper surface of the second circuit pattern (160) may not come into contact with the second protective layer (185). That is, the second-2 portion (170) of the second barrier layer may be located between the upper surface of the second circuit pattern (160) and the second protective layer (185). Accordingly, the upper surface of the second circuit pattern (160) may be spaced apart from the second protective layer (185) by the thickness of the second-2 portion (170) of the second barrier layer.

[0132] The lower surface of the second circuit pattern (160) may be positioned higher than the upper surface of the insulating layer (140) and higher than the lower surface of the second protective layer (185).

[0133] As described above, the upper, lower, and side surfaces of the second circuit pattern (160) do not come into contact with the insulating layer (140) and the second protective layer (185). Accordingly, in the embodiment, the problem of copper ions constituting the second circuit pattern (160) migrating to the second protective layer (185) can be resolved.

[0134] That is, the second circuit pattern (160) protrudes over the upper surface of the insulating layer (140) and is covered by the second protective layer (185), but may not come into direct contact with the second protective layer (185) by the second-2 portion (170) of the second barrier layer. That is, the second-2 portion (170) of the second barrier layer may be located between the side and upper surface of the second circuit pattern (160) and the second protective layer (185). Accordingly, the side and upper surface of the second circuit pattern (160) may be spaced apart from the second protective layer (185) by the thickness of the second-2 portion (170) of the second barrier layer.

[0135] Meanwhile, referring to FIG. 15, the first protective layer (180A) in another embodiment may include an opening (not shown) that exposes a part of the first-1 portion (110) of the first barrier layer.

[0136] Additionally, in another embodiment, the second protective layer (185A) may include an opening that exposes a portion of the second-2 portion (170) of the second barrier layer.

[0137] Accordingly, in the embodiment, a first barrier layer surrounding the first circuit pattern (130) and a second barrier layer surrounding the second circuit pattern (160) can be formed.

[0138] Specifically, the first barrier layer may be disposed between the first circuit pattern (130) and the insulating layer (140). Additionally, the first barrier layer may be disposed between the first circuit pattern (130) and the first protective layer (180). Specifically, the first barrier layer includes a first-1 portion (110) disposed between the first circuit pattern (130) and the first protective layer (180). Additionally, the first barrier layer includes a first-2 portion (120) disposed between the first circuit pattern (130) and the insulating layer (140). The first-1 portion (110) and the first-2 portion (120) of the first barrier layer may each be composed of a plurality of layers. That is, the first-1 portion (110) of the first barrier layer includes a first-1 metal layer (111). The first-1 metal layer (111) may be formed of a metallic material including palladium (Pd). The first-1 metal layer (111) may function to prevent copper ions constituting the first circuit pattern (130) from migrating to the first protective layer (180).

[0139] Additionally, the first-1 portion (110) of the first barrier layer includes a first-2 metal layer (112) disposed between the lower surface of the first circuit pattern (130) and the first-1 metal layer (111). The first-2 metal layer (112) may be a seed layer of the first-1 metal layer (111). That is, the first-1 metal layer (111) is composed of palladium, and accordingly, the first-1 metal layer (111) cannot be directly formed on the first circuit pattern (130). Therefore, in the embodiment, gold (Au) with a relatively large grain size is formed on the lower surface of the first circuit pattern (130). And, the first-1 metal layer (111) can be formed by plating the first-2 metal layer (112) as a seed layer. At this time, the first-1 metal layer (111) can be referred to as the first-1 palladium layer. Also, the first-2 metal layer (112) can be referred to as the first-1 gold layer.

[0140] The first-second metal layer (112) may be disposed with a first width below the lower surface of the first circuit pattern (130). At this time, the first width of the first-second metal layer (112) may be larger than the second width of the lower surface of the first circuit pattern (130). Accordingly, the first circuit pattern (130) may not come into contact with the first protective layer (180).

[0141] The first-1 metal layer (111) can be disposed below the lower surface of the first-2 metal layer (112) having a first width equal to that of the first-2 metal layer (112).

[0142] That is, the first-2 portion (120) of the first barrier layer includes a second-1 metal layer (121). The second-1 metal layer (121) may be formed from a metallic material including palladium (Pd). The second-1 metal layer (111) may function to prevent copper ions constituting the first circuit pattern (130) from migrating to the insulating layer (140).

[0143] Additionally, the first-2 portion (120) of the first barrier layer includes a second-2 metal layer (122) disposed between the side and top surfaces of the first circuit pattern (130) and the second-1 metal layer (121). The second-2 metal layer (122) may be a seed layer of the second-1 metal layer (121). That is, the second-1 metal layer (121) is composed of palladium, and thus the second-1 metal layer (121) cannot be directly formed on the first circuit pattern (130). Therefore, in the embodiment, gold (Au) with a relatively large grain size is formed on the side and top surfaces of the first circuit pattern (130). And, the second-1 metal layer (121) can be formed by plating the second-2 metal layer (122) as a seed layer. At this time, the above 2-1 metal layer (121) can be referred to as the 1-2 palladium layer. Also, the 2-2 metal layer (122) can be referred to as the 1-2 gold layer.

[0144] The second-2 metal layer (122) may be arranged to surround the side and top surfaces of the first circuit pattern (130). Additionally, the second-1 metal layer (121) may be arranged to surround the second-2 metal layer (122).

[0145] Meanwhile, the upper surface of the first-2 metal layer (112) may include a first region that contacts the lower surface of the first circuit pattern (130). Additionally, the upper surface of the first-2 metal layer (112) may include a second region that contacts the second-1 metal layer (121). Furthermore, the upper surface of the first-2 metal layer (112) may include a third region that contacts the second-2 metal layer (122). Accordingly, the first-1 metal layer (111) in the embodiment may not contact the first circuit pattern (130), the second-1 metal layer (121), and the second-2 metal layer (122).

[0146] The second barrier layer may be disposed between the second circuit pattern (160) and the insulating layer (140). Additionally, the second barrier layer may be disposed between the second circuit pattern (160) and the second protection layer (185).

[0147] Specifically, the second barrier layer includes a second-1 portion (150) disposed between the second circuit pattern (160) and the insulating layer (140). Additionally, the second barrier layer includes a second-2 portion (170) disposed between the second circuit pattern (160) and the second protective layer (185).

[0148] The 2-1 portion (150) and 2-2 portion (170) of the second barrier layer may each be composed of a plurality of layers.

[0149] That is, the second-1 portion (150) of the second barrier layer includes a third-1 metal layer (151). The third-1 metal layer (151) may be formed from a metallic material including palladium (Pd). The third-1 metal layer (151) may function to prevent copper ions constituting the second circuit pattern (160) from migrating to the insulating layer (140).

[0150] Additionally, the second-1 portion (150) of the second barrier layer includes a third-2 metal layer (152) disposed between the lower surface of the second circuit pattern (160) and the third-1 metal layer (151). The third-2 metal layer (152) may be a seed layer of the third-1 metal layer (151). That is, the third-1 metal layer (151) is composed of palladium, and accordingly, the third-1 metal layer (151) cannot be directly formed on the second circuit pattern (160). Therefore, in the embodiment, gold (Au) with a relatively large grain size is formed on the lower surface of the second circuit pattern (160). And, the third-1 metal layer (151) can be formed by proceeding with plating the third-2 metal layer (152) as a seed layer. At this time, the above 3-1 metal layer (151) can be referred to as the 1-1 palladium layer. Also, the 3-2 metal layer (152) can be referred to as the 2-1 gold layer.

[0151] The above third-2 metal layer (152) may be disposed with a first width below the lower surface of the second circuit pattern (160). At this time, the first width of the third-2 metal layer (152) may be larger than the second width of the lower surface of the second circuit pattern (160). Accordingly, the second circuit pattern (160) may not come into contact with the insulating layer (140).

[0152] The above 3-1 metal layer (151) can be disposed below the lower surface of the above 3-2 metal layer (152) having a first width equal to that of the above 3-2 metal layer (152).

[0153] That is, the second-2 portion (170) of the second barrier layer includes a fourth-1 metal layer (171). The fourth-1 metal layer (171) may be formed from a metallic material including palladium (Pd). The second-1 metal layer (111) may function to prevent copper ions constituting the second circuit pattern (160) from migrating to the second protective layer (185).

[0154] Additionally, the second-2 portion (170) of the second barrier layer includes a fourth-2 metal layer (172) disposed between the side and top surfaces of the second circuit pattern (160) and the fourth-1 metal layer (171). The fourth-2 metal layer (172) may be a seed layer of the fourth-1 metal layer (171). That is, the fourth-1 metal layer (171) is composed of palladium, and thus the fourth-1 metal layer (171) cannot be directly formed on the second circuit pattern (160). Therefore, in the embodiment, gold (Au) with a relatively large grain size is formed on the side and top surfaces of the second circuit pattern (160). Furthermore, the fourth-1 metal layer (171) may be formed by plating the fourth-2 metal layer (172) as a seed layer. At this time, the above 4-1 metal layer (171) can be referred to as the 2-2 palladium layer. Also, the 4-2 metal layer (172) can be referred to as the 2-2 gold layer.

[0155] The above 4-2 metal layer (172) may be arranged to surround the side and top surfaces of the above 2 circuit pattern (160). Additionally, the above 4-1 metal layer (171) may be arranged to surround the above 4-2 metal layer (172).

[0156] Meanwhile, the upper surface of the third-2 metal layer (152) may include a first region that contacts the lower surface of the second circuit pattern (160). Additionally, the upper surface of the third-2 metal layer (152) may include a second region that contacts the fourth-1 metal layer (171). Furthermore, the upper surface of the third-2 metal layer (152) may include a third region that contacts the fourth-2 metal layer (172). Accordingly, the third-1 metal layer (151) in the embodiment may not contact the second circuit pattern (160), the fourth-1 metal layer (171), and the fourth-2 metal layer (172).

[0157] In the above embodiment, a printed circuit board comprising an insulating layer and a circuit pattern is provided. At this time, the circuit pattern is formed from a metallic material containing copper. At this time, the circuit pattern formed from the metallic material containing copper does not come into direct contact with the insulating layer. To this end, a barrier layer is disposed around the circuit pattern. For example, in the embodiment, a gold metal layer containing gold (Au) is disposed surrounding the circuit pattern, and a palladium metal layer containing palladium (Pd) is disposed surrounding the gold metal layer. The palladium metal layer can prevent copper constituting the circuit pattern from penetrating toward the insulating layer, thereby suppressing copper migration and improving reliability. Additionally, the gold metal layer is disposed between the palladium metal layer and the circuit pattern to form the palladium metal layer. At this time, the gold metal layer contains gold (Au) with a grain size larger than that of other layers, and accordingly, this brings about the effect of stably forming the palladium metal layer.

[0158] In addition, in the embodiment, a barrier layer as described above is formed for the circuit pattern disposed on the outermost layer among the circuit patterns. This can prevent the copper constituting the circuit pattern on the outermost layer from migrating to the solder resist.

[0159] In addition, in the embodiment, a portion of the barrier layer is disposed over the surface of the embedded pattern in the ETS structure. At this time, the barrier layer is disposed protruding over the surface of the embedded pattern, and this can function as a mounting pad on which a solder layer for device mounting is disposed. That is, in the ETS structure, conventionally, since the embedded pattern is formed as a fine pattern, a simple pattern alone could not function as a mounting pad; consequently, a separate mounting pad had to be formed with a structure that is embedded inside the insulating layer or protrudes over the surface of the insulating layer. In this case, when the mounting pad is embedded inside the insulating layer, the spacing of the fine pattern due to the width of the mounting pad widens, and consequently, there were problems with circuit integration density. Furthermore, in the case where the mounting pad is structured to protrude outside the insulating layer, a separate process had to be performed to form it. In contrast, in the embodiment, when forming the barrier layer on the embedded pattern, a portion of the barrier layer has a structure that protrudes over the surface of the insulating layer, and accordingly, the barrier layer can be utilized as a mounting pad, thereby simplifying the manufacturing process.

[0160] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0161] Although the above description has focused on the embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

Claim 1 A circuit board comprising: an insulating layer formed of glass having via holes penetrating the upper and lower surfaces; a first through-via disposed within the via holes of the insulating layer; and a second through-via disposed between the inner wall of the via holes of the insulating layer and the side of the first through-via, wherein the second through-via has a width in a different horizontal direction from the upper surface of the insulating layer toward the lower surface of the insulating layer, and the second through-via comprises a first part disposed on the inner wall of the via holes and having a metallic material different from the metallic material of the first through-via, and a second part disposed between the first part and the side of the first through-via and having a metallic material different from the metallic material of the first through-via and the metallic material of the first part, wherein the first through-via comprises copper, the first part of the second through-via comprises palladium, and the second part of the second through-via comprises gold. Claim 2 A circuit board according to claim 1, comprising: an upper circuit layer disposed on the upper surface of the first through-via and the second through-via; an upper barrier layer disposed on the upper circuit layer; and an upper protective layer disposed on the upper barrier layer, wherein the upper barrier layer comprises a first-1 portion disposed between the upper protective layer and the upper circuit layer and a first-2 portion disposed between the insulating layer and the upper circuit layer, wherein the first-1 portion of the upper barrier layer comprises a first-1 gold (Au) layer disposed on the lower surface of the upper circuit layer and a first-1 palladium (Pd) layer disposed on the lower surface of the first-1 gold (Au) layer, and the first-2 portion of the upper barrier layer comprises a first-2 gold (Au) layer disposed surrounding the side and upper surfaces of the upper circuit layer and a first-2 palladium (Pd) layer disposed surrounding the first-2 gold (Au) layer. Claim 3 In paragraph 2, the circuit board, wherein the upper circuit layer does not come into contact with the upper protective layer and the insulating layer by the first-1 and first-2 portions of the upper barrier layer. Claim 4 A circuit board according to claim 3, wherein the first-1 gold (Au) layer has a first width, the lower surface of the upper circuit layer has a second width smaller than the first width, and the lower surface of the first-1 gold (Au) layer includes a first region in contact with the lower surface of the upper circuit layer, a second region in contact with the first-2 palladium (Pd) layer, and a third region in contact with the first-2 gold (Au) layer. Claim 5 A circuit board according to any one of claims 1 to 4, wherein the width of the second through-via in the horizontal direction decreases toward the lower surface of the insulating layer. Claim 6 In paragraph 2, a lower circuit layer disposed on the lower surface of the first through-via and the second through-via; a lower barrier layer disposed covering the lower circuit layer; A circuit board comprising a lower protective layer disposed on the lower surface of the insulating layer, wherein the lower barrier layer comprises a 2-1 portion disposed between the insulating layer and the lower circuit layer and a 2-2 portion disposed between the lower protective layer and the lower circuit layer, wherein the 2-1 portion of the lower barrier layer comprises a 2-1 gold (Au) layer disposed on the lower surface of the lower circuit layer and a 2-1 palladium (Pd) layer disposed between the lower surface of the 2-1 gold (Au) layer and the upper surface of the insulating layer, wherein the 2-2 portion of the lower barrier layer comprises a 2-2 gold (Au) layer disposed surrounding the side and upper surfaces of the lower circuit layer and a 2-2 palladium (Pd) layer disposed surrounding the 2-2 gold (Au) layer, and wherein the lower circuit layer does not come into contact with the insulating layer and the lower protective layer by the 2-1 portion and the 2-2 portion of the lower barrier layer. Claim 7 A circuit board according to any one of claims 1 to 4, wherein the width of the first through-via in the horizontal direction decreases toward the lower surface of the insulating layer. Claim 8 A circuit board according to claim 6, wherein the width in the horizontal direction of each of the first and second parts of the second through-via decreases toward the lower surface of the insulating layer. Claim 9 A circuit board according to any one of claims 1 to 4, wherein the second through-via has a slope in which the width in the horizontal direction gradually decreases from the upper surface of the insulating layer toward the lower surface of the insulating layer. Claim 10 A circuit board according to any one of claims 1 to 4, wherein the first through-via has a slope in which the width in the horizontal direction gradually decreases from the upper surface of the insulating layer toward the lower surface of the insulating layer. Claim 11 A circuit board according to any one of claims 1 to 4, wherein the side of the first through-via and the side of the second through-via have the same slope. Claim 12 A circuit board according to claim 6, wherein the width of the 2-1 gold (Au) layer is greater than the width of the lower surface of the lower circuit layer, and the lower surface of the 2-1 gold (Au) layer comprises a first region in contact with the lower surface of the lower circuit layer, a second region in contact with the 2-2 palladium (Pd) layer, and a third region in contact with the 2-2 gold (Au) layer.

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