Image sensor including pixel including internal capacitor

Abstract

An image sensor comprising pixels including an internal capacitor is disclosed. Each of the plurality of pixels of the image sensor comprises a photodetector circuit including a photodiode and generating a detection signal, and an analog-to-digital converter that converts the detection signal using a ramp signal. The photodetector circuit includes a floating diffusion node having a parasitic capacitor that accumulates photocharge generated from the photodiode, and an overflow transistor that electrically connects the floating diffusion node and the first internal capacitor of the analog-to-digital converter.

Description

Technology Field

[0001] The technical concept of the present disclosure relates to an image sensor, and more specifically, to an image sensor comprising a pixel including an internal capacitor. Background Technology

[0002] An image sensor is a device that captures a two-dimensional or three-dimensional image of an object. An image sensor generates an image of an object using a photoelectric conversion element that responds to the intensity of light reflected from the object. Recently, with the development of the computer and telecommunications industries, there has been an increasing demand for high-performance image sensors in various electronic devices, such as digital cameras, camcorders, PCS (Personal Communication Systems), gaming devices, security cameras, medical micro cameras, and mobile phones.

[0003] Image sensors can increase resolution by arranging a larger number of pixels. As the size of each pixel gradually decreases, a pixel structure may be required to efficiently increase the capacitance of the floating diffusion node. The problem to be solved

[0004] The problem that the technical concept of the present disclosure aims to solve is to provide an image sensor including a pixel capable of increasing the capacitance of a floating diffusion node using an internal capacitor. means of solving the problem

[0005] To achieve the above objectives, an image sensor comprising a plurality of pixels according to the technical concept of the present disclosure, wherein each of the plurality of pixels comprises a photodetector circuit comprising a photodiode and generating a detection signal, and an analog-to-digital converter that converts the detection signal using a ramp signal, and the photodetector circuit may include a floating diffusion node having a parasitic capacitor that accumulates photocharge generated from the photodiode, and an overflow transistor that electrically connects the floating diffusion node and the first internal capacitor of the analog-to-digital converter.

[0006] An image sensor that operates in a plurality of modes according to illuminance according to the technical concept of the present disclosure comprises a pixel array including a plurality of pixels each including a light detection circuit and an analog-to-digital converter that converts a detection signal detected by the light detection circuit, and a pixel driver that provides an overflow control signal to the pixel array, wherein in response to the overflow control signal, a photocharge generated in the light detection circuit may be stored in an internal capacitor included in the analog-to-digital converter.

[0007] In an image sensor comprising a plurality of pixels according to the technical concept of the present disclosure, each of the plurality of pixels comprises a photodiode, a photodetection circuit that generates a detection signal, and a pixel signal generation circuit that generates a pixel signal corresponding to the detection signal, wherein the photodetection circuit may comprise a floating diffusion node that accumulates photocharge generated from the photodiode, and an overflow transistor that electrically connects the floating diffusion node and the capacitor of the pixel signal generation circuit.

[0008] In an image sensor comprising a plurality of pixels according to the technical concept of the present disclosure, each of the plurality of pixels comprises a photodetection circuit that detects a light signal and outputs a detection signal, and a pixel signal generation circuit that outputs a pixel signal according to the detection signal, and the photodetection circuit may include a photodiode that generates a photocharge according to the light signal, a floating diffusion node that accumulates a photocharge and has a parasitic capacitor, a reset transistor that resets the floating diffusion node, a source follower that generates a detection signal according to the voltage of the floating diffusion node, and an overflow transistor that electrically connects the floating diffusion node and an output node to which the detection signal is output. Effects of the invention

[0009] An image sensor according to the technical concept of the present disclosure may include an overflow transistor that electrically connects an internal capacitor included in a pixel to a floating diffusion node. By turning on the overflow transistor, the image sensor can increase the equivalent capacitance of the floating diffusion node at high illumination levels and increase the pixel's full well capacity (FWC). Conversely, at low illumination levels, it can decrease the equivalent capacitance of the floating diffusion node and operate to have a high conversion gain. That is, the image sensor can secure a wide dynamic range (WDR) without increasing the pixel area.

[0010] Furthermore, various technical effects can be derived from embodiments of the technical concept of the present disclosure. Such unmentioned technical effects will be easily derived or inferred by those skilled in the art from the description below. Brief explanation of the drawing

[0011] FIG. 1 is a block diagram showing an image sensor according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram showing a portion of pixels included in an image sensor according to an embodiment of the present disclosure. FIG. 3 is a timing diagram illustrating control signals and ramp signals provided to pixels included in an image sensor according to an embodiment of the present disclosure. Figure 4 is a diagram for showing the potential level of a pixel in the sampling interval during an overflow operation. FIG. 5 is a block diagram showing a portion of pixels included in an image sensor according to an embodiment of the present disclosure. FIG. 6 is a block diagram showing a portion of pixels included in an image sensor according to an embodiment of the present disclosure. FIG. 7 is a block diagram showing an image sensor according to an embodiment of the present disclosure. FIGS. 8 and FIGS. 9 are block diagrams showing pixels included in an image sensor according to an embodiment of the present disclosure. FIGS. 12 and FIGS. 13 are block diagrams showing pixels included in an image sensor according to an embodiment of the present disclosure. FIG. 12 is a block diagram of an electronic device including a multi-camera module. Figure 13 is a detailed block diagram of the camera module of Figure 12. Specific details for implementing the invention

[0012] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0013] FIG. 1 is a block diagram showing an image sensor according to an embodiment of the present disclosure. The pixel (PX) described in FIG. 1 is a digital pixel, which is used to illustrate an example of a pixel that includes a capacitor inside.

[0014] The image sensor (10) can be mounted on an electronic device having an image or light sensing function. For example, the image sensor (10) can be mounted on electronic devices such as a camera, smartphone, wearable device, Internet of Things (IoT), tablet PC (Personal Computer), PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), navigation device, etc. Additionally, the image sensor (10) can be mounted on electronic devices equipped as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, etc.

[0015] The image sensor (10) may include a pixel array (100), a pixel driver (Row Driver, 200), a ramp signal generator (Ramp Generator, 300), a controller (400), a digital signal processing unit (500), and an interface circuit (600). The pixel array (100) may include a plurality of pixels (PX), and each of the plurality of pixels (PX) may be configured to detect an optical signal from the outside and output a digital output signal (DOUT) corresponding to the detected optical signal.

[0016] Multiple pixels (PX) can detect light signals using light-sensing elements and convert them into digital output signals (DOUT), which are electrical signals. Each of the multiple pixels (PX) can detect light in a specific spectral region. For example, the multiple pixels (PX) may include a red pixel that converts light in the red spectral region into an electrical signal, a green pixel that converts light in the green spectral region into an electrical signal, and a blue pixel that converts light in the blue spectral region into an electrical signal. A color filter for transmitting light in a specific spectral region may be placed on the upper portion of each of the multiple pixels (PX), and a micro-lens for light concentration may be placed.

[0017] A pixel (PX) may include a light detection circuit (110), an analog-to-digital converter (ADC; hereinafter ADC, 120), and a memory (130). The light detection circuit (110) may include a light detection element and may convert a light signal detected from the outside into an electrical signal, i.e., an analog signal, which is a detection signal. For example, the light detection element may include a photodiode, a phototransistor, a photogate, or a pinned photodiode. The detection signal may include a detection signal according to the reset operation of the pixel (PX) and a detection signal according to the light detection operation of the pixel (PX).

[0018] The ADC (120) can convert the detection signal output from the photodetection circuit (110) into a digital signal, and the memory (130) can store the converted digital signal. The memory (130) can output a digital output signal (DOUT) under the control of the pixel driver (200). The ADC (120) can convert the detection signal into a digital signal by comparing the detection signal with a ramp signal (RAMP).

[0019] The image sensor (10) according to the present disclosure may operate in a plurality of operating modes depending on the illuminance. Depending on the operating mode, the equivalent capacitance of the floating diffusion node, where charge corresponding to the light signal is accumulated, may vary for each pixel (PX). For example, the image sensor (10) may relatively increase the equivalent capacitance of the floating diffusion node by electrically connecting the floating diffusion node of the light detection circuit (110) and the internal capacitor included in the ADC (120) in a high-illuminance environment. Alternatively, for example, the image sensor (10) may relatively decrease the equivalent capacitance of the floating diffusion node by electrically disconnecting the floating diffusion node and the internal capacitor included in the ADC (120) in a low-illuminance environment.

[0020] The pixel driver (200) can output control signals (CTRL) for controlling multiple pixels (PX) included in the pixel array (100). In response to the control signals (CTRL) generated from the pixel driver (200), each of the multiple pixels (PX) can generate a detection signal, convert the detection signal into a digital signal using a ramp signal (RAMP), store the digital signal, and output the stored digital signal as a digital output signal (DOUT). Additionally, in response to the control signals (CTRL) generated from the pixel driver (200), the operating mode of each of the multiple pixels (PX) can be changed, and the equivalent capacitance of the floating diffusion node can be changed.

[0021] A ramp signal generator (300) can generate a ramp signal (RAMP) and output it to a pixel array (100). The ramp signal (RAMP) can be provided to an ADC (120) of a pixel (PX) and used as a reference signal to be compared with a detection signal. In an exemplary embodiment, the ramp signal (RAMP) may be a signal that decreases or increases at a constant rate (i.e., an increasing / decreasing signal with a single slope).

[0022] The controller (400) can control the overall operations of the image sensor (10). For example, the controller (400) can control the operation timing of the image sensor (10) based on control information received from an external device (e.g., an image signal processor (ISP), an application processor (AP), etc.) through the interface circuit (600). The pixel driver (200) and the ramp signal generator (300) can generate a control signal (CTRL) and a ramp signal (RAMP) based on the timing signals provided by the controller (400).

[0023] The digital signal processing unit (500) can perform digital signal processing on digital output signals (DOUT) received from the pixel array (100) to provide final image data (ID) to an external device. The digital output signal (DOUT) may include a reset value corresponding to the reset operation of the pixel (PX) and an image signal value corresponding to the light detection operation of the pixel (PX). The digital signal processing unit (500) can determine a final digital value corresponding to the light signal detected by a single pixel (PX) by performing operations on the reset value and the image signal value. The final digital values ​​determined at each of the multiple pixels (PX) can be combined to generate final image data (ID). That is, a correlated double sampling operation can be implemented through the digital output signal (DOUT) generated by the operation of the ADC (120) included in the pixel (PX) and the digital signal processing operation of the digital signal processing unit (500).

[0024] The interface circuit (600) may be configured to receive control information from an external device or output final image data (ID). In an exemplary embodiment, the interface circuit (600) may exchange the information described above with an external device based on a predetermined protocol.

[0025] FIG. 2 is a block diagram showing a portion of a pixel included in an image sensor according to an embodiment of the present disclosure. Hereinafter, in order to clearly explain the technical concept of the present disclosure, the structure and operation of the pixel (PX) of FIG. 1 are described based on an exemplary circuit diagram, but the scope of the present disclosure is not limited thereto, and the pixel (PX) can be modified in various forms. The light detection circuit (110) described in FIG. 2 is an example of the light detection circuit (110) of FIG. 1, and the ADC (120) described in FIG. 2 is an example of the ADC (120) of FIG. 1. In addition, the reset control signal (RS), transmission control signal (TS), selection control signal (SEL), overflow control signal (OFS), and switching control signal (SS) described in FIG. 2 may be included in the control signals (CTRL) of FIG. 1.

[0026] Referring to FIG. 2, the light detection circuit (110) may include a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a source follower (SF), and a select transistor (SX). The photodiode (PD) may be replaced with other photoelectric conversion elements.

[0027] A photodiode (PD) can generate photocharges that vary depending on the intensity of incident light. A transfer transistor (TX) can transfer photocharges to a floating diffusion node (FD) according to a transfer control signal (TS) output from a pixel driver (200 in FIG. 1).

[0028] Photocharge generated from a photodiode (PD) can be accumulated in the floating diffusion node (FD). The floating diffusion node (FD) may substantially have a parasitic capacitor (CFD), and said photocharge can be accumulated in the parasitic capacitor (CFD). A reset transistor (RX) can reset the floating diffusion node (FD) to the power supply voltage (VDD) level according to a reset control signal (RS) provided from the pixel driver (200).

[0029] Depending on the potential according to the photocharge accumulated in the floating diffusion node (FD), the source follower (SF) can transmit a detection signal (DS) to the output node (NO). The source follower (SF) is connected to the output node (NO) and can provide a current path through which current flows in the source follower (SF) according to a selection control signal (SEL) output from the pixel driver (200).

[0030] In FIG. 2, the light detection circuit (110) of a pixel (PX) is shown as having a 4T (4-transistor) structure including a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a source follower (SF), and a select transistor (SX); however, each of the plurality of pixels (PX) included in the image sensor according to the present disclosure is not limited to the structure of FIG. 2. At least one of the transfer transistor (TX), the reset transistor (RX), the source follower (SF), and the select transistor (SX) may be omitted.

[0031] A pixel (PX) according to the present disclosure may include an overflow transistor (SOF). The overflow transistor (SOF) may be connected between a floating diffusion node (FD) and an output node (NO). The overflow transistor (SOF) may electrically connect or electrically disconnect the floating diffusion node (FD) and the output node (NO) in response to an overflow control signal (OFS) output from a pixel driver (200).

[0032] The ADC (120) may be, for example, a single slope ADC. The ADC (120) may include a comparator (121), a first switch (SW1), a second switch (SW2), a first capacitor (C1), and a second capacitor (C2). The comparator (121) may include a differential amplifier, and a detection signal (DS) may be received as a first input signal (INN) through the first capacitor (C1) at the first input terminal of the comparator (121), and a ramp signal (RAMP) may be received as a second input signal (INP) through the second capacitor (C2) at the second input terminal of the comparator (121). The comparator (121) may compare the detection signal (DS) and the ramp signal (RAMP) received through the capacitors (C1, C2) and output a comparison result signal (COUT).

[0033] The first capacitor (C1) may be a capacitor having a relatively large capacitance connected to the output node (NO) of the photodetector circuit (110). When the overflow transistor (SOF) is turned on, the floating diffusion node (FD) and the output node (NO) are connected to each other, so that the parasitic capacitor (CFD) of the floating diffusion node (FD) and the first capacitor (C1) of the ADC (120) can be electrically connected to each other. Therefore, when the overflow transistor (SOF) is turned on, the equivalent capacitance of the floating diffusion node (FD) can be increased, and a larger amount of photocharge generated in the photodiode (PD) can be accumulated in the parasitic capacitor (CFD) of the floating diffusion node (FD) and the first capacitor (C1) of the ADC (120). That is, the maximum charge storage capacity (full well capacity; FWC) of the pixel (PX) can be increased. Accordingly, the image sensor according to the present disclosure can increase the equivalent capacitance of the floating diffusion node (FD) at high illumination levels by turning the overflow transistor (SOF) on / off, thereby enabling high dynamic range (HDR) without increasing the area of ​​the pixel (PX). Additionally, at low illumination levels, high conversion gain can be obtained by reducing the equivalent capacitance of the floating diffusion node (FD). That is, wide dynamic range (WDR) can be secured.

[0034] When the first switch (SW1) and the second switch (SW2) are turned on by the switching control signal (SS), the input and output terminals of the comparator (121) can be connected to each other, and the comparator (121) can be reset. For example, the comparator (121) can be reset in response to the switching control signal (SS) during the Auto-Zero period before the comparison operation of the comparator (121) is performed.

[0035] FIG. 3 is a timing diagram illustrating control signals and ramp signals provided to a pixel included in an image sensor according to an embodiment of the present disclosure. FIG. 4 is a diagram for showing the potential level of a pixel in a sampling interval (A) during an overflow operation.

[0036] Referring to FIGS. 2 and 3, the pixel (PX) can operate in multiple operation modes depending on the illuminance. For example, in the high illuminance operation mode, it can perform an overflow operation mode and a high conversion gain (HCG) mode, whereas in the low illuminance operation mode, it can perform only the high conversion gain (HCG) mode.

[0037] The overflow operation mode may refer to an operation mode for sensing photocharges generated and overflowed from the photodiode (PD). The overflow operation mode may include the operations described below. In the overflow operation mode, the select control signal (SEL) may be maintained at a low level, and the select transistor (SX) may be maintained in an off state. When the overflow operation mode is initiated, the reset control signal (RS) and the transmission control signal (TS) may simultaneously have high levels, thereby allowing the photodiode (PD) and the floating diffusion node (FD) to be reset together.

[0038] When the transmission control signal (TS) transitions from a high level to a low level, the overflow control signal (OFS) can transition from a low level to a high level. In response to the overflow control signal (OFS), the overflow transistor (SOF) can be turned on, and the floating diffusion node (FD) and the output node (NO) can be connected. The FWC of the pixel (PX) can have the sum of the capacitance of the capacitor (CFD) of the floating diffusion node (FD) and the capacitance of the first capacitor (C1) of the ADC (120). That is, the charge overflowing from the photodiode (PD) is not drained but can be accumulated in the expanded FWC. Since the FWC is increased, it is also possible to increase the time for accumulating charge.

[0039] The switching control signal (SS) transitions from a low level to a high level, and the switching control signal (SS) can maintain a high level until the comparison operation is performed in the comparator (121), that is, until the sampling operation is performed. Therefore, the input terminal where the first input signal (INN) of the comparator (121) is input is connected to the output terminal where the comparison result signal (COUT) is output, so that the voltage of the input terminal can be stabilized.

[0040] The voltage (VFD) of the floating diffusion node (FD) can be gradually reduced when the reset control signal (RS) transitions from a high level to a low level, the reset operation of the floating diffusion node (FD) is completed, and the charge accumulated in the photodiode (PD) begins to overflow. As the photocharge overflowed in the floating diffusion node (FD) and the first capacitor (C1) of the ADC (120) accumulates, the voltage (VFD) of the floating diffusion node (FD) can be gradually reduced.

[0041] Referring to FIGS. 2 to 4, the switching control signal (SS) can be transitioned from a high level to a low level to perform sampling in the sampling interval (A). At this time, the voltage level of the first input signal (INN) when the comparator (121) is in a reset state can be referred to as the auto zero voltage (AZV).

[0042] Charges can be charged to the floating diffusion node (FD) and the first capacitor (C1) by the charge overflowing from the photodiode (PD), and a first input signal (INN) corresponding to the amount of charged charge (Q2) can be sampled as a first image signal (S1).

[0043] To convert the first image signal (S1), which is an analog signal, into a digital signal, the ramp signal (RAMP) can be gradually increased after an offset is applied in the sampling interval (A). When the voltage level of the first image signal (S1) becomes lower than the ramp signal (RAMP), the polarity of the comparison result signal (COUT) of the comparator (121) may change. Based on the time point (T1) when the polarity of the comparison result signal (COUT) changes, the first image signal (S1) can be converted into a digital signal.

[0044] When the digital conversion of the first image signal (S1) is completed, the reset control signal (RS) can be transitioned from a low level to a high level, the charge stored in the floating diffusion node (FD) and the first capacitor (C1) can be drained, and the voltage (VFD) of the floating diffusion node (FD) can be reset to the power supply voltage (VDD). Due to the change in the voltage (VFD) of the floating diffusion node (FD), the voltage level of the first input signal (INN) can be increased, and the first input signal (INN) can be sampled as the first reset signal (R1).

[0045] To convert the first reset signal (R1), which is an analog signal, into a digital signal, the ramp signal (RAMP) can be gradually increased after an offset is applied. When the voltage level of the first reset signal (R1) becomes lower than that of the ramp signal (RAMP), the polarity of the comparison result signal (COUT) of the comparator (121) may change. Based on the time point (T2) when the polarity of the comparison result signal (COUT) changes, the first reset signal (R1) can be converted into a digital signal.

[0046] Referring again to FIGS. 2 and 3, the HCG mode may refer to a mode for sensing photocharges generated in a photodiode (PD) that have not overflowed. The HCG mode may include the operations described below. In the HCG mode, the overflow control signal (OFS) may be maintained at a low level, the overflow transistor (SOF) may be maintained in an off state, and the floating diffusion node (FD) and the output node (NO) of the photodetector circuit (110) may be electrically isolated. Additionally, in the HCG mode, the selection control signal (SEL) may be maintained at a high level, and the selection transistor (SX) may be maintained in an on state.

[0047] When the HCG mode starts, the reset control signal (RS) may have a high level, and the floating diffusion node (FD) may be reset so that the voltage (VFD) of the floating diffusion node (FD) is reset to the power supply voltage (VDD). When the reset control signal (RS) transitions from a high level to a low level and the reset operation of the floating diffusion node (FD) is completed, the switching control signal (SS) transitions from a low level to a high level and the comparator (121) may be reset.

[0048] When the switching control signal (SS) transitions back from a high level to a low level, a comparison operation between the first input signal (INN) and the ramp signal (RAMP) can be performed. The first input signal (INN) can be sampled as the second reset signal (R2).

[0049] To convert the second reset signal (R2), which is an analog signal, into a digital signal, the ramp signal (RAMP) can be gradually reduced after an offset is applied. When the voltage level of the second reset signal (R2) becomes higher than that of the ramp signal (RAMP), the polarity of the comparison result signal (COUT) of the comparator (121) may change. Based on the point in time when the polarity of the comparison result signal (COUT) changes, the second reset signal (R2) can be converted into a digital signal.

[0050] When the digital conversion of the second reset signal (R2) is completed, the transmission control signal (TS) can be transitioned from a low level to a high level, and the charges accumulated in the photodiode (PD) can be accumulated in the floating diffusion node (FD). Depending on the amount of charge accumulated in the photodiode (PD) (e.g., Q1 in FIG. 4), the voltage (VFD) of the floating diffusion node (FD) can be reduced. A first input signal (INN) corresponding to the amount of charge (Q1) can be sampled as a second image signal (S2).

[0051] To convert the second image signal (S2), which is an analog signal, into a digital signal, the ramp signal (RAMP) can be gradually reduced after an offset is applied. When the voltage level of the second image signal (S2) becomes higher than the ramp signal (RAMP), the polarity of the comparison result signal (COUT) of the comparator (121) may change. Based on the point in time when the polarity of the comparison result signal (COUT) changes, the second image signal (S2) can be converted into a digital signal.

[0052] An image sensor according to the present disclosure is capable of detecting high-intensity light without wasting overflowed charges by performing an overflow operation mode and an HCG mode in a high-intensity mode. Additionally, in the HCG mode, the equivalent capacitance of the floating diffusion node (FD) is reduced compared to the overflow operation mode, thereby increasing the potential change of the floating diffusion node (FD) and increasing the conversion gain. On the other hand, the image sensor may increase the conversion gain by performing only the HCG mode in a low-intensity mode.

[0053] FIG. 5 is a block diagram showing a portion of a pixel included in an image sensor according to an embodiment of the present disclosure. The light detection circuit (110a) described in FIG. 5 is an example of the light detection circuit (110) of FIG. 1, and in the description of FIG. 5, redundant descriptions of the same reference numerals as in FIG. 2 will be omitted.

[0054] Referring to FIG. 5, the light detection circuit (110a) may include a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a source follower (SF), a select transistor (SX), an overflow transistor (SOF), and a conversion gain transistor (DCGX). The conversion gain transistor (DCGX) may be turned on / off according to a conversion gain control signal (DCGS). The control signals (RS, DCGS, TS, OFS, SEL) provided to the light detection circuit (110a) may be some of the control signals (CTRL) generated by the pixel driver (200 in FIG. 1).

[0055] The first terminal of the reset transistor (RX) can be connected to the pixel voltage (VPIX), and the second terminal can be connected to the reset node (NR). The first terminal of the conversion gain transistor (DCGT) can be connected to the reset node (NR), and the second terminal of the conversion gain transistor (DCGT) can be connected to the floating diffusion node (FD).

[0056] The reset node (NR) may substantially have a parasitic capacitor (CDCG), and the photocharge may be accumulated in the parasitic capacitor (CDCG). In an exemplary embodiment, the image sensor may support a dual conversion gain (DCG) function by operating in a Low Conversion Gain (LCG) mode and an HCG mode. In LCG mode, the conversion gain control signal (DCGS) may be at a high level when the transmission control signal (TS) is maintained at a high level to accumulate the photocharge generated from the photodiode (PD) in the floating diffusion node (FD). While the photocharge is accumulating in the capacitor (CFD) of the floating diffusion node (FD), the conversion gain transistor (DCGX) is turned on, and the photocharge may also be accumulated in the capacitor (CDCG) of the conversion gain transistor (DCGX). Therefore, the effect of substantially increasing the equivalent capacitance of the floating diffusion node (FD) may occur, and the conversion gain may be reduced.

[0057] On the other hand, in HCG mode, when the transmission control signal (TS) is maintained at a high level, the conversion gain control signal (DCGS) can be maintained at a low level. The equivalent capacitance of the floating diffusion node (FD) can be relatively small, but the conversion efficiency can be increased. Therefore, the image sensor according to the present disclosure can perform overflow mode, LCG mode, and HCG mode all within a single frame, and dynamic range expansion is possible.

[0058] In an exemplary embodiment, an additional capacitor may be connected to the reset node (NR), and when the conversion gain transistor (DCGT) is turned on, the additional capacitor and the floating diffusion node (FD) are electrically connected to each other, thereby further increasing the equivalent capacitance of the floating diffusion node (FD).

[0059] FIG. 6 is a block diagram showing a portion of a pixel included in an image sensor according to an embodiment of the present disclosure. The light detection circuit (110b) described in FIG. 6 is an example of the light detection circuit (110) of FIG. 1, and in the description of FIG. 6, redundant descriptions of the same reference numerals as in FIG. 2 and FIG. 5 will be omitted.

[0060] Referring to FIG. 6, the light detection circuit (110b) may include a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a source follower (SF), a select transistor (SX), and a conversion gain transistor (DCGX). The control signals (RS, DCGS, TS, OFS, SEL) provided to the light detection circuit (110b) may be some of the control signals (CTRL) generated by the pixel driver (200 in FIG. 1).

[0061] The light detection circuit (110b) may further include an overflow transistor (SOFa). The overflow transistor (SOFa) may be connected between the floating diffusion node (FD) and the reset node (NR). The overflow transistor (SOFa) may electrically connect or electrically disconnect the floating diffusion node (FD) and the reset node (NR) in response to an overflow control signal (OFS) output from the pixel driver (200 in FIG. 1).

[0062] An image sensor according to the present disclosure can control pixels in an overflow operation mode by simultaneously turning on an overflow transistor (SOFa) and a conversion gain transistor (DCGT) so that photocharges generated and overflowed from a photodiode (PD) are accumulated in a capacitor (CFD) of a floating diffusion node (FD), a capacitor (CDCG) of a conversion gain transistor (DCGX), and a first capacitor (C1) of an ADC (120). Alternatively, the image sensor can control pixels in an LCG mode by turning off the overflow transistor (SOFa) and turning on the conversion gain transistor (DCGT) so that photocharges generated and overflowed from a photodiode (PD) are accumulated in a capacitor (CFD) of a floating diffusion node (FD) and a capacitor (CDCG) of a conversion gain transistor (DCGX). Alternatively, the image sensor can control the pixels in HCG mode by turning off both the overflow transistor (SOFa) and the conversion gain transistor (DCGT) so that photocharges generated and overflowed from the photodiode (PD) accumulate only in the capacitor (CFD) of the floating diffusion node (FD).

[0063] FIG. 7 is a block diagram illustrating an image sensor according to an embodiment of the present disclosure. The pixel (PX') described in FIG. 7 is a pixel capable of global shutter operation, and is intended to illustrate an example of a pixel that includes a capacitor inside. Compared to the image sensor (10) of FIG. 1, the image sensor (10') of FIG. 7 may include an ADC (510) outside the pixel array (100') rather than including the ADC (510) inside each pixel (PX'). In the description of FIG. 7, redundant descriptions of reference numerals identical to those in FIG. 1 will be omitted.

[0064] Referring to FIG. 7, the image sensor (10') may include a pixel array (100'), a pixel driver (200'), a ramp signal generator (300'), a controller (400'), a readout circuit (500'), and an interface circuit (600'). The pixel array (100') may include a plurality of pixels (PX'), and each of the plurality of pixels (PX) may be configured to detect an optical signal from the outside and output a pixel signal (PXS) corresponding to the detected optical signal.

[0065] In a pixel array (100'), multiple pixels (PX') can be arranged in a matrix form consisting of multiple rows and multiple columns. In a global shutter mode, the image sensor (10') can control the photocharge accumulation time of pixels (PX') placed in different rows to be the same, and can eliminate image distortion caused by differences in photocharge accumulation time.

[0066] A pixel (PX') may include a light detection circuit (110') and a pixel signal generation circuit (120'). The light detection circuit (110) may include a light sensing element and may convert a light signal detected from the outside into an electrical signal, i.e., an analog signal, which is a detection signal. The detection signal may include a detection signal resulting from a reset operation of the light detection circuit (110') and a detection signal resulting from a light detection operation of the light detection circuit (110').

[0067] A pixel signal generation circuit (120') can receive a detection signal, generate a pixel signal (PXS) corresponding to the detection signal, and output the pixel signal (PXS) through a column line. The pixel signal generation circuit (120') may include a capacitor internally and can store an amount of charge corresponding to the detection signal in the internal capacitor. For example, the pixel signal generation circuit (120') may include a first capacitor in which charge corresponding to a light detection operation is accumulated, and a second capacitor in which charge corresponding to a reset operation is accumulated. By including the first capacitor and the second capacitor, the timing of photocharge accumulation of pixels (PX') placed in different rows can be controlled to be the same.

[0068] The image sensor (10') according to the present disclosure may operate in a plurality of operating modes depending on the illuminance. Depending on the operating mode, the equivalent capacitance of the floating diffusion node, where charge corresponding to the light signal is accumulated, may vary for each pixel (PX'). For example, the image sensor (10') may relatively increase the equivalent capacitance of the floating diffusion node by electrically connecting the floating diffusion node of the light detection circuit (110') and the internal capacitor included in the pixel signal generation circuit (120') in a high-illumination environment. Alternatively, for example, the image sensor (10') may relatively decrease the equivalent capacitance of the floating diffusion node by electrically disconnecting the floating diffusion node and the internal capacitor included in the pixel signal generation circuit (120') in a low-illumination environment.

[0069] The pixel driver (200') can output a control signal (CTRL') for controlling a plurality of pixels (PX') included in the pixel array (100'). In response to the control signal (CTRL') generated from the pixel driver (200'), each of the plurality of pixels (PX') can operate in a plurality of operation modes according to illumination. In an exemplary embodiment, the pixel driver (200') can determine the activation and deactivation timing of the control signals (CTRL') for each of the plurality of pixels (PX') in order to operate in a global shutter mode.

[0070] The ramp signal generator (300') can generate a ramp signal (RAMP') and provide the ramp signal (RAMP') to a readout circuit (500'), e.g., an ADC (510). The ramp signal (RAMP') is a signal for converting an analog signal into a digital signal and can be generated to have the form of a triangular wave.

[0071] The readout circuit (500') may include an ADC (510) and a memory (520). The ADC (510) may sample and hold a pixel signal (PXS) provided from a pixel array (100'), and may perform a correlated double sampling operation by double-sampling a reset signal and an image signal and outputting a level corresponding to the difference. The ADC (510) may receive a ramp signal (RAMP'), compare the reset signal and the image signal respectively, and output a comparison result signal. The ADC (510) may convert the comparison result signal into a digital signal. The memory (520) may latch the digital signal and sequentially output the latched image data (ID).

[0072] FIGS. 8 and 9 are block diagrams illustrating pixels included in an image sensor according to an embodiment of the present disclosure. The pixels (PX', PXa') described in FIGS. 8 and 9 are examples of pixels capable of global shutter operation, and the image sensor according to the present disclosure is not limited to the circuit configuration of the pixels (PX', PXa'). It will be obvious that the circuit configuration of the pixel signal generation circuit (120') included in each of the pixels (PX', PXa') can be varied in various ways.

[0073] The reset control signal (RS), conversion gain control signal (DCGS), transmission control signal (TS), overflow control signal (OFS), precharge control signal (PC), sampling control signals (SAMPS1, SAMPS2), and selection control signals (SEL1, SEL2) described in FIGS. 8 and 9 may be included in the control signals (CTRL') of FIG. 7. In the description of FIGS. 8 and 9, redundant descriptions of symbols identical to those in FIGS. 2, 5, and 6 will be omitted.

[0074] Referring to FIG. 8, a pixel (PX') may include a photodetection circuit (110') and a pixel signal generation circuit (120') that outputs a first pixel signal (PXS1) and a second pixel signal (PXS2) according to a detection signal (DS) output from the photodetection circuit (110'). The photodetection circuit (110') may include a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a source follower (SF), a precharge transistor (PCX), an overflow transistor (SOF), and a conversion gain transistor (DCGX). The photodetection circuit (110') may output a detection signal (DS) corresponding to a photo signal. However, the photodetection circuit (110') as shown in FIG. 8 may not include a conversion gain transistor (DCGX).

[0075] An overflow transistor (SOF) can be connected between a floating diffusion node (FD) and an output node (NO). The overflow transistor (SOF) can electrically connect or electrically disconnect the floating diffusion node (FD) and the output node (NO) in response to an overflow control signal (OFS) output from a pixel driver (200).

[0076] The first terminal of the precharge transistor (PCX) can be connected to the output node (NO), and the second terminal can be supplied with a ground voltage. The precharge transistor (PCX) can operate as a current source according to the precharge control signal (PC). In an exemplary embodiment, an additional transistor may be connected in series between the source follower (SF) and the precharge transistor (PCX).

[0077] The pixel signal generation circuit (120') may include a first sampling transistor (SAMP1), a second sampling transistor (SAMP2), a first capacitor (C1'), a second capacitor (C2'), a first source follower (SF1), a second source follower (SF2), a first selection transistor (SX1), and a second selection transistor (SX2).

[0078] The first sampling transistor (SAMP1) can be connected between the output node (NO) and the first node (N1) and can be turned on / off according to the first sampling control signal (SAMPS1). The second sampling transistor (SAMP2) can be connected between the output node (NO) and the second node (N2) and can be turned on or off according to the second sampling control signal (SAMPS2).

[0079] The first terminal of the first capacitor (C1') may be connected to the first node (N1), and a power supply voltage (VDD) may be applied to the second terminal. However, this is not limited thereto, and a ground voltage may also be applied to the second terminal of the first capacitor (C1'). When the first sampling transistor (SAMP1) is turned on, a charge according to the detection signal (DS) may be accumulated in the first capacitor (C1'). For example, a charge according to the photocharge accumulation operation may be accumulated in the first capacitor (C1').

[0080] The first terminal of the second capacitor (C2') may be connected to the second node (N2), and a power supply voltage (VDD) may be applied to the second terminal. However, this is not limited thereto, and a ground voltage may also be applied to the second terminal of the second capacitor (C2'). When the second sampling transistor (SAMP2) is turned on, a charge corresponding to the detection signal (DS) may be accumulated in the second capacitor (C2'). For example, a charge corresponding to the reset operation of the floating diffusion node (FD) may be accumulated in the second capacitor (C2').

[0081] A power supply voltage (VDD) may be applied to the first terminal of the first source follower (SF1), and the second terminal of the first source follower (SF1) may be connected to the first select transistor (SX1). The first source follower (SF1) can buffer a signal according to the amount of charge charged in the first capacitor (C1'), and can output a first pixel signal (PXS1) by amplifying the potential change at the first node (N1).

[0082] The first terminal of the first selection transistor (SX1) is connected to the first source follower (SF1), and the second terminal of the first selection transistor (SX1) can be connected to the first column line (CL1). In response to the first selection control signal (SEL1), the first selection transistor (SX1) can output an image signal (SIG) corresponding to the photocharge accumulation operation to the first column line (CL1) as the first pixel signal (PXS1).

[0083] A power supply voltage (VDD) may be applied to the first terminal of the second source follower (SF2), and the second terminal of the second source follower (SF2) may be connected to the second select transistor (SX2). The second source follower (SF2) can buffer a signal according to the amount of charge charged in the second capacitor (C2'), and can output a second pixel signal (PXS2) by amplifying the potential change at the second node (N2).

[0084] The first terminal of the second selection transistor (SX2) is connected to the second source follower (SF2), and the second terminal of the second selection transistor (SX2) can be connected to the second column line (CL2). In response to the second selection control signal (SEL2), the second selection transistor (SX2) can output a reset signal (RST) corresponding to a reset operation to the second column line (CL2) as the second pixel signal (PXS2).

[0085] The first capacitor (C1') may be a capacitor having a relatively large capacitance. When the overflow transistor (SOF) and the first sampling transistor (SAMP1) are turned on and the precharge transistor (PCX) is turned off, the floating diffusion node (FD), the output node (NO), and the first node (N1) are connected to each other, so that the parasitic capacitor (CFD) of the floating diffusion node (FD) and the first capacitor (C1') of the pixel signal generation circuit (120') can be electrically connected to each other. Therefore, when the overflow transistor (SOF) is turned on, the equivalent capacitance of the floating diffusion node (FD) can be increased, and a larger amount of photocharge generated from the photodiode (PD) can be accumulated in the parasitic capacitor (CFD) of the floating diffusion node (FD) and the first capacitor (C1'). The maximum charge storage capacity (FWC) of the pixel (PX') can be increased.

[0086] An image sensor according to the present disclosure can control pixels in an overflow operation mode by turning on the conversion gain transistor (DCGT), the overflow transistor (SOF), and the first sampling transistor (SAMP1), and turning off the precharge transistor (PCX), so that photocharges generated and overflowed from the photodiode (PD) are accumulated in the capacitor (CFD) of the floating diffusion node (FD), the capacitor (CDCG) of the conversion gain transistor (DCGX), and the first capacitor (C1') of the pixel signal generation circuit (120'). However, not limited thereto, the conversion gain transistor (DCGT) may remain in an off state in the overflow operation mode.

[0087] Alternatively, the image sensor may control the pixels in LCG mode by turning off the overflow transistor (SOF) and turning on the conversion gain transistor (DCGT) so that photocharges generated and overflowed from the photodiode (PD) accumulate in the capacitor (CFD) of the floating diffusion node (FD) and the capacitor (CDCG) of the conversion gain transistor (DCGX). Alternatively, the image sensor may control the pixels in HCG mode by turning off both the overflow transistor (SOF) and the conversion gain transistor (DCGT) so that photocharges generated and overflowed from the photodiode (PD) accumulate only in the capacitor (CFD) of the floating diffusion node (FD).

[0088] Referring to FIG. 9, a pixel (PXa') may include a photodetection circuit (110a') and a pixel signal generation circuit (120') that outputs a first pixel signal (PXS1) and a second pixel signal (PXS2) according to a detection signal (DS) output from the photodetection circuit (110a'). The photodetection circuit (110a') may include a photodiode (PD), a transfer transistor (TX), a reset transistor (RX), a source follower (SF), a precharge transistor (PCX), an overflow transistor (SOFa), and a conversion gain transistor (DCGX).

[0089] The overflow transistor (SOFa) can electrically connect or electrically disconnect the floating diffusion node (FD) and the reset node (NR) in response to an overflow control signal (OFS) output from the pixel driver (200 in FIG. 1).

[0090] In an overflow operation mode, the image sensor can control pixels by turning on the conversion gain transistor (DCGT), the overflow transistor (SOFa), and the first sampling transistor (SAMP1), and turning off the precharge transistor (PCX), so that photocharges generated and overflowed from the photodiode (PD) are accumulated in the capacitor (CFD) of the floating diffusion node (FD), the capacitor (CDCG) of the conversion gain transistor (DCGX), and the first capacitor (C1') of the pixel signal generation circuit (120'). Alternatively, in an LCG mode, the image sensor can control pixels by turning off the overflow transistor (SOFa) and turning on the conversion gain transistor (DCGT), so that photocharges generated and overflowed from the photodiode (PD) are accumulated in the capacitor (CFD) of the floating diffusion node (FD) and the capacitor (CDCG) of the conversion gain transistor (DCGX). Alternatively, the image sensor can control the pixels in HCG mode by turning off both the overflow transistor (SOFa) and the conversion gain transistor (DCGT) so that photocharges generated and overflowed from the photodiode (PD) accumulate only in the capacitor (CFD) of the floating diffusion node (FD).

[0091] Referring to FIGS. 8 and 9, the image sensor according to the present disclosure can increase the equivalent capacitance of a floating diffusion node (FD) at high illumination and decrease the equivalent capacitance of a floating diffusion node (FD) at low illumination by turning the overflow transistor (SOF, SOFa) on / off, and can secure a wide dynamic range without increasing the area of ​​the pixel (PX). Additionally, since the pixel (PX') further includes a conversion gain transistor (DCGX), the image sensor can operate in an overflow mode, an LCG mode, and an HCG mode by controlling the on / off of the overflow transistor (SOF, SOFa) and the conversion gain transistor (DCGX).

[0092] FIGS. 10 and 11 are block diagrams illustrating pixels included in an image sensor according to an embodiment of the present disclosure. The pixels (PXb', PXc') described in FIGS. 10 and 11 are examples of pixels capable of global shutter operation, and the image sensor according to the present disclosure is not limited to the circuit configuration of the pixels (PXb', PXc'). It will be obvious that the circuit configuration of the pixel signal generation circuit (120') included in each of the pixels (PXb', PXc') can be varied in various ways.

[0093] The reset control signal (RS), conversion gain control signal (DCGS), transmission control signal (TS), overflow control signal (OFS), precharge control signal (PC), precharge selection control signal (PSEL), sampling control signals (SAMPS1, SAMPS2), and selection control signal (SEL') described in FIGS. 10 and 11 may be included in the control signals (CTRL') of FIG. 7. In the description of FIGS. 10 and 11, redundant descriptions of symbols identical to those in FIGS. 8 and 9 will be omitted.

[0094] Referring to FIG. 10, a pixel (PXb') may include a light detection circuit (110') and a pixel signal generation circuit (120b') that outputs a pixel signal (PXS) according to a detection signal (DS) output from the light detection circuit (110'). The pixel signal generation circuit (120b') may include a precharge select transistor (PSEL), a first sampling transistor (SAMP1), a second sampling transistor (SAMP2), a first capacitor (C1'), a second capacitor (C2'), a source follower (SF'), and a select transistor (SX').

[0095] The precharge select transistor (PSX) can be connected between the output node (NO) of the photodetection circuit (110') and the sensing node (SO) of the photodetection circuit (110b'), and can reset the sensing node (NS) by turning it on or off according to the precharge select control signal (PSEL).

[0096] The first sampling transistor (SAMP1) can be connected to a sensing node (NS). The first sampling transistor (SAMP1) can be turned on / off according to a first sampling control signal (SAMPS1), thereby allowing charge corresponding to the detection signal (DS) to be accumulated in the first capacitor (C1'). For example, charge corresponding to the photocharge accumulation operation can be accumulated in the first capacitor (C1').

[0097] The second sampling transistor (SAMP2) can be connected to the sensing node (NS). The second sampling transistor (SAMP2) can be turned on / off according to the second sampling control signal (SAMPS2), thereby allowing charge corresponding to the detection signal (DS) to be accumulated in the second capacitor (C2'). For example, charge corresponding to the photocharge accumulation operation can be accumulated in the second capacitor (C2'). For example, charge corresponding to the reset operation of the floating diffusion node (FD) can be accumulated in the second capacitor (C2').

[0098] The source follower (SF') can amplify the potential change at the sensing node (NS) to output a pixel signal (PXS), and the select transistor (SX') can output the pixel signal (PXS) to the column line (CL) in response to the select control signal (SEL'). The pixel signal (PXS) can output an image signal (SIG) corresponding to the photocharge accumulation operation and a reset signal (RST) corresponding to the reset operation for the floating diffusion node (FD).

[0099] The image sensor according to the present disclosure can control pixels in an overflow operation mode by turning on the conversion gain transistor (DCGT), the overflow transistor (SOF), the precharge select transistor (PSX), and the first sampling transistor (SAMP1), and turning off the precharge transistor (PCX), so that photocharges generated and overflowed from the photodiode (PD) are accumulated in the capacitor (CFD) of the floating diffusion node (FD), the capacitor (CDCG) of the conversion gain transistor (DCGX), and the first capacitor (C1') of the pixel signal generation circuit (120b'). However, not limited thereto, the conversion gain transistor (DCGT) may remain in an off state in the overflow operation mode.

[0100] Alternatively, the image sensor may control the pixels in LCG mode by turning off the overflow transistor (SOF) and turning on the conversion gain transistor (DCGT) so that photocharges generated and overflowed from the photodiode (PD) accumulate in the capacitor (CFD) of the floating diffusion node (FD) and the capacitor (CDCG) of the conversion gain transistor (DCGX). Alternatively, the image sensor may control the pixels in HCG mode by turning off both the overflow transistor (SOF) and the conversion gain transistor (DCGT) so that photocharges generated and overflowed from the photodiode (PD) accumulate only in the capacitor (CFD) of the floating diffusion node (FD).

[0101] Referring to FIGS. 10 and FIGS. 11, the photodetection circuit (110c') may include a pixel (PXb'), a photodetection circuit (110a'), and a pixel signal generation circuit (120b') that outputs a pixel signal (PXS) according to a detection signal (DS) output from the photodetection circuit (110a'). The image sensor according to the present disclosure can increase the equivalent capacitance of a floating diffusion node (FD) at high illumination and decrease the equivalent capacitance of a floating diffusion node (FD) at low illumination by turning an overflow transistor (SOF, SOFa) on / off, and can secure a high dynamic range without increasing the area of ​​the pixel (PX). Additionally, since the pixel (PX') further includes a conversion gain transistor (DCGX), the image sensor can operate in an overflow mode, LCG mode, and HCG mode by controlling the on / off of the overflow transistors (SOF, SOFa) and the conversion gain transistor (DCGX).

[0102] FIG. 12 is a block diagram of an electronic device including a multi-camera module. FIG. 13 is a detailed block diagram of the camera module of FIG. 12. FIG. 13 describes the detailed configuration of the camera module (1100b), but the following description may be applied equally to other camera modules (1100a, 1100c) according to the embodiment.

[0103] Referring to FIG. 12, the electronic device (1000) may include a camera module group (1100), an application processor (1200), a PMIC (1300), and an external memory (1400). The camera module group (1100) may include a plurality of camera modules (1100a, 1100b, 1100c). Although an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged is shown in the drawing, the embodiments are not limited thereto.

[0104] Referring to FIGS. 12 and 13, the camera module (1100b) may include a prism (1105), an optical path folding element (OPFE, hereinafter referred to as "OPFE") (1110), an actuator (1130), an image sensing device (1140), and a storage unit (1150).

[0105] The prism (1105) may modify the path of light (L) incident from the outside by including a reflective surface (1107) of a light-reflecting material. The OPFE (1110) may include, for example, groups of m (where m is a natural number) optical lenses. The actuator (1130) may move the OPFE (1110) or the optical lenses (hereinafter referred to as optical lenses) to a specific position.

[0106] The image sensing device (1140) may include an image sensor (1142), control logic (1144), and memory (1146). The image sensor (1142) may sense an image of a sensing target using light (L) provided through an optical lens. The image sensor (1142) may be the image sensor (10) described in FIG. 1 and may be the image sensor (10') described in FIG. 7.

[0107] The control logic (1144) can control the overall operation of the camera module (1100b). For example, the control logic (1144) can control the operation of the camera module (1100b) according to a control signal provided through the control signal line (CSLb).

[0108] In an exemplary embodiment, one of the plurality of camera modules (1100a, 1100b, 1100c) camera module (e.g., 1100b) is a camera module in the form of a folded lens including the previously described prism (1105) and OPFE (1110), and the remaining camera modules (e.g., 1100a, 1100b) may be camera modules in the form of a vertical camera module that do not include the prism (1105) and OPFE (1110), but the embodiments are not limited thereto.

[0109] In an exemplary embodiment, one of the plurality of camera modules (1100a, 1100b, 1100c) (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor (1200) may generate a 3D depth image by merging image data values ​​provided from this depth camera with image data values ​​provided from other camera modules (e.g., 1100a or 1100b).

[0110] In an exemplary embodiment, at least two of the plurality of camera modules (1100a, 1100b, 1100c) may have different field of view angles. In this case, for example, the optical lenses of at least two of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited thereto.

[0111] In addition, in an exemplary embodiment, the viewing angles of each of the plurality of camera modules (1100a, 1100b, 1100c) may differ from one another. In this case, the optical lenses included in each of the plurality of camera modules (1100a, 1100b, 1100c) may also differ from one another, but are not limited thereto.

[0112] In an exemplary embodiment, each of the plurality of camera modules (1100a, 1100b, 1100c) may be physically separated from one another. That is, instead of the plurality of camera modules (1100a, 1100b, 1100c) dividing and using the sensing area of ​​a single image sensor (1142), an independent image sensor (1142) may be placed inside each of the plurality of camera modules (1100a, 1100b, 1100c).

[0113] Referring again to FIG. 12, the application processor (1200) may include an image processing device (1210), a memory controller (1220), and an internal memory (1230). The application processor (1200) may be implemented separately from a plurality of camera modules (1100a, 1100b, 1100c). For example, the application processor (1200) and the plurality of camera modules (1100a, 1100b, 1100c) may be implemented separately from each other as separate semiconductor chips.

[0114] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator (1214), and a camera module controller (1216).

[0115] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0116] Image data values ​​generated from each camera module (1100a, 1100b, 1100c) can be provided to corresponding sub-image processors (1212a, 1212b, 1212c) through separate image signal lines (ISLa, ISLb, ISLc). For example, an image data value generated from camera module (1100a) can be provided to sub-image processor (1212a) through image signal line (ISLa), an image data value generated from camera module (1100b) can be provided to sub-image processor (1212b) through image signal line (ISLb), and an image data value generated from camera module (1100c) can be provided to sub-image processor (1212c) through image signal line (ISLc). The transmission of such image data values ​​can be performed, for example, using a Camera Serial Interface (CSI) based on MIPI (Mobile Industry Processor Interface), but the embodiments are not limited thereto.

[0117] Image data values ​​provided to each sub-image processor (1212a, 1212b, 1212c) may be provided to an image generator (1214). The image generator (1214) may generate an output image using image data provided from each sub-image processor (1212a, 1212b, 1212c) according to image generating information or a mode signal.

[0118] Specifically, the image generator (1214) can generate an output image by merging at least some of the image data values ​​generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal. Additionally, the image generator (1214) can generate an output image by selecting any one of the image data values ​​generated from camera modules (1100a, 1100b, 1100c) having different viewing angles according to image generation information or a mode signal.

[0119] The camera module controller (1216) can provide control signals to each camera module (1100a, 1100b, 1100c). The control signals generated from the camera module controller (1216) can be provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0120] The application processor (1200) stores received image data values, that is, encoded data, in a memory (1230) provided internally or in a storage (1400) outside the application processor (1200), and subsequently reads the encoded data from the memory (1230) or the storage (1400) to decode it, and can display an image generated based on the decoded image data values. For example, a corresponding sub-processor among a plurality of sub-processors (1212a, 1212b, 1212c) of the image processing device (1210) can perform decoding, and can also perform image processing on the decoded image data values.

[0121] The PMIC (1300) can supply power, for example, power voltage, to each of the plurality of camera modules (1100a, 1100b, 1100c). For example, the PMIC (1300) can supply first power to the camera module (1100a) through a power signal line (PSLa), supply second power to the camera module (1100b) through a power signal line (PSLb), and supply third power to the camera module (1100c) through a power signal line (PSLc), under the control of the application processor (1200).

[0122] Up to this point, the present invention has been described with reference to the embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

Claim 1 An image sensor comprising a plurality of pixels, wherein each of the plurality of pixels comprises: a photodetection circuit comprising a photodiode and generating a detection signal; and an analog-to-digital converter that converts the detection signal using a ramp signal, wherein the photodetection circuit comprises: a floating diffusion node having a parasitic capacitor that accumulates photocharge generated in the photodiode; and an overflow transistor that electrically connects the floating diffusion node and a first internal capacitor of the analog-to-digital converter to each other, wherein the overflow transistor is connected between the floating diffusion node and the first internal capacitor. Claim 2 An image sensor according to claim 1, wherein the light detection circuit further includes a source follower that amplifies a voltage change of the floating diffusion node and outputs it to an output node, and the overflow transistor is connected between the floating diffusion node and the output node. Claim 3 An image sensor according to claim 2, wherein the light detection circuit further comprises: a reset transistor that resets the floating diffusion node to a power supply voltage; and a conversion gain transistor connected between the reset node connected to one end of the reset transistor and the floating diffusion node. Claim 4 delete Claim 5 An image sensor according to claim 1, wherein the analog-to-digital converter comprises: a second internal capacitor into which the ramp signal is input; and a comparator that compares the detection signal received through the first internal capacitor and the ramp signal received through the second internal capacitor with each other and outputs a comparison result signal. Claim 6 An image sensor according to claim 1, characterized in that, during the period in which the overflow transistor is in the ON state, the ramp signal is generated to increase at a constant slope. Claim 7 An image sensor according to claim 1, wherein the light detection circuit further includes a selection transistor connected to an output node where the detection signal is output, and wherein the selection transistor is in an off state during the period in which the overflow transistor is in an on state. Claim 8 An image sensor that operates in a plurality of modes according to illumination, comprising: a pixel array including a plurality of pixels each including a light detection circuit and an analog-to-digital converter that converts a detection signal detected by the light detection circuit; and a pixel driver that provides an overflow control signal to the pixel array, wherein in response to the overflow control signal, a photocharge generated by the light detection circuit is stored in an internal capacitor included in the analog-to-digital converter, and the light detection circuit includes an overflow transistor connected between a floating diffusion node of the light detection circuit where the photocharge is accumulated and the internal capacitor, and controlled by the overflow control signal. Claim 9 An image sensor according to claim 8, wherein in an overflow operation mode according to a high illumination environment, the pixel driver generates an overflow control signal such that the photocharge generated in the photodetection circuit is stored in an internal capacitor included in the analog-to-digital converter. Claim 10 An image sensor according to claim 8, wherein in a high conversion gain (HCG) mode according to a low light environment, the pixel driver generates an overflow control signal to electrically isolate the floating diffusion node of the photodetection circuit where the photocharge is accumulated and the internal capacitor included in the analog-to-digital converter. Claim 11 delete Claim 12 An image sensor according to claim 8, wherein the photodetection circuit further comprises: a floating diffusion node having a parasitic capacitor that accumulates the photocharge; a reset transistor that resets the floating diffusion node to a power supply voltage; and a conversion gain transistor connected between the reset node and the floating diffusion node, the reset node being connected to one end of the reset transistor. Claim 13 delete Claim 14 An image sensor according to claim 8, wherein the analog-to-digital converter converts the detection signal into a digital signal using a ramp signal, and the analog-to-digital converter converts the detection signal according to the photocharge stored in the internal capacitor into a digital signal, and then converts the detection signal according to the state in which the photodetection circuit is reset. Claim 15 An image sensor comprising a plurality of pixels, wherein each of the plurality of pixels comprises: a photodetector circuit that generates a detection signal and includes a capacitor that stores a charge corresponding to the detection signal and a pixel signal generating circuit that generates a pixel signal corresponding to the detection signal; wherein the photodetector circuit comprises: a floating diffusion node that accumulates a photocharge generated from the photodetector; and an overflow transistor that electrically connects the floating diffusion node and the capacitor of the pixel signal generating circuit to each other; wherein the pixel signal generating circuit comprises: a first capacitor that stores a charge corresponding to the voltage of the floating diffusion node in which the photocharge is accumulated; a second capacitor that stores a charge corresponding to the voltage of the reset floating diffusion node; and at least one source follower that outputs a first pixel signal according to the amount of charge charged in the first capacitor or a second pixel signal according to the amount of charge charged in the second capacitor. Claim 16 An image sensor according to claim 15, wherein the photodetection circuit further includes a source follower that amplifies a voltage change of the floating diffusion node and outputs it to an output node, and the overflow transistor is connected between the floating diffusion node and the output node. Claim 17 An image sensor according to claim 16, wherein the light detection circuit further comprises: a reset transistor that resets the floating diffusion node to a power supply voltage; and a conversion gain transistor connected between the reset node connected to one end of the reset transistor and the floating diffusion node. Claim 18 An image sensor according to claim 15, wherein the photodetection circuit further comprises: a source follower that amplifies a voltage change of the floating diffusion node and outputs it to an output node; a reset transistor that resets the floating diffusion node to a power supply voltage; and a conversion gain transistor connected between the reset node and the floating diffusion node connected to one end of the reset transistor, wherein the overflow transistor is connected between the reset node and the output node. Claim 19 delete Claim 20 An image sensor according to claim 15, wherein the image sensor operates in a plurality of operation modes according to illuminance, and in a high-illumination environment, photocharges generated in the photodetection circuit are stored in the floating diffusion node and the first capacitor.

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