Manufacturing method of semiconductor test device

Abstract

The present invention relates to a method for manufacturing a semiconductor test device. A method for manufacturing a semiconductor test device according to one embodiment of the present invention is a method for manufacturing a semiconductor test device that is interposed between semiconductor memories or between a semiconductor memory and an interposer to perform a test of electrical connection, comprising: (a) a step of preparing a connector in which a membrane portion and a holder portion are connected, the membrane portion having a plurality of opening patterns; (b) a step of forming a conductive thin film layer on at least the surface of the membrane portion; and (c) a step of removing a portion of the conductive thin film layer to mutually insulate at least adjacent opening patterns.

Description

Technology Field

[0001] The present invention relates to a method for manufacturing a semiconductor test device. More specifically, it relates to a method for manufacturing a semiconductor test device capable of performing a test by contacting a microbump of a semiconductor device. Background Technology

[0002] As semiconductor technology advances rapidly, there is an increasing demand for higher integration and performance in packaging technology for semiconductor integrated circuits. Consequently, technologies regarding three-dimensional structures that vertically stack multiple semiconductor chips are developing in various ways, moving away from two-dimensional structures in which semiconductor chips containing integrated circuits are arranged planarly on a printed circuit board (PCB) using wires or bumps.

[0003] This three-dimensional structure can be realized through a stacked semiconductor device that vertically stacks multiple semiconductor chips. Then, the semiconductor chips mounted vertically in this manner are electrically connected to each other through Through Silicon Via (TSV) and mounted on a substrate for a semiconductor package.

[0004] In the case of stacked semiconductor devices, microbumps can be placed to facilitate physical contact between stacked semiconductor chips. Since various signals are transmitted between the stacked semiconductor chips through TSVs and bumps, a test is required to verify whether they are properly connected. The problem to be solved

[0005] Accordingly, the present invention has been devised to solve the various problems of the prior art as described above, and aims to provide a semiconductor test device capable of performing a test by contacting a microbump of a semiconductor device and a method for manufacturing the same.

[0006] In addition, the present invention aims to provide a semiconductor test device and a method for manufacturing the same that can prevent damage to microbumps and perform connection in a precise alignment state.

[0007] However, these tasks are exemplary and do not limit the scope of the invention. means of solving the problem

[0008] The above objective of the present invention is achieved by a method for manufacturing a semiconductor test device that is interposed between semiconductor memories or between a semiconductor memory and an interposer to perform a test of electrical connection, comprising: (a) preparing a connector having a plurality of opening patterns connected to a membrane portion and a holder portion; (b) forming a conductive thin film layer on at least the surface of the membrane portion; and (c) removing a portion of the conductive thin film layer to mutually insulate at least adjacent opening patterns.

[0009] And, the above objective of the present invention is achieved by a method for manufacturing a semiconductor test device that is interposed between semiconductor memories or between a semiconductor memory and an interposer to perform a test of electrical connection, comprising: (a) preparing a connector having a plurality of opening patterns and a membrane portion and a holder portion connected thereto; (b) forming a sacrificial layer on at least the surface of the membrane portion; (c) forming a conductive thin film layer on the surface of the membrane portion and the sacrificial layer; and (d) removing the sacrificial layer and removing a portion of the conductive thin film layer to mutually insulate at least adjacent opening patterns.

[0010] The above step (a) may include: (a1) preparing a support member which is a conductive substrate and includes a first surface and a second surface opposite to the first surface; (a2) forming a metal thin film portion having a plurality of opening patterns on the first surface of the support member by electroforming; (a3) ​​forming the holder portion by etching the remainder excluding the edge portion of the support member on the second surface of the support member; and (a4) forming an insulating layer portion of an insulating material on the surface of the metal thin film portion to form the membrane portion.

[0011] In step (c) above, a portion of the conductive thin film layer may be removed to form an electrical connection path from the top to the bottom of each of the opening patterns.

[0012] The conductive thin film layer can be formed on the side of each of the above-mentioned opening patterns.

[0013] The conductive thin film layer may be further formed horizontally at the upper side of the opening pattern or further formed horizontally at the lower side of the opening pattern.

[0014] The method may further include a step of reducing the thickness of the holder portion prior to step (a), between step (a) and step (b), or between step (b) and step (c).

[0015] The thickness of the holder portion can be reduced to 100㎛ to 300㎛.

[0016] The above step (c) may include: (c1) the membrane portion including a second surface connected to the holder portion and a first surface opposite to the second surface, and forming a first etch prevention pattern on at least the opening pattern on the first surface; (c2) etching a portion other than the conductive thin film layer covered by the first etch prevention pattern on the first surface; (c3) forming a second etch prevention pattern on the second surface; and (c4) etching a portion other than the conductive thin film layer covered by the second etch prevention pattern on the second surface.

[0017] In step (c1) or step (c2) above, a template may be placed at the lower part of the holder portion to support the holder portion.

[0018] In step (c3) above, a second template may be attached to the first surface of the membrane portion via a temporary adhesive portion, and the second template may be supported by the membrane portion.

[0019] The connector of step (a) above further includes a plurality of grid portions extending along a first horizontal direction or a second horizontal direction perpendicular to the first horizontal direction in the hollow region of the holder portion, and the grid portions partition a plurality of cell regions, and after the step of removing a portion of the conductive thin film layer to mutually insulate at least adjacent opening patterns, the grid portions can be cut to provide the semiconductor test device of the cell region unit size.

[0020] The above metal thin film portion may be made of at least one of invar, super invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy, and nickel.

[0021] The above conductive thin film layer may include at least one material among Cu, Ag, Au, Pt, Pd, and Sn.

[0022] The hollow region of the holder portion is provided as a space for accommodating the semiconductor memory, and each of the opening patterns can correspond to a plurality of micro bumps formed on the lower part of the semiconductor memory.

[0023] The area of ​​the semiconductor memory corresponds to the size of a single cell or multiple cells, or to the size of a silicon wafer, and the horizontal area of ​​the hollow region of the holder part may be provided as an area larger than the semiconductor memory.

[0024] The width of the above opening pattern may be 5㎛ to 100㎛.

[0025] The holder portion is formed from a silicon wafer, and the metal thin film portion is formed by electroforming on the silicon wafer, and the metal thin film portion includes Invar or Super Invar material, and a connecting portion including Ni and Si, or a connecting portion including Fe, Ni and Si, may be interposed between the support portion and the mask.

[0026] The metal thin film portion may include: a first metal thin film portion having a first width of the opening pattern; and a second metal thin film portion having a second width of the opening pattern that is narrower than the first width.

[0027] A portion of the second metal thin film that protrudes further in the lateral direction than the first metal thin film portion may be provided as a cantilever portion.

[0028] In step (d) above, when the sacrificial layer is lifted off and removed, the conductive thin film layer formed on the sacrificial layer can be lifted off and removed together. Effects of the invention

[0029] According to the present invention configured as described above, there is an effect of being able to perform a test by contacting the microbump of a semiconductor device.

[0030] In addition, according to the present invention, there is an effect of preventing damage to microbumps and performing a connection in a precise alignment state.

[0031] Of course, the scope of the present invention is not limited by these effects. Brief explanation of the drawing

[0032] FIG. 1 is a schematic diagram showing a semiconductor chip structure according to one embodiment. FIG. 2 is a schematic cross-sectional view showing a semiconductor chip structure according to one embodiment. FIG. 3 is a schematic diagram showing a semiconductor test device according to a first embodiment of the present invention. FIGS. 4 and 5 are schematic diagrams showing a form of testing the electrical connection between a stacked semiconductor memory and an interposer by applying a semiconductor test device according to one embodiment of the present invention. FIGS. 6 and 7 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to one embodiment of the present invention. FIGS. 8 and 9 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to another embodiment of the present invention. FIG. 10 is a schematic diagram showing a semiconductor test device according to a second embodiment of the present invention. FIGS. 11 and 12 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to another embodiment of the present invention. FIG. 13 is a schematic diagram showing a semiconductor test device according to a third embodiment of the present invention. FIGS. 14 to 15 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to a third embodiment of the present invention. FIGS. 16 and 17 are schematic diagrams showing the form of a semiconductor test device according to the fourth to sixth embodiments of the present invention. FIG. 18 is a schematic diagram showing a semiconductor test device according to the seventh embodiment of the present invention. FIG. 19 is a schematic diagram showing a semiconductor test device according to the eighth embodiment of the present invention. FIGS. 20 and 21 are schematic cross-sectional views showing the shape of an opening pattern and a conductive thin film layer according to various embodiments of the present invention. FIG. 22 is a schematic plan view showing an opening pattern and a microbump and contact shape according to various embodiments of the present invention. FIG. 23 is a schematic diagram showing the manufacturing process of a semiconductor test device according to the seventh embodiment of the present invention. FIG. 24 is a schematic side cross-sectional view and a schematic plan view showing a conductive cantilever portion protruding between opening patterns according to one embodiment of the present invention. FIG. 25 is a schematic diagram showing a form of controlling a conductive cantilever part by applying an external magnetic force according to an embodiment of the present invention. FIGS. 26 to 33 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to the ninth embodiment of the present invention. FIGS. 34 to 37 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to the 10th embodiment of the present invention. Figure 38 is a cross-sectional micrograph of a metal film produced by electroplating according to a comparative example. FIG. 39 is a cross-sectional microscope image of a metal thin film portion produced by electroplating according to one embodiment of the present invention. FIG. 40 is a schematic cross-sectional view showing a metal film produced by electroplating according to a comparative example. FIG. 41 is a schematic side cross-sectional view showing a metal thin film portion produced by electroplating according to one embodiment of the present invention. FIG. 42 is a cross-sectional micrograph of a metal thin film portion formed by electroplating on a support portion according to one embodiment of the present invention. FIGS. 43 and 44 are drawings showing line data and composition in the depth direction of a metal thin film portion formed by electroplating on a support portion according to one embodiment of the present invention. FIG. 45 is an enlarged side cross-sectional view of FIG. 41 (b), which is a schematic side cross-sectional view showing the crystal shape of a metal thin film portion before and after a planarization process according to one embodiment of the present invention. FIG. 46 is a planar microscope image of a metal thin film portion after a planarization process according to one embodiment of the present invention. FIG. 47 is a schematic diagram showing a semiconductor test device according to the 11th embodiment of the present invention. FIGS. 48 to 50 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to the 11th embodiment of the present invention. FIG. 51 is a schematic diagram showing a form of testing electrical connections by applying a semiconductor test device according to the 11th embodiment of the present invention. FIGS. 52 to 54 are schematic diagrams illustrating a method for manufacturing a semiconductor test device according to the 12th embodiment of the present invention. FIGS. 55 to 56 are schematic diagrams illustrating another method of manufacturing a semiconductor test device according to the 12th embodiment of the present invention. FIG. 57 is a schematic diagram showing the form of a semiconductor test device according to the 13th to 14th embodiments of the present invention. Specific details for implementing the invention

[0033] The following detailed description of the invention refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that various embodiments of the invention are different but need not be mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in relation to one embodiment. It should also be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the invention. Accordingly, the following detailed description is not intended to be limiting, and the scope of the invention is limited only by the appended claims, including all equivalents to those claimed therein, provided they are appropriately described. Similar reference numerals in the drawings refer to the same or similar functions across various aspects, and lengths, areas, thicknesses, etc., and shapes may be exaggerated for convenience.

[0034] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings in order to enable a person skilled in the art to easily practice the present invention.

[0035] FIG. 1 is a schematic diagram showing a semiconductor chip structure according to one embodiment. FIG. 2 is a schematic cross-sectional view showing a semiconductor chip structure according to one embodiment.

[0036] Referring to FIGS. 1 and 2, a semiconductor device (10) according to one embodiment may include a base substrate (11), a package substrate (12), an interposer (13), a first semiconductor package (14), and a second semiconductor package (15). The semiconductor device (10) may be implemented as a package, which is a system for assembling heterogeneous semiconductor chips into a single package. Each of the semiconductor chips assembled into a single package in the semiconductor device (10) may correspond to a semiconductor package. For example, the semiconductor device (10) may be provided as a semiconductor package in which AI semiconductor chips are combined.

[0037] The base substrate (11) and the package substrate (12) may be provided as printed circuit boards (PCBs) having circuit patterns. For example, the base substrate (11) may be provided as the base of a graphics card. The base substrate (11) may be equipped with PCI Express, a display connector, etc. Bumps (B1) may be interposed between the base substrate (11) and the package substrate (12) to transmit electrical signals.

[0038] An interposer (13) may be provided to accommodate a plurality of semiconductor packages (14, 15). For example, a plurality of upper pads (not shown) may be formed on the silicon interposer (13), and the first semiconductor package (14) and the second semiconductor package (15) may be electrically connected through these upper pads. The first semiconductor package (14) and the second semiconductor package (15) may be stacked on a package substrate (12) via the interposer (13).

[0039] The first semiconductor package (14) may be provided as a processor. The first semiconductor package (14) may be stacked on an interposer (13). For example, the first semiconductor package (14) may be electrically connected on the interposer (13) through the combination of a micro bump (MB1) of the first semiconductor package (14), which is a GPU, and an upper pad (not shown) of the interposer (13).

[0040] The second semiconductor package (15) may be provided as a memory package. For example, the second semiconductor package (15) may be provided as a High Bandwidth Memory (HBM), which is a stacked semiconductor memory. The second semiconductor package (15) may include a memory die (16) and a controller die (17) stacked in multiple layers. The multiple memory dies (16) and the controller die (17) may transmit electrical signals through Through Silicon Via (TSV; EL). The second semiconductor package (15) may be coupled to an upper pad (not shown) of an interposer (13) through a microbump (MB2) on the bottom of the second semiconductor package (15), and the second semiconductor package (15) and the interposer (13) may be electrically connected.

[0041] High-Blockchain Memory (HBM) can be manufactured into individual dies and chips through dicing after being fabricated and tested in a stacked wafer form. Conventionally, testing was performed on the stacked wafers prior to dicing. After dicing, it becomes difficult to make contact with individual dies and chips using probes. Conventional probes are equipped with pins of approximately 100 µm. However, the microbumps on the underside of increasingly integrated HBMs have a size and pitch ranging from several to tens of µm, making it difficult to make contact with conventional probes. Components that are difficult to contact with probes may undergo testing after being assembled into a single package; however, this can lead to a problem where the remaining normal components must be discarded due to a few defective parts.

[0042] In addition, the microbumps (MB2) located on the underside of individual stacked semiconductor memories are small in size and can be easily deformed by pressure. Consequently, when attempting to test individual stacked semiconductor memories, there is a problem in that some of the microbumps may be damaged, pressed, or misaligned during the compression process, which can lead to product defects. Therefore, there is a need for a semiconductor test device capable of preventing damage to the microbumps.

[0043] Meanwhile, in addition to individual stacked semiconductor memories, there is a possibility that some microbumps may be damaged when testing in a stacked wafer state. Accordingly, there is a need for a semiconductor test device capable of performing tests by making contact that accurately aligns the microbumps without damaging them.

[0044] The present invention is characterized by providing a semiconductor test device capable of preventing damage to microbumps and performing tests by contacting microbumps, and a method for manufacturing the same.

[0045] FIG. 3 is a schematic diagram showing a semiconductor test device according to a first embodiment of the present invention. FIG. 4 and 5 are schematic diagrams showing a form of testing the electrical connection between a stacked semiconductor memory and an interposer by applying a semiconductor test device according to an embodiment of the present invention.

[0046] Referring to FIGS. 3 to 5, a semiconductor test device (100: 100-1) according to an embodiment of the present invention can be interposed between a stacked semiconductor memory (15) and an interposer (13') to perform a test of electrical connections. Hereinafter, the second semiconductor package (15) described above is assumed to be a stacked semiconductor memory (HBM) for explanation. Meanwhile, FIGS. 3 to 5 shows three electrical path sections (130) for convenience of explanation, but it should be noted that the electrical path sections (130) can be formed to correspond to the number of lower microbumps (MB: MB2) of the stacked semiconductor memory.

[0047] Meanwhile, for convenience of explanation, the present invention exemplifies the use of a semiconductor test device (100) between a stacked semiconductor memory (15) and an interposer (13'); however, if the semiconductor memory requires testing of electrical connections, it can be applied to DRAM or the like, not necessarily HBM. Additionally, the semiconductor test device (100) may be interposed between the semiconductor memory and the interposer (13'), or the semiconductor test device (100) may be interposed between the semiconductor memory and the semiconductor memory to test electrical connections. Furthermore, the interposer (13') can be understood as a concept including a support substrate that is positioned to face the semiconductor memory and on which electrical connections are performed.

[0048] A semiconductor test device (100: 100-1) according to the first embodiment may include a membrane portion (110: 110-1) and a holder portion (150). The membrane portion (110) includes a plurality of opening patterns (P), and an electrical connection path may be provided from the top to the bottom of each opening pattern (P). This electrical connection path may be provided through an electrical path portion (130) comprising a conductive material.

[0049] According to one embodiment, the membrane portion (110) may be formed of an insulating material. Each opening pattern (P) formed in the membrane portion (110) may be in one-to-one contact with the microbumps (MB: MB2) on the lower part of the stacked semiconductor memory (15). Accordingly, the membrane portion (110) must be able to form a plurality of opening patterns (P) at a level of several to tens of micrometers. In addition, since the temperature may rise due to electrical contact during testing, the membrane portion (110) may use a material that has low thermal expansion and contraction due to temperature changes, that is, a material with a low coefficient of thermal expansion (CTE). In addition, the membrane portion (110) may use a flexible material that is particularly durable, has no deformation in the X and Y directions, and reduces the possibility of damage to the microbumps (MB: MB2). In consideration of this, the membrane portion (110) may use insulating materials such as polyimide, rubber, resin, Teflon, polymer, curable photoresist, inorganic insulator, and organic insulator.

[0050] A plurality of opening patterns (P) may be formed along the thickness direction of the membrane portion (110). The plurality of opening patterns (P) may be formed at regular intervals along the horizontal direction (XY plane direction). For example, the pitch between the opening patterns (P) may be several tens of µm, for example, about 10 to 150 µm, and the width (W1) of the opening pattern (P) may be smaller, about 5 to 100 µm. About tens of thousands of microbumps (MB2) are arranged on the bottom of a stacked semiconductor memory (15), and the opening patterns (P) may be formed to correspond to these microbumps (MB2). An area where about tens of thousands of opening patterns (P) are clustered along the XY plane direction is referred to as a cell portion (C). In order to form opening patterns (P) with such fine width (W1) and spacing, the overall thickness of the membrane portion (110) must also be thin. For example, the membrane portion (110) may be provided in the shape of a thin film with a thickness (T1) of about 5 to 50 μm.

[0051] The holder portion (150) may be connected to the membrane portion (110) to provide fixed support for the membrane portion (110). The membrane portion (110) and the holder portion (150) may be connected to each other through an adhesive means or by welding. The holder portion (150) may be in the shape of a frame in which the interior is provided as a hollow area (R). The hollow area (R) may be provided as a space for accommodating a stacked semiconductor memory (15) to be tested. Accordingly, the hollow area (R) is preferably a rectangular shape to correspond to the shape of the stacked semiconductor memory (15), but is not limited thereto. As an example, the size (horizontal area) of the hollow area (R) may correspond to the size of the stacked semiconductor memory (15), which is (width) x (height) (several mm to tens of mm) x (several mm to tens of mm). As another example, the size of the hollow region (R) may correspond to the size of a stacked semiconductor memory including multiple cells / multiple dies or a silicon wafer, or may be provided with a larger size. The area of ​​the cell portion (C) may also correspond to the area of ​​the hollow region (R) described above.

[0052] The holder part (150) may be made of a material with a low coefficient of thermal expansion (CTE) so as not to cause thermal deformation. The holder part (150) may be made of invar, super invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy, quartz, glass, etc.

[0053] The membrane section (110) may be provided with an electrical connection path from the top to the bottom of each opening pattern (P), and the electrical connection path may be formed through an electrical path section (130) containing a conductive material.

[0054] For example, the electrical path (130) may include conductive materials such as conductive rubber, metal power composite, conductive metal, graphene, CNT (Carbon Nano Tube), quantum dot, and MLCC (Multilayer Ceramic Capacitor).

[0055] The electrical path portion (130) can be filled within the opening pattern (P). To ensure smooth contact with the microbump (MB2) of the stacked semiconductor memory (15) and to prevent excessive stress from being applied to the microbump (MB2), the path portion (130) may include an elastic matrix made of an elastic material. The elastic matrix may be made of materials such as polyimide, rubber, resin, or polymer.

[0056] Additionally, the electrical path section (130) must include a conductive material to provide an electrical connection path while having elasticity. For example, the electrical path section (130) may be provided with a plurality of conductive particles, a plurality of rods, a plurality of wires, a plurality of balls, a plurality of flakes, etc. dispersed within an elastic matrix. The plurality of particles, rods, wires, balls, flakes, etc. may have sizes ranging from nanometer scale to several micrometer scale, and they may be interconnected within the elastic matrix to form an electrical connection path from the top to the bottom of the electrical path section (130).

[0057] Each electrical path section (130) is filled within each opening pattern (P) so as to be spaced apart from one another, thereby preventing the electrical path sections (130) from being shorted to one another. The electrical path sections (130) can be filled within the opening pattern (P) with a thickness equal to that of the membrane section (110). Alternatively, the electrical path sections (130) can be filled within the opening pattern (P) with a thickness greater than that of the membrane section (110) so as to protrude above the upper / lower surface of the membrane section (110). In this case, if the electrical path section (130) protrudes excessively above the upper / lower surface of the membrane section (110), contact stability may be reduced during the process of contacting and being pressed with the microbumps (MB2); therefore, it is preferable that the thickness of the electrical path section (130) be formed to be only thicker by a thickness of 50% or less of the thickness (T1) of the membrane section (110). Accordingly, there is an advantage that the microbumps (MB2) on the lower part of the stacked semiconductor memory (15) can be stably contacted only with the electrical path portion (130).

[0058] As shown in FIG. 4(a), a stacked semiconductor memory (15) requiring testing may be provided. A plurality of microbumps (MB: MB2) may be formed on the lower part of the stacked semiconductor memory (15). Subsequently, the stacked semiconductor memory (15) may be accommodated in a hollow region (R) provided by a holder portion (150) of a semiconductor test device (100: 100-1). The microbumps (MB) may each come into contact with the electrical path portions (130) of the semiconductor test device (100).

[0059] Next, as shown in FIG. 4(b), a test interposer (13') can be prepared. The test interposer (13') can also have connecting electrodes (CE), such as bumps and internal circuits, formed in the same way as the interposer (13). When a semiconductor test device (100) containing a stacked semiconductor memory (15) is placed on the test interposer (13'), the lower end of the electrical path portion (130) can come into contact with the connecting electrodes (CE).

[0060] Next, as shown in FIG. 5, a stacked semiconductor memory (15) can be pressed from above using a sponge pad (18) and a chuck (19). When stress is applied downward to the stacked semiconductor memory (15), the elastic matrix of the electrical path section (130) is pressed and can be electrically connected to the microbumps (MB). As the electrical path section (130) is slightly pressed by elasticity, all electrical path sections (130) and all microbumps (MB) can be stably contacted. When the electrical path section (130) is pressed, the conductivity increases as multiple conductive particles, rods, wires, balls, plates, etc. within the electrical path section (130) form new conductive paths, thereby allowing electrical signals to be transmitted from the top to the bottom of the electrical path section (130). Here, since the electrical path section (130) has elasticity, the stress applied to the microbumps (MB) can be minimized, thereby preventing damage to the microbumps (MB). Since an electrical connection can be made from the microbump (MB) through the electrical path section (130) to the test interposer (13'), a test of the stacked semiconductor memory (15) can be performed. In addition, a test package substrate (12') can be further connected to the bottom of the test interposer (13') to perform the test.

[0061] When the stress pressing on the stacked semiconductor memory (15) is released, the elastic matrix of the electrical path section (130) is restored to its original shape and the conductivity is lowered, thereby allowing the electrical connection with the microbump (MB) to be released. Here, the release of the electrical connection may include the meaning of terminating the test by releasing the contact between some of the electrical path sections (130) and some of the microbumps (MB).

[0062] FIGS. 6 and 7 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to one embodiment of the present invention.

[0063] Referring to FIG. 6(a), a support substrate (210) may be provided. The support substrate (210) may be made of a plate-shaped material such as glass, wafer, or quartz. Subsequently, a membrane portion (110') may be formed on the support substrate (210). Subsequently, to form an opening pattern (P) on the membrane portion (110'), a patterned etching-resistant pattern (220) may be formed on the membrane portion (110'). As an example, the etching-resistant pattern (220) may be made of photoresist, oxide, nitride, etc.

[0064] Next, referring to FIG. 6(b), the membrane portion (110') can be etched to form an opening pattern (P). Wet etching, dry etching, scribing, etc., can be used. After forming the opening pattern (P), the anti-etching pattern (220) can be removed and cleaned.

[0065] Next, referring to FIG. 6 (c), an electrical path portion (130) can be formed within the opening pattern (P). The electrical path portion (130) can be formed using methods such as printing, deposition, sputtering, plating, or spraying without limitation. The electrical path portion (130) can be formed to be the same thickness as or thicker than the thickness of the membrane portion (110).

[0066] Next, referring to FIG. 7 (d), a holder portion (150) can be connected to a membrane portion (110). The holder portion (150) can be connected by interposing an adhesive means on the edge portion of the membrane portion (110) where the opening pattern (P) is not formed, or the connection can be performed through welding, etc.

[0067] Next, referring to FIG. 7(e), the membrane portion (110) can be separated from the support substrate (210). Separation can be performed by applying heat, chemical treatment, applying ultrasound, or irradiating light at the interface between the membrane portion (110) and the support substrate (210). After separation of the support substrate (210) and the membrane portion (110), the membrane portion (110) is connected to the holder portion (150), and the manufacturing of the semiconductor test device (100) in which an electrical path portion (130) is formed in the opening pattern (P) can be completed.

[0068] FIGS. 8 and 9 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to another embodiment of the present invention.

[0069] Referring to FIG. 8(a), a support substrate (210') having a trench (TR) formed therein can be provided. The location where the trench (TR) is formed may correspond to the location where the opening pattern (P) or the electrical path portion (130) is to be formed. The depth of the trench (TR) formed may correspond to the height at which the electrical path portion (130) protrudes over the membrane portion (110).

[0070] Next, referring to FIG. 8(b), a membrane portion (110") can be formed on a support substrate (210'). A portion of the membrane portion (110") can be formed within a trench (TR) of the support substrate (210').

[0071] Next, referring to (c) of FIG. 8, in order to form an opening pattern (P) on the membrane portion (110), a patterned anti-etching pattern (not shown) [see 220 in FIG. 6] can be formed on the membrane portion (110). Subsequently, the membrane portion (110) can be etched to form the opening pattern (P). Wet etching, dry etching, scribing, etc., may be used. Alternatively, the opening pattern (P) on the membrane portion (110) can be formed by pressing the membrane portion (110) with a mold using imprinting without the need to form an anti-etching pattern.

[0072] Next, referring to FIG. 9 (d), an electrical path section (130) can be formed within the opening pattern (P). The electrical path section (130) can be formed using methods such as printing, deposition, sputtering, plating, or spraying without limitation. As the electrical path section (130) is formed in the trench (TR) as well as in the opening pattern (P), the electrical path section (130) can be formed thicker than the thickness of the membrane section (110).

[0073] Next, a holder portion (150) can be connected to the membrane portion (110). The connection of the holder portion (150) may be performed before the formation of the electrical path portion (130).

[0074] Next, referring to FIG. 9 (e), the membrane portion (110) can be separated from the support substrate (210') to complete the manufacturing of the semiconductor test device (100).

[0075] FIG. 10 is a schematic diagram showing a semiconductor test apparatus according to a second embodiment of the present invention. Hereinafter, the description of the same configuration as that of the semiconductor test apparatus of the first embodiment described above through FIG. 3 to 5 will be omitted, and only the differences will be described.

[0076] Referring to FIG. 10, a semiconductor test device (100: 100-2) according to a second embodiment may include a membrane portion (110: 110-2) and a holder portion (150). The membrane portion (110) includes a plurality of opening patterns (P), and an electrical connection path may be provided from the top to the bottom of each opening pattern (P). This electrical connection path may be provided through an electrical path portion (130) comprising a conductive material.

[0077] According to one embodiment, the membrane portion (110: 110-2) may include a metal thin film portion (111) and an insulating layer portion (115). Each opening pattern (P) formed in the metal thin film portion (111) may be in one-to-one contact with a microbump (MB: MB2) on the lower part of the stacked semiconductor memory (15).

[0078] The membrane portion (110) must be able to form multiple opening patterns (P) at a level of several to tens of micrometers. In addition, the membrane portion (110) may use a material that has low thermal expansion and contraction due to temperature changes, that is, a material with a low coefficient of thermal expansion (CTE). In addition, the membrane portion (110) may use a material that is durable and does not have deformation in the X and Y directions. Considering this, the metal thin film portion (111) of the membrane portion (110) may use materials such as invar, super invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy. Alternatively, the metal thin film portion (111) may include a metal material capable of electroplating as nickel (Ni), cobalt (Co), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), etc., or a combination thereof, or an alloy thereof, and capable of forming a silicide with the silicon component of the support portion (30') [or conductive substrate (30'), see FIG. 26] described later. Alternatively, the metal thin film portion (111) may include a super invar material containing ternary or higher Co.

[0079] The thickness (T2) of the membrane portion (110), the spacing and width (W3) of the opening pattern (P), etc., can be formed with the same size as described above in FIG. 3. However, the thickness of the insulating layer portion (115) formed on the surface of the metal thin film portion (111) may be further considered. The insulating layer portion (115) may be formed with a thickness smaller than about 5 μm. Considering this, the thickness (T2) of the membrane portion (110) is derived by considering the thickness (T3) of the metal thin film portion (111) and the thickness (T4) of the insulating layer portion (115), and the width (W2) of the opening pattern (P) of the membrane portion (110) can be derived by considering the width (W3) of the opening pattern of the metal thin film portion and the width (W4) of the insulating layer portion (115).

[0080] Since the metal thin film portion (111) is made of a conductive material, there is a risk of short circuit when it comes into contact with the microbump (MB). Therefore, the surface of the metal thin film portion (111) can be coated with an insulating layer portion (115) so that the surface of the membrane portion (110) exhibits insulating properties.

[0081] The formation process and material of the electric path section (130) and the holder section (150) are the same as described in detail in FIG. 3.

[0082] The semiconductor test device (100: 100-2) according to the second embodiment of the present invention has the advantage of a simple manufacturing process because the basic frame of the membrane part (110) can be composed of a metal thin film part (111). It is easy to form a metal thin film part (111) having a fine aperture pattern (P) by applying processes such as photolithography and electroplating, and the process of coating an insulating layer part (115) can also be performed simply.

[0083] In addition, if the holder portion (150) is made of the same material as the metal thin film portion (111) or of a metal material, there is an advantage of being able to interconnect with higher adhesion, and there is also an advantage of being easy to perform welding.

[0084] In addition, since the membrane portion (110: 110-2) includes a metal thin film portion (111), there is an advantage in that the membrane portion (110) can be controlled by applying magnetic force from the outside. For example, as shown in FIG. 4, in the process of aligning the microbump (MB) of the stacked semiconductor memory (15) with the electrical path portion (130), there is a unique effect in that the membrane portion (110) [or the electrical path portion (130)] can be controlled to make close contact with the microbump (MB) by applying magnetic force without the need to apply physical stress. Alternatively, in the process of aligning the microbump (MB) of the stacked semiconductor memory (15) with the electrical path portion (130), close contact with the membrane portion (110) [or the electrical path portion (130)] can be performed by simultaneously applying magnetic force while applying relatively less physical stress.

[0085] Meanwhile, if the material of the holder portion (150) is a conductive material, when the holder portion (150) is connected to the ground electrode, the metal thin film portion (111) can be grounded through the holder portion (150). Accordingly, it is possible to prevent current from unexpectedly flowing through the metal thin film portion (111) and adversely affecting the test of the stacked semiconductor memory (15).

[0086] FIGS. 11 and 12 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to another embodiment of the present invention.

[0087] Referring to FIG. 11 (a), a support substrate (210) can be prepared. The support substrate (210) may be made of a plate-shaped material such as glass, wafer, or quartz. Subsequently, a temporary adhesive portion (230) may be formed on the support substrate (210). The temporary adhesive portion (230) may be made of a material that can be removed and cleaned after providing temporary adhesive force, such as dry film resist or liquid wax. Subsequently, a metal sheet may be adhered to the temporary adhesive portion (230). Subsequently, a patterned etching-resistant pattern (240) may be formed on the metal sheet, and then etching may be performed between the patterns of the etching-resistant pattern (240). An opening pattern (P1) is formed by etching on the metal sheet, and a metal thin film portion (111) may be manufactured.

[0088] Next, referring to FIG. 11 (b), the holder portion (150) of the metal thin film portion (111) can be connected. The holder portion (150) can be connected by interposing an adhesive means on the edge portion of the membrane portion (110) where the opening pattern (P) is not formed, or the connection can be performed through welding, etc. When welding is performed, a weld bead (WB) is formed, and the metal thin film portion (111) and the holder portion (150) can be connected integrally.

[0089] Next, referring to (c) of FIG. 11, the metal thin film portion (111) can be separated from the support substrate (210). Separation can be performed by applying heat, chemical treatment, applying ultrasound, or irradiating light to the temporary adhesive portion (230) between the membrane portion (110) and the support substrate (210).

[0090] Next, referring to (d) of FIG. 12, an insulating layer (115) can be coated on the surface of the connection between the metal film portion (111) and the holder portion (150). The insulating layer (115) may be an insulating material such as polyimide, rubber, resin, Teflon, polymer, curable photoresist, inorganic insulator, or organic insulator, which was used when forming the insulating material membrane portion (110) described above in FIG. 3. As long as the insulating layer (115) covers the surface of the metal film portion (111), it is not necessary to coat the entire surface of the holder portion (150).

[0091] An insulating layer (115) is coated on the opening pattern (P1) of the metal thin film portion (111) so that the opening pattern (P: P2) of the membrane portion (110: 110-2) can be determined.

[0092] Next, referring to FIG. 12 (e), an electrical path section (130) can be formed within an opening pattern (P: P2). The electrical path section (130) can be formed using methods such as printing, deposition, sputtering, plating, or spraying without limitation. The electrical path section (130) can be formed to be the same thickness as or thicker than the thickness of the membrane section (110). Through this, the manufacturing of a semiconductor test device (100: 100-2) in which an insulating layer section (115) is coated on the surface of a metal thin film section (111) is connected to a holder section (150) and an electrical path section (130) is formed in the opening pattern (P) can be completed.

[0093] FIG. 13 is a schematic diagram showing a semiconductor test apparatus according to a third embodiment of the present invention. Hereinafter, the description of the configuration identical to the semiconductor test apparatus (100-1, 100-2) of the first and second embodiments described above through FIG. 3 to 5 and FIG. 10 will be omitted, and only the differences will be described.

[0094] Referring to FIG. 13, a semiconductor test device (100: 100-3) according to a third embodiment may include a membrane portion (110: 110-3) and a holder portion (150). The membrane portion (110) includes a plurality of opening patterns (P), and an electrical connection path may be provided from the top to the bottom of each opening pattern (P). This electrical connection path may be provided through an electrical path portion (130) comprising a conductive material.

[0095] According to one embodiment, the membrane portion (110: 110-3) may include a metal thin film portion (111) and an insulating layer portion (115a). Each opening pattern (P) formed in the metal thin film portion (111) may be in one-to-one contact with a microbump (MB: MB2) on the lower part of the stacked semiconductor memory (15).

[0096] The membrane portion (110) must be able to form multiple opening patterns (P) at a level of several to tens of micrometers. In addition, the membrane portion (110) may use a material that has low thermal expansion and contraction due to temperature changes, that is, a material with a low coefficient of thermal expansion (CTE). In addition, the membrane portion (110) may use a material that is durable and does not have deformation in the X and Y directions. Considering this, the metal thin film portion (111) of the membrane portion (110) may use materials such as invar, super invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy. Alternatively, the metal thin film portion (111) may include a metal material capable of electroplating as nickel (Ni), cobalt (Co), titanium (Ti), chromium (Cr), tungsten (W), molybdenum (Mo), etc., or a combination thereof, or an alloy thereof, and capable of forming a silicide with the silicon component of the support portion (30') [or conductive substrate (30'), see FIG. 26] described later. Alternatively, the metal thin film portion (111) may include a super invar material containing ternary or higher Co.

[0097] The thickness (T2) of the membrane portion (110), the spacing and width (W3) of the opening pattern (P), etc., can be formed with the same size as described above in FIG. 10. The thickness (T2) of the membrane portion (110) can be derived by considering the thickness (T3) of the metal thin film portion (111) and the thickness (T4) of the insulating layer portion (115), and the width (W2) of the opening pattern (P) of the membrane portion (110) can be derived by considering the width (W3) of the opening pattern of the metal thin film portion and the width (W4) of the insulating layer portion (115).

[0098] Since the metal thin film portion (111) is made of a conductive material, there is a risk of short circuit when it comes into contact with the microbump (MB). Therefore, the surface of the metal thin film portion (111) can be coated with an insulating layer portion (115: 115a) so that the surface of the membrane portion (110) exhibits insulating properties. An insulating layer portion (115: 115b) may also be formed on the surface of the holder portion (150), but it is not necessary for the insulating layer portion (115: 115b) to be formed on the surface of the holder portion (150) as long as the purpose is to provide insulation without contact with the microbump (MB). In this specification, an example is described by assuming that an insulating layer portion (115: 115b) is formed on at least the lower surface of the holder portion (150) to improve insulation with the lower interposer (13') [see FIG. 5].

[0099] The formation process and material of the electric path section (130) are the same as described in detail in FIG. 3.

[0100] A semiconductor test device (100: 100-3) according to the third embodiment is characterized in that the holder portion (150) is integrally connected to the metal thin film portion (111). Here, the meaning of being integrally connected is understood to mean that the metal thin film portion (111) and the holder portion (150) are connected as one body using the same material, rather than being connected via an adhesive means. The metal thin film portion (111) and the holder portion (150) can be understood as a specific portion being designated as the metal thin film portion (111) and the remaining portion as the holder portion (150) by removing a part of the metal sheet (105) described later in FIG. 13.

[0101] Since the metal thin film portion (111) and the holder portion (150) are composed of components derived from the same raw material, they may be made of the same metal material. The metal thin film portion (111) and the holder portion (150) may use materials such as Invar, Super Invar, Nickel-Iron Alloy, Nickel-Cobalt Alloy, Nickel-Iron-Cobalt Alloy, etc., which have a low coefficient of thermal expansion to prevent thermal deformation.

[0102] For example, the thickness (T5) of the holder portion (150) may be 150 μm to 1,000 μm, corresponding to the thickness of the raw material metal sheet (210). When the thickness of the hollow region (R') is subtracted from the holder portion (150), a membrane portion (110: 110-3) may be derived. For example, the thickness (T2) of the membrane portion (110) may be about 5 to 50 μm.

[0103] The semiconductor test device (100: 100-3) according to the third embodiment of the present invention has the advantage of a simple manufacturing process because the basic frame of the membrane part (110: 110-3) can be composed of a metal thin film part (111). Furthermore, there is an advantage of a simpler manufacturing process because the metal thin film part (111) and the holder part (150) can be simultaneously implemented from a single raw material in a simple process without the need to perform a separate process of connecting the metal thin film part (111) and the holder part (150) to each other. There is an advantage that it is easy to form the holder part (150) having a hollow region (R') and the metal thin film part (111) having a fine opening pattern (P) by applying processes such as photolithography and electroplating, and the process of coating the insulating layer part (115) can also be performed simply.

[0104] In addition, since the metal thin film portion (111) and the holder portion (150) are integrally formed from the same metal material, there is an advantage that the possibility of the metal thin film portion (111) and the holder portion (150) becoming misaligned or deformed is very low.

[0105] In addition, since the membrane portion (110: 110-3) includes a metal thin film portion (111), there is an advantage that the membrane portion (110) can be controlled by applying magnetic force from the outside, as described above in FIG. 10.

[0106] Meanwhile, since the material of the holder portion (150) is a conductive material, the holder portion (150) can be connected to a ground electrode to ground the metal thin film portion (111) through the holder portion (150). Alternatively, the metal thin film portion (111) can be grounded by connecting a ground electrode to it. Accordingly, it is possible to prevent current from unexpectedly flowing through the metal thin film portion (111) and adversely affecting the test of the stacked semiconductor memory (15). The influence on adjacent microbumps (MB) caused by induced current, leakage current, crosstalk, etc. of the metal thin film portion (111) can be minimized. Of course, insulation can also be achieved in parts other than the electrical path portion (130) by coating an insulating layer portion (115) on all surfaces of the metal thin film portion (111) and the holder portion (150).

[0107] FIGS. 14 and 15 are schematic diagrams illustrating the manufacturing process of a semiconductor test device according to a third embodiment of the present invention. Hereinafter, the description of the process identical to the manufacturing process of the semiconductor test device of the second embodiment described above through FIGS. 11 and 12 will be omitted, and only the differences will be described.

[0108] Referring to FIG. 14 (a), a support substrate (210) can be prepared. Then, a temporary adhesive portion (230) can be formed on the support substrate (210). Then, a metal sheet (105) can be adhered to the temporary adhesive portion (230).

[0109] Next, referring to FIG. 15(b), the thickness can be reduced on the upper surface of the metal sheet (105). The thickness reduction can be achieved using methods such as touch polishing, dry etching, and wet etching without limitation. For example, the thickness can be reduced by forming an etching-resistant pattern (235) on the upper surface of the metal sheet (105) excluding the portion where the cell portion (C) is to be formed, and by performing etching on the exposed portion of the metal sheet (105). As a result of the thickness reduction in the central portion of the metal sheet (105) [the portion where the cell portion (C) is to be formed], a hollow region (R') can be formed.

[0110] Next, referring to (c) of FIG. 15, a patterned etch-resistant pattern (240) is formed on a hollow region (R') of a metal sheet (105'), and then etching can be performed between the patterns of the etch-resistant pattern (240). An opening pattern (P3) is formed by etching on the portion of the metal sheet (105') exposed between the patterns of the etch-resistant pattern (240), and a metal thin film portion (111) can be manufactured.

[0111] The portion that is thin and has opening patterns (P3) formed therein is provided as a metal thin film portion (111), and the portion that is thick and is integrally connected to the edge of the metal thin film portion (111) can be provided as a holder portion (150).

[0112] Next, referring to FIG. 15 (d), the metal thin film portion (111) and the holder portion (150) can be separated from the support substrate (210). Separation can be performed by applying heat, chemical treatment, applying ultrasound, or irradiating light to the temporary adhesive portion (230) between the membrane portion (110) and the support substrate (210). Cleaning of the etching-resistant patterns (235, 240) can also be performed.

[0113] Since the thickness (T5) of the holder portion (150) is thicker than the thickness (T3) of the metal thin film portion (111), the rigidity of the holder portion (150) is high, and it can provide support to the metal thin film portion (111) in the vertical and lateral directions. Additionally, the edge of the metal thin film portion (111) is entirely connected to the holder portion (150). Accordingly, even without applying a tensile force in the lateral outward direction to the entire edge of the holder portion (150), the tensile force can be uniformly transmitted to the entire edge of the metal thin film portion (111). In other words, even if a tensile force is applied to a certain point of the holder portion (150), the tensile force is not applied only to the point where the tensile force is applied to the metal thin film portion (111), but rather the tensile force can be uniformly distributed along the edge of the metal thin film portion (111) around that point. Ultimately, there is an advantage in that only the holder part (150) is controlled to achieve a uniform and fine tensile force distribution on the edge of the metal thin film part (111), thereby allowing it to be stretched taut.

[0114] Next, referring to FIG. 15 (e), an insulating layer (115: 115a, 115b) can be coated on the surface of the connection between the metal film portion (111) and the holder portion (150). The insulating layer (115) may be an insulating material such as polyimide, rubber, resin, Teflon, polymer, curable photoresist, inorganic insulator, or organic insulator, which was used when forming the insulating membrane portion (110) described above in FIG. 3. The insulating layer (115) does not necessarily need to be coated on the entire surface of the holder portion (150) as long as it covers the surface of the metal film portion (111).

[0115] Meanwhile, the right dotted line portion of FIG. 15 (e) is a section of the membrane portion (110: 110-4) according to another embodiment. Referring to the dotted line portion, the metal thin film portion (111-2) and the insulating layer (115a) at the bottom of the holder portion (150-2), rather than the side of the holder portion (150), can be set as the membrane portion (110: 110-4). The holder portion (150-2) is integrally connected to the membrane portion (110-4), and the insulating layer (115a) can be coated on the surface of the metal thin film portion (111-2).

[0116] An insulating layer (115) is coated on the opening pattern (P3) of the metal thin film portion (111) so that the opening pattern (P: P4) of the membrane portion (110: 110-3) can be determined.

[0117] Next, referring to (f) of FIG. 15, an electrical path portion (130) can be formed within the opening pattern (P: P4). Through this, the manufacture of a semiconductor test device (100: 100-3) in which the metal thin film portion (111) and the holder portion (150) are integrally connected and have the same material can be completed.

[0118] FIGS. 16 and 17 are schematic diagrams showing the form of a semiconductor test device according to the fourth to sixth embodiments (100: 100-4 to 100-6) of the present invention.

[0119] Referring to FIG. 16 (a), the semiconductor test device (100: 100-4) may provide a plurality of hollow regions (R: R'-a, R'-b, R'-c) [or a plurality of cell sections (C1, C2, C3). The plurality of hollow regions (R) may be arranged along the X-axis and Y-axis directions on a horizontal plane.

[0120] The size (horizontal area) of each hollow region (R': R'-a, R'-b, R'-c) can correspond to the size of a stacked semiconductor memory (15), which is (width) x (height) (several mm to tens of mm) x (several mm to tens of mm). In order to partition each hollow region (R'), in addition to the holder portion (150) being placed on the edge portion of the semiconductor test device (100: 100-4), grid portions (155) having a thickness corresponding to that of the holder portion (150) are also formed in the center portion, so that the grid portions (155) can partition the hollow regions (R') and provide multiple of them. Accordingly, the semiconductor test device (100: 100-4) can perform tests on multiple stacked semiconductor memories (15) at once.

[0121] As another example, referring to FIG. 16(b), cutting (SP) can be performed on the semiconductor test device (100: 100-4) of FIG. 16(a). Through cutting (SP), the semiconductor test device (100: 100-4) can be separated into a plurality of semiconductor test devices (100: 100-5a, 100-5b, 100-5c). Testing of the stacked semiconductor memory (15) can be performed through each of the semiconductor test devices (100: 100-5a, 100-5b, 100-5c). Accordingly, the present invention has the advantage of enabling mass production of a plurality of semiconductor test devices (100: 100-5a, 100-5b, 100-5c).

[0122] As another example, referring to FIG. 17, the size (horizontal area) of the hollow region (R': R'-L) of the semiconductor test device (100: 100-6) may have an area corresponding to a stacked semiconductor memory (15-L) including multiple cells / multiple dies. Alternatively, the size of the hollow region (R': R'-L) may correspond to the size of a silicon wafer or be larger than that. Accordingly, the present invention has the advantage of being able to provide a semiconductor test device (100: 100-6) capable of performing tests on stacked semiconductor memories of various sizes.

[0123] FIG. 18 is a schematic diagram showing a semiconductor test apparatus according to the seventh embodiment of the present invention. FIG. 19 is a schematic diagram showing a semiconductor test apparatus according to the eighth embodiment of the present invention. Hereinafter, the description of configurations identical to the semiconductor test apparatuses (100-1, 100-2, 100-3) of the first, second, and third embodiments described above through FIG. 3 to 5 and FIG. 10 will be omitted, and only the differences will be described.

[0124] Referring to FIG. 18, a semiconductor test device (100: 100-7) according to the seventh embodiment may include a membrane portion (110: 110-2) and a holder portion (150). The membrane portion (110) includes a plurality of opening patterns (P), and an electrical connection path may be provided from the top to the bottom of each opening pattern (P). This electrical connection path may be provided through a conductive thin film layer (140) formed on the side of the opening pattern (P).

[0125] According to one embodiment, the membrane portion (110: 110-2) may include a metal thin film portion (111) and an insulating layer portion (115). Each opening pattern (P) formed in the metal thin film portion (111) may correspond one-to-one with a microbump (MB: MB2) at the bottom of the stacked semiconductor memory (15). A conductive thin film layer (140) formed on the insulating layer portion (115) within the opening pattern (P) (or on the side of the opening pattern (P)) may come into contact with the microbump (MB). The material, size, etc. of the membrane portion (110) may be the same as that of the membrane portion (110) described above in FIG. 10.

[0126] A semiconductor test device (100: 100-7) according to the seventh embodiment is characterized by including a conductive thin film layer (140) formed on the side of an opening pattern (P) instead of an electrical path portion (130) filled in the opening pattern (P). The conductive thin film layer (140) is formed entirely on the side of the opening pattern (P) and can provide an electrical connection from the top to the bottom of the opening pattern (P).

[0127] The conductive thin film layer (140) may include a conductive material. Preferably, the conductive thin film layer (140) may include a material such as Cu, Ag, Au, Pt, Sn, Pd, etc., which has excellent conductivity and low resistance. The conductive thin film layer (140) is formed by deposition, sputtering, etc., and is preferably formed as a thin film of approximately 1 nm to 1 μm that does not affect the width of the aperture pattern (P).

[0128] Referring to FIG. 19, a semiconductor test device (100: 100-8) according to the eighth embodiment may include a membrane portion (110: 110-3) and a holder portion (150). The membrane portion (110) includes a plurality of opening patterns (P), and an electrical connection path may be provided from the top to the bottom of each opening pattern (P). This electrical connection path may be provided through a conductive thin film layer (140) formed on the side of the opening pattern (P).

[0129] According to one embodiment, the membrane portion (110: 110-3) may include a metal thin film portion (111) and an insulating layer portion (115a).

[0130] In the semiconductor test device (100: 100-8) according to the 8th embodiment, the holder portion (150) can be integrally connected with the metal thin film portion (111). Here, the meaning of being integrally connected is understood as the metal thin film portion (111) and the holder portion (150) being connected as one body with the same material, rather than being connected via an adhesive means.

[0131] In addition, similar to the seventh embodiment, the semiconductor test device (100: 100-7) according to the eighth embodiment is characterized by including a conductive thin film layer (140) formed on the side of the opening pattern (P) instead of an electrical path portion (130) filled in the opening pattern (P). The conductive thin film layer (140) is formed entirely on the side of the opening pattern (P) to provide an electrical connection from the top to the bottom of the opening pattern (P).

[0132] Meanwhile, as in the first embodiment described above in FIG. 3, an embodiment may also be provided that includes a membrane portion (110: 110-1) and a holder portion (150), and has a conductive thin film layer (140) formed on the side of each opening pattern (P) formed in the membrane portion (110: 110-1) made of an insulating material.

[0133] FIGS. 20 and 21 are schematic cross-sectional views showing the shape of an opening pattern and a conductive thin film layer according to various embodiments of the present invention.

[0134] Referring to FIGS. 20 and 21, shapes of multiple aperture patterns (P: Pa ~ Pe) and conductive thin film layers (140a ~ 140f) that can contact microbumps (MB: MB2) at the bottom of a stacked semiconductor memory (15) can be proposed.

[0135] Referring to FIG. 20(a), a vertical opening pattern (Pa) and a conductive thin film layer (140a) formed on its side may be provided. Since the conductive thin film layer (140a) may also be formed in a vertical direction, the width of the opening pattern (Pa) extending to the upper corner (CP1) and the lower corner (CP2) may be constant. A microbump (MB: MB2) may come into contact with the upper corner (CP1).

[0136] Referring to FIG. 20 (b) and (c), an opening pattern (Pb, Pc) in the shape of an inverse taper overall and a conductive thin film layer (140b, 140c) formed on its side may be provided. FIG. 20 (c) may show a concave curvature on the side of the opening pattern (Pc) as a result of isotropic etching, such as wet etching, for example. The conductive thin film layer (140b, 140c) is shaped such that the width of the opening pattern (Pb, Pc) decreases from the upper corner (CP1) to the lower corner (CP2). A microbump (MB) may come into contact with the upper corner (CP1). In this process, at least a portion of the microbump (MB), which is approximately spherical in shape, may be accommodated within the inverse taper-shaped opening pattern (Pb, Pc). The microbump (MB) is guided along the side of the opening pattern (Pb, Pc) and may come into contact with the conductive thin film layer (140b, 140c). Accordingly, it has the effect of providing stable contact for multiple microbumps (MB). In addition, it has the effect of guiding contact with the conductive thin film layers (140b, 140c) and allowing partial accommodation within the opening pattern (Pb, Pc) regardless of the diameter size of the microbumps (MB).

[0137] Referring to FIG. 21 (a), the width of the opening pattern (Pd) decreases as it goes from the top corner (CP1) to the center corner (CP3), and then increases as it goes from the center corner (CP3) to the bottom corner (CP2). FIG. 21 (a) may be the result of, for example, wet etching being performed on the top surface and the bottom surface respectively, so that the top pattern (P1) and the bottom pattern (P2) are connected and the opening pattern (Pd) is formed. The microbump (MB) is guided along the side formed in reverse tapering from the top corner (CP1) to the center corner (CP3) of the opening pattern (Pd) and can come into contact with the conductive thin film layer (140d). In addition, there is an advantage that the connecting electrode (CE) [see FIG. 4 (b)] of the test interposer (13') from the bottom of the opening pattern (Pd) is guided along the side formed tapered from the bottom corner (CP2) to the center corner (CP3) and can come into contact with the conductive thin film layer (140d).

[0138] Referring to FIG. 21(b), an opening pattern (Pe) having an overall inverse taper shape can be provided, with a two-stage concave curvature shape from the upper corner (CP1) to the middle corner (CP3) and from the middle corner (CP3) to the lower corner (CP2). FIG. 21(b) may, for example, provide an opening pattern (Pe) by performing a first wet etching on the upper surface to form an upper pattern (P3), and then performing a second wet etching on the same upper surface to form a lower pattern (P4), so that the upper pattern (P3) and the lower pattern (P4) are connected. Similar to FIG. 20(b) and (c), at least a portion of a roughly spherical microbump (MB) can be accommodated within the inverse taper-shaped opening pattern (Pe) to ensure stable contact with the conductive thin film layer (140e).

[0139] Referring to FIG. 21 (c), in addition to forming a conductive thin film layer (140f) on the side of the opening pattern (Pa), conductive thin film layers (141, 142) may also be formed around the upper and lower parts of the opening pattern (Pa). That is, conductive thin film layers (141, 142) may be further formed on the upper surface of the membrane part (110) in a horizontal direction from the upper corner (CP1) of the side of the opening pattern (Pa), and on the lower surface of the membrane part (110) in a horizontal direction from the lower corner (CP2). It is preferable that the width (WP) of the conductive thin film layers (141, 142) formed in the horizontal direction be formed within a range that does not affect the adjacent opening pattern (Pa). For example, the width (WP) of the conductive thin film layers (141, 142) formed in the horizontal direction may be 50% or less (greater than 0) of the width of the opening pattern (Pa).

[0140] Since the conductive thin film layer (140f) further includes conductive thin film layers (141, 142) formed horizontally on the upper and lower surfaces of the membrane (110) as well as on the side of the opening pattern (Pa), contact stability with the microbump (MB) can be improved. In particular, there is an effect of improving contact stability with various shapes of microbumps (MB) in addition to spherical microbumps (MB).

[0141] FIG. 22 is a schematic plan view showing an opening pattern and a microbump and contact shape according to various embodiments of the present invention.

[0142] When viewed from the planar direction (upper plane direction), the shape of the opening pattern (P) can be a square, hexagon, polygon, etc. Taking a spherical microbump (MB) as an example, in a square-shaped opening pattern (P) as in (a) of FIG. 22, contact points (CP) appear at approximately 4 locations, and in a hexagonal-shaped opening pattern (P) as in (b) of FIG. 22, contact points (CP) appear at approximately 6 locations. Since a conductive thin film layer (140) is formed on the edge of the opening pattern (P), an electrical connection path can be formed along the contact points (CP) to the bottom of the opening pattern (P). Even if a slight alignment error occurs, an electrical connection is established if at least one contact point (CP) is formed, which is advantageous for forming a stable electrical connection path.

[0143] FIG. 23 is a schematic diagram illustrating the manufacturing process of a semiconductor test device according to the seventh embodiment of the present invention. The description of the process identical to the manufacturing process of the semiconductor test device of the second embodiment described above through FIG. 11 and 12 is omitted, and only the differences are described.

[0144] By performing the same process as in FIG. 11 (a) to FIG. 11 (c), a connection between a metal thin film portion (111) and a holder portion (150) can be prepared. Next, referring to FIG. 23 (d), an insulating layer portion (115) can be coated on the surface of the connection between the metal thin film portion (111) and the holder portion (150). The insulating layer portion (115) is coated on the opening pattern (P1) of the metal thin film portion (111) so that the opening pattern (P: P2) of the membrane portion (110: 110-2) can be determined.

[0145] Next, referring to FIG. 23 (e), a conductive thin film layer (140) can be formed on the side of the opening pattern (P: P2). The conductive thin film layer (140) may include materials such as Cu, Ag, Au, Pt, and Sn, which have excellent conductivity and low resistance. For example, a conductive thin film layer (140) made of Cu or Sn can be formed through sputtering, and a conductive thin film layer (140) made of Ag, Au, Pt, Sn, or Pd can be formed through thermal evaporation. In addition, methods such as printing, plating, and spraying may be used. The thickness of the conductive thin film layer (140) can be formed to be approximately 1 μm or less. Even if the conductive thin film layer (140) is formed, there is almost no effect on the width of the opening pattern (P).

[0146] Through this, the manufacturing of a semiconductor test device (100: 100-7) can be completed, in which a membrane part (110: 110-2) having an insulating layer part (115) coated on the surface of a metal thin film part (111) is connected to a holder part (150) and a conductive thin film layer (140) is formed on an opening pattern (P).

[0147] Meanwhile, the semiconductor test device (100: 100-8) according to the eighth embodiment of FIG. 19 can also be manufactured by further performing the process of forming a conductive thin film layer (140) on the side of the opening pattern (P) after performing steps (a) of FIG. 14 to (e) of FIG. 15.

[0148] FIG. 24 is a schematic side cross-sectional view and a schematic plan view showing a conductive cantilever portion protruding between opening patterns according to one embodiment of the present invention.

[0149] Referring to FIG. 24, the conductive thin film layer (140g) may further include a conductive cantilever portion (CT) protruding between the opening patterns (P: Pf). The conductive cantilever portion (CT) may be formed protruding in a cantilever shape. The conductive cantilever portion (CT) may be formed integrally at the same time during the formation process of the conductive thin film layer (140g), or may be formed by performing additional processes. The conductive cantilever portion (CT) may protrude between the opening patterns (P) in a state thinner than the thickness of the membrane portion, so as to provide elastic contact with the microbump (MB). For example, referring to FIG. 24 (b), the conductive cantilever portion (CT) may provide the opening pattern (P: Pf) in a rounded shape so that the surface of the microbump (MB) naturally settles on the conductive cantilever portion (CT).

[0150] FIG. 25 is a schematic diagram showing a form of controlling a conductive cantilever part by applying an external magnetic force according to an embodiment of the present invention.

[0151] Referring to the left drawing of FIG. 25, an alignment error or step error may occur in a specific microbump (MB') among a plurality of microbumps (MB), so that it does not come into contact with the conductive thin film layer (140g). In this case, the shape of the cantilever part (CT) can be controlled by applying a magnetic force (M) from the outside.

[0152] Referring to the right side of FIG. 25, a force (IF) that pulls the cantilever part (CT) can be applied by applying an external magnetic force (M). Accordingly, the cantilever part (CT) can come into contact with the microbump (MB') to form an electrical connection. In addition, the contact force can be adjusted by bending the cantilever part (CT) up or down depending on the application of the magnetic force (M). For example, if a gap is created due to a step difference between adjacent microbumps, the cantilever part (CT) can be controlled to bend upward, and if the microbump causes about 10-15% deformation upon contact, the cantilever part (CT) can be controlled to bend downward.

[0153] FIGS. 26 to 33 are schematic diagrams showing the manufacturing process of a semiconductor test device (100: 100-9) according to the ninth embodiment of the present invention.

[0154] The metal thin film portion (111) can be formed using a thin film formation method such as a rolling process or an electroplating process. In FIGS. 26 to 33 below, a method of forming the metal thin film portion (111) of the membrane portion (110: 110-8) using electroplating is described. Meanwhile, FIGS. 26 to 33 illustrate a semiconductor test device (100: 100-9) including a plurality of cell portions (C), but it should be noted that it can also be manufactured to include a single cell portion (C) using the same manufacturing process.

[0155] Referring to FIG. 26, a support member (30') is prepared. To enable electroforming, the support member (30') may be a conductive substrate (30') made of a conductive material. To have conductivity and simultaneously low resistance, 10 on the support member (30') [or the conductive substrate (30')] 19 cm -3Higher concentration doping can be performed. Doping may be performed over the entire support portion (30') or only on the surface portion of the support portion (30'). According to one embodiment, the surface resistance of the support portion (30') is 5 x 10 -4 ~ 1 X 10 -2 It can be ohm·cm. The support portion (30') can be used as a cathode electrode in electroplating.

[0156] Unlike metals having metal oxides on the surface or polycrystalline silicon having grain boundaries, doped single-crystal silicon has no defects, so there is an advantage that a uniform plating film [or metal thin film part (111)] can be produced by forming a uniform electric field across the entire surface during electroplating. Since the metal thin film part (111) produced through the uniform plating film does not require an additional process to remove or eliminate defects, there is an advantage of reducing process costs and improving productivity.

[0157] Next, a patterned insulating portion (M1) can be formed on one side of the support portion (30'). The insulating portion (M1) is a part formed to protrude (in relief) on one side of the support portion (30') and may have insulating properties to prevent the formation of a plating film [or a metal thin film portion (111)]. Accordingly, the insulating portion (M1) may be formed from any one of photoresist, silicon oxide, and silicon nitride. The insulating portion (M1) may be formed by silicon oxide or silicon nitride on the support portion (30') by methods such as deposition, and may also use thermal oxidation or thermal nitridation methods with the support portion (30') as a base. Photoresist may also be formed using printing methods, etc.

[0158] The width (md) of the insulating portion (M1) can correspond to the upper width of the opening pattern (P). The upper width of the opening pattern (P) can correspond to the minimum width at which the microbump (MB) or connecting electrode (CE) can make contact. The width (md) of the insulating portion (M1) can be formed to a level of several to tens of μm to correspond to the width of the opening pattern (P). Meanwhile, as described below, since a trench portion (TR) is formed in the support portion (30'), the insulating portion (M1) can be formed thinly with a thickness within the range for forming the trench portion (TR). Considering that the trench portion (TR) corresponds to the thickness of the metal thin film portion (111) (about 5 to 50 μm), the insulating portion (M1) can be formed thinly with a thickness of about 0.5 to 5 μm. Therefore, there is an advantage in that it is easy to form the insulating portion (M1) and the use of material can be reduced.

[0159] Next, the support portion (30') can be etched (EC1). Etching (EC1) can be performed on the surface of the first side (or upper side) of the support portion (30') exposed between the patterns of the insulating portion (M1). Dry etching or wet etching can be used for the etching (EC1). Wet etching has isotropic etching characteristics, and dry etching has anisotropic characteristics, which has the advantage of being able to etch precisely to a desired width. Alternatively, laser etching, which enables precise etching using a femtosecond or picosecond laser, may be used. In the case of laser etching, the process of forming the first insulating portion (M1) may be omitted.

[0160] A trench portion (TR) formed by indentation on the first surface (or upper surface) of the support portion (30') can be formed by etching (EC1). The depth (h) of the trench portion (TR) can correspond approximately to the thickness of the metal thin film portion (111) to be formed. For example, the depth (h) of the trench portion (TR) can be about 5 to 50 μm.

[0161] Multiple trench sections (TR) can be formed by patterning. On the support section (30') corresponding to the cell section (C), the trench section (TR) can be formed to correspond inversely to the opening pattern (P). In other words, the part of the cell section (C) where the trench section (TR) is not formed can later become the opening pattern (P).

[0162] The trench portion (TR) may include a bottom surface (BS) and a side surface (SS). The side surface (SS) may be formed vertically or inclined at a predetermined angle. When using wet etching (EC1), since wet etching has isotropic etching characteristics, the side surface (SS) may be formed inclined at a predetermined angle. That is, the side surface (SS) of the trench portion (TR) may be formed tapered. By etching while considering the crystal direction of the support portion (30') made of single-crystal silicon material, the taper angle of the trench portion (TR) may be implemented to correspond to the etching direction.

[0163] Next, referring to FIG. 27 (a), electroplating can be performed on a support member (30') to form a metal thin film member (111': 111'a). The support member (30') is used as a cathode, and an anode member (not shown) facing it is prepared. The anode member (not shown) is immersed in a plating solution (not shown), and the support member (30') may be immersed in the plating solution (not shown) in whole or in part. Since the insulating member (M1) has insulating properties, a plating film may not be formed in the part corresponding to the insulating member (M1). In particular, the plating film may be formed within the trench member (TR) to form the metal thin film member (111'). The thickness of the metal thin film member (111') can be formed so as to fill the trench member (TR) and not extend above the insulating member (M1). In other words, electroplating can be performed such that the top of the metal thin film portion (111') is higher than the height of the first surface (or upper surface) of the support portion (30') and lower than the height of the top of the insulation portion (M1).

[0164] Meanwhile, the composition of the metal thin film portion (111') can be controlled so that it has a coefficient of thermal expansion (CTE) similar to that of the silicon material of the support portion (30'). After the manufacturing process, the support portion (30') can be provided as a silicon material holder portion (150), and the metal thin film portion (111) must have a coefficient of thermal expansion similar to that of the holder portion (150: 30) so that sagging does not occur on the holder portion (150: 30). In addition, changes in the alignment error of the cell portion (C) and the opening pattern (P) on the holder portion (150: 30) can be minimized.

[0165] Considering this, the thermal expansion coefficient of the silicon support (30') and the metal thin film portion (111') after the heat treatment (H) described later is approximately (3.5±1) X 10 -6 The composition of the metal thin film portion (111') can be controlled so that it becomes / ℃. Even if the metal thin film portion (111') is made of Invar material, the thermal expansion coefficient can be controlled to be as similar as possible to that of the silicon material support portion (30') by electroplating with a different composition ratio of Fe and Ni. Alternatively, depending on the process temperature conditions, the thermal expansion coefficient of the metal thin film portion (111') can be controlled to be smaller or larger than that of the support portion (30') so that the metal thin film portion (111') can be tightly connected on the support portion (30').

[0166] In addition, during the subsequent processes such as heat treatment (H) and etching (EC2), the metal thin film portion (111') produced by electroplating needs to be well adhered to the support portion (30') without peeling off. To achieve this, various methods can be considered.

[0167] As a first step, the native oxide of the support (30') on which electroplating is performed can be controlled. Oxides may be formed on the surface of the support (30') made of silicon wafer material. On a surface with such oxides, a uniform electric field is not generated, so the plating film [metal thin film portion (111')] may not be formed uniformly, and the adhesion between the formed plating film [metal thin film portion (111')] and the support (30') may be low. Therefore, it is desirable to perform the electroplating process after performing a process to remove the native oxide.

[0168] Alternatively, another film that mediates adhesion between the plating film [metal thin film portion (111')] and the support portion (30') can be further formed. In addition to the barrier film described later, a film or a combination of films that provides adhesion to both sides of the film can be used.

[0169] As another method, the surface of the support member (30') can be pretreated before electroplating. Through physical or chemical treatment, the plating film [metal thin film part (111')] generated during the electroplating process can be formed with stronger adhesion on the support member (30'). In addition, the plating method during the electroplating process can be controlled so that the plating film [metal thin film part (111')] is formed with strong adhesion on the support member (30').

[0170] Meanwhile, referring to FIG. 27(b), the trench portion (TR) may have a recessed trench shape with two sides (SS) [see FIG. 26], and may also be understood to include a stepped shape with only one side (SS). FIG. 27(b) also includes a trench portion (TR) in the shape of a stepped (37) having a bottom surface (37a) and one side surface (37b). Accordingly, a metal thin film portion (111') can be formed by electroplating within the stepped (37) space of the edge portion of the support portion (30').

[0171] Meanwhile, referring to FIG. 28, the metal thin film portion (111': 111'b) may be configured as a laminate of two or more plating layers so that the metal thin film portion (111'b) has a coefficient of thermal expansion similar to that of the silicon material of the support portion (30'). At this time, the first metal thin film portion (111'-1) may be formed from a metal material capable of forming silicide with the support portion (30'). The first metal thin film portion (111'-1) may be formed from a material such as Ni, Co, Ti, Cr, W, Mo, etc., which has high adhesion to the support portion (30') when produced by electroplating. The second metal thin film portion (111'-2) may be formed from a material such as Invar, Super Invar, etc., which has a small coefficient of thermal expansion when produced by electroplating. Since the first and second metal thin film portions (111'-1, 111'-2) each have different coefficients of thermal expansion, the coefficient of thermal expansion of the metal thin film portion (111') can be controlled by adjusting the thickness ratio of the first and second metal thin film portions (111'-1, 111'-2). The specific thickness of the first and second metal thin film portions (111'-1, 111'-2) can be controlled by adjusting the electroplating time.

[0172] Additionally, the current density can be controlled during electroplating to form two or more layers of different compositions for the metal thin film portion (111': 111'b). For example, the metal thin film portion (111'b) may include a first metal thin film portion (111'-1), which is a pure Ni layer or a Ni-rich alloy layer, and a second metal thin film portion (111'-2), which is an Invar alloy layer. First, a first current density can be applied to form a first metal thin film portion (111'-1), which is a pure Ni or an alloy layer containing more than 60 wt% of Ni, on at least a portion of the bottom surface (BS) and side surface (SS) of the trench portion (TR). Then, by applying a second current density different from the first current density, a second metal thin film portion (111'-2), which is a FeNi alloy layer (Invar layer) containing 36 wt% to 42 wt% Ni, can be formed on the first metal thin film portion (111'-1). The second current density may be a value lower than the first current density. For example, when the first current density is applied in a plating solution environment capable of forming a FeNi alloy, a Ni-rich layer is plated, and as the second current density is changed, a layer with an increasing proportion of Fe can be plated.

[0173] However, the first metal thin film portion (111'-1) needs to have a thinner thickness than the second metal thin film portion (111'-2). In order to match the second metal thin film portion (111'-2) with a low coefficient of thermal expansion, it is preferable that the first metal thin film portion (111'-1) be formed only to a extent that secures adhesion with the support portion (30'). Taking this into consideration, it is preferable that the thickness of the first metal thin film portion (111'-1) be 2% to 20% of the thickness of the second metal thin film portion (111'-2).

[0174] Ni in the first metal thin film portion (111'-1) is advantageous for forming silicide through heat treatment at a relatively lower temperature than invar. Additionally, since Ni in the first metal thin film portion (111'-1) has good adhesion to invar, it can facilitate adhesion between the silicon material support portion (30') and the second metal thin film portion (111'-2). There is an advantage in that a connecting portion (40) can be formed through heat treatment (H) [see FIG. 29] at a temperature lower than 400°C by interposing the Ni-rich first metal thin film portion (111'-1).

[0175] As another example, the metal thin film portion (111'b) may be configured such that a pure Ni layer or a Ni-rich alloy layer is included in the lower and upper layers, and an Invar alloy layer is interposed in the middle layer. At this time, during the process of performing electroplating, a first current density may be applied to create a pure Ni or an alloy layer containing more than 60 wt% of Ni on at least a portion of the lower surface (BS) and side surface (SS) of the trench portion (TR) as a lower layer (first metal thin film portion), a second current density different from the first current density may be applied to create a FeNi alloy layer (Invar layer) containing 36 wt% to 42 wt% of Ni as an middle layer (second metal thin film portion), and a first current density different from the second current density (or a third current density) may be applied to create a pure Ni or an alloy layer containing more than 60 wt% of Ni as an upper layer (third metal thin film portion). The second current density may be a value smaller than the first current density (or the third current density). The thickness of the third metal thin film portion may correspond to the thickness of the first metal thin film portion.

[0176] At this time, the upper layer, which is pure Ni or an alloy layer containing more than 60 wt% Ni, contains more Ni than the FeNi alloy layer (Invar layer) containing Fe, so it has the advantage of reducing the degree of oxidation during the heat treatment (H) process described later. In addition, as the upper layer is removed first during the planarization (PS) process described later, it also has the advantage of protecting the intermediate layer.

[0177] Meanwhile, an auxiliary connection portion (not shown) may be further formed on at least a portion of the trench portion (TR) before electroplating the metal thin film portion (111': 111'a, 111'b) of FIGS. 27 and 28. For example, when the support portion (30') is a silicon wafer, the adhesion strength is higher when the metal thin film portion (111), made of a material such as Invar or Super Invar, is attached to the support portion (30') via an auxiliary connection portion made of a material such as Ni or Cu, compared to when it is directly attached to the support portion (30'). Taking this into consideration, the auxiliary connection portion may include at least one of Ni, Cu, Ti, Au, Ag, Al, Sn, In, Bi, Zn, Sb, Ge, and Cd. If the material of the auxiliary connection portion is difficult to electroplat, it may be formed using a sputtering or brazing method. The auxiliary connection may be formed from a material such as Ni, Cu, Ti, Au, Ag, Al, which has high adhesion to the support (30') when produced by electroplating. Alternatively, the auxiliary connection may be formed from a material such as Sn, In, Bi, Zn, Sb, Ge, Cd, which has high adhesion to the support (30') when produced by sputtering or brazing. The auxiliary connection may be formed thinly with a thickness of 0.01㎛ to 0.2㎛.

[0178] Next, referring to FIG. 29, the metal thin film portion (111') and the support portion (30') can be heat-treated (H). A removal process of the insulating portion (M1) can be performed before and after the heat treatment (H). The heat treatment can be performed at a temperature of 100°C to 800°C. For example, as in FIG. 27, when the metal thin film portion (111') is formed directly on the support portion (30'), the heat treatment can be performed at a temperature of 300°C to 800°C. As another example, as in FIG. 28, when the first metal thin film portion (111'-1) is formed between the second metal thin film portion (111'-2) and the support portion (30'), the heat treatment (H) can be performed at a temperature of about 100°C to 800°C, and more preferably at a low temperature range of about 100°C to 400°C. In the heat treatment (H) process, a predetermined pressure may be applied to perform the heat treatment with less heat.

[0179] Generally, compared to an Invar sheet produced by rolling, an Invar sheet produced by electroplating has a higher coefficient of thermal expansion. Therefore, the coefficient of thermal expansion can be lowered by performing heat treatment on the Invar sheet, but slight deformation may occur in the Invar sheet during this heat treatment process. If heat treatment is performed only on the metal thin film portion (111) that exists separately, some deformation may occur in the opening pattern (P). Therefore, if heat treatment (H) is performed while the support portion (30') and the metal thin film portion (111') are bonded together, there is an advantage in preventing the shape of the opening pattern (P) from being slightly deformed due to the heat treatment.

[0180] In addition, the present invention is in a form in which a metal thin film portion (111') is perfectly accommodated within a recessed trench portion (TR) of a support portion (30'). When heat treatment (H) is performed in this state, a unique effect is produced in which the side (SS) and bottom surface (BS) of the trench portion (TR) can prevent the metal thin film portion (111') from deforming in the horizontal direction. Furthermore, since the metal thin film portion (111') is accommodated in the trench portion (TR) and the contact area between the support portion (30') and the metal thin film portion (111') is further secured, the present invention has the advantage of being favorable for forming a connection portion (40) by heat treatment (H).

[0181] Meanwhile, the Invar thin film and silicon wafer produced by electroplating have a thermal expansion coefficient of approximately 3 to 4 ppi, which is almost the same. Therefore, even when heat treatment (H) is performed, the metal thin film portion (111') and the support portion (30') have the same degree of thermal expansion, so no misalignment due to thermal expansion occurs between them, and micro-deformation of the opening pattern (P) can be prevented.

[0182] In addition, the present invention is characterized by the connection of a metal thin film portion (111') and a support portion (30') due to heat treatment (H). During the heat treatment (H) process, a connecting portion (40) may be formed between the metal thin film portion (111') and the support portion (30'). The connecting portion (40) may be provided as an intermetallic compound in which the components of the metal thin film portion (111') and the components of the support portion (30') are combined. As the Fe and Ni components of the metal thin film portion (111') and the Si components of the support portion (30') are combined, the connecting portion (40) may be provided as a silicide containing Ni and Si, containing Fe, Ni and Si, or containing Fe and Ni. The metal thin film portion (111') and the support portion (30') may be interconnected via the connecting portion (40) by the bonding force of the intermetallic compound.

[0183] Additionally, according to one embodiment, the heat treatment (H) process can be carried out in multiple steps. As a 2-step heat treatment, Ni2Si can be formed in a low-temperature region (about 250 to 350°C) to adhere the metal thin film portion (111) onto the support portion (30'), and then the temperature can be gradually raised to a high-temperature region (about 450 to 650°C) to perform the heat treatment. In the case of the Invar metal thin film portion formed by electroplating, since it has a microcrystalline and / or amorphous structure, if the temperature is rapidly raised during heat treatment, the Invar metal thin film portion may detach or separate from the silicon wafer support portion (30') due to volume shrinkage. Therefore, it is preferable to adhere the Invar metal thin film portion to the silicon wafer support portion (30') at a low temperature and then gradually raise the temperature to a high temperature to perform the heat treatment.

[0184] In addition, according to one embodiment, a reducing atmosphere must be maintained during heat treatment (H). The reducing atmosphere can be formed with H2, Ar, or N2 atmospheres, and preferably, dry N2 gas can be used to prevent oxidation of the Invar metal thin film. To prevent oxidation of the Invar metal thin film, it is necessary to manage the O2 concentration to be less than 100 ppm. Or < 10 -2 A vacuum atmosphere of torr can be formed. The heat treatment (H) can be carried out for 30 minutes to 2 hours.

[0185] As an adhesive layer (40) (adhesive layer), such as Ni silicide or (Ni, Fe)Si silicide, is formed at the interface of a metal thin film portion (111') electroplated on a silicon wafer support portion (30'), the metal thin film portion (111') and the support portion (30') can be interconnected through the adhesive layer (40).

[0186] Meanwhile, to control the reaction between Ni, Fe-Ni and Si during heat treatment (H), a barrier film (not shown) may be formed on the support (30') before electroplating the metal thin film portion (111') on the support (30'). The barrier film can prevent the components of the plating film of the metal thin film portion (111') [e.g., Ni, Fe-Ni] from penetrating into the silicon support (30') without control. At the same time, it is desirable for the barrier film to be conductive so that electroplating can be performed on the surface. Considering this, the barrier film may include materials such as titanium nitride (TiN), titanium / titanium nitride (Ti / TiN), tungsten carbide (WC), titanium tungsten (WTi), and graphene. Thin film formation processes such as barrier film deposition can be used without limitation. The barrier film can control the reaction between Fe, Ni, and Si to form a uniform silicide, and can ensure that the metal thin film portion (111) and the connecting portion (40) are attached with appropriate adhesion force. In addition, the barrier film may be composed of a film or a combination of films capable of providing a predetermined adhesion force or adhesion force so that the metal thin film portion (111') is not separated from the supporting portion (30') when the metal thin film portion (111') is electroplated on the supporting portion (30').

[0187] By controlling the temperature and time, the thickness (silicide thickness) of the connecting part (40) can be controlled from 10 to 300 nm to connect the supporting part (30') and the metal thin film part (111').

[0188] Meanwhile, if the aforementioned auxiliary connecting part (not shown) is further included, the auxiliary connecting part between the metal thin film part (111') and the support part (30') can mediate a connection between the metal thin film part (111') and the support part (30') through a phase change in which the auxiliary connecting part between the metal thin film part (111') and the support part (30') is melted into a liquid state by heat treatment and then solidified back into a solid state during the heat treatment (H). The auxiliary connecting part can act as an adhesion layer or a glue layer. Alternatively, the connection can be performed by changing the interface state of the metal thin film part (111'), the support part (30'), and the auxiliary connecting part in such a way that the metal component of the auxiliary connecting part diffuses into the metal thin film part (111') and the support part (30'), or conversely, the component of the metal thin film part (111') and the support part (30') diffuses into the auxiliary connecting part, or the components of each other diffuse.

[0189] Meanwhile, FIGS. 29 to 33 show the state in which the connecting part (40) is formed after heat treatment (H), but the heat treatment process may be omitted considering the connection strength between the metal thin film part (111') and the supporting part (30').

[0190] Next, referring to FIG. 30, the metal thin film portion (111') can be flattened (PS). Here, flattening (PS) means polishing one side (top surface) of the metal thin film portion (111') to a mirror finish while simultaneously removing a portion of the upper part of the metal thin film portion (111') to reduce the thickness (20' -> 20). Flattening (PS) can be performed using methods such as lapping, polishing, and buffing.

[0191] After flattening (PS), the metal thin film portion (111) and the support portion (30') may share at least the same upper surface. The metal thin film portion (111) may share the same upper surface as the support portion (30') after the upper surface is flattened (PS) while the metal thin film portion (111) is recessed and received in the trench portion (TR) of the support portion (30').

[0192] Meanwhile, the heat treatment (H) of FIG. 29 and the flattening (PS) of FIG. 30 may be applied in the opposite order. First, the metal thin film portion (111') is flattened (PS) to reduce its thickness (111' -> 111), and then the connection portion (40) can be created through the heat treatment (H).

[0193] Next, referring to FIG. 31 (a), the support member (30') can be etched (EC2). The etching (EC2) can be performed on the second surface (bottom) which is opposite to the first surface (top surface) of the support member (30') connected to the metal thin film portion (111). The etching (EC2) can be performed on the portion of the support member (30') corresponding to the cell portion (C) of the metal thin film portion (111). The portion corresponding to the partition portion (SR) of the metal thin film portion (111) is not etched. Optionally, a thickness reduction process may be performed on the entire bottom surface (second surface) or the center of the support member (30') before the etching (EC2) of the support member (30').

[0194] When the etching (EC2) is completed, the support portion (30) may be formed to provide a hollow region (R) and leave only the edge portion. The support portion (30) may be provided as a holder portion (150). Since the support portion (30') is a silicon wafer, there is an advantage in that the etching (EC2) can be performed using existing semiconductor-related technology and MEMS (Micro Electro Mechanical Systems)-related technology.

[0195] To provide etch resistance, an insulating portion (M2) may be formed on the lower surface of the support portion (30') in the remaining portion excluding the portion corresponding to the cell portion (C). The insulating portion (M2) may be formed by forming a photoresist using a printing method, etc., or may be formed by forming silicon oxide or silicon nitride acting as a hard mask using methods such as thermal oxidation or thermal nitridation. Meanwhile, a metal may be used as a mask for etching. The portion exposed on the lower surface of the support portion (30') that is not covered by the insulating portion (M2) can be etched (EC2).

[0196] In addition, the present invention has the effect that the connecting portion (40) formed between the support portion (30') and the metal thin film portion (111) can serve as a stopper in the etching (EC2) process. When the etching (EC2) proceeds from the second surface of the support portion (30') toward the first surface and reaches the connecting portion (40), the etching (EC2) may not proceed further. Accordingly, damage to the metal thin film portion (111) or the opening pattern (P) can be prevented during the etching (EC2) process.

[0197] A metal thin film portion (111) is accommodated in the trench portion (TR), so that the shape of the metal thin film portion (111) is maintained during the etching (EC2) process, and the portion between adjacent trench portions (TR) in the support portion (30') is removed after the etching (EC2) process. This empty space can be provided as an opening pattern (P) of the metal thin film portion (111). If the side (SS) of the trench portion (TR) includes a slanted shape or a tapered shape, the side of the opening pattern (P) may also include a corresponding slanted shape or a tapered shape.

[0198] A connection body can be provided in which the metal thin film portion (111) and the holder portion (150: 30) are integrally connected, as the central portion of the support portion (30') is etched to form a hollow region (R).

[0199] Meanwhile, referring to FIG. 31(b), the trench section (TR) may have a recessed trench shape with two sides (SS) [see FIG. 26], and it can be understood to include a stepped shape with only one side (SS). FIG. 31(b) illustrates a trench section (TR) in the shape of a stepped (37) having a bottom surface (37a) and one side surface (37b). The trench section (TR) may also have a shape in which the sides are inclined like a taper [see FIG. 26]. In the connection body in which the metal thin film portion (111) of FIG. 31 (b) and the holder portion (150:30) are integrally connected, a trench portion (TR) in the form of a step (37) is formed in the holder portion (150:30), and since the metal thin film portion (111) is formed by electroplating within the trench portion (TR), at least a portion of the metal thin film portion (111) can be placed in the recessed trench portion (TR) of the holder portion (150:30).

[0200] Next, referring to FIG. 32, the insulating portion (M2) can be removed, and an insulating layer portion (115) can be coated on the surface of the connection between the metal thin film portion (111) and the holder portion (150: 30). The insulating layer portion (115) is coated on the opening pattern (P) of the metal thin film portion (111) so that the opening pattern (P) of the membrane portion (110: 110-9) can be determined. The process of forming the insulating layer portion (115) is the same as described above in FIG. 12.

[0201] Next, referring to FIG. 33, a conductive thin film layer (140) can be formed on the side of the opening pattern (P). The process of forming the conductive thin film layer (140) is the same as described above in FIG. 23. Through this, a membrane part (110: 110-9) having an insulating layer part (115) coated on the surface of a metal thin film part (111) is connected to a holder part (150), and the manufacture of a semiconductor test device (100: 100-9) having a conductive thin film layer (140) formed on the opening pattern (P) can be completed.

[0202] FIGS. 34 to 37 are schematic diagrams illustrating the manufacturing process of a semiconductor test device (100: 100-10) according to the 10th embodiment of the present invention. FIGS. 34 to 37 describe an example in which a plurality of opening patterns (P) are formed in a single cell portion (C).

[0203] Referring to FIG. 34 (a), a support member (30') is prepared. Then, a patterned first insulating member (M1) is formed on one side of the support member (30'), and then etching (EC) can be performed on the surface of the support member (30') exposed between the patterns of the first insulating member (M1).

[0204] Next, referring to FIG. 34(b), a trench portion (TR) formed by etching (EC) can be formed on the support portion (30'). Subsequently, a patterned second insulating portion (M2) can be formed on the upper surface of the support portion (30'), excluding the area where the trench portion (TR) is formed. The second insulating portion (M2) may have a narrower width than the first insulating portion (M1). The width of the second insulating portion (M2) may correspond to the width of the opening pattern (P).

[0205] Next, referring to FIG. 34 (c), electroplating can be performed on the support portion (30') to form a metal thin film portion (111: 111-1, 111-2). The first metal thin film portion (111-1) fills the trench portion (TR), and the second metal thin film portion (111-2) can be further formed on the first metal thin film portion (111-1). The second metal thin film portion (111-2) is not formed in the portion where the second insulating portion (M2) is placed, and the portion where the second insulating portion (M2) is located can be provided as an opening pattern (P). The first and second metal thin film portions (111-1, 111-2) may be formed at once through the same process or each may be formed through two separate processes.

[0206] Electroplating can be performed on the second metal thin film portion (111-2) with a longer width along both sides of the second insulating portion (M2) than on the first metal thin film portion (111-1). When considering only the metal thin film portion (111), the two sides of the second metal thin film portion (111-2) appear to be more protruding. This protruding part can be provided as a cantilever portion (CT), such as the conductive cantilever portion (CT) described above in FIGS. 24 and 25. In other words, based on the first metal thin film portion (111-1) having a first width of the opening pattern (P) and the second metal thin film portion (111-2) having a second width of the opening pattern (P) that is narrower than the first width, the part of the second metal thin film portion (111-2) that protrudes further in the lateral direction than the first metal thin film portion (111-1) can be provided as a cantilever portion (CT).

[0207] Meanwhile, the first and second metal thin film portions (111-1, 111-2) may be formed in a different way from steps (a) to (c) of FIG. 34. Referring to FIG. 35 (a'), a first trench portion (TR1) and a second trench portion (TR2) may be formed on the support portion (30'). The width of the second trench portion (TR2) may be formed to be wider than that of the first trench portion (TR1).

[0208] Next, referring to (b') of FIG. 35, electroplating can be performed on the support portion (30') to form a metal thin film portion (111: 111-1, 111-2). The first metal thin film portion (111-1) can be formed by filling the first trench portion (TR1), and the second metal thin film portion (111-2) can be formed by filling the second trench portion (TR2) of the first metal thin film portion (111-1).

[0209] Meanwhile, after forming the metal thin film portion (111) of FIGS. 34 and FIGS. 35, the heat treatment (H) process described in FIG. 29 and the flattening (PS) process described in FIG. 30 may be applied. For convenience of explanation, the connecting portion (40) is omitted from the illustration below, but if the heat treatment (H) process is performed, the connecting portion (40) may be formed between the metal thin film portion (111) and the support portion (30').

[0210] Next, referring to FIG. 36, the support member (30') can be etched (EC2). The etching (EC2) can be performed on the second surface (bottom) which is opposite to the first surface (top surface) of the support member (30') connected to the metal thin film portion (111). When the etching (EC2) of the support member (30') exposed between the third insulating portion (M3) is completed, the support member (30) can be formed to provide a hollow region (R) and only the edge portion remains. As the central portion of the support member (30') is etched to provide a hollow region (R), a connection body in which the metal thin film portion (111) and the holder portion (150: 30) are integrally connected can be provided.

[0211] Next, referring to FIG. 37, the third insulating part (M3) can be removed, and an insulating layer part (115) can be coated on the surface of the connection between the metal thin film part (111) and the holder part (150: 30). Subsequently, a conductive thin film layer (140) can be formed on the side of the opening pattern (P). Through this, the membrane part (110: 110-10) with the insulating layer part (115) coated on the surface of the metal thin film part (111) is connected to the holder part (150), and the manufacture of a semiconductor test device (100: 100-10) with a conductive thin film layer (140) formed on the opening pattern (P) can be completed.

[0212] Meanwhile, in the semiconductor test device (100: 100-9, 100-10) of FIG. 33 and FIG. 37, instead of the conductive thin film layer (140), an electrical path portion (130) may be filled into the opening pattern (P) to form an electrical connection path.

[0213] Alternatively, instead of forming a trench portion (TR) on the support portion (30'), a patterned insulating portion (not shown) may be formed, and then electroplating may be performed on the support portion (30') to form a metal thin film portion (111) including a plurality of opening patterns (P). Afterward, the support portion (30') may be etched to form a holder portion (150), and a conductive thin film layer (140) may be further formed on the side of the insulating layer portion (115) and the opening pattern (P) to manufacture a semiconductor test device (100).

[0214] FIG. 38 is a cross-sectional micrograph of a metal film produced by electroplating according to a comparative example. FIG. 39 is a cross-sectional micrograph of a metal thin film portion produced by electroplating according to an embodiment of the present invention.

[0215] The comparative example in Fig. 38 shows a metal thin film formed by electroplating on a conductive substrate. It can be observed that crystals of the plating film appear in a vertical direction or in a column-like shape. From another perspective, it can be seen that the change in the composition of the plating film during the electroplating process occurs along the vertical direction. This may be the result of the metal thin film forming crystals in a vertical direction from the surface of the conductive substrate when the thin film is electroplated without an insulating layer such as PR. Alternatively, even if an insulating layer such as PR is present, it may be the result of the metal thin film forming crystals only in a vertical direction from the surface of the conductive substrate.

[0216] An embodiment of the present invention in FIG. 39 shows a metal thin film portion (111) formed by electroplating on a support portion (30') in which a trench portion (TR) is formed through the same process as FIG. 26 to FIG. 29 described above. In particular, FIG. 39 shows an image of the body portion of the metal thin film portion (111) between adjacent opening patterns (P). Unlike the comparative example in FIG. 38, the present invention can be seen to show that the crystals of the metal thin film are not in a vertical shape or a column-like shape, but rather have a shape tilted at a predetermined angle in the vertical direction. From another perspective, this can also be seen as a change in the composition of the metal thin film portion (111') [or plating film] during the electroplating process occurring in a combination of the vertical and horizontal directions.

[0217] Further comparison with Figures 40 and 41 is as follows.

[0218] FIG. 40 is a schematic side cross-sectional view showing a metal film produced by electroplating according to a comparative example. FIG. 41 is a schematic side cross-sectional view showing a metal thin film portion produced by electroplating according to an embodiment of the present invention.

[0219] Referring to FIG. 40, the electroplating process according to the comparative example involves forming an insulating portion (MP), such as PR, on a conductive substrate (CP), and forming a metal thin film (MS: MS1 to MS3) by electroplating through the space between the patterns of the insulating portion (MP). The metal thin film (MS) may be formed to a degree that partially exceeds the height of the insulating portion (MP) (MS1), formed to a degree lower than the height of the insulating portion (MP) (MS2), or formed to a degree that exceeds the height of the insulating portion (MP) and covers the insulating portion (MP) (MS3).

[0220] The common point in the three cases above is that the metal thin film (MS) is electroplated to form crystals in a vertical direction from the surface (Sa) of the conductive substrate (CP) exposed between the insulating part (MP) patterns. Since the side (Sb) of the insulating part (MP) is an insulator, it cannot serve as the reference point for the start of electroplating. Consequently, electroplating is performed and crystals can be formed only in a vertical direction from the exposed horizontal surface (Sa) of the conductive substrate (CP) which possesses conductive properties.

[0221] Referring to FIG. 41 (a), in the electroplating process according to the present invention, the surface of the support member (30') is not formed only in the horizontal plane direction during electroplating, but due to the trench section (TR), the lower surface (S1) and the side surface (S2) of the trench section (TR) of the support member (30') can serve as the reference for starting electroplating. Ultimately, a crystal can be formed by combining electroplating performed in the vertical direction (normal direction) from the lower surface (S1) of the trench section (TR) of the support member (30') having conductive properties and electroplating performed in the vertical direction (normal direction) from the side surface (S2) of the trench section (TR). That is, a crystal can be formed while receiving forces in the vertical and horizontal directions.

[0222] FIG. 42 is a cross-sectional micrograph of a metal thin film portion formed by electroplating on a support portion according to one embodiment of the present invention. FIG. 42 may correspond to a cross-sectional micrograph of FIG. 41 (a).

[0223] Referring further to FIG. 41 (a) and FIG. 42, the composition and crystal form may differ in each region (Z1, Z2, Z3) of the metal thin film portion (111'). As previously described, the metal thin film portion (111') can be plated to form two layers having different compositions by adjusting the current density in FIG. 28. In addition to this method, the composition and crystal form may differ in each region (Z1, Z2, Z3) due to structural causes that form the trench portion (TR) in the present invention.

[0224] The first region (Z1) is a region corresponding to the first surface (S1), which is the lower surface of the metal thin film portion (111') [or the lower surface of the trench portion (TR)]. The first region (Z1) can receive many characteristics of electroplating starting from the first surface (S1). The crystal shape can also be formed with more force acting in the vertical direction than in the horizontal direction.

[0225] The second region (Z2) can receive the characteristics of electroplating starting from the second surface (S2), which is the side of the opening pattern (P) [or, the side of the trench portion (TR)] together with the first surface (S1). Accordingly, the crystal shape can also be formed by a combination of vertical and horizontal forces.

[0226] The third region (Z3) is a region where the insulating part (M1) can be placed, corresponding to the upper surface of the metal thin film part (111'). The third region (Z3) cannot serve as a reference for the start of electroplating by the insulating part (M1) [silicon oxide, PR, etc.]. Accordingly, as electroplating continues from the second region (Z2), crystals can be formed by combining forces in the resin direction and the horizontal direction, but the form of the force may differ as it is at a greater distance than the second region (Z2).

[0227] Ultimately, the composition of the first surface (S1), which is the lower surface of the metal thin film portion (111), and the second surface (S2), which is the side of the opening pattern (P), and the composition of the third surface (S3), which is the upper surface of the metal thin film portion (111) may also be different.

[0228] Meanwhile, referring to FIG. 41 (b), the metal thin film portion (111') can be heat-treated (H) and then planarized (PS), or the metal thin film portion (111') can be heat-treated after planarization (PS) to provide the metal thin film portion (111) [see FIG. 29 and FIG. 30]. Afterwards, the third surface (S3) can become the upper surface of the opening pattern (P) [or the upper surface of the metal thin film portion (111)] by etching (EC2) of the support portion (30') [see FIG. 31].

[0229] FIG. 43 is a planar microscope image of a metal thin film portion after a planarization process according to one embodiment of the present invention. FIG. 43 shows the planar view of the metal thin film portion after performing planarization (PS) in FIG. 42.

[0230] During the heat treatment (H) process, magnetic domains may be formed as crystals within the metal thin film portion (111') grow. Referring to FIGS. 42 and FIGS. 43, it can be seen that irregularly shaped dark gray / light gray figures appear in the metal thin film portion (111'). These dark gray / light gray figures may correspond to magnetic domains.

[0231] FIGS. 43 and 44 are drawings showing line data and composition in the depth direction of a metal thin film portion formed by electroplating on a support portion according to one embodiment of the present invention.

[0232] Composition analysis was performed along the direction from the surface of the metal thin film portion downwards, as shown in the line data direction of FIG. 43. The X-axis of the data in FIG. 44 represents the surface of the metal thin film portion as 0 and the distance moved downwards by 4 μm, and the Y-axis represents the amount of the component. Referring to FIG. 44 (c), the amount of Si increases rapidly starting from about 2.6 μm. Therefore, it can be confirmed that the metal thin film portion (111') formed in the trench portion (TR) has a thickness of about 2.6 μm from the top surface to the bottom surface, and that a support portion (30') made of silicon wafer material appears from about 2.6 μm onwards.

[0233] Additionally, referring to FIG. 44 (a), it can be seen that the amount of Ni increases rapidly around 2.6 μm. That is, it can be seen that the proportion of Ni is relatively higher in the parts indicated by the dotted ellipses in FIG. 44 (a) and (b) than in other parts. In other words, it can be seen that the composition is nickel-rich near the first surface (S1), which is the lower surface of the metal thin film part (111'), than near the third surface (S3), which is the upper surface. Likewise, not only the first surface (S1) but also the second surface (S2), which is the starting surface for electroplating, may have a nickel-rich composition than near the third surface (S3). Since the metal thin film (MS) according to the comparative example described above in FIG. 40 is nickel-rich only on the lower surface, it can be distinguished from the metal thin film part (111') of the present invention.

[0234] FIG. 45 is an enlarged side cross-sectional view of FIG. 41 (b), which is a schematic side cross-sectional view showing the crystal shape of the metal thin film portion before and after the planarization process according to one embodiment of the present invention. FIG. 46 is a planar microscope image of the metal thin film portion after the planarization process according to one embodiment of the present invention. FIG. 46 (a) is a Z-axis step map observed in AFM mode at -100 to 100 nm, and FIG. 46 (b) is a magnetic domain map observed in MFM mode at -10 to 2.5 deg.

[0235] Referring to FIG. 45 (a), as described above in FIG. 42, magnetic domains (GR) can be formed as crystals within the metal thin film portion (111') grow during the heat treatment (H) process. That is, the presence of magnetic domains (GR) is a result of the heat treatment of the metal thin film portion (111'), and can be distinguished from a plating film that has undergone only general electroplating. In addition, the present invention may perform a planarization (PS) process after the heat treatment (H).

[0236] Referring to FIG. 45 (b), as the upper surface of the metal thin film portion (111') is flattened by the flattening (PS) process, the magnetic domains (GR') on the upper surface [third surface (S3)] of the metal thin film portion (111') can also have a flattened upper surface shape. That is, the magnetic domains have an irregular three-dimensional shape, but as the upper surface is flattened, they can have a three-dimensional shape that includes at least one horizontal side surface. After the flattening (PS) process, the surface roughness (Ra) of the upper surface of the metal thin film portion (111') can also be controlled. The upper surface of the metal thin film portion (111') may have a high roughness due to fine irregularities resulting from electroplating and heat treatment, but after flattening (PS), such as polishing, the surface roughness (Ra) can be lowered. Preferably, the surface roughness (Ra) may be smaller than 0.1 μm, and the surface roughness (Rz) may be smaller than 1.0 μm.

[0237] Referring to FIG. 46, magnetic domains (GR') can be observed on the upper surface of the metal thin film portion (111'). The size of the magnetic domains (GR') is on a scale of several μm, preferably about 1 μm, and can be observed according to the grain size and direction.

[0238] In addition, patterns such as waves, stripes, and wrinkles can be observed in the domains (GR'), which appear to be patterns formed during the process of generating crystals with N and S poles through electroplating.

[0239] FIG. 47 is a schematic diagram showing a semiconductor test device (100: 100-11) according to the 11th embodiment of the present invention.

[0240] Referring to FIG. 47, a semiconductor test device (100: 100-11) is shown in which a cantilever portion (CT) is formed on a metal thin film portion (111) as described above in FIG. 37. An insulating layer portion (115) may be formed on the surface of the cantilever portion (CT), and a conductive thin film layer (140) may be formed thereon.

[0241] A conductive thin film layer (140) may be formed on the side of the opening pattern (P). Additionally, as shown in (c) of FIG. 21, the conductive thin film layer (140) may be formed not only on the side of the opening pattern (P) but also around the top and bottom of the opening pattern (P). Microbumps (MB) may come into contact with the conductive thin film layer (140) on the top of the opening pattern (P), thereby forming an electrical connection from the top to the bottom of the opening pattern (P).

[0242] FIGS. 48 to 50 are schematic diagrams showing the manufacturing process of a semiconductor test device (100: 100-11) according to the 11th embodiment of the present invention.

[0243] Referring to FIG. 48(a), a support member (30') is prepared. To enable electroforming, the support member (30') may be a conductive substrate (30') made of a conductive material. To have conductivity and simultaneously low resistance, 10 on the support member (30') [or the conductive substrate (30')] 19 cm -3 Higher concentration doping can be performed. Doping may be performed over the entire support portion (30') or only on the surface portion of the support portion (30'). According to one embodiment, the surface resistance of the support portion (30') is 5 x 10 -4 ~ 1 X 10 -2 It can be ohm·cm. The support portion (30') can be used as a cathode electrode in electroplating.

[0244] If the support member (30') is made of silicone material, a silicon oxide layer (32) may be formed on one side.

[0245] Next, a patterned first insulating portion (M1) can be formed on one side of the support portion (30'). Subsequently, a first etching (EC1) can be performed on the surface of the support portion (30') exposed between the patterns of the first insulating portion (M1). The first etching (EC1) can be wet or dry, but dry etching, which has anisotropic etching characteristics and can clearly show the desired shape, may be considered.

[0246] Next, referring to FIG. 48 (b), a first trench (TR1) can be formed by being recessed on the first surface (or upper surface) of the support (30') by the first etching (EC1). The depth (h) of the first trench (TR1) may correspond approximately to the thickness of the metal thin film portion (111) to be formed. For example, the depth (h) of the first trench (TR1) may be about 5 to 50 μm. Later, both ends of the first trench (TR1) may be provided as a space to be formed for a cantilever portion (CT).

[0247] Next, referring to (c) of FIG. 48, a patterned second insulating portion (M2) can be formed on one side of the support portion (30') and on the first trench portion (TR1). Subsequently, a second etching (EC2) can be performed on the surface of the first trench portion (TR1) exposed between the patterns of the second insulating portion (M2). The second etching (EC2) can be wet or dry, but dry etching, which has anisotropic etching characteristics and can clearly reveal the desired shape, may be considered.

[0248] Next, referring to (d) of FIG. 49, a second trench (TR2) can be formed by a second etching (EC2) to form a depression with a narrower width on the first trench (TR1). The first and second trenches (TR1, TR2) can be combined to form a trench (TR).

[0249] Next, referring to FIG. 49 (e), a metal thin film portion (111) can be formed by performing electroplating on a support portion (30'). The metal thin film portion (111: 111-1, 111-2) can be formed within a trench portion (TR: TR1, TR2). The first metal thin film portion (111-1) can fill the second trench portion (TR2), and the second metal thin film portion (111-2) can be formed by further forming on the first metal thin film portion (111-1) to fill the first trench portion (TR1).

[0250] Meanwhile, after forming the metal thin film portion (111), the heat treatment (H) process described in FIG. 29 and the flattening (PS) process for the portion of the metal thin film portion (111) that exceeds the height of the support portion (30') described in FIG. 30 may be applied. For convenience of explanation, the connecting portion (40) is omitted from the illustration below, but if the heat treatment (H) process is performed, the connecting portion (40) may be formed between the metal thin film portion (111) and the support portion (30').

[0251] Next, referring to (f) of FIG. 49, the support member (30') can be subjected to a third etching (EC3). The third etching (EC3) can be performed on the second surface (bottom) which is opposite to the first surface (top surface) of the support member (30') connected to the metal thin film portion (111). The third etching (EC3) can be performed on the portion corresponding to the cell portion (C), excluding the edge portion. Optionally, a thickness reduction process may be performed on the entire bottom surface or the center of the support member (30') before the third etching (EC3) of the support member (30'). When the etching (EC3) of the support member (30') exposed between the third insulating portions (M3) is completed, the support member (30) may be formed to provide a hollow region (R) and leave only the edge portion. The remaining edge portion is provided as a holder portion (150:30), and a connection body in which the metal thin film portion (111) and the holder portion (150:30) are integrally connected may be provided.

[0252] The space between the patterns of the metal thin film portion (111) from which the support portion (30) has been removed may be provided as an opening pattern (P). The metal thin film portion (111) may provide cantilever portions (CT) on both sides of the pattern. A portion of the second metal thin film portion (111-2) protruding on both sides of the first metal thin film portion (111-1) may be provided as a cantilever portion (CT).

[0253] Meanwhile, heat treatment may be performed before etching the lower surface of the support member (30'). Due to the heat treatment, the metal thin film member (111) and the support member (30') can be connected. The heat treatment process and the connection part are the same as described above in FIG. 29.

[0254] Next, referring to (g) of FIG. 50, an insulating layer (115) can be formed on the metal thin film portion (111). Subsequently, a conductive thin film layer (140) can be further formed on the insulating layer portion (115) by plating or other thin film forming methods.

[0255] Next, referring to (h) of FIG. 50, a fourth insulating part (M4), such as PR, can be formed in the opening pattern (P). Then, a fourth etching (EC4) can be performed to etch the exposed portion of the conductive thin film layer (140), excluding the portion covered by the fourth insulating part (M4).

[0256] Next, referring to (i) of FIG. 50, the conductive thin film layer (140) can be left only around the opening pattern (P) after the fourth etching (EC4). In other words, the semiconductor test device (100: 100-11) can have the conductive thin film layer (140) formed only on the surface of the cantilever portion (CT).

[0257] Meanwhile, when manufacturing a semiconductor test device (100: 100-11) according to the 11th embodiment, instead of the process of FIGS. 49 to 51, the process of FIGS. 26 to 37 described above may be applied by changing only the formation location of the conductive thin film layer (140).

[0258] FIG. 51 is a schematic diagram showing a form of testing electrical connections by applying a semiconductor test device according to the 11th embodiment of the present invention.

[0259] Referring to FIG. 51, each opening pattern (P) formed in the membrane portion (110: 110-11) can correspond one-to-one with the microbump (MB) on the bottom of the stacked semiconductor memory (15) [or semiconductor memory]. Since the width of the opening pattern (P) on the opposite side is relatively wide, there is an advantage that the connecting electrode (CE), etc. of the interposer (13') can be guided along the tapered side and come into contact with the conductive thin film layer (140). Since the conductive thin film layer (140) is formed on the cantilever portion (CT) protruding in a cantilever shape, the microbump (MB) / connecting electrode (CE) can make elastic contact on the upper and lower surfaces. Since the opening pattern (P) is formed with a large space due to the cantilever portion (CT) positioned on the upper and lower sides, elastic contact can be provided more easily.

[0260] According to one embodiment, the width of the opening pattern may be about 10 μm, the width of the cantilever portion (CT) may be about 8 to 10 μm, the thickness of the cantilever portion (CT) may be about 3 to 5 μm, and the thickness of the metal thin film portion (111) excluding the thickness of the cantilever portion (CT) may be about 10 μm.

[0261] FIGS. 52 to 54 are schematic diagrams illustrating a method for manufacturing a semiconductor test device (100: 100-12) according to the 12th embodiment of the present invention.

[0262] In the following, a manufacturing process of a semiconductor test device that embodies step (h) of FIG. 50 described above is explained. A process of forming an insulating portion, which is an etching prevention pattern (or, etching prevention layer), on the upper surface of a membrane portion (110), and a process of forming an insulating portion, which is an etching prevention pattern (or, etching prevention layer), on the lower surface of a membrane portion (110) are each performed to form a conductive thin film layer (140) corresponding to each opening pattern (P).

[0263] The process following the step of preparing a connector in which a membrane part (110) having a plurality of opening patterns and a holder part (150: 30) are connected by forming an insulating layer part (115) on a metal thin film part (111) as described in step (g) of FIG. 50 above will be explained.

[0264] First, referring to FIG. 52 (a), a conductive thin film layer (140) can be formed on the surface of at least the membrane portion (110). The conductive thin film layer (140) can be formed on the membrane portion (110) or the insulating layer portion (115) using plating, deposition, or other thin film forming methods. The conductive thin film layer (140) can also be formed on the surface of the holder portion (150: 30) in addition to the membrane portion (110).

[0265] Next, referring to FIG. 52(b), a first etching prevention pattern (M5) [or a fifth insulating part (M5)] can be formed on an opening pattern (P) on the upper surface (first surface) of the membrane part (110). Hereinafter, based on the shape illustrated in FIG. 52(b), the upper surface of the membrane part (110) is referred to as the first surface and the lower surface as the second surface. After coating a photoresist or the like on the upper surface of the membrane part (110), the first etching prevention pattern (M5) can be formed through an exposure / development process. The position of the first etching prevention pattern (M5) formed on the upper surface of the membrane part (110) can correspond to a conductive thin film layer (140: 141) [see FIG. 53(c)] to be left thereafter. That is, the position of the first etching prevention pattern (M5) formed on the upper surface (first surface) of the membrane portion (110) can correspond to a conductive thin film layer (140: 141) further formed in a horizontal direction from the upper side of the opening pattern (P).

[0266] Next, etching (EC5) [or, fifth etching (EC5)] can be performed in one direction on the upper surface (first surface) of the membrane portion (110) to etch the portion of the exposed conductive thin film layer (140) excluding the portion covered by the first etching prevention pattern (M5) [or, fifth insulating portion (M5)].

[0267] Meanwhile, optionally, a template (70) may be placed at the bottom of the connection between the membrane portion (110) and the holder portion (150) to prevent unintended etching on the lower surface (second surface) of the membrane portion (110). The template (70) is provided in a wide plate shape to support the holder portion (150) and, at the same time, prevent the etching solution from penetrating in the direction of the opening pattern (P) from the hollow region (R) of the holder portion (150), thereby allowing the etching process to be performed only on the upper surface of the membrane portion (110). Meanwhile, if the etching process is possible on the upper surface of the membrane portion (110) without the template (70), the template (70) may not be used.

[0268] Next, referring to FIG. 53 (c), the first etching prevention pattern (M5) [or the fifth insulating part (M5)] can be removed. On the upper surface (first surface) of the membrane part (110), the conductive thin film layer (140) may be left with a conductive thin film layer (141) that is further formed horizontally at the upper side of the opening pattern (P). The conductive thin film layer (142') on the lower surface (second surface) of the membrane part (110) may be in a state where etching is not performed and it covers the surface of the lower surface (second surface) of the membrane part (110).

[0269] Next, referring to FIG. 53 (d), after flipping the connection between the membrane portion (110) and the holder portion (150), a second etching prevention pattern (M6) [or a sixth insulating portion (M6)] can be formed on the opening pattern (P) on the lower surface (second surface) of the membrane portion (110). After coating a photoresist or the like on the lower surface (second surface) of the membrane portion (110), the second etching prevention pattern (M6) can be formed through an exposure / development process. The position of the second etching prevention pattern (M6) formed on the membrane portion (110) can correspond to the conductive thin film layer (140: 142) [see FIG. 54 (e)] to be left thereafter. That is, the position of the second anti-etching pattern (M6) formed on the lower surface (second surface) of the membrane portion (110) can correspond to a conductive thin film layer (140: 142) further formed in a horizontal direction at the lower side of the opening pattern (P).

[0270] Next, etching (EC6) [or sixth etching (EC6)] can be performed in one direction on the lower surface (second surface) of the membrane portion (110) to etch the portion of the exposed conductive thin film layer (140) excluding the portion covered by the second etching prevention pattern (M6) [or sixth insulating portion (M6)].

[0271] Meanwhile, optionally, a second template (73) may be placed on the membrane portion (110) and the upper surface (first surface) to prevent unintended etching on the upper surface (first surface) of the membrane portion (110). After step (c) of FIG. 53, the connection between the membrane portion (110) and the holder portion (150) may be flipped so that it is supported by the second template (73). Alternatively, the second template (73) may be adhered to the upper surface (first surface) of the membrane portion (110) without flipping the connection between the membrane portion (110) and the holder portion (150).

[0272] The template (70) or the second template (73) may be made of a material through which light, such as a laser or light for exposing an anti-etching pattern, can be transmitted. The template (70) / second template (73) may be made of materials such as glass, silica, quartz, alumina (Al2O3), borosilicate glass, or zirconia.

[0273] The upper surface (first surface) of the membrane portion (110) and the second template (73) can be bonded together via a temporary adhesive portion (75). The temporary adhesive portion (75) may use a dry film resist layer (DFR layer), and the dry film resist layer may be provided as a film-type photoresist. Alternatively, the temporary adhesive portion (75) may use liquid wax or liquid photoresist, but using a dry film resist layer allows bonding to be performed in a low-temperature region of about 60°C or lower, and has the effect of achieving both the bonding and the formation of an etching-prevention pattern without using a liquid wax layer and a liquid photoresist layer respectively, so using a dry film resist layer as the temporary adhesive portion (75) may be considered more preferable.

[0274] Meanwhile, the holder portion (150:30) may have a thickness reduced to 100㎛ to 300㎛. The process of reducing the thickness of the holder portion (150:30) can be performed 1) during the process of forming a connection in which the membrane portion (110) and the holder portion (150:30) are connected, 2) before forming a conductive thin film layer (140) on the surface of the membrane portion (110) of FIG. 52 (a), and 3) between the processes of FIG. 53 (c) and FIG. 53 (d).

[0275] As shown in the enlarged view on the right of FIG. 53 (e), by using a holder portion (150-2) with a relatively thin thickness of 100㎛ to 300㎛, etching can be smoothly performed on the exposed portion of the conductive thin film layer (140) excluding the portion covered by the second etching prevention pattern (M6) [or the sixth insulating portion (M6)]. If the thickness of the holder portion (150: 30) is too thick, the masking process for the formation of the second etching prevention pattern (M6) [or the sixth insulating portion (M6)] and exposure / development may be difficult, and the inconvenience of having to form a thick second etching prevention pattern (M6), such as photoresist, may arise, so it is desirable to reduce the thickness. Of course, if there is no problem with the smooth formation of the second etching prevention pattern (M6), a holder part (150: 30) with no thickness reduction can be used as shown in the left enlarged view (e) of FIG. 53.

[0276] Next, referring to FIG. 54 (e), the second etching prevention pattern (M6) [or the sixth insulating part (M6)] can be removed. On the lower surface (second surface) of the membrane part (110), the conductive thin film layer (140) may be left with a conductive thin film layer (142' -> 142) that is further formed horizontally at the lower side of the opening pattern (P).

[0277] After the formation of the conductive thin film layer (142), the second template (73) can be debonded from the membrane portion (110). The debonding of the second template (73) can be performed by applying heat, chemical treatment, ultrasonic treatment, or UV treatment to the temporary adhesive portion (75). For example, if at least one of applying heat, chemical treatment, ultrasonic treatment, or UV treatment is applied to the temporary adhesive portion (75), which is a dry film resist layer, the adhesive force between the second template (73) and the membrane portion (110) is weakened, and the second template (73) can be debonded.

[0278] Next, referring to (f) of FIG. 54, the semiconductor test device (100: 100-12) may have a conductive thin film layer (141) remaining in a horizontal direction at the top of the side of the opening pattern (P) as well as at the bottom of the side of the opening pattern (P), and a conductive thin film layer (142) remaining in a horizontal direction at the bottom of the side of the opening pattern (P). Since one unit of the interconnected conductive thin film layer (140) is formed spaced apart from each opening pattern (P), the opening patterns (P) can be insulated from each other.

[0279] FIGS. 55 and 56 are schematic diagrams illustrating another method of manufacturing a semiconductor test device according to the 12th embodiment of the present invention. Hereinafter, the description of the configuration identical to the manufacturing process of the conductive thin film layer (140) described above through FIGS. 52 to 54 will be omitted, and only the differences will be described. The process following the step of preparing a connector in which a membrane part (110) having a plurality of opening patterns and a holder part (150: 30) are connected by forming an insulating layer part (115) on a metal thin film part (111) as described above in step (g) of FIG. 50 will be described.

[0280] First, referring to FIG. 55 (a), a sacrificial layer (M7), such as a photoresist [or an etching prevention layer (M7), a seventh insulating layer (M7)] can be formed on the surface of the membrane portion (110). The sacrificial layer (M7) can also be formed on the surface of the holder portion (150: 30) in addition to the membrane portion (110).

[0281] Next, referring to FIG. 55 (b), a portion of the sacrificial layer (M7) can be patterned through an exposure / development process. The sacrificial layer (M7) [or, etching prevention layer (M7), seventh insulating portion (M7)] can be left only in the portion outside the area where the conductive thin film layer (140) is to be formed.

[0282] Next, referring to FIG. 55 (c), a conductive thin film layer (140: 140', 140") can be formed on the surface of the membrane portion (110) and on the sacrificial layer (M7). The conductive thin film layer formed on the surface of the membrane portion (110) is denoted as 140', and the conductive thin film layer formed on the anti-etching layer (M7) is denoted as 140". The conductive thin film layer (140) can be formed on the membrane portion (110) and the sacrificial layer (M7) using plating, deposition, or other thin film forming methods. The conductive thin film layer (140) can also be formed on the surface of the holder portion (150: 30) in addition to the membrane portion (110).

[0283] Next, referring to (d) of FIG. 56, the sacrificial layer (M7) can be removed. When the sacrificial layer (M7) is removed in a lift-off (LO) manner, the conductive thin film layer (140) on the sacrificial layer (M7) can also be lifted off (LO) and removed.

[0284] Next, referring to (e) of FIG. 56, the semiconductor test device (100: 100-12) may have a conductive thin film layer (141) remaining in a horizontal direction at the top of the side of the opening pattern (P) as well as at the bottom of the side of the opening pattern (P), and a conductive thin film layer (142) remaining in a horizontal direction at the bottom of the side of the opening pattern (P). Since one unit of the interconnected conductive thin film layer (140) is formed spaced apart from each opening pattern (P), the opening patterns (P) can be insulated from each other.

[0285] FIG. 57 is a schematic diagram showing the form of a semiconductor test device according to the 13th to 14th embodiments of the present invention.

[0286] Referring to FIG. 57(a), the semiconductor test device (100: 100-13) is formed such that a conductive thin film layer (140, 141, 142) is formed on the side of the opening pattern (P), as in FIG. 54 and FIG. 56. The semiconductor test device (100: 100-13) may provide a plurality of hollow regions (R: R'-a, R'-b) [or a plurality of cell sections (C1, C2). In FIG. 57(a), for convenience, two hollow regions (R: R'-a, R'-b) or two cell sections (C1, C2) are shown, but a larger number may be included. The plurality of hollow regions (R) may be arranged along the X-axis and Y-axis directions on a horizontal plane.

[0287] The size (horizontal area) of each hollow region (R': R'-a, R'-b) can correspond to the size of a stacked semiconductor memory (15), which is (width) x (height) (several mm to tens of mm) x (several mm to tens of mm). In order to partition each hollow region (R'), in addition to the holder portion (150) being placed on the edge portion of the semiconductor test device (100: 100-12), grid portions (155) having a thickness corresponding to that of the holder portion (150) are also formed in the center portion, so that the grid portions (155) can partition the hollow regions (R') and provide multiple of them. Accordingly, the semiconductor test device (100: 100-12) can perform tests on multiple semiconductor memories at once.

[0288] As another example, referring to FIG. 57(b), cutting (SP) can be performed on the semiconductor test device (100: 100-13) of FIG. 57(a). Through cutting (SP) of the grid section (155), the semiconductor test device (100: 100-13) can be separated into a plurality of semiconductor test devices (100: 100-14a, 100-14b). A test of the semiconductor memory can be performed through each of the semiconductor test devices (100: 100-14a, 100-14b). Accordingly, the present invention has the advantage of enabling mass production of a plurality of semiconductor test devices (100: 100-14a, 100-14b).

[0289] As described above, the present invention can provide a semiconductor test device capable of performing a test by contacting a microbump of a semiconductor device and a method for manufacturing the same, and has the effect of preventing damage to the microbump and performing a connection in a precise alignment state.

[0290] Although the present invention has been illustrated and described with reference to preferred embodiments as described above, it is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the scope of the invention without departing from the spirit of the invention. Such modifications and changes should be deemed to fall within the scope of the present invention and the appended claims. Explanation of the symbols

[0291] 10: Semiconductor device 13: Interposer 15: Second semiconductor package, stacked semiconductor memory 30': Support, conductive substrate 40: Connection part 70, 73: Template 100: Semiconductor test device 110: Membrane section 111: Metal thin film part 115: Insulation layer 130: Electrical path section 140, 141, 142: Conductive thin film layer 150: Holder part CT: Cantilever section MB, MB2: Micro bump P: Opening pattern R: China region TR: Trench section

Claims

Claim 1 A method for manufacturing a semiconductor test device that is interposed between semiconductor memories or between a semiconductor memory and an interposer to perform electrical connection testing, comprising: (a) preparing a connector in which a membrane portion having a plurality of opening patterns and a holder portion are connected; (b) forming a conductive thin film layer on at least the surface of the membrane portion; and (c) removing a portion of the conductive thin film layer to mutually insulate at least adjacent opening patterns; wherein step (a) comprises: (a1) preparing a support portion which is a conductive substrate and includes a first surface and a second surface opposite to the first surface; (a2) forming a metal thin film portion having a plurality of opening patterns on the first surface of the support portion by an electroforming method; (a3) ​​forming the holder portion by etching the remainder excluding the edge portion of the support portion on the second surface of the support portion; and (a4) forming an insulating layer portion of an insulating material on the surface of the metal thin film portion to constitute the membrane portion. Claim 2 A method for manufacturing a semiconductor test device that performs electrical connection testing interposed between semiconductor memories or between a semiconductor memory and an interposer, comprising: (a) preparing a connector in which a membrane portion having a plurality of opening patterns and a holder portion are connected; (b) forming a sacrificial layer on at least the surface of the membrane portion; (c) forming a conductive thin film layer on the surface of the membrane portion and the sacrificial layer; (d) removing the sacrificial layer and removing a portion of the conductive thin film layer to mutually insulate at least adjacent opening patterns; wherein step (a) comprises: (a1) preparing a support portion which is a conductive substrate and includes a first surface and a second surface opposite to the first surface; (a2) forming a metal thin film portion having a plurality of opening patterns on the first surface of the support portion by an electroforming method; (a3) ​​forming the holder portion by etching the remainder excluding the edge portion of the support portion on the second surface of the support portion; (a4) forming an insulating layer portion of an insulating material on the surface of the metal thin film portion to form the membrane portion A method for manufacturing a semiconductor test device comprising the step of configuring. Claim 3 delete Claim 4 A method for manufacturing a semiconductor test device according to claim 1, wherein in step (c), a portion of the conductive thin film layer is removed to form an electrical connection path from the top to the bottom of each of the opening patterns. Claim 5 A method for manufacturing a semiconductor test device according to claim 4, wherein the conductive thin film layer is formed on the side of each of the opening patterns. Claim 6 A method for manufacturing a semiconductor test device according to claim 4, wherein the conductive thin film layer is further formed horizontally at the upper side of the opening pattern or further formed horizontally at the lower side of the opening pattern. Claim 7 A method for manufacturing a semiconductor test device, further comprising, in claim 1 or 2, a step of reducing the thickness of the holder portion prior to step (a), between step (a) and step (b), or between step (b) and step (c). Claim 8 A method for manufacturing a semiconductor test device according to claim 7, wherein the thickness of the holder portion is reduced to 100㎛ to 300㎛. Claim 9 A method for manufacturing a semiconductor test device according to claim 1, wherein step (c) comprises: (c1) a step in which the membrane portion includes a second surface connected to the holder portion and a first surface opposite to the second surface, and a step of forming a first etch prevention pattern on at least the opening pattern on the first surface; (c2) a step of etching a portion other than the conductive thin film layer covered by the first etch prevention pattern on the first surface; (c3) a step of forming a second etch prevention pattern on the second surface; and (c4) a step of etching a portion other than the conductive thin film layer covered by the second etch prevention pattern on the second surface. Claim 10 A method for manufacturing a semiconductor test device according to claim 9, wherein, in step (c1) or step (c2), a template is placed on the lower part of the holder portion to support the holder portion. Claim 11 A method for manufacturing a semiconductor test device according to claim 9, wherein in step (c3), a second template is attached to a first surface of the membrane portion via a temporary adhesive portion, and the second template supports the membrane portion. Claim 12 A method for manufacturing a semiconductor test device according to claim 1 or 2, wherein the connector of step (a) further comprises a plurality of grid portions extending along a first horizontal direction or a second horizontal direction perpendicular to the first horizontal direction in a hollow region of the holder portion, wherein the grid portions partition a plurality of cell regions, and after the step of removing a portion of the conductive thin film layer to mutually insulate at least adjacent opening patterns, the grid portions are cut to provide the semiconductor test device of the cell region unit size. Claim 13 A method for manufacturing a semiconductor test device according to claim 1 or 2, wherein the metal thin film portion is made of at least one of invar, super invar, nickel-iron alloy, nickel-cobalt alloy, nickel-iron-cobalt alloy, and nickel. Claim 14 A method for manufacturing a semiconductor test device according to claim 1 or 2, wherein the conductive thin film layer comprises at least one material selected from Cu, Ag, Au, Pt, Pd, and Sn. Claim 15 A method for manufacturing a semiconductor test device according to claim 1 or 2, wherein the hollow region of the holder portion is provided as a space for accommodating the semiconductor memory, and each of the opening patterns corresponds to a plurality of micro bumps formed on the lower portion of the semiconductor memory. Claim 16 A method for manufacturing a semiconductor test device according to claim 15, wherein the area of ​​the semiconductor memory corresponds to the size of a single cell or multiple cells, or corresponds to the size of a silicon wafer, and the horizontal area of ​​the hollow region of the holder part is provided as an area larger than the semiconductor memory. Claim 17 A method for manufacturing a semiconductor test device according to claim 1 or 2, wherein the width of the opening pattern is 5㎛ to 100㎛. Claim 18 A method for manufacturing a semiconductor test device according to claim 1 or 2, wherein the holder portion is formed from a silicon wafer, the metal thin film portion is formed by electroforming on the silicon wafer, the metal thin film portion comprises Invar or Super Invar material, and a connecting portion comprising Ni and Si, or a connecting portion comprising Fe, Ni and Si, is interposed between the support portion and the metal thin film portion. Claim 19 A method for manufacturing a semiconductor test device according to claim 1 or 2, wherein the metal thin film portion comprises: a first metal thin film portion having a first width of the opening pattern; and a second metal thin film portion having a second width of the opening pattern that is narrower than the first width. Claim 20 A method for manufacturing a semiconductor test device according to claim 19, wherein a portion of the second metal thin film portion that protrudes further in the lateral direction than the first metal thin film portion is provided as a cantilever portion. Claim 21 A method for manufacturing a semiconductor test device according to claim 2, wherein in step (d), when the sacrificial layer is lifted off and removed, the conductive thin film layer formed on the sacrificial layer is lifted off and removed together.

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