Input sensing panel and display apparatus and method for manufacturing the same

Abstract

A display device comprising an input sensing panel including a pixel, a first sensing insulating layer disposed on the display panel, a first conductive layer disposed on the first sensing insulating layer, a second sensing insulating layer covering the first conductive layer, a second conductive layer disposed on the second sensing insulating layer and including a plurality of mesh lines, a passivation layer disposed on the second conductive layer, and a third sensing insulating layer covering the passivation layer, wherein the passivation layer has the same shape as the second conductive layer in a planar manner.

Description

Technology Field

[0001] The present invention relates to a display device including an input sensing panel with improved sensing sensitivity and a method for manufacturing the same. Background Technology

[0002] The display device may include a display panel for displaying images and an input detection panel for detecting external inputs. The input detection panel may be formed integrally with the display panel through a continuous process. Alternatively, the input detection panel may be formed through a separate process from the display panel and then coupled to the display panel. The problem to be solved

[0003] One objective of the present invention is to provide a display device including an input sensing panel with improved rigidity and sensing sensitivity, and a method for manufacturing a display device including an input sensing panel with improved sensing sensitivity. means of solving the problem

[0004] A display device according to the present invention comprises: a display panel including a base layer, a circuit element layer including a transistor disposed on the base layer, a display element layer including a light-emitting element connected to the transistor, and a thin film encapsulation layer covering the display element layer; an input sensing panel including a first sensing insulating layer disposed directly on the thin film encapsulation layer, a first conductive layer disposed on the first sensing insulating layer, a second sensing insulating layer covering the first conductive layer, a second conductive layer disposed on the second sensing insulating layer, a passivation layer disposed on the second conductive layer, and a third sensing insulating layer covering the passivation layer, wherein the dielectric constant of the passivation layer is higher than the dielectric constant of the third sensing insulating layer.

[0005] The above passivation layer may be characterized by comprising any one of silicon nitride, silicon oxide, and silicon oxynitride, and the third sensing insulating layer may be characterized by comprising an organic material.

[0006] The above passivation layer may be characterized by being in contact with the second conductive layer and having a shape corresponding to the second conductive layer on a planar surface.

[0007] The thickness of the passivation layer may be characterized as being smaller than the thickness of the third sensing insulation layer.

[0008] The side of the passivation layer and the side of the second conductive layer may be characterized by being aligned with each other and inclined at a predetermined angle from the second sensing insulating layer.

[0009] The thickness of the second sensing insulating layer overlapping with the above passivation may be characterized as being greater than the thickness in other areas.

[0010] A portion of the upper surface of the second conductive layer in contact with the passivation layer may be characterized by being exposed by the passivation layer and in contact with the third sensing insulating layer.

[0011] The upper surface of the second conductive layer and the side surface connected to the upper surface may be characterized by being covered by the passivation layer.

[0012] The above-mentioned third sensing insulating layer may further include a high-refractive index layer covering the third sensing insulating layer and having a higher refractive index than the third sensing insulating layer, and the side of the passivation layer may be exposed from the third sensing insulating layer.

[0013] The input sensing panel may include a first sensing electrode comprising first sensing patterns arranged in a first direction and a conductive pattern disposed between the first sensing patterns, a second sensing electrode insulated from the first sensing electrode and extending in a second direction intersecting the first direction, and sensing wiring connected to the first sensing electrode and the second sensing electrode, wherein the first conductive layer is composed of a portion of the conductive patterns and the sensing wiring, and the second conductive layer is composed of the remaining portion of the first sensing patterns, the second sensing electrode, and the sensing wiring.

[0014] The second conductive layer may be characterized by including a plurality of mesh lines extending in directions intersecting each other, and the passivation layer on the plane may have a shape corresponding to the mesh lines.

[0015] The above passivation layer may be characterized by not overlapping with the sensing wiring.

[0016] The first sensing patterns may be characterized by being connected to the conductive pattern through a sensing contact hole defined in the second sensing insulating layer.

[0017] The above input detection panel may be characterized by detecting external input by a capacitive method.

[0018] An input sensing panel according to the present invention comprises a first sensing insulating layer, a first conductive layer disposed on the first sensing insulating layer, a second sensing insulating layer covering the first conductive layer, a second conductive layer disposed on the second sensing insulating layer, a passivation layer disposed on the second conductive layer, and a third sensing insulating layer covering the passivation layer, wherein the side surface of the passivation layer and the side surface of the second conductive layer are aligned with each other and inclined at a predetermined angle from the second sensing insulating layer.

[0019] The above passivation layer may be characterized by comprising any one of silicon nitride, silicon oxide, and silicon oxynitride, and the third sensing insulating layer may be characterized by comprising an organic material.

[0020] The dielectric constant of the passivation layer may be characterized as being higher than the dielectric constant of the third sensing insulation layer.

[0021] A method for manufacturing a display device according to the present invention comprises the steps of: forming a first sensing insulating layer and a first conductive layer on a display panel including an active area and a peripheral area; forming a second sensing insulating layer covering the first conductive layer and a second conductive layer including a conductive material on the second sensing insulating layer; forming a passivation layer on the second conductive layer; simultaneously etching the second conductive layer and the passivation layer through a photoresist process; and forming a third sensing insulating layer covering the passivation layer, wherein the passivation layer includes an inorganic material.

[0022] The second sensing insulating layer may be characterized in that, when the second conductive layer and the passivation layer are simultaneously etched, at least a portion of the second sensing insulating layer is removed to form a side of the second sensing insulating layer aligned with the side of the second conductive layer.

[0023] After the step of forming the second sensing insulating layer and before the step of forming the second conductive layer, the method may further include the step of forming a contact hole penetrating the first sensing insulating layer and the second insulating layer in the surrounding area.

[0024] After the step of simultaneously etching the second conductive layer and the passivation layer, the method may further include the step of removing the passivation layer in an area overlapping with the contact hole to expose the second conductive layer. Effects of the invention

[0025] According to the present invention, by placing a passivation layer with a dielectric constant higher than that of the sensing insulating layer between the conductive layer and the sensing insulating layer, the amount of change in capacitance between the sensing electrodes and the external input can be increased. Accordingly, a display device with improved sensing sensitivity can be provided. Brief explanation of the drawing

[0026] FIG. 1 is a perspective view of a display device according to one embodiment of the present invention. FIG. 2 is an exploded perspective view of a display device according to one embodiment of the present invention. FIG. 3a is a cross-sectional view of a display module according to one embodiment of the present invention. FIG. 3b is a cross-sectional view of a display module according to one embodiment of the present invention. FIG. 3c is a cross-sectional view of a display module according to one embodiment of the present invention. FIG. 4 is a plan view of a display panel according to one embodiment of the present invention. FIG. 5a is an equivalent circuit diagram of a pixel according to one embodiment of the present invention. FIG. 5b is a cross-sectional view of a display panel according to one embodiment of the present invention. FIG. 6 is a cross-sectional view of a display module according to one embodiment of the present invention. FIG. 7 is a plan view of an input detection panel according to one embodiment of the present invention. FIG. 8 is a plan view showing an enlarged view of the TT' area illustrated in FIG. 7. FIG. 9 is a plan view of a passivation layer according to one embodiment of the present invention. FIG. 10 is a plan view of an input detection panel according to one embodiment of the present invention. FIG. 11 is a plan view showing an enlarged view of the QQ' area illustrated in FIG. 10. FIG. 12 is a plan view of a passivation layer according to one embodiment of the present invention. FIG. 13 is a cross-sectional view of an input detection panel according to one embodiment of the present invention. FIG. 14 is a cross-sectional view of an input detection panel according to one embodiment of the present invention. FIG. 15 is a cross-sectional view of an input detection panel according to one embodiment of the present invention. FIG. 16 is a cross-sectional view of an input detection panel according to one embodiment of the present invention. FIGS. 17a to 17e are cross-sectional views of a method for manufacturing an input sensing panel according to an embodiment of the present invention. FIGS. 18a to 18e are cross-sectional views of a method for manufacturing an input sensing panel according to an embodiment of the present invention. Specific details for implementing the invention

[0027] In this specification, where a component (or region, layer, part, etc.) is described as being "on," "connected," or "combined" with another component, it means that it may be directly placed / connected / combined with the other component, or that a third component may be placed between them.

[0028] Identical reference numerals denote identical components. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the effective illustration of the technical content. "And / or" includes all one or more combinations that the associated components may define.

[0029] Terms such as "first," "second," etc., may be used to describe various components, but said components should not be limited by said terms. These terms are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be named the second component, and similarly, the second component may be named the first component. A singular expression includes a plural expression unless the context clearly indicates otherwise.

[0030] Additionally, terms such as "below," "lower side," "above," and "upper side" are used to describe the relationships between the components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0031] Terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which the present invention pertains. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly ideal or overly formal sense unless explicitly defined herein.

[0033] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0034] FIG. 1 is a perspective view of a display device according to an embodiment of the present invention. FIG. 2 is an exploded perspective view of a display device according to an embodiment of the present invention. FIG. 3a is a cross-sectional view of a display module according to an embodiment of the present invention. FIG. 3b is a cross-sectional view of a display module according to an embodiment of the present invention. FIG. 3c is a cross-sectional view of a display module according to an embodiment of the present invention.

[0035] Referring to FIGS. 1 and 2, the display device (EA) may be a device that is activated by an electrical signal. The display device (EA) may include various embodiments. For example, the display device (EA) may be used in large display devices such as televisions, monitors, or external billboards, as well as small and medium-sized display devices such as personal computers, notebook computers, personal digital terminals, car navigation units, game consoles, portable electronic devices, and cameras.

[0036] Furthermore, these are described merely as examples and, of course, may be adopted in other display devices without departing from the concept of the present invention. In this embodiment, the display device (EA) is illustrated as a smartphone.

[0037] A display device (EA) can display an image (IM) toward a third direction (DR3) on a display surface (FS) parallel to each of the first direction (DR1) and the second direction (DR2). The image (IM) may include a still image as well as a dynamic image. In FIG. 1, a clock window and icons are shown as examples of the image (IM). The display surface (FS) on which the image (IM) is displayed may correspond to the front surface of the display device (EA) and may correspond to the front surface of the window panel (WP).

[0038] In this embodiment, the front (or top) and back (or bottom) surfaces of each member are defined based on the direction in which the image (IM) is displayed. The front and back surfaces face each other in the third direction (DR3), and the normal direction of each of the front and back surfaces may be parallel to the third direction (DR3). Meanwhile, the directions indicated by the first to third directions (DR1, DR2, DR3) are relative concepts and may be converted to other directions. In this specification, "on a plane" may mean when viewed from the third direction (DR3).

[0039] The display device (EA) may include a window panel (WP), a display module (DM), and a housing (HU). In this embodiment, the window panel (WP) and the housing (HU) may be combined with each other to form the exterior of the display device (EA).

[0040] The window panel (WP) may include an optically transparent insulating material. For example, the window panel (WP) may include glass or plastic. The window panel (WP) may have a multilayer structure or a single layer structure. For example, the window panel (WP) may include a plurality of plastic films bonded by an adhesive, or a glass substrate and a plastic film bonded by an adhesive.

[0041] As described above, the front surface of the window panel (WP) can define the display surface (FS) of the display device (EA). The transmission area (TA) may be an optically transparent area. For example, the transmission area (TA) may be an area with a visible light transmittance of about 90% or more.

[0042] The bezel region (BZA) may be a region with a relatively low light transmittance compared to the transmission region (TA). The bezel region (BZA) may define the shape of the transmission region (TA). The bezel region (BZA) is adjacent to the transmission region (TA) and may surround the transmission region (TA).

[0043] The bezel area (BZA) may have a predetermined color. The bezel area (BZA) may cover the surrounding area (NAA) of the display module (DM) to block the surrounding area (NAA) from being visible from the outside. Meanwhile, this is illustrated as an example, and in a window panel (WP) according to one embodiment of the present invention, the bezel area (BZA) may be omitted.

[0044] The display module (DM) can display an image (IM) and detect external input. The display module (DM) may include a front (IS) that includes an active area (AA) and a peripheral area (NAA). The active area (AA) may be an area that is activated according to an electrical signal.

[0045] In this embodiment, the active area (AA) is an area where an image (IM) is displayed and may simultaneously be an area where an external input is detected. The transparent area (TA) may overlap with at least a portion of the active area (AA). For example, the transparent area (TA) may overlap with the front surface or at least a portion of the active area (AA).

[0046] Accordingly, the user can view the image (IM) through the transmission area (TA) or provide an external input. However, this is illustrated as an example, and the display module (DM) according to one embodiment of the present invention may have the area where the image (IM) is displayed and the area where an external input is detected separated from each other within the active area (AA), and is not limited to any one embodiment.

[0047] The peripheral area (NAA) may be an area covered by the bezel area (BZA). The peripheral area (NAA) may be adjacent to the active area (AA). The peripheral area (NAA) may surround the active area (AA). Driving circuits or driving wiring for driving the active area (AA) may be placed in the peripheral area (NAA).

[0048] In this embodiment, the display module (DM) may include a display panel (DP), an input sensing panel (ISP), and a driving circuit (DC).

[0049] The display panel (DP) may be a configuration that substantially generates an image (IM). The image (IM) generated by the display panel (DP) can be visible to a user from the outside through a transparent area (TA).

[0050] The input sensing panel (ISP) can sense external inputs applied from the outside. As described above, the input sensing panel (ISP) can sense external inputs provided to the window panel (WP).

[0051] External input may include various forms of input provided from outside the display device (EA). External input may be provided in various forms. For example, external input may include contact by a part of the body, such as a user's hand, as well as external input applied at close proximity to the display device (EA) or at a predetermined distance (e.g., hovering). Additionally, it may take various forms such as force, pressure, light, etc., and is not limited to any one embodiment.

[0052] The driving circuit (DC) can be electrically connected to the display panel (DP) and the input sensing panel (ISP). The driving circuit (DC) may include a main circuit board (MB) and a flexible circuit board (CF).

[0053] A flexible circuit board (CF) can be electrically connected to a display panel (DP). The flexible circuit board (CF) can connect the display panel (DP) and the main circuit board (MB). However, this is illustrated as an example, and the flexible circuit board (CF) according to the present invention may not be connected to the main circuit board (MB), and the flexible circuit board (CF) may be a rigid board.

[0054] A flexible circuit board (CF) can be connected to pads (display pads) of a display panel (DP) placed in a peripheral area (NAA). The flexible circuit board (CF) can provide an electrical signal to the display panel (DP) to drive the display panel (DP). The electrical signal may be generated on the flexible circuit board (CF) or on the main circuit board (MB).

[0055] The main circuit board (MB) may include various driving circuits for driving the display module (DM) or connectors for power supply. The main circuit board (MB) may be connected to the display module (DM) through a flexible circuit board (CF).

[0056] A display module (DM) according to one embodiment of the present invention can be easily controlled through a single main circuit board (MB). However, this is exemplary, and in the display module (DM) according to one embodiment of the present invention, the display panel (DP) and the input detection panel (ISP) may be connected to different main circuit boards and are not limited to any one embodiment.

[0057] The housing (HU) can be combined with the window panel (WP). The housing (HU) can be combined with the window panel (WP) to provide a predetermined internal space. The display module (DM) can be accommodated in the internal space.

[0058] The housing (HU) may include a material with relatively high rigidity. For example, the housing (HU) may include glass, plastic, or metal, or may include multiple frames and / or plates composed of a combination thereof. The housing (HU) can reliably protect the components of the display device (EA) housed in the internal space from external impact.

[0059] Referring to FIG. 3a, in this embodiment, the display module (DM) may include a display panel (DP) and an input sensing panel (ISP).

[0060] The display panel (DP) may include a base layer (BS), a circuit element layer (ML-D), a display element layer (EML), and a thin film encapsulation layer (ECL).

[0061] The base layer (BS) may be a base layer on which a circuit element layer (ML-D), a display element layer (EML), a thin film encapsulation layer (ECL), and an input sensing panel (ISP) can be stacked. The base layer (BS) may be flexible or rigid, may be provided as a single layer or may have a multilayer structure, and is not limited to either one.

[0062] The circuit element layer (ML-D) may be disposed on the base layer (BS). The circuit element layer (ML-D) may include a plurality of insulating layers, a plurality of conductive layers, and a semiconductor layer. The plurality of conductive layers of the circuit element layer (ML-D) may form a control circuit for signal lines or pixels (PX, see FIG. 4).

[0063] A display element layer (EML) may be disposed on a circuit element layer (ML-D). The display element layer (EML) may include organic light-emitting diodes. However, this is exemplary, and the display element layer (EML) according to one embodiment of the present invention may include inorganic light-emitting diodes, organic-inorganic light-emitting diodes, or a liquid crystal layer.

[0064] The thin film encapsulation layer (ECL) may include an organic layer and a plurality of inorganic layers that seal the organic layer. The thin film encapsulation layer (ECL) can seal the display element layer (EML) to block moisture and oxygen from entering the display element layer (EML).

[0065] An input sensing panel (ISP) is placed on a thin film encapsulation layer (ECL). The input sensing panel (ISP) can be formed on the thin film encapsulation layer (ECL) through a continuous process. In this case, the input sensing panel (ISP) can be described as being 'directly placed' on the display panel (DP). Being directly placed may mean that no third component is placed between the input sensing panel (ISP) and the display panel (DP). That is, a separate adhesive member may not be placed between the input sensing panel (ISP) and the display panel (DP).

[0066] The input sensing panel (ISP) can detect external input by either a self-capacitance type or a mutual capacitance type. The sensing patterns included in the input sensing panel (ISP) can be arranged and connected in various modified forms to suit the method.

[0067] In this embodiment, the input sensing panel (ISP) can sense external input by a mutual capacitance type, and in order to improve the sensing sensitivity, a layer having a high dielectric constant may be additionally disposed in the conductive layer. A detailed description will be provided later.

[0068] Referring to FIG. 3b, in this embodiment, the display module (DM-1) may include a display panel (DP), an input sensing panel (ISP), and an optical member (POL).

[0069] An optical element (POL) may be placed on an input sensing panel (ISP) to reduce the external light reflectivity of the display panel (DP) with respect to light incident on the display panel (DP). For example, the optical element (POL) may include at least one of an anti-reflective film, a polarizing film, and a gray filter.

[0070] Referring to FIG. 3c, in this embodiment, the display module (DM-2) may include a display panel (DP), an input detection panel (ISP), and an optical filter member (OM).

[0071] The light filter member (OM) can selectively transmit light provided from the display panel (DP). The light filter member (OM) may include a plurality of color filters and a light-blocking pattern disposed between the color filters.

[0072] Color filters can selectively transmit corresponding light among red, green, and blue light. In this case, each of the color filters may comprise a polymer photosensitive resin and a pigment or dye.

[0073] Additionally, the optical filter member (OM) may further include a flattening layer disposed on the color filters.

[0074] The flattening layer can be placed on the color filters to cover irregularities generated during the formation process of the color filters. Accordingly, the configuration placed on the optical filter member (OM) can be stably combined with the optical filter member (OM).

[0076] FIG. 4 is a plan view of a display panel according to an embodiment of the present invention. FIG. 5a is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. FIG. 5b is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0077] Referring to FIG. 4, the display panel (DP) can be divided into an active area (AA) and a peripheral area (NAA). The active area (AA) of the display panel (DP) is an area where an image is displayed, and the peripheral area (NAA) may be an area where a driving circuit or driving wiring is arranged. In the active area (AA), light-emitting elements of each of a plurality of pixels (PX) may be arranged. The active area (AA) may overlap with at least a part of the transmission area (TA), and the peripheral area (NAA) may be covered by a bezel area (BZA).

[0078] The display panel (DP) may include a driving circuit (GDC), a plurality of signal lines (SGL, hereinafter signal lines), a plurality of pixels (PX, hereinafter pixels), a plurality of lower contact holes (CTN1, CTN2, CTN3), a plurality of contact lines (CTL1, CTL2, CTL3), and a plurality of pads (PD) connected to the corresponding contact lines.

[0079] Each pixel (PX) may include a light-emitting element and a plurality of transistors connected thereto. The pixels (PX) may emit light in response to an applied electrical signal.

[0080] The signal lines (SGL) may include scan lines (GL), data lines (DL), power lines (PL), and control signal lines (CSL). The scan lines (GL) may each be connected to a corresponding pixel (PX) among the pixels (PX). The data lines (DL) may each be connected to a corresponding pixel (PX) among the pixels (PX). The power line (PL) may be connected to the pixels (PX) to provide power voltage. The control signal line (CSL) may provide control signals to the scanning driving circuit.

[0081] The driving circuit (GDC) may be placed in the peripheral area (NAA). The driving circuit (GDC) may include a scanning driving circuit. The scanning driving circuit may generate scan signals and sequentially output the scan signals to the scan lines (GL). The scanning driving circuit may further output another control signal to the driving circuit of the pixels (PX).

[0082] The scanning driving circuit may include a plurality of thin-film transistors formed through the same process as the driving circuit of the pixels (PX), such as the LTPS (Low Temperature Polycrystalline Silicon) process or the LTPO (Low Temperature Polycrystalline Oxide) process.

[0083] A display panel (DP) according to the present invention may include a bending area (BA) and a non-bending area (NBA) adjacent to the bending area (BA). The bending area (BA) of the display panel (DP) may be an area to which the flexible circuit board (CF) described in FIG. 2 is attached and which is bent toward the back surface of the display panel (DP). Accordingly, the flexible circuit board (CF) and the main circuit board (MB) may be placed on the back surface of the display panel (DP) while attached to the bending area (BA) of the display panel (DP). Data lines (DL) and signal lines (SGL) may extend from the non-bending area (NBA) to the bending area (BA) and be connected to the corresponding pad (PD).

[0084] In one embodiment, the width in the second direction (DR2) of the display panel (DP) may be greater in the non-bending area (NBA) than in the bending area (BA).

[0085] The display panel (DP) may include contact holes (CTN1, CTN2, CTN3) defined in the surrounding area (NAA). The lower contact holes (CTN1, CTN2, CTN3) may overlap with the upper contact holes (CTN-1, CTN-2, CTN-3) of the input sensing panel (ISP) described later.

[0086] The contact lines (CTL1, CTL2, CTL3) can be extended from the lower contact holes (CTN1, CTN2, CTN3) to the bending area (BA) and connected to the corresponding pads (PD).

[0087] Each of the first contact lines (CTL1) extends from a corresponding first lower contact hole (CTN1) at one end, and each of the first contact lines (CTL1) can be connected to a corresponding pad (PD) at the other end.

[0088] Each of the second contact lines (CTL2) extends from a corresponding second lower contact hole (CTN2) at one end, and each of the second contact lines (CTL2) can be connected to a corresponding pad (PD) at the other end.

[0089] Each of the third contact lines (CTL3) extends from a corresponding third lower contact hole (CTN3) at one end, and each of the third contact lines (CTL3) can be connected to a corresponding pad (PD) at the other end.

[0090] Figure 4 illustrates three lower contact holes (CTN1, CTN2, CTN3), but this is an exemplary illustration of the arrangement relationship of the lower contact holes, and the arrangement relationship and number of lower contact holes are not limited to any one, as long as they overlap with the upper contact holes of the input sensing panel (ISP).

[0091] Referring to FIG. 5a, the signal circuit diagram of one pixel (PX) among a plurality of pixels is illustrated in an enlarged manner. FIG. 5a illustrates, in an exemplary manner, a pixel (PX) connected to the i-th scan line (GLi) and the i-th light emission control line (EPi).

[0092] A pixel (PX) may include a light-emitting element (OLED) and a pixel circuit (CC). The pixel circuit (CC) may include a plurality of transistors (T1-T7) and a capacitor (CP). The plurality of transistors (T1-T7) may be formed through a Low Temperature Polycrystalline Silicon (LTPS) process or a Low Temperature Polycrystalline Oxide (LTPO) process.

[0093] The pixel circuit (CC) controls the amount of current flowing to the light-emitting element (OLED) in response to a data signal. The light-emitting element (OLED) can emit light with a predetermined brightness in response to the amount of current provided by the pixel circuit (CC). To this end, the level of the first power supply (ELVDD) may be set higher than the level of the second power supply (ELVSS). The light-emitting element (OLED) may include an organic light-emitting element or a quantum dot light-emitting element.

[0094] Each of the plurality of transistors (T1-T7) may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience within this specification, either the input electrode or the output electrode may be referred to as the first electrode, and the other as the second electrode.

[0095] The first electrode of the first transistor (T1) is connected to the first power source (ELVDD) via the fifth transistor (T5), and the second electrode of the first transistor (T1) is connected to the anode electrode (first electrode) of the light-emitting element (OLED) via the sixth transistor (T6). The first transistor (T1) may be referred to as a driving transistor within this specification.

[0096] The first transistor (T1) controls the amount of current flowing through the light-emitting element (OLED) in response to the voltage applied to the control electrode of the first transistor (T1).

[0097] The second transistor (T2) is connected between the data line (DL) and the first electrode of the first transistor (T1). The control electrode of the second transistor (T2) is connected to the i-th scan line (GLi). The second transistor (T2) is turned on when the i-th scan signal is provided to the i-th scan line (GLi), thereby electrically connecting the data line (DL) and the first electrode of the first transistor (T1).

[0098] The third transistor (T3) is connected between the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). The control electrode of the third transistor (T3) is connected to the i-th scan line (GLi). The third transistor (T3) is turned on when the i-th scan signal is provided to the i-th scan line (GLi), thereby electrically connecting the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). Thus, when the third transistor (T3) is turned on, the first transistor (T1) is connected in the form of a diode.

[0099] The fourth transistor (T4) is connected between the node (ND) and the initialization power generation unit (not shown). The control electrode of the fourth transistor (T4) is connected to the i-1th scan line (GLi-1). The fourth transistor (T4) is turned on when the i-1th scan signal is provided to the i-1th scan line (GLi-1) and provides an initialization voltage (Vint) to the node (ND).

[0100] The fifth transistor (T5) is connected between the power line (PL) and the first electrode of the first transistor (T1). The control electrode of the fifth transistor (T5) is connected to the i-th light emission control line (EPi).

[0101] The sixth transistor (T6) is connected between the second electrode of the first transistor (T1) and the anode electrode (first electrode) of the light-emitting element (OLED). Also, the control electrode of the sixth transistor (T6) is connected to the i-th light-emitting control line (EPi).

[0102] The seventh transistor (T7) is connected between an initialization power generation unit (not shown) and the anode electrode of a light-emitting element (OLED). The control electrode of the seventh transistor (T7) is connected to the i+1th scan line (GLi+1). The seventh transistor (T7) is turned on when the i+1th scan signal is provided to the i+1th scan line (GLi+1), thereby providing an initialization voltage (Vint) to the anode electrode of the light-emitting element (OLED).

[0103] The seventh transistor (T7) can improve the black expression capability of the pixel (PX). Specifically, when the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (OLED) is discharged. Then, when black luminance is implemented, the light-emitting element (OLED) does not emit light due to leakage current from the first transistor (T1), and accordingly, the black expression capability can be improved.

[0104] Additionally, in FIG. 5a, the control electrode of the seventh transistor (T7) is shown connected to the i+1th scan line (GLi+1), but the present invention is not limited thereto. In another embodiment of the present invention, the control electrode of the seventh transistor (T7) may be connected to the ith scan line (GLi) or the i-1th scan line (GLi-1).

[0105] A capacitor (CP) is placed between the power line (PL) and the node (ND). The capacitor (CP) stores a voltage corresponding to the data signal. Depending on the voltage stored in the capacitor (CP), the amount of current flowing through the first transistor (T1) when the fifth transistor (T5) and the sixth transistor (T6) are turned on can be determined.

[0106] In the present invention, the equivalent circuit of the pixel (PX) is not limited to the equivalent circuit shown in FIG. 5a. In other embodiments of the present invention, the pixel (PX) can be implemented in various forms to emit light from a light-emitting element (OLED). FIG. 5a is illustrated based on a PMOS, but is not limited thereto. In another embodiment of the present invention, the pixel circuit (CC) may be composed of an NMOS. In yet another embodiment of the present invention, the pixel circuit (CC) may be composed of a combination of an NMOS and a PMOS.

[0107] Referring to FIG. 5b, the display panel (DP) may include a base layer (BS), a plurality of insulating layers (BFL to INS5, PDL), and a thin film encapsulation layer (ECL).

[0108] The base layer (BS) may include a flexible plastic substrate. For example, the base layer (BS) may include transparent polyimide (PI). A buffer layer (BFL) is disposed on the base layer (BS), and the buffer layer (BFL) may be an inorganic layer. A semiconductor pattern may be disposed on the buffer layer (BFL). The semiconductor pattern may include polysilicon. However, it is not limited thereto, and the semiconductor pattern may include amorphous silicon or a metal oxide.

[0109] The semiconductor pattern can be doped with an N-type or P-type dopant. The electrical properties of the semiconductor pattern may vary depending on whether or not it is doped. The semiconductor pattern may include high-doping and low-doping regions. The conductivity of the high-doping region is greater than that of the low-doping region and can substantially serve as the source and drain electrodes of the transistor (TR). The low-doping region can substantially correspond to the active (or channel) of the transistor.

[0110] The source (S), active (A), and drain (D) of the transistor (TR) can be formed from a semiconductor pattern. A first insulating layer (INS1) can be disposed on the semiconductor pattern. The gate (G) of the transistor (TR) can be disposed on the first insulating layer (INS1). A second insulating layer (INS2) can be disposed on the gate (G). A third insulating layer (INS3) can be disposed on the second insulating layer (INS2). The transistor (TR) of FIG. 5b may correspond to the sixth transistor (T6) among the transistors (T1-T6) described in FIG. 5a.

[0111] A connecting electrode (CNE) is positioned between a transistor (TR) and a light-emitting element (OLED) to connect the transistor (TR) and the light-emitting element (OLED). The connecting electrode (CNE) is positioned on a third insulating layer (INS3) and can be connected to a drain (D) through a first contact hole (CH1) defined in the first to third insulating layers (INS1~INS3). However, this is not limited thereto. If additional insulating layers are positioned above or below the connecting electrode (CNE), additional connecting electrodes connected to the connecting electrode (CNE) may be positioned by penetrating the additional insulating layers, or the connecting electrode (CNE) may be omitted and the first electrode (AE) of the light-emitting element (OLED) may be directly connected to the drain (D). This is not limited to any single embodiment.

[0112] The fourth insulating layer (INS4) may be disposed on the connecting electrode (CNE). The fifth insulating layer (INS5) may be disposed on the fourth insulating layer (INS4). The first insulating layer (INS1) to the fourth insulating layer (INS4) may be inorganic layers, and the fifth insulating layer (INS5) may be an organic layer.

[0113] A first electrode (AE) may be disposed on the fifth insulating layer (INS5). The first electrode (AE) may be connected to a connecting electrode (CNE) through a second contact hole (CH2) defined in the fifth insulating layer (INS5). A pixel defining film (PDL) that exposes a predetermined portion of the first electrode (AE) may be disposed on the first electrode (AE) and the fifth insulating layer (INS5). An opening (PX_OP) for exposing a predetermined portion of the first electrode (AE) may be defined in the pixel defining film (PDL). The portion of the first electrode (AE) exposed by the opening (PX_OP) may be defined as a light-emitting region (PXA), and a non-light-emitting region (NPA) may be adjacent to the light-emitting region (PXA).

[0114] The hole control layer (HC) may be disposed on the first electrode (AE) and the pixel definition film (PDL). The hole control layer (HC) may be disposed in common in the light-emitting region (PXA) and the non-light-emitting region (NPA). The hole control layer (HC) may include a hole transport layer and a hole injection layer.

[0115] The emitting layer (EL) may be disposed on the hole control layer (HC). The emitting layer (EL) may be disposed in the region corresponding to the aperture (PX_OP). The emitting layer (EL) may include organic and / or inorganic materials. The emitting layer (EL) may generate any one of red, green, and blue light.

[0116] The electronic control layer (EC) may be disposed on the emitting layer (EL) and the hole control layer (HC). The electronic control layer (EC) may be disposed in common in the emitting region (PXA) and the non-emitting region (NPA). The electronic control layer (EC) may include an electron transport layer and an electron injection layer.

[0117] The second electrode (CE) may be placed on the electronic control layer (EC). The second electrode (CE) may be placed in common on the pixels (PX). The layer from the buffer layer (BFL) to the light-emitting element (OLED) may be defined as the pixel layer (PXL).

[0118] A thin film encapsulation layer (ECL) can be disposed on a light-emitting element (OLED) to cover the light-emitting element (OLED). The thin film encapsulation layer (ECL) may include a first inorganic encapsulation layer (E1) disposed on a pixel (PX), a second inorganic encapsulation layer (E3) disposed on the first inorganic encapsulation layer (E1), and an organic encapsulation layer (E2) disposed between the first and second inorganic encapsulation layers (E1, E3).

[0119] The first and second inorganic encapsulation layers (E1, E3) contain inorganic materials and can protect pixels from moisture / oxygen. The organic encapsulation layer (E2) contains organic materials and can protect pixels (PX) from foreign substances such as dust particles. The organic encapsulation layer (E2) can be formed through a solution process such as spin coating, slit coating, or an inkjet process.

[0120] The lower contact holes (CTN1, CTN2, CTN3) described in FIG. 4 are formed by penetrating at least one of the insulating layers included in the circuit element layer (ML-D), the display element layer (EML), and the thin film encapsulation layer (ECL), and the contact lines (CTL1, CTL2, CTL3) may be placed on the same layer as any one of the conductive patterns included in the buffer layer (BFL) to the third insulating layer (ISN3) and extend into a bending region (BA, see FIG. 4).

[0121] FIG. 6 is a cross-sectional view of a display module according to an embodiment of the present invention. FIG. 7 is a plan view of an input detection panel according to an embodiment of the present invention. FIG. 8 is a plan view showing an enlarged view of the TT' region illustrated in FIG. 7. FIG. 9 is a plan view of a passivation layer according to an embodiment of the present invention.

[0122] The display module (DM) may include a display panel (DP) and an input sensing sensor (ISP), and may be applied in the same way as described in FIG. 5b regarding the cross-section of the display panel (DP).

[0123] The input sensing panel (ISP) may include a first sensing insulating layer (TIL1), a first conductive layer (TML1), a second sensing insulating layer (TIL2), a second conductive layer (TML2), and a third sensing insulating layer (TIL3). The first sensing insulating layer (TIL1) of the input sensing panel (ISP) may be placed directly on a thin film encapsulation layer (ECL). Meanwhile, according to one embodiment of the input sensing panel (ISP), the first sensing insulating layer (TIL1) may be omitted.

[0124] Each of the first conductive layer (TML1) and the second conductive layer (TML2) may have a single-layer structure or a multi-layer structure. The conductive layer of the multi-layer structure may include at least two of a transparent conductive layer and a metal layer. The conductive layer of the multi-layer structure may include metal layers containing different metals.

[0125] The first conductive layer (TML1) and the second conductive layer (TML2) may be transparent conductive layers comprising at least one of ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), PEDOT, metal nanowires, and graphene. The first conductive layer (TML1) and the second conductive layer (TML2) may be metal layers comprising molybdenum, silver, titanium, copper, aluminum, and alloys thereof.

[0126] For example, the first conductive layer (TML1) and the second conductive layer (TML2) may each have a three-layer structure composed of titanium / aluminum / titanium. A metal with relatively high durability and low reflectivity may be applied to the outer layer of the conductive layer, and a metal with high electrical conductivity may be applied to the inner layer of the conductive layer.

[0127] Each of the first sensing insulating layer (TIL1) to the third sensing insulating layer (TIL3) may include an inorganic film or an organic film. In one embodiment, each of the first sensing insulating layer (TIL1) and the second sensing insulating layer (TIL2) may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0128] The third sensing insulating layer (TIL3) may include an organic film. The organic film may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyimide resin, a polyamide resin, and a perylene resin.

[0129] Although not illustrated in FIG. 6, the input sensing panel (ISP) according to the present invention may further include a high dielectric constant layer disposed on a second conductive layer (TML2) and covered by a third sensing insulating layer (TIL3). The high dielectric constant layer may be a layer having a dielectric constant higher than the dielectric constant of the third sensing insulating layer (TIL3). A detailed description will be provided later.

[0130] Referring to FIG. 7, in this embodiment, the input sensing panel (ISP) may include a plurality of sensing electrodes (TE1, TE2) and a plurality of sensing wires (TL1, TL2, TL3).

[0131] The input sensing panel (ISP) can be divided into an active area (AA-I) and a peripheral area (NAA-I) adjacent to the active area (AA-I). The active area (AA-I) and peripheral area (NAA-I) of the input sensing panel (ISP) can correspond to the active area (AA) and peripheral area (NAA) of the display panel (DP).

[0132] A plurality of sensing electrodes (TE1, TE2) may include a first sensing electrode (TE1) and a second sensing electrode (TE2).

[0133] A first sensing electrode (TE1) extends in a first direction (DR1) and may be provided in multiple numbers and arranged along two directions (DR2). The first sensing electrode (TE1) may include first sensing patterns (SP1) and first conductive patterns (BP1). The first sensing patterns (SP1) may be arranged along the first direction (DR1). At least one first conductive pattern (BP1) may be connected to two first sensing patterns (SP1) that are adjacent to each other.

[0134] The second sensing electrode (TE2) extends in a second direction (DR2) and may be provided in multiple numbers and arranged along the first direction (DR1). The second sensing electrode (TE2) may include second sensing patterns (SP2) and second conductive patterns (BP2). The second sensing patterns (SP2) and the second conductive patterns (BP2) are a single pattern formed by the same process, but for convenience of explanation, they are described separately as the second sensing patterns (SP2) and the second conductive patterns (BP2).

[0135] The second sensing patterns (SP2) can be arranged along the second direction (DR2). At least one second conductive pattern (BP2) can be placed between two adjacent second sensing patterns (SP2).

[0136] The sensing wires (TL1, TL2, TL3) may include a first sensing wire (TL1), a second sensing wire (TL2), and a third sensing wire (TL3).

[0137] The input sensing panel (ISP) according to the present invention may include a plurality of upper contact holes (CTN-1, CTN-2, CTN-3) defined in a peripheral area (NAA-I). The upper contact holes (CTN-1, CTN-2, CTN-3) may be formed by penetrating a first sensing insulating layer (TIL1) and a second sensing insulating layer (TIL2). The upper contact holes (CTN-1, CTN-2, CTN-3) may overlap with the corresponding lower contact holes (CTN1, CTN2, CTN3).

[0138] One end of the first sensing wire (TL1) is connected to the second sensing electrode (TE2), and the other end of the first sensing wire (TL1) can be extended to the third upper contact hole (CTN-3). The other end of the first sensing wire (TL1) can be connected to the third contact line (CTL3, see FIG. 4) through the third lower contact hole (CTN3, see FIG. 4) and the third upper contact hole (CTN-3) that overlap each other.

[0139] One end of the second sensing wire (TL2) is connected to one end of the first sensing electrode (TE1), and the other end of the second sensing wire (TL2) can be extended to the second upper contact hole (CTN-2). The other end of the second sensing wire (TL2) can be connected to the second contact line (CTL2, see FIG. 4) through the second lower contact hole (CTN2, see FIG. 4) and the second upper contact hole (CTN-2) that overlap each other.

[0140] One end of the third sensing wire (TL3) is connected to the other end of the first sensing electrode (TE1), and the other end of the third sensing wire (TL3) can be extended to the first upper contact hole (CTN-1). The other end of the third sensing wire (TL3) can be connected to the first contact line (CTL1, see FIG. 4) through the first lower contact hole (CTN1, see FIG. 4) and the first upper contact hole (CTN-1) that overlap each other.

[0141] A first sensing electrode (TE1) according to one embodiment of the present invention may be connected to a second sensing wire (TL2) and a third sensing wire (TL3). Accordingly, the sensitivity according to the region can be maintained uniformly for the first sensing electrode (TE1), which has a relatively longer length compared to the second sensing electrode (TE2).

[0142] The contact lines (CTL1, CTL2, CTL3) can be connected to the corresponding pads (PD) and connected to the pads of the flexible circuit board (CF). Thus, the sensing electrodes (TE1, TE2) can be electrically connected to the flexible circuit board (CF) and the main circuit board (MB) connected to the bending area (BA) of the display panel (DP).

[0143] However, this is not limited thereto, and the first sensing electrode (TE1) may have a sensing wiring connected to only one end or the other end, and in this case, either of the first and second upper contact holes (CTN-1, CTN-2) may be omitted.

[0144] FIG. 8 illustrates the arrangement relationship of the first sensing patterns (SP1), first conductive patterns (BP1), second sensing patterns (SP2), and second conductive patterns (BP2) in a plan view, and the sensing insulating layers (TIL1, TIL2, TIL3) and passivation layer (PVX) described later are omitted.

[0145] In this embodiment, the first sensing patterns (SP1) and the second sensing electrode (TE2) may include a mesh line (MSL). The mesh line (MSL) may include a first mesh line (MSL1) extended in a fourth direction (DR4) and a second mesh line (MSL2) extended in a fifth direction (DR5).

[0146] The mesh lines (MSL1, MSL2) overlap with the light-emitting region (PXA) described in FIG. 5b and overlap with the non-light-emitting region (NPA). The mesh lines (MSL1, MSL2) define a plurality of mesh openings (MSL-OP). The line width of the mesh lines (MSL1, MSL2) may be several micrometers to several nanometers. The plurality of mesh openings (MSL-OP) may correspond one-to-one with the light-emitting region (PXA) provided for each pixel (PX).

[0147] In this embodiment, the first sensing pattern (SP1) and the second sensing electrode (TE2) can form the second conductive layer (TML2) described in FIG. 6.

[0148] The first sensing patterns (SP1) can be connected to the corresponding first conductive pattern (BP1) through a sensing contact hole (TNT) defined in the second sensing insulating layer (TIL2). Thus, even if the first sensing patterns (SP1) are placed on the same layer as the second sensing electrode (TE2), they can be placed insulated from the second sensing electrode (TE2) through the first conductive pattern (BP1) placed on the first sensing insulating layer (TIL1). Therefore, the first conductive pattern (BP1) and the second conductive pattern (BP2) placed on different layers can overlap each other in a plane.

[0149] A portion of each of the sensing wires (TL1, TL2, TL3) may be included in the first conductive layer (TML1), and the remaining portion may be included in the second conductive layer (TML2). Wires disposed on different layers may be connected to each other through contact holes defined in the second sensing insulating layer (TIL2). However, this is not limited thereto, and the sensing wires (TL1, TL2, TL3) may be included in only one of the first conductive layer (TML1) and the second conductive layer (TML2).

[0150] Referring to FIG. 9, an input sensing panel (ISP) according to the present invention may include a passivation layer (PVX). The passivation layer (PVX) may be disposed on a second conductive layer (TML2). In this embodiment, the passivation layer (PVX) may be directly disposed on first sensing patterns (SP1) and a second sensing electrode (TE2) that overlap with an active region (AA-I) of the second conductive layer (TML2). Thus, the passivation layer (PVX) may not overlap with a peripheral region (NAA).

[0151] In this embodiment, the passivation layer (PVX) may have a shape corresponding to the patterns included in the second conductive layer (TML2) in a planar view. In this specification, "corresponding shape" does not mean an exactly identical shape, but may be expressed as a corresponding shape if a configuration disposed on one layer has an overlapping shape with a configuration disposed on another layer when viewed in a planar view. For example, a shape in which the configuration disposed on one of the overlapping layers is entirely covered or partially exposed may also be included in the corresponding shape. Additionally, the corresponding shape may include a process error range caused by a difference in the etching rate of the etchant when patterning is performed using the same mask in the patterning process.

[0152] The passivation layer (PVX) may have a shape corresponding in a plane to the first sensing patterns (SP1), the second sensing patterns (SP2), and the second conductive pattern (BP2). That is, the passivation layer (PVX) may have a shape corresponding in a plane to the first sensing patterns (SP1), the second sensing patterns (SP2), and the second conductive pattern (BP2) disposed on the second conductive layer (TML2) by the same process with the same mask.

[0153] In this embodiment, the dielectric constant of the passivation layer (PVX) may be higher than the dielectric constant of the third sensing insulating layer (TIL3) covering the passivation layer (PVX). For example, the dielectric constant of the third sensing insulating layer (TIL3) may be 2.6 to 3.5, and the dielectric constant of the passivation layer (PVX) may be 3.75 to 7.

[0154] The thickness of the passivation layer (PVX) may be smaller than the thickness of the third sensing insulating layer (TIL3) covering the passivation layer (PVX). For example, the thickness of the third sensing insulating layer (TIL3) may be 1.25 µm and the thickness of the passivation layer (PVX) may be 0.5 µm.

[0155] The passivation layer (PVX) may comprise a material different from the third sensing insulating layer (TIL3) covering the passivation layer (PVX). For example, the passivation layer (PVX) may comprise an inorganic material. The inorganic material may comprise any one of silicon nitride, silicon oxide, and silicon oxynitride. The third sensing insulating layer (TIL3) may comprise an acrylic organic material.

[0156] The passivation layer (PVX) can increase the change in Capacitance (Cap) between the sensing electrodes (TE1, TE2) when the input sensing panel (ISP) of the present invention senses an external input by a mutual capacitance type.

[0157] That is, by placing a passivation layer (PVX) with a higher dielectric constant than the third sensing insulating layer (TIL3) between the second conductive layer (TML2) and the third sensing insulating layer (TIL3), the amount of change in Cap between the sensing electrodes (TE1, TE2) and the external input can be increased. Accordingly, a display device (EA) with improved sensing sensitivity can be provided.

[0158] FIG. 10 is a plan view of an input sensing panel according to an embodiment of the present invention. FIG. 11 is a plan view showing an enlarged view of the QQ' region illustrated in FIG. 10. FIG. 12 is a plan view of a passivation layer according to an embodiment of the present invention. Identical or similar reference numerals are used for configurations identical or similar to those described in FIG. 6 to 9, and redundant descriptions are omitted.

[0159] Referring to FIGS. 10 and FIGS. 11, an input sensing panel (ISP-A) according to one embodiment may include a first sensing electrode (TE1) and a second sensing electrode (TE2).

[0160] The first sensing electrode (TE1) extends in a second direction (DR2) and is provided in multiple numbers and can be arranged along the first direction (DR1). The first sensing electrode (TE1) may include first sensing patterns (SP1) and a first conductive pattern (BP1). The first conductive pattern (BP2) may be placed between adjacent first sensing patterns (SP1) to connect the first sensing patterns (SP1).

[0161] The second sensing electrode (TE2) extends in the first direction (DR1) and is provided in multiple numbers and can be arranged along the second direction (DR2). The second sensing patterns (SP2) and the second conductive patterns (BP2) are a single pattern formed by the same process, but for convenience of explanation, they are described separately as the second sensing patterns (SP2) and the second conductive patterns (BP2).

[0162] The sensing wires (TL1, TL2, TL3) may include a first sensing wire (TL1), a second sensing wire (TL2), and a third sensing wire (TL3).

[0163] The input sensing panel (ISP-A) according to the present invention may include a plurality of upper contact holes (CTN-1, CTN-2, CTN-3) defined in a peripheral area (NAA-I). The upper contact holes (CTN-1, CTN-2, CTN-3) may be formed by penetrating the first sensing insulating layer (TIL1) and the second sensing insulating layer (TIL2) described in FIG. 6. The upper contact holes (CTN-1, CTN-2, CTN-3) may overlap with the corresponding lower contact holes (CTN1, CTN2, CTN3).

[0164] One end of the first sensing wire (TL1) is connected to the first sensing electrode (TE1), and the other end of the first sensing wire (TL1) can be extended to the third upper contact hole (CTN-3). The other end of the first sensing wire (TL1) can be connected to the third contact line (CTL3, see FIG. 4) through the third lower contact hole (CTN3, see FIG. 4) and the third upper contact hole (CTN-3) that overlap each other.

[0165] One end of the second sensing wire (TL2) is connected to one end of the second sensing electrode (TE2), and the other end of the second sensing wire (TL2) can be extended to the second upper contact hole (CTN-2). The other end of the second sensing wire (TL2) can be connected to the second contact line (CTL2, see FIG. 4) through the second lower contact hole (CTN2, see FIG. 4) and the second upper contact hole (CTN-2) that overlap each other.

[0166] One end of the third sensing wire (TL3) is connected to the other end of the second sensing electrode (TE2), and the other end of the third sensing wire (TL3) can be extended to the first upper contact hole (CTN-1). The other end of the third sensing wire (TL3) can be connected to the first contact line (CTL1, see FIG. 4) through the first lower contact hole (CTN1, see FIG. 4) and the first upper contact hole (CTN-1) which overlap each other.

[0167] Figure 11 shows an enlarged view of an area defined as a sensing unit of one of the input sensing panels (ISP-A).

[0168] A single sensing unit may include parts of each of the first sensing patterns (SP1) arranged between the first conductive pattern (BP1) and parts of each of the second sensing patterns (SP2) integrally connected between the second conductive pattern (CP2). Meanwhile, a sensing unit of one embodiment may further include a plurality of dummy patterns (DUP).

[0169] Within the sensing unit, first sensing patterns (SP1) may include a first part (SP1a) and a second part (SP1b). The first part (SP1a) may surround first and third parts (SP2c1, SP2c3), and the second part (SP1b) may surround second and fourth parts (SP2c2, SP2c4).

[0170] In the sensing unit, the first conductive pattern (BP1) may have a curved shape. For example, on a plane, the first conductive pattern (BP1) may be either a "∧" or "∨" shape.

[0171] Each of the second sensing patterns (SP2) within the sensing unit may include extension portions (SP2a, SP2b) and branch portions (SP2c1 to SP2c4). The extension portions (SP2a, SP2b) may extend along a first direction (DR1). The extension portions (SP2a, SP2b) may include a first extension portion (SP2a) extended along the first direction (DR1) and a second extension portion (SP2b) extended from the first extension portion (SP2a) to a first cross direction (DRa) and a second cross direction (DRb).

[0172] The first to fourth parts (SP2c1 to SP2c4) may extend along the first cross direction (DRa) and the second cross direction (DRb) with the second conductive pattern (BP2) in between.

[0173] Within the sensing unit, the second conductive pattern (BP2) may be positioned between the parts of the first sensing patterns (SP1) that protrude toward each other along the second direction (DR2). The second conductive pattern (BP2) may connect the first extended parts (SP2a) of the second sensing patterns (SP2).

[0174] Each of the dummy patterns (DUP) may be electrically floating patterns. Each of the dummy patterns (DUP) may be patterns insulated from the first and second sensing electrodes (TE1, TE2). The dummy patterns (DUP) may include first to fourth dummy patterns (DUP1 to DUP4) depending on the placement location.

[0175] According to the present invention in this embodiment, the first sensing pattern (SP1) and the second sensing electrode (TE2) may form the second conductive layer (TML2) described in FIG. 6. The first conductive pattern (BP1) may form the first conductive layer (TML1). The first sensing patterns (SP1) may be connected to the corresponding first conductive pattern (BP1) through a sensing contact hole defined in the second sensing insulating layer (TIL2).

[0176] Referring to FIG. 12, in this embodiment, the input sensing panel (ISP-A) may include a passivation layer (PVX-A). The passivation layer (PVX-A) may be disposed on a second conductive layer (TML2, see FIG. 6) and covered by a third sensing insulating layer (TIL3, see FIG. 6).

[0177] In this embodiment, the passivation layer (PVX-A) can be directly disposed on the first sensing patterns (SP1) and the second sensing electrode (TE2) that overlap with the active region (AA-I) of the second conductive layer (TML2). Accordingly, the passivation layer (PVX-A) can be non-overlapping with the surrounding region (NAA).

[0178] The passivation layer (PVX-A) may have a shape corresponding in a plane to the first sensing patterns (SP1), the second sensing patterns (SP2), and the second conductive pattern (BP2). That is, the passivation layer (PVX-A) may have a shape corresponding in a plane to the first sensing patterns (SP1), the second sensing patterns (SP2), and the second conductive pattern (BP2) disposed on the second conductive layer (TML2) by the same process with the same mask.

[0179] In this embodiment, the dielectric constant of the passivation layer (PVX-A) may be higher than the dielectric constant of the third sensing insulating layer (TIL3) covering the passivation layer (PVX-A). The thickness of the passivation layer (PVX-A) may be smaller than the thickness of the third sensing insulating layer (TIL3) covering the passivation layer (PVX-A).

[0180] The passivation layer (PVX-A) may comprise a material different from the third sensing insulating layer (TIL3) covering the passivation layer (PVX-A). For example, the passivation layer (PVX-A) may comprise an inorganic material. The inorganic material may comprise at least one of silicon oxide and silicon nitride. The third sensing insulating layer (TIL3) may comprise an acrylic organic material.

[0182] FIG. 13 is a cross-sectional view of an input detection panel according to an embodiment of the present invention. FIG. 14 is a cross-sectional view of an input detection panel according to an embodiment of the present invention. FIG. 15 is a cross-sectional view of an input detection panel according to an embodiment of the present invention. FIG. 16 is a cross-sectional view of an input detection panel according to an embodiment of the present invention. Identical or similar reference numerals are assigned to configurations identical or similar to those described in FIG. 1 to 12, and redundant descriptions are omitted.

[0183] Hereinafter, the first conductive pattern (TML1) and the second conductive pattern (TNL2) described in FIGS. 13 to 16 may be configurations included in the first conductive layer (TML1) and the second conductive layer (TML2) that overlap with the active region (AA-I) among the patterns described in FIGS. 6 to 12.

[0184] Referring to FIG. 13, in this embodiment, an input sensing panel (ISP) may be disposed on a thin film encapsulation layer (ECL). The input sensing panel (ISP) includes sensing insulating layers (TIL1, TIL2, TIL3), conductive patterns (TML1, TML2), and a passivation layer (PVX).

[0185] A first sensing insulating layer (TIL1) is placed directly on a thin film encapsulation layer (ECL). A first conductive pattern (TML1) is placed on the first sensing insulating layer (TIL1). A second sensing insulating layer (TIL2) is placed on the first sensing insulating layer (TIL1) to cover the first conductive pattern (TML1). A second conductive pattern (TIL2) is placed on the second sensing insulating layer (TIL2). A passivation layer (PVX) is placed on the second conductive pattern (TIL2). A third sensing insulating layer (TIL3) is placed on the second sensing insulating layer (TIL2) to cover the second conductive pattern (TML2) and the passivation layer (PVX).

[0186] In this embodiment, the second sensing insulating layer (TIL2) that overlaps with the second conductive pattern (TML2) may include a side (IS) that protrudes in the thickness direction more than the adjacent second sensing insulating layer.

[0187] The second conductive pattern (TML2) includes an upper surface (TU) in contact with the passivation layer (PVX) and a side surface (TS) connected to the upper surface (TU). In this embodiment, the entire surface of the upper surface (TU) of the second conductive pattern (TML2) can be covered by the passivation layer (PVX).

[0188] The passivation layer (PVX) may include a side (PS). In this embodiment, the side (PS) of the passivation layer (PVX), the side (TS) of the second conductive pattern (TML2), and the side (IS) of the second sensing insulating layer (TIL2) may be aligned with each other. Additionally, the aligned sides (PS, TS, IS) may be inclined at a predetermined angle from the second sensing insulating layer (TIL2).

[0190] Referring to FIG. 14, in this embodiment, an input sensing panel (ISP-A) may be disposed on a thin film encapsulation layer (ECL). The input sensing panel (ISP-A) includes sensing insulating layers (TIL1, TIL2, TIL3), conductive patterns (TML1, TML2), and a passivation layer (PVX-A).

[0191] In this embodiment, the second sensing insulating layer (TIL2) that overlaps with the second conductive pattern (TML2) may include a side (IS) that protrudes in the thickness direction more than the adjacent second sensing insulating layer.

[0192] The second conductive pattern (TML2) includes an upper surface (TU) in contact with the passivation layer (PVX-A) and a side surface (TS) connected to the upper surface (TU). In this embodiment, the side surface (TS) of the second conductive pattern (TML2) and the side surface (IS) of the second sensing insulating layer (TIL2) may be aligned with each other. Additionally, the aligned sides (TS, IS) may be inclined at a predetermined angle from the second sensing insulating layer (TIL2).

[0193] In this embodiment, a portion of the upper surface (TU) of the second conductive pattern (TML2) may be exposed from the passivation layer (PVX-A). The portion of the upper surface (TU) of the second conductive pattern (TML2) exposed by the passivation layer (PVX-A) may come into contact with the third sensing insulating layer (TIL3).

[0195] Referring to FIG. 15, in this embodiment, an input sensing panel (ISP-B) may be disposed on a thin film encapsulation layer (ECL). The input sensing panel (ISP-B) includes sensing insulating layers (TIL1, TIL2, TIL3), conductive patterns (TML1, TML2), and a passivation layer (PVX-B).

[0196] In this embodiment, the second sensing insulating layer (TIL2) that overlaps with the second conductive pattern (TML2) may include a side (IS) that protrudes in the thickness direction more than the adjacent second sensing insulating layer.

[0197] The second conductive pattern (TML2) includes an upper surface (TU) in contact with the passivation layer (PVX-B) and a side surface (TS) connected to the upper surface (TU). In this embodiment, the side surface (TS) of the second conductive pattern (TML2) and the side surface (IS) of the second sensing insulating layer (TIL2) may be aligned with each other. Additionally, the aligned sides (TS, IS) may be inclined at a predetermined angle from the second sensing insulating layer (TIL2).

[0198] In this embodiment, the passivation layer (PVX-B) can be in contact with the upper surface (TU), side surface (TS) of the second conductive pattern (TML2), and the side surface (IS) of the second sensing insulating layer (TIL2).

[0200] Referring to FIG. 16, in this embodiment, an input sensing panel (ISP-C) may be disposed on a thin film encapsulation layer (ECL). The input sensing panel (ISP-C) includes sensing insulating layers (TIL1, TIL2, TIL3-C), conductive patterns (TML1, TML2), a passivation layer (PVX-C), and a high refractive index layer (HRF).

[0201] In this embodiment, the second sensing insulating layer (TIL2) that overlaps with the second conductive pattern (TML2) may include a side (IS) that protrudes in the thickness direction more than the adjacent second sensing insulating layer.

[0202] The second conductive pattern (TML2) includes an upper surface (TU) in contact with the passivation layer (PVX-C) and a side surface (TS) connected to the upper surface (TU). In this embodiment, the side surface (TS) of the second conductive pattern (TML2) and the side surface (IS) of the second sensing insulating layer (TIL2) may be aligned with each other. Additionally, the aligned sides (TS, IS) may be inclined at a predetermined angle from the second sensing insulating layer (TIL2).

[0203] The passivation layer (PVX-C) can come into contact with the upper surface (TU), side surface (TS) of the second conductive pattern (TML2), and the side surface (IS) of the second sensing insulating layer (TIL2).

[0204] In this embodiment, the third sensing insulating layer (TIL3-C) may be patterned to cover the passivation layer (PVX-C). Thus, the side (PS) of the passivation layer (PVX-C) may be exposed from the third sensing insulating layer (TIL3-C).

[0205] In this embodiment, the input sensing panel (ISP-C) may include a high refractive index layer (HRF) covering the third sensing insulating layer (TIL3-C). The high refractive index layer (HRF) may be disposed on the second sensing insulating layer (TIL2-C) to provide a flat surface.

[0206] The high refractive index layer (HRF) according to the present invention may have a refractive index equal to or lower than that of the passivation layer (PVX-C) and a refractive index higher than that of the third sensing insulating layer (TIL-3). Accordingly, even if light provided from the display panel (DP) reaches the third sensing insulating layer (TIL3-C) via the high refractive index layer (HRF), total reflection can easily occur. Accordingly, an input sensing panel (ISP-C) capable of reducing the loss of light provided from the display panel (DP) can be provided.

[0207] The high refractive index layer (HRF) may include a base layer containing a polymer material and a high refractive index material included in the base layer. The base layer may include, for example, at least one of acrylic, epoxy, siloxane, imide, and compounds thereof, such as polydiarylsiloxane, methyltrimethoxysilane, or tetramethoxysilane.

[0208] The high refractive index material may include at least one of zirconium oxide (ZrO2), titanium oxide (TiO2), silicon oxide (SiO2), zinc oxide (ZnO2), and mixtures thereof.

[0210] FIGS. 17a to 17e are cross-sectional views of a method for manufacturing an input sensing panel according to an embodiment of the present invention. FIGS. 18a to 18d are cross-sectional views of a method for manufacturing an input sensing panel according to an embodiment of the present invention. Identical or similar reference numerals are used for configurations identical or similar to those described in FIGS. 1 to 13, and redundant descriptions are omitted.

[0211] FIGS. 17a to 17e illustrate a method for manufacturing configurations formed in the active area (AA-I) of an input sensing panel (ISP), and FIGS. 18a to 18e illustrate a method for manufacturing the peripheral area (NAA-I) of an input sensing panel (ISP). Hereinafter, drawings proceeding in the same process will be described simultaneously.

[0212] Referring to FIG. 17a, a method for manufacturing a display device according to the present embodiment may include the steps of forming a first sensing insulating layer (TIL1) on a thin film encapsulation layer (ECL) and forming a first conductive pattern (TML2) on the first sensing insulating layer (TIL1).

[0213] The first sensing insulating layer (TIL1) can be formed by depositing an inorganic material on a thin film encapsulation layer (ECL). The first conductive pattern (TML2) can be selectively patterned by photolithography after applying a conductive material on the first sensing insulating layer (TIL1).

[0214] Referring to FIGS. 17b to 17d, the method for manufacturing a display device according to the present embodiment may include the steps of forming a second sensing insulating layer (TIL2) on a first sensing insulating layer (TIL1), forming a second conductive pattern (TML2) on the second sensing insulating layer (TIL2), and forming a passivation layer (PVX) on the second conductive pattern (TML2).

[0215] The second sensing insulating layer (TIL2) can be formed by depositing it on the first sensing insulating layer (TIL1). Subsequently, a conductive material is applied on the second sensing insulating layer (TIL2) to form a second conductive pattern (TML2), and an inorganic material is deposited on the second conductive pattern (TML2) to form a passivation layer (PVX).

[0216] Subsequently, the passivation layer (PVX) and the second conductive pattern (TML2) can be etched in batches using a photolithography method through the first mask (PR1). Thus, the side (PS) of the passivation layer (PVX) and the side (TS) of the second conductive pattern (TML2) can be aligned with each other.

[0217] At this time, due to the difference in etching rate, a portion of the second sensing insulating layer (TIL2) that does not overlap with the second conductive pattern (TML2) may be removed. Accordingly, a step difference may be formed between the portion of the second sensing insulating layer (TIL2) that overlaps with the second conductive pattern (TML2) and the portion that does not overlap with the second conductive pattern (TML2).

[0218] According to the method for manufacturing a display device according to the present embodiment, the side (PS) of the passivation layer (PVX), the side (TS) of the second conductive pattern (TML2), and the side (IS) of the second sensing insulating layer (TIL2) are aligned with each other, and the aligned sides (PS, TS, IS) can be formed in a shape inclined at a predetermined angle from the second sensing insulating layer (TIL2).

[0219] Referring to FIGS. 18a through 18d, while the process described in FIGS. 17a and FIG. 17e is carried out in the surrounding area (NAA-I), the steps of forming an upper contact hole (TPN) in the first sensing insulating layer (TIL1) and the second sensing insulating layer (TIL2), and forming a sensing wire (TDT) that overlaps with the upper contact hole (TPN) may be carried out. The upper contact hole (TPN) may correspond to any one of the upper contact holes (CTN-1, CTN-2, CTN-3) described in FIG. 7, and the sensing wire (TDT) may correspond to any one of the corresponding sensing wires (TL1, TL2, TL3).

[0220] The upper contact hole (TPN) can be formed by penetrating the first sensing insulating layer (TIL1) and the second sensing insulating layer (TIL2) after forming the first sensing insulating layer (TIL1) and the second sensing insulating layer (TIL2).

[0221] At this time, the insulating layers included in the display panel (DP) described in FIG. 5b can be simultaneously penetrated to simultaneously form the lower contact holes (CTN1, CTN2, CTN3) described in FIG. 4.

[0222] Subsequently, a conductive material can be applied to the second sensing insulating layer (TIL2) to form a second conductive pattern (TML2). Subsequently, a passivation layer (PVX-P) can be formed on the second conductive pattern (TML2).

[0223] Subsequently, the passivation layer (PVX-P) and the second conductive pattern (TML2) can be etched in batches by photolithography using the second mask (PR2). The patterned second conductive pattern (TML2) can be provided as a sensing wire (TDT). The sensing wire (TDT) illustrates a portion of the sensing wire that overlaps with the upper contact holes (CNT-1, CNT-2, CNT-3) among the sensing wires (TL1, TL2, TL3) described in FIG. 7.

[0224] Subsequently, referring to FIG. 17e, the method may include the step of forming a third sensing insulating layer (TIL3) on the second sensing insulating layer (TIL2). The third sensing insulating layer (TIL3) may be formed by applying an organic material onto the second sensing insulating layer (TIL2).

[0225] At this time, the third sensing insulating layer (TIL3) may not be deposited in the surrounding area (NAA-I), or the sensing wiring (TDT) may be exposed by depositing and then patterning.

[0226] Subsequently, referring to FIG. 18e, the method may further include the step of removing the passivation layer (PVX-P) formed on the sensing wiring (TDT) in the surrounding area (NAA-I). Thus, the sensing wiring (TDT) can be connected to the corresponding contact lines (CTL1, CTL2, CTL3, see FIG. 4) through the lower contact holes (CNT1, CNT2, CNT3, see FIG. 4) that overlap with the upper contact hole (TPN).

[0228] Although the present invention has been described above with reference to preferred embodiments, those skilled in the art or those with ordinary knowledge in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention as described in the claims set forth below.

[0229] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0230] EA: Display device DP: Display Panel ISP: Input Detection Panel TE1, TE2: Sensing electrodes SP1, SP2: Detection Patterns BP1, BP2: Challenge Patterns PVX: Passivation layer TIL1, TIL2, TIL3: Sensing wires CTN-1, CTN-2, CTN-3: Upper contact holes CTN1, CTN2, CTN3: Lower contact holes

Claims

Claim 1 A display panel comprising a base layer, a circuit element layer including a transistor disposed on the base layer, a display element layer including a light-emitting element connected to the transistor, and a thin film encapsulation layer covering the display element layer; and an input sensing panel comprising a first sensing insulating layer disposed directly on the thin film encapsulation layer, a first conductive layer disposed on the first sensing insulating layer, a second sensing insulating layer covering the first conductive layer, a second conductive layer disposed on the second sensing insulating layer, a passivation layer disposed directly on the second conductive layer, and a third sensing insulating layer covering the passivation layer, wherein the dielectric constant of the passivation layer is higher than the dielectric constant of the third sensing insulating layer, the side of the passivation and the side of the second conductive layer are inclined at a predetermined angle from the second sensing insulating layer, and the side of the passivation and the side of the second conductive layer are in contact with the third sensing insulating layer. Claim 2 A display device according to claim 1, wherein the passivation layer comprises any one of silicon nitride, silicon oxide, and silicon oxynitride, and the third sensing insulating layer comprises an organic material. Claim 3 A display device according to claim 1, wherein the passivation layer is in contact with the second conductive layer and has a shape corresponding to the second conductive layer in a planar form. Claim 4 A display device according to claim 1, characterized in that the thickness of the passivation layer is smaller than the thickness of the third sensing insulation layer. Claim 5 A display device according to claim 1, wherein the side of the passivation layer and the side of the second conductive layer are aligned with each other along an inclined direction. Claim 6 A display device according to claim 1, characterized in that the thickness of the second sensing insulating layer overlapping with the passivation is greater than the thickness in other areas. Claim 7 A display device according to claim 1, characterized in that a portion of the upper surface of the second conductive layer in contact with the passivation layer is exposed by the passivation layer and comes into contact with the third sensing insulating layer. Claim 8 A display device according to claim 1, wherein the upper surface and the side surface of the second conductive layer are covered by the passivation layer. Claim 9 A display device according to claim 8, further comprising a high-refractive index layer covering the third sensing insulating layer and having a higher refractive index than the third sensing insulating layer, wherein the side of the passivation layer is exposed from the third sensing insulating layer. Claim 10 A display device according to claim 1, wherein the input sensing panel comprises: a first sensing electrode including first sensing patterns arranged in a first direction and a conductive pattern disposed between the first sensing patterns; a second sensing electrode insulated from the first sensing electrode and extended in a second direction intersecting the first direction; and sensing wiring connected to the first sensing electrode and the second sensing electrode, wherein the first conductive layer is composed of a portion of the conductive patterns and the sensing wiring, and the second conductive layer is composed of the first sensing patterns, the second sensing electrode, and the remainder of the sensing wiring. Claim 11 A display device according to claim 10, wherein the second conductive layer comprises a plurality of mesh lines extending in directions intersecting each other, and the passivation layer in a planar plane has a shape corresponding to the mesh lines. Claim 12 A display device according to claim 10, wherein the passivation layer does not overlap with the sensing wiring. Claim 13 A display device according to claim 11, wherein the first sensing patterns are connected to the conductive pattern through a sensing contact hole defined in the second sensing insulating layer. Claim 14 A display device according to claim 1, wherein the input detection panel detects an external input by a capacitive method. Claim 15 An input sensing panel comprising: a first sensing insulating layer; a first conductive layer disposed on the first sensing insulating layer; a second sensing insulating layer covering the first conductive layer; a second conductive layer disposed on the second sensing insulating layer; a passivation layer directly disposed on the second conductive layer; and a third sensing insulating layer covering the passivation layer, wherein the dielectric constant of the passivation layer is higher than the dielectric constant of the third sensing insulating layer, the side of the passivation layer and the side of the second conductive layer are aligned with each other and inclined at a predetermined angle from the second sensing insulating layer, and the side of the passivation layer and the side of the second conductive layer are in contact with the third sensing insulating layer. Claim 16 An input sensing panel according to claim 15, wherein the passivation layer comprises any one of silicon nitride, silicon oxide, and silicon oxynitride, and the third sensing insulating layer comprises an organic material. Claim 17 delete Claim 18 A method for manufacturing a display device comprising: forming a first sensing insulating layer and a first conductive layer on the first sensing insulating layer on a display panel including an active area and a peripheral area; forming a second sensing insulating layer covering the first conductive layer and a second conductive layer including a conductive material on the second sensing insulating layer; forming a passivation layer including an inorganic material on the second conductive layer; simultaneously etching the second conductive layer and the passivation layer through a photoresist process; and forming a third sensing insulating layer covering the passivation layer, wherein the dielectric constant of the passivation layer is higher than the dielectric constant of the third sensing insulating layer, the side of the passivation and the side of the second conductive layer are inclined at a predetermined angle from the second sensing insulating layer, and the side of the passivation and the side of the second conductive layer are in contact with the third sensing insulating layer. Claim 19 A method for manufacturing a display device according to claim 18, wherein when the second sensing insulating layer and the second conductive layer and the passivation layer are simultaneously etched, at least a portion of the second sensing insulating layer is removed to form a side of the second sensing insulating layer aligned with the side of the second conductive layer. Claim 20 A method for manufacturing a display device according to claim 19, further comprising the step of forming a contact hole penetrating the first sensing insulating layer and the second sensing insulating layer in the surrounding area after the step of forming the second sensing insulating layer and before the step of forming the second conductive layer. Claim 21 A method for manufacturing a display device according to claim 20, further comprising the step of removing the passivation layer to expose the second conductive layer in an area overlapping with the contact hole after the step of simultaneously etching the second conductive layer and the passivation layer.

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