Display device

Abstract

The present invention discloses a display device. The present invention comprises a substrate, a display substrate including a display element disposed on the substrate, and a sealing film including an inorganic sealing layer and an organic sealing layer disposed on the display substrate to shield the display element, wherein at least one of the inorganic sealing layer and the upper surface of the display substrate is provided with a control groove for controlling the position of the end of the organic sealing layer, and the end of the organic sealing layer does not overlap with the control groove, or the organic sealing layer overlaps only partially with the control groove.

Description

Technology Field

[0001] Embodiments of the present invention relate to a device, and more specifically, to a display device. Background Technology

[0002] Mobile-based electronic devices are being widely used. In addition to small electronic devices such as mobile phones, tablet PCs have recently become widely used as mobile electronic devices.

[0003] Such portable electronic devices include a display device to support various functions and to provide visual information, such as images or videos, to the user. Recently, as other components for driving the display device have become miniaturized, the proportion of the display device within the electronic device is gradually increasing, and structures capable of bending from a flat state to a predetermined angle are also being developed. The problem to be solved

[0004] Generally, a display device may include various organic layers. If the upper surface of an organic layer disposed in the upper portion among these organic layers is not flat, a phenomenon may occur where stripes are visible when the display device is not in operation or an image appears distorted when the display device is in operation. Embodiments of the present invention provide a display device including a uniform organic layer. means of solving the problem

[0005] One embodiment of the present invention discloses a display device comprising a substrate, a display substrate including a display element disposed on the substrate, and a sealing film including an inorganic sealing layer and an organic sealing layer disposed on the display substrate to shield the display element, wherein at least one of the inorganic sealing layer and the upper surface of the display substrate is provided with a control groove for controlling the position of the end of the organic sealing layer, and the end of the organic sealing layer does not overlap with the control groove or the organic sealing layer overlaps only partially with the control groove.

[0006] In this embodiment, the control groove may be disposed on the upper surface of at least one of the inorganic layer, organic layer, and metal layer of the display substrate.

[0007] In this embodiment, the control grooves are provided in plurality, and the plurality of control grooves may be arranged to be spaced apart from each other in a first direction and a second direction on a plane.

[0008] In this embodiment, the display substrate may further include a damper disposed on the substrate.

[0009] In this embodiment, one of the control groove and the dam part may be positioned further inward than the other of the control groove and the dam part.

[0010] In this embodiment, the planar shape of the control groove may be one of a circle, an ellipse, or a polygon.

[0011] In the present embodiment, the control grooves are provided in plurality, and the planar shape of some of the plurality of control grooves and the planar shape of other of the plurality of control grooves may be different from each other.

[0012] In the present embodiment, the control grooves are provided in multiple numbers, and the sides of some of the multiple control grooves and the sides of other of the multiple control grooves may be different from each other.

[0013] In this embodiment, the side of the control groove may be inclined.

[0014] In this embodiment, the side of the control groove may be stepped.

[0015] In this embodiment, the maximum width of the control groove passing through the center of the control groove may be 100 μm or less.

[0016] In this embodiment, the control groove may be formed in different layers in the depth direction.

[0017] Another embodiment of the present invention discloses a display device comprising a substrate, a display element disposed on the substrate, a sealing film disposed on the display element to shield the display element, a touch layer disposed on the sealing film to receive an external signal, and a refractive layer disposed on the touch layer to refract light emitted from the display element, wherein a control groove is provided on the upper surface of the touch layer to control the position of the end of the refractive layer, and the end of the refractive layer does not overlap with the control groove, or the refractive layer overlaps only partially with the control groove.

[0018] In this embodiment, the control grooves are provided in plurality, and the plurality of control grooves may be arranged to be spaced apart from each other in a first direction and a second direction on a plane.

[0019] In this embodiment, the planar shape of the control groove may be one of a circle, an ellipse, or a polygon.

[0020] In the present embodiment, the control grooves are provided in plurality, and the planar shape of some of the plurality of control grooves and the planar shape of other of the plurality of control grooves may be different from each other.

[0021] In the present embodiment, the control grooves are provided in multiple numbers, and the sides of some of the multiple control grooves and the sides of other of the multiple control grooves may be different from each other.

[0022] In this embodiment, the side of the control groove may be inclined.

[0023] In this embodiment, the side of the control groove may be stepped.

[0024] In this embodiment, the maximum width of the control groove passing through the center of the control groove may be 100㎛ or less.

[0025] Other aspects, features, and advantages other than those described above will become clear from the following drawings, claims, and detailed description of the invention. Effects of the invention

[0026] The display device according to the embodiments of the present invention can prevent the visibility of stripes, etc., by precisely controlling the position of the end of the organic layer. In addition, the display device according to the embodiments of the present invention can maintain a uniform height of the organic layer arranged to correspond to the display area by forming the highest point of the organic layer high when forming the organic layer. Brief explanation of the drawing

[0027] FIG. 1 is a schematic perspective view of a display device according to one embodiment. FIG. 2 is a simplified cross-sectional view of a display device according to one embodiment. FIG. 3 is a schematic plan view of a display panel according to one embodiment. FIG. 4 is an equivalent circuit diagram showing a pixel according to one embodiment. FIG. 5 is a cross-sectional view schematically showing a part of a display device according to one embodiment of the present invention. FIGS. 6a to 6e are plan views schematically showing the first control groove illustrated in FIG. 5. FIGS. 7a to 7d are cross-sectional views schematically showing the first control groove illustrated in FIG. 5. FIGS. 8A and FIGS. 8B are cross-sectional views schematically showing the second control groove illustrated in FIGS. 5. FIG. 9 is a cross-sectional view schematically showing a display device according to one embodiment of the present invention. FIGS. 10a to 10c are cross-sectional views schematically showing the first control groove illustrated in FIG. 9. FIG. 11a is a cross-sectional view schematically showing a display device according to another embodiment of the present invention. FIGS. 11b to 11d are cross-sectional views showing the first control groove illustrated in FIG. 11a in detail. FIG. 12a is a cross-sectional view schematically showing a display device according to another embodiment of the present invention. FIGS. 12b to 12d are cross-sectional views showing the first control groove illustrated in FIG. 12a in detail. FIGS. 13a to 13c are cross-sectional views schematically showing the second control groove illustrated in FIGS. 11a and FIGS. 12a. FIGS. 14a and FIGS. 14b are cross-sectional views schematically showing a display device according to another embodiment of the present invention. FIGS. 15a and FIGS. 15b are cross-sectional views schematically showing the first control groove illustrated in FIGS. 14a and FIGS. 14b. Specific details for implementing the invention

[0028] The present invention is capable of various modifications and may have various embodiments; specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various forms.

[0029] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0030] In the following embodiments, terms such as first, second, etc. are used not in a limiting sense, but for the purpose of distinguishing one component from another component.

[0031] In the following examples, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0032] In the following embodiments, terms such as "include" or "have" mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0033] In the following embodiments, when a part such as a film, region, or component is described as being on or above another part, it includes not only cases where it is directly on top of another part, but also cases where another film, region, or component is interposed in between.

[0034] In the drawings, the size of components may be exaggerated or reduced for convenience of explanation. For example, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, so the present invention is not necessarily limited to what is illustrated.

[0035] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to three axes in an orthogonal coordinate system and can be interpreted in a broader sense that includes them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0036] Where an embodiment can be implemented differently, a specific process sequence may be performed differently from the order described. For example, two processes described consecutively may be performed substantially simultaneously or proceed in the reverse order of the description.

[0037] FIG. 1 is a schematic perspective view of a display device according to one embodiment. FIG. 2 is a simplified cross-sectional view of a display device according to one embodiment, which may correspond to a cross-section along line I-I' of FIG. 1.

[0038] Referring to FIGS. 1 and 2, the display device according to embodiments of the present invention may be implemented as an electronic device such as a smartphone, mobile phone, smart watch, navigation device, game console, TV, vehicle head unit, notebook computer, laptop computer, tablet computer, PMP (Personal Media Player), PDA (Personal Digital Assistant). Additionally, the electronic device may be a flexible device.

[0039] The display device (1) may include a display area (DA) where an image is displayed and a peripheral area (PA) placed around the display area (DA). The display device (1) may provide a predetermined image using light emitted from a plurality of pixels placed in the display area (DA).

[0040] The display device (1) can be provided in various shapes, for example, in the form of a rectangular plate having two pairs of sides parallel to each other. When the display device is provided in the form of a rectangular plate, one pair of sides may be provided longer than the other pair of sides. In one embodiment of the present invention, for convenience of explanation, the case where the display device is a rectangular shape having a pair of long sides and a pair of short sides is shown, and the direction of extension of the short side is indicated as the first direction (x direction), the direction of extension of the long side as the second direction (y direction), and the direction perpendicular to the direction of extension of the long side and the short side as the third direction (z direction). In another embodiment, the display device (1) may be a non-rectangular shape. A non-rectangular shape may be, for example, a circle, an ellipse, a polygon that is partly circular, or a polygon excluding a square.

[0041] When the display area (DA) is viewed as a planar shape, the display area (DA) may be a rectangular shape as shown in FIG. 1. In another embodiment, the display area (DA) may be a polygonal shape such as a triangle, pentagon, or hexagon, or a circular shape, an elliptical shape, an irregular shape, etc.

[0042] The peripheral area (PA) is an area placed around the display area (DA) and may be a type of non-display area where pixels are not placed. The display area (DA) may be entirely surrounded by the peripheral area (PA). Various wirings that transmit electrical signals to be applied to the display area (DA), and pads to which printed circuit boards or driver IC chips are attached may be located in the peripheral area (PA).

[0043] In the following description, an organic light-emitting display device is used as an example of a display device (1) according to one embodiment of the present invention, but the display device of the present invention is not limited thereto. As another embodiment, the display device (1) of the present invention may be a display device such as an inorganic light-emitting display (Inorganic Light Emitting Display or Inorganic EL Display) or a quantum dot light-emitting display.

[0044] Referring to FIG. 2, the display device (1) may include a display panel (10), an input sensing layer (40) disposed on the display panel (10), and an optical function layer (50).

[0045] The display panel (10) can display an image. The display panel (10) includes pixels placed in a display area (DA). The pixels may include display elements. The display elements may be connected to a pixel circuit. The display elements may include an organic light-emitting diode, or a quantum dot organic light-emitting diode, etc.

[0046] The input detection layer (40) acquires coordinate information based on an external input, such as a touch event. The input detection layer (40) may include a sensing electrode (or touch electrode) and trace lines connected to the sensing electrode. The input detection layer (40) may be placed on a display panel (10). The input detection layer (40) may detect external input using a mutual capping method or / and a self capping method.

[0047] The input sensing layer (40) may be formed directly on the display panel (10) or formed separately and then bonded through an adhesive layer such as an optical clear adhesive. For example, the input sensing layer (40) may be formed continuously after the process of forming the display panel (10), in which case the input sensing layer (40) may be part of the display panel (10), and an adhesive layer may not be interposed between the input sensing layer (40) and the display panel (10). FIG. 2 illustrates the input sensing layer (40) being interposed between the display panel (10) and the optical functional layer (50), but in another embodiment, the input sensing layer (40) may be placed on the optical functional layer (50).

[0048] The optical functional layer (50) may include a color conversion layer and an anti-reflection layer. The color conversion layer can convert light emitted from the display panel (10) into a specific wavelength band. At this time, the color conversion layer may include a quantum dot layer, a light-transmitting layer, and a bank layer. At this time, the bank layer may be a layer that blocks light and may be in the form of a resin containing dyes, etc. The anti-reflection layer can reduce the reflectivity of light (external light) incident from the outside toward the display panel (10). The anti-reflection layer may include a black matrix and color filters. The color filters may be arranged considering the color of light emitted from each pixel of the display panel (10).

[0049] FIG. 3 is a schematic plan view of a display panel according to one embodiment.

[0050] Referring to FIG. 3, various components forming a display panel (10) are arranged on a substrate (100). The substrate (100) includes a display area (DA) and a peripheral area (PA) surrounding the display area (DA).

[0051] A plurality of pixels (P) and signal lines capable of applying electrical signals to the pixels (P) may be arranged in the display area (DA). Each pixel (P) may be implemented as a display element such as an organic light-emitting diode (OLED). Each pixel (P) may emit light, for example, red, green, blue, or white. The display area (DA) may be covered with a sealing member to be protected from the outside air or moisture.

[0052] Signal lines capable of applying electrical signals to multiple pixels (P) may include multiple scan lines (SL) and multiple data lines (DL). Each of the multiple scan lines (SL) may extend in a first direction (x-direction), and each of the multiple data lines (DL) may extend in a second direction (y-direction). The multiple scan lines (SL) may be arranged, for example, in multiple rows to transmit scan signals to the pixels (P), and the multiple data lines (DL) may be arranged, for example, in multiple columns to transmit data signals to the pixels (P). Each of the multiple pixels (P) may be connected to at least one corresponding scan line (SL) among the multiple scan lines (SL) and to a corresponding data line (DL) among the multiple data lines (DL).

[0053] The signal lines may further include a plurality of driving voltage lines (PL), a plurality of light emission control lines (EL), etc. Each of the plurality of light emission control lines (EL) may extend in the x-direction, and each of the plurality of driving voltage lines (PL) may extend in the y-direction. The plurality of light emission control lines (EL) may be arranged, for example, in a plurality of rows to transmit light emission control signals to pixels (P). The plurality of driving voltage lines (PL) may be arranged, for example, in a plurality of columns to transmit driving voltage signals (driving voltages) to pixels (P).

[0054] Each pixel circuit driving a pixel (P) can be electrically connected to an outer circuit located in a peripheral area (PA). The peripheral area (PA) is an area where pixels (P) are not located, where various electronic components or printed circuit boards may be electrically attached, and voltage lines supplying power to drive the pixels (P) may be located. For example, a first scan driving circuit (SDRV1), a second scan driving circuit (SDRV2), a terminal section (PAD), and a power supply line may be located in the peripheral area (PA). The power supply line may include a driving voltage supply line (11) and a common voltage supply line (13).

[0055] The first scan driving circuit (SDRV1) can apply a scan signal to each pixel circuit that drives pixels (P) through scan lines (SL). The second scan driving circuit (SDRV2) can apply a light emission control signal to each pixel circuit through light emission control lines (EL). The second scan driving circuit (SDRV2) can be located on the opposite side of the first scan driving circuit (SDRV1) with respect to the display area (DA) and can be approximately parallel to the first scan driving circuit (SDRV1).

[0056] A terminal portion (PAD) may be placed on one side of the substrate (100). The terminal portion (PAD) is exposed without being covered by an insulating layer and is connected to a display circuit board (30). A display driving portion (32) may be placed on the display circuit board (30).

[0057] The display driving unit (32) can generate a control signal to be transmitted to the first scan driving circuit (SDRV1) and the second scan driving circuit (SDRV2). The display driving unit (32) generates a data signal, and the generated data signal can be transmitted to the pixel circuits of the pixels (P) through the fan-out lines (FW) and the data lines (DL) connected to the fan-out lines (FW). The fan-out lines (FW) can be provided to extend in the y-direction.

[0058] The display driving unit (32) can supply a driving voltage (ELVDD) to the driving voltage supply line (11) and a common voltage (ELVSS) to the common voltage supply line (13). The driving voltage (ELVDD) can be applied to the pixel circuits of the pixels (P) through the driving voltage line (PL) connected to the driving voltage supply line (11). The common voltage (ELVSS) can be applied to the opposing electrodes of the display elements through the common voltage supply line (13).

[0059] The driving voltage supply line (11) is connected to the terminal portion (PAD) and may be provided by extending in the x-direction from the lower side of the display area (DA). The common voltage supply line (13) is connected to the terminal portion (PAD) and has a loop shape with one side (e.g., the lower side of the display area (DA)) open, and may partially surround the display area (DA). The common voltage supply line (13) may be provided by extending in the y-direction from the left and right sides of the display area (DA) and extending in the x-direction from the upper side of the display area (DA).

[0060] FIG. 4 is an equivalent circuit diagram showing a pixel according to one embodiment.

[0061] Referring to FIG. 4, the pixel circuit (PC) includes first to seventh transistors (T1 to T7), and depending on the type of transistor (p-type or n-type) and / or operating conditions, the first terminal of each of the first to seventh transistors (T1 to T7) may be a source terminal or a drain terminal, and the second terminal may be a terminal different from the first terminal. For example, if the first terminal is a source terminal, the second terminal may be a drain terminal.

[0062] The pixel circuit (PC) can be connected to a first scan line (SL) that transmits a first scan signal (Sn), a second scan line (SL-1) that transmits a second scan signal (Sn-1), a third scan line (SL+1) that transmits a third scan signal (Sn+1), a light emission control line (EL) that transmits a light emission control signal (En), a data line (DL) that transmits a data signal (DATA), a driving voltage line (PL) that transmits a driving voltage (ELVDD), and an initialization voltage line (VL) that transmits an initialization voltage (Vint).

[0063] The first transistor (T1) includes a gate terminal connected to the second node (N2), a first terminal connected to the first node (N1), and a second terminal connected to the third node (N3). The first transistor (T1) acts as a driving transistor and receives a data signal (DATA) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element. The light-emitting element may be an organic light-emitting diode (OLED).

[0064] The second transistor (T2) (switching transistor) includes a gate terminal connected to the first scan line (SL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1) (or the first terminal of the first transistor (T1). The second transistor (T2) can perform a switching operation in which it is turned on according to the first scan signal (Sn) received through the first scan line (SL) and transmits the data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0065] The third transistor (T3) (compensation transistor) includes a gate terminal connected to the first scan line (SL), a first terminal connected to the second node (N2) (or the gate terminal of the first transistor (T1)), and a second terminal connected to the third node (N3) (or the second terminal of the first transistor (T1)). The third transistor (T3) can be turned on according to the first scan signal (Sn) received through the first scan line (SL) to diode-connect the first transistor (T1). The third transistor (T3) may have a structure in which two or more transistors are connected in series.

[0066] The fourth transistor (T4) (first initialization transistor) includes a gate terminal connected to the second scan line (SL-1), a first terminal connected to the initialization voltage line (VL), and a second terminal connected to the second node (N2). The fourth transistor (T4) is turned on according to the second scan signal (Sn-1) received through the second scan line (SL-1) to transmit an initialization voltage (Vint) to the gate terminal of the first transistor (T1), thereby initializing the gate voltage of the first transistor (T1). The fourth transistor (T4) may have a structure in which two or more transistors are connected in series.

[0067] The fifth transistor (T5) (first light-emitting control transistor) includes a gate terminal connected to the light-emitting control line (EL), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first node (N1). The sixth transistor (T6) (second light-emitting control transistor) includes a gate terminal connected to the light-emitting control line (EL), a first terminal connected to the third node (N3), and a second terminal connected to the pixel electrode of the organic light-emitting diode (OLED). The fifth transistor (T5) and the sixth transistor (T6) are simultaneously turned on according to the light-emitting control signal (En) received through the light-emitting control line (EL), so that current flows through the organic light-emitting diode (OLED).

[0068] The seventh transistor (T7) (second initialization transistor) includes a gate terminal connected to the third scan line (SL+1), a second terminal of the sixth transistor (T6), a first terminal connected to the pixel electrode of the organic light-emitting diode (OLED), and a second terminal connected to the initialization voltage line (VL). The seventh transistor (T7) is turned on according to the third scan signal (Sn+1) received through the third scan line (SL+1) to transmit an initialization voltage (Vint) to the pixel electrode of the organic light-emitting diode (OLED), thereby initializing the voltage of the pixel electrode of the organic light-emitting diode (OLED). The seventh transistor (T7) may be omitted.

[0069] The capacitor (Cst) includes a first electrode connected to the second node (N2) and a second electrode connected to the driving voltage line (PL).

[0070] An organic light-emitting diode (OLED) includes a pixel electrode and a counter electrode facing the pixel electrode, and the counter electrode may receive a common voltage (ELVSS). The organic light-emitting diode (OLED) may display an image by receiving a driving current from a first transistor (T1) and emitting light in a predetermined color. The counter electrode may be provided in common, i.e., integrally, to a plurality of pixels.

[0071] FIG. 4 illustrates a case where the fourth transistor (T4) and the seventh transistor (T7) are connected to the second scan line (SL-1) and the third scan line (SL+1), respectively, but the present invention is not limited thereto. In another embodiment, the fourth transistor (T4) and the seventh transistor (T7) are both connected to the second scan line (SL-1) and can be driven according to the second scan signal (Sn-1).

[0072] FIG. 5 is a cross-sectional view schematically showing a part of a display device according to one embodiment of the present invention.

[0073] Referring to FIG. 5, when manufacturing a display panel (10), various layers can be sequentially formed on a substrate (100).

[0074] Specifically, a pixel circuit (PC) and an organic light-emitting diode (OLED) electrically connected to the pixel circuit (PC) may be disposed in the display area (DA) of the substrate (100). The pixel circuit (PC) may include a first thin-film transistor (TFT1) and a capacitor (Cst).

[0075] The substrate (100) may be formed of various materials such as metal or plastic. According to one embodiment, the substrate (100) may be a flexible substrate, and the substrate (100) may include a first base layer, a first barrier layer, a second base layer, and a second barrier layer that are sequentially stacked. The first base layer and the second base layer may each include a polymer resin. For example, the first base layer and the second base layer may include polymer resins such as polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), cellulose triacetate (TAC), and cellulose acetate propionate (CAP). The polymer resin may be transparent. The first barrier layer and the second barrier layer may each be a single layer or a multilayer containing inorganic materials such as amorphous silicon, silicon nitride, and / or silicon oxide, as layers that prevent the penetration of external foreign substances.

[0076] A buffer layer (110) may be disposed on the substrate (100). The buffer layer (110) can block foreign matter or moisture penetrating through the substrate (100). The buffer layer (110) may include inorganic materials such as silicon oxide, silicon nitride and / or silicon oxynitride, and may be formed as a single layer or a multilayer.

[0077] The first thin-film transistor (TFT1) may be one of the transistors described with reference to FIG. 4, for example, the first transistor (T1) which is a driving transistor. The first thin-film transistor (TFT1) may include a semiconductor layer (ACT), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE).

[0078] The semiconductor layer (ACT) may include amorphous silicon, polycrystalline silicon, oxide semiconductor material, or organic semiconductor material. The semiconductor layer (ACT) may include a channel region (CH) that overlaps with the gate electrode (GE), and source regions (SE) and drain regions (DE) disposed on both sides of the channel region (CH) and containing impurities. Here, the impurities may include N-type impurities or P-type impurities. The source region (SE) and drain region (DE) may be the source electrode and drain electrode of the first thin-film transistor (TFT1).

[0079] The gate electrode (GE) can be formed as a single layer or a multilayer using one or more materials selected from, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu), taking into consideration adhesion with adjacent layers, surface flatness of the stacked layers, and processability. A first gate insulating layer (111) may be disposed between the semiconductor layer (ACT) and the gate electrode (GE).

[0080] The capacitor (Cst) includes a lower electrode (CE1) and an upper electrode (CE2) that overlap with the second gate insulating layer (112) in between. The capacitor (Cst) may overlap with the first thin-film transistor (TFT1). FIG. 5 illustrates that the gate electrode (GE) of the first thin-film transistor (TFT1) is the lower electrode (CE1) of the capacitor (Cst). In another embodiment, the capacitor (Cst) may not overlap with the first thin-film transistor (TFT1).

[0081] The first gate insulating layer (111) and the second gate insulating layer (112) may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. The first gate insulating layer (111) and the second gate insulating layer (112) may be a single layer or a multilayer containing the aforementioned materials.

[0082] The capacitor (Cst) may be covered by an interlayer insulating layer (113). Each interlayer insulating layer (113) may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, etc. Each interlayer insulating layer (113) may be a single layer or a multilayer containing the aforementioned material.

[0083] A driving voltage line (PL) and a first connecting electrode (CM1) may be disposed on the interlayer insulation layer (113). Each of the driving voltage line (PL) and the first connecting electrode (CM1) may be formed as a single layer or a multilayer of one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In one embodiment, each of the driving voltage line (PL) and the first connecting electrode (CM1) may be formed as a multilayer of Ti / Al / Ti.

[0084] A first insulating layer (115) may be disposed on a driving voltage line (PL) and a first connecting electrode (CM1). A data line (DL) and a second connecting electrode (CM2) may be disposed on the first insulating layer (115). The data line (DL) and the second connecting electrode (CM2) may contain the same material as the driving voltage line (PL). For example, the data line (DL) and the second connecting electrode (CM2) may each be formed as a single layer or a multilayer of one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In one embodiment, the data line (DL) and the second connecting electrode (CM2) may each be formed as a multilayer of Ti / Al / Ti. The data line (DL) and the second connecting electrode (CM2) may be covered by a second insulating layer (116). As shown in FIG. 5, at least a portion of the data line (DL) may overlap with the driving voltage line (PL). In another embodiment, the data line (DL) may not overlap with the driving voltage line (PL).

[0085] In the embodiment of FIG. 5, the data line (DL) is placed on the upper layer of the driving voltage line (PL), but in other embodiments, the data line (DL) may be placed on the interlayer insulation layer (113), or the driving voltage line (PL) may be placed on the first insulation layer (115), so that the data line (DL) and the driving voltage line (PL) are placed on the same layer. In yet another embodiment, the driving voltage line (PL) may have a two-layer structure including a lower driving voltage line placed on the interlayer insulation layer (113) and an upper driving voltage line placed on the first insulation layer (115) and electrically connected to the lower driving voltage line.

[0086] The first insulating layer (115) and the second insulating layer (116) may be organic insulating layers as flattening insulating layers. For example, each of the first insulating layer (115) and the second insulating layer (116) may include an organic insulating material such as a general-purpose polymer like polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, a siloxane polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylene polymer, a vinyl alcohol polymer, and blends thereof. In one embodiment, the first insulating layer (115) and / or the second insulating layer (116) may be an organic insulating layer containing polyimide or an organic insulating layer containing siloxane.

[0087] In the display area (DA) above the second insulating layer (116), display elements, such as organic light-emitting elements (OLED1, OLED2, OLED3), may be disposed. At this time, the organic light-emitting elements (OLED1, OLED2, OLED3) are disposed spaced apart from each other and may include a first organic light-emitting element (OLED1), a second organic light-emitting element (OLED1), and a third organic light-emitting element (OLED3) that emit different colors. These first organic light-emitting elements (OLED1), second organic light-emitting elements (OLED1), and third organic light-emitting elements (OLED3) may emit different colors or emit the same color. The organic light-emitting elements (OLED1, OLED2, OLED3) may include a pixel electrode (221), an intermediate layer (222), and a counter electrode (223). For the sake of convenience of explanation, the first organic light-emitting diode (OLED1), the second organic light-emitting diode (OLED1), and the third organic light-emitting diode (OLED3) will be described in detail below, focusing on cases where they emit different colors.

[0088] The pixel electrode (221) of the organic light-emitting diode (OLED) is disposed on the second insulating layer (116) and can be connected to the first thin-film transistor (TFT1) through the first connecting electrode (CM1) on the interlayer insulating layer (113) and the second connecting electrode (CM2) on the first insulating layer (115).

[0089] The pixel electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In another embodiment, the pixel electrode (221) may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. In yet another embodiment, the pixel electrode (221) may further include a film formed of ITO, IZO, ZnO, or In2O3 above and below the aforementioned reflective film.

[0090] A third insulating layer (118) may be disposed on the second insulating layer (116). The third insulating layer (118) may include an opening (OP) corresponding to each pixel in the display area (DA), that is, an opening that exposes a part of the pixel electrode (221). The third insulating layer (118) is a pixel defining layer, and the opening (OP) of the third insulating layer (118) may define the light-emitting area of ​​the pixel. The light-emitting area may be an area where a light-emitting layer is disposed and light is emitted. That is, the third insulating layer (118) may be disposed to correspond to the remaining area excluding the light-emitting area, i.e., the non-light-emitting area. The size of the light-emitting area may vary depending on the color of the light emitted by the pixel.

[0091] Additionally, the third insulating layer (118) can serve to prevent arcs from occurring at the edge of the pixel electrode (221) by increasing the distance between the edge of the pixel electrode (221) and the opposing electrode (223) above the pixel electrode (221). The third insulating layer (118) may be formed from an organic material such as polyimide (PI) or HMDSO (hexamethyldisiloxane), for example.

[0092] The intermediate layer (222) includes a light-emitting layer. The light-emitting layer may include a polymer or low-molecular-weight organic material that emits light of a predetermined color. In one embodiment, the intermediate layer (222) may include a first functional layer disposed below the light-emitting layer and / or a second functional layer disposed above the light-emitting layer. The first functional layer and / or the second functional layer may include a layer that is integral across a plurality of pixel electrodes (221), or a layer patterned to correspond to each of the plurality of pixel electrodes (221). In such a case, the light-emitting layer may be disposed on each of the first organic light-emitting element (OLED1), the second organic light-emitting element (OLED1), and the third organic light-emitting element (OLED3). At this time, the light-emitting layers disposed on each of the first organic light-emitting element (OLED1), the second organic light-emitting element (OLED1), and the third organic light-emitting element (OLED3) may include different materials. In another embodiment, a light-emitting layer may be disposed to cover the first organic light-emitting element (OLED1), the second organic light-emitting element (OLED1), and the third organic light-emitting element (OLED3). In this case, the light-emitting layers disposed on the first organic light-emitting element (OLED1), the second organic light-emitting element (OLED1), and the third organic light-emitting element (OLED3) may be of the same material and may be disposed on the front surface of the display area (DA). At this time, it is also possible for the light-emitting layer to have a structure in which multiple different light-emitting layers are stacked.

[0093] The first functional layer may be a single layer or a multilayer. For example, if the first functional layer is formed of a polymer material, the first functional layer may be a single-layer hole transport layer (HTL) and may be formed of polyethylene dihydroxythiophene (PEDOT) or polyaniline (PANI). If the first functional layer is formed of a low-molecular-weight material, the first functional layer may include a hole injection layer (HIL) and a hole transport layer (HTL).

[0094] A second functional layer is not always provided. For example, when the first functional layer and the light-emitting layer are formed from a polymer material, it is desirable to form a second functional layer to improve the characteristics of the organic light-emitting device. The second functional layer may be a single layer or a multilayer. The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0095] The counter electrode (223) is positioned to face the pixel electrode (221) with an intermediate layer (222) in between. The counter electrode (223) may be made of a conductive material with a low work function. For example, the counter electrode (223) may include a (semi)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode (223) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi)transparent layer comprising the aforementioned materials.

[0096] The opposing electrode (223) is formed integrally with a plurality of organic light-emitting diodes (OLEDs) in the display area (DA) and is positioned on top of the intermediate layer (222) and the third insulating layer (118), facing the plurality of pixel electrodes (221).

[0097] A plurality of spacers (SPCs) may be further disposed in the non-luminous region of the display area (DA). The spacers (SPCs) may be disposed around the pixel electrodes (221), that is, between the pixel electrodes (221). The spacers (SPCs) may be disposed on the third insulating layer (118). The spacers (SPCs) may be an island-shaped insulating pattern. The spacers (SPCs) may be polygonal, such as squares, circles, triangles, or ellipses. The spacers (SPCs) may include an organic insulating material such as polyimide. Alternatively, the spacers (SPCs) may include an inorganic insulating material such as silicon nitride or silicon oxide, or may include both organic and inorganic insulating materials. The spacers (SPCs) may include a material different from the third insulating layer (118). Alternatively, the spacer (SPC) may include the same material as one of the first insulating layer (115), the second insulating layer (116), and the third insulating layer (118). The opposing electrode (223) may be placed on top of the spacer (SPC).

[0098] A thin film encapsulation layer (300) is disposed on the counter electrode (223) so that the display panel (10) can be protected from external foreign matter or moisture. The thin film encapsulation layer (300) may include at least one organic encapsulation layer and at least one inorganic encapsulation layer. FIG. 5 illustrates that the thin film encapsulation layer (300) includes first and second inorganic encapsulation layers (310, 330) and an organic encapsulation layer (320) interposed between them. In other embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and the stacking order may be changed.

[0099] If necessary, a plurality of layers including a capping layer (230) may be interposed between the first inorganic sealing layer (310) and the opposing electrode (223). FIG. 5 illustrates the capping layer (230), but in other embodiments, the capping layer (230) may be omitted.

[0100] The first and second inorganic encapsulation layers (310, 330) may include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride, etc. The organic encapsulation layer (320) may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof. Since the first inorganic encapsulation layer (310) is formed along the underlying structure, its upper surface may not be flat. The organic encapsulation layer (320) may have sufficient thickness to cover the first inorganic encapsulation layer (310). The upper surface of the organic encapsulation layer (320) may be substantially flat. The second inorganic sealing layer (330) extends outward from the organic sealing layer (320) and comes into contact with the first inorganic sealing layer (310), thereby preventing the organic sealing layer (320) from being exposed to the outside.

[0101] Next, the peripheral area (PA) is described. The peripheral area (PA) of FIG. 5 may correspond to a portion of the lower side of the display area (DA) illustrated in FIG. 3. The peripheral area (PA) may include a first sub-peripheral area (SPA1) relatively adjacent to the display area (DA) and a second sub-peripheral area (SPA2) relatively adjacent to the edge of the substrate (100) outside the first sub-peripheral area (SPA1). In the first sub-peripheral area (SPA1), a first insulating layer (115), a second insulating layer (116), and a third insulating layer (118) may be disposed extending from the display area (DA). The second sub-peripheral area (SPA2) may be a type of dam area in which at least one dam portion (DAM) is disposed. FIG. 5 illustrates two dam portions (DAM).

[0102] The above-described dam (DAM) may include a first dam (DAM1) and a second dam (DAM2). In this case, the first and second dams (DAM1, DAM2) may be located on top of an inorganic layer. For example, the first and second dams (DAM1, DAM2) may be placed on top of an inorganic insulating layer comprising at least one of a buffer layer (110), a first gate insulating layer (111), a second gate insulating layer (112), and an interlayer insulating layer (113).

[0103] A first dam (DAM1) may be provided in the second sub-peripheral area (SPA2). In the second sub-peripheral area (SPA2), a second dam (DAM2) may be further provided between the first dam (DAM1) and the first sub-peripheral area (SPA1), which is relatively closer to the indication area (DA) than the first dam (DAM1).

[0104] Each of the multiple dams (DAMs) may have a multilayer structure comprising multiple layers. In order for the dams (DAMs) to function as positioning devices for the organic encapsulation layer, it is preferable that the height of the first dam (DAM1) located at the outermost edge be relatively higher than that of the second dam (DAM2). A greater number of layers may be included so that the height of the first dam (DAM1) located at the outermost edge from the display area (DA) is higher than that of the second dam (DAM2). For example, the second dam (DAM2) may each include two layers: a first layer (116D), which is the lowest layer stacked in the direction away from the upper surface of the substrate (100), i.e., the z-direction, and a second layer (118D) on the first layer (116D). The first dam (DAM1) may include three layers, a first layer (116D) which is the lowest layer stacked in the z-direction, a second layer (118D) on the first layer (116D), and a third layer (119D) on the second layer (118D).

[0105] Each of the multiple dams (DAM) may include multiple organic insulating layers. For example, the first layer (116D) may be formed simultaneously with the same material when the second insulating layer (116) is formed in the display area (DA). The second layer (118D) may be formed simultaneously with the same material when the third insulating layer (118) is formed in the display area (DA). The third layer (119D) may be formed simultaneously with the same material when the spacer (SPC) is formed in the display area (DA).

[0106] Referring to FIG. 5, as illustrated in FIG. 3, a driving voltage supply line (11) may be placed in a peripheral area (PA) below the display area (DA). The driving voltage supply line (11) may be placed in a first sub-peripheral area (SPA1) and a second sub-peripheral area (SPA2). The driving voltage supply line (11) may be placed between the first insulating layer (115) and the second insulating layer (116) in the first sub-peripheral area (SPA1), and placed on top of the interlayer insulating layer (113) in the second sub-peripheral area (SPA2).

[0107] A plurality of holes (11H) may be defined in the driving voltage supply line (11) located in the first sub-peripheral area (SPA1). The holes (11H) can function as outgassing passages to release gas generated from the first insulating layer (115) to the outside, thereby preventing or reducing the problem of gas or moisture generated from the first insulating layer (115) penetrating into the display area (DA) and degrading the quality of the image implemented in the display device. The driving voltage supply line (11) may include the same material as one of the wires disposed between the first insulating layer (115) and the second insulating layer (116) in the display area (DA). For example, the driving voltage supply line (11) may include the same material as the data line (DL) disposed on the first insulating layer (115) of the display area (DA).

[0108] In the first sub-peripheral area (SPA1), at least one additional wiring may be provided that is disposed between the interlayer insulation layer (113) and the first insulation layer (115) and overlaps with the driving voltage supply line (11). The at least one wiring may include the same material as one of the wirings disposed between the interlayer insulation layer (113) and the first insulation layer (115) in the display area (DA). For example, the at least one wiring may include the same material as the driving voltage line (PL) disposed on the interlayer insulation layer (113) of the display area (DA).

[0109] A plurality of fan-out lines (FW) may be arranged in the peripheral area (PA) below the display area (DA). In one embodiment, as shown in FIG. 5, the fan-out lines (FW) may be arranged on different layers with at least one insulating layer in between. For example, a first fan-out line (FW1) above the first gate insulating layer (111) and a second fan-out line (FW2) above the second gate insulating layer (112) may be arranged alternately. Accordingly, the spacing between adjacent fan-out lines (FW) can be reduced. In another embodiment, the fan-out lines (FW) may be arranged on the same layer. For example, the fan-out lines (FW) may be arranged above the first gate insulating layer (111) or above the second gate insulating layer (112). The fan-out lines (FW) may be arranged in the first sub-peripheral area (SPA1) and the second sub-peripheral area (SPA2).

[0110] The first scan driving circuit (SDRV1) and the second scan driving circuit (SDRV2) can be placed in the first sub-peripheral area (SPA1).

[0111] The first inorganic encapsulation layer (310) and the second inorganic encapsulation layer (330) cover the first and second dams (DAM1, DAM2) and may be formed extending to the outside of the first and second dams (DAM1, DAM2). The position of the organic encapsulation layer (320) is limited by the first and second dams (DAM1, DAM2) so that the material for forming the organic encapsulation layer (320) may be prevented from overflowing to the outside of the first and second dams (DAM1, DAM2). An input sensing layer (not indicated) may be disposed on the thin film encapsulation layer (300) as described above. The input sensing layer may include a touch sensing layer (TSL). At this time, the touch sensing layer (TSL) may have a structure in which a first touch conductive layer (TCL1), a first touch insulating layer (TNS1), a second touch conductive layer (TCL2), and a second touch insulating layer (TNS2) are sequentially stacked. The touch sensing layer (TSL) may further include a touch buffer layer (TBF).

[0112] In some embodiments, the second touch conductive layer (TCL2) acts as a touch electrode that detects whether contact is made, and the first touch conductive layer (TCL1) can act as a connecting part that connects the patterned second touch conductive layer (TCL2) in one direction.

[0113] In some embodiments, both the first touch conductive layer (TCL1) and the second touch conductive layer (TCL2) can function as touch electrodes. For example, the first touch insulating layer (TNS1) includes a via hole that exposes the upper surface of the first touch conductive layer (TCL1), and the first touch conductive layer (TCL1) and the second touch conductive layer (TCL2) can be connected through the via hole. By using the first touch conductive layer (TCL1) and the second touch conductive layer (TCL2) in this manner, the resistance of the touch electrode is reduced, and the response speed of the touch sensing layer (TSL) can be improved.

[0114] In some embodiments, the touch electrode may be formed with a mesh structure to allow light emitted from the organic light-emitting elements (OLED1, OLED2, OLED3) to pass through. Accordingly, the first touch conductive layer (TCL1) and the second touch conductive layer (TCL2) may be arranged so as not to overlap with the light-emitting regions of the organic light-emitting elements (OLED1, OLED2, OLED3).

[0115] The first touch conductive layer (TCL1) and the second touch conductive layer (TCL2) may each be a single film or a multilayer film made of a conductive material with good conductivity. For example, the first touch conductive layer (TCL1) and the second touch conductive layer (TCL2) may be a single film or a multilayer film made of a conductive material including a transparent conductive layer, aluminum (Al), copper (Cu), molybdenum (Mo), and / or titanium (Ti). The transparent conductive layer may include a transparent conductive oxide such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc. Additionally, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, graphene, etc. In some embodiments, the first touch conductive layer (TCL1) may be provided with molybdenum (Mo), and the second touch conductive layer (TCL2) may be provided with a stacked structure of Ti / Al / Ti.

[0116] The first touch conductive layer (TCL1) or the second touch conductive layer (TCL2) as described above can be connected to a touch wiring (CNM) passing through a peripheral area (PA). At this time, the touch wiring (CNM) can be connected to a terminal portion (PAD) shown in FIG. 3.

[0117] The first touch insulating layer (TNS1) and the second touch insulating layer (TNS2) may each be provided with an inorganic or organic material. The inorganic material may be at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, or silicon oxynitride. The organic material may be at least one of acrylic resin, methacrylate resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

[0118] In one embodiment, the second touch insulating layer (TNS2) may be disposed over the entire display area (DA). In this case, a light-functional film, such as a color filter or a polarizing film, may be disposed on the second touch insulating layer (TNS2).

[0119] As another embodiment, a color filter may be disposed on the second touch insulating layer (TNS2), or a quantum dot layer, a light-transmitting layer, and a color filter may be disposed. For convenience of explanation, the following description will focus on the case where a quantum dot layer, a light-transmitting layer, and a color filter are disposed on the second touch insulating layer (TNS2).

[0120] The second touch insulating layer (TNS2) may be formed in a pattern shape. For example, the second touch insulating layer (TNS2) may be formed to completely shield the second touch conductive layer (TCL2). A high refractive index layer (700) may be disposed on the second touch insulating layer (TNS2) as described above. The high refractive index layer (700) may be disposed to cover the entire front surface of the display area (DA).

[0121] The second touch insulating layer (TNS2) and the high refractive index layer (700) may have different refractive indices. For example, the refractive index of the second touch insulating layer (TNS2) may be smaller than the refractive index of the high refractive index layer (700). Specifically, the refractive index of the second touch insulating layer (TNS2) may be about 1.3 to about 1.6, and the refractive index of the high refractive index layer (700) may be about 1.7 to about 1.9.

[0122] The high refractive index layer (700) may include an acrylic-based or siloxane-based organic material. In some embodiments, the high refractive index layer (700) may include polydiarylsiloxane, methyltrimethoxysilane, or tetramethoxysilane. In one embodiment, the high refractive index layer (700) may be formed by applying and curing using an inkjet printing process. In another embodiment, the high refractive index layer (700) may be formed by an evaporation process.

[0123] In one embodiment, the high refractive index layer (700) may have metal oxide particles dispersed therein, such as zinc oxide (ZnO), titanium oxide (TiO2), zirconium oxide (ZrO2), or barium titanate (BaTiO3). In one embodiment, the high refractive index layer (700) may be formed by applying an organic material containing metal oxide particles using an inkjet. A touch buffer layer (TBF) may be further provided between the thin film encapsulation layer (300) and the touch sensing layer (TSL). The touch buffer layer (TBF) may be formed directly on the upper surface of the thin film encapsulation layer (300). The touch buffer layer (TBF) may serve to prevent damage to the thin film encapsulation layer (300) and to block interference signals that may occur during the operation of the touch sensing layer (TSL). The touch buffer layer (TBF) may be silicon oxide (SiO2) or silicon nitride (SiN x It includes inorganic insulating materials such as silicon oxynitride (SiON), and can be provided as a single layer or multiple layers.

[0124] Although not illustrated in the drawing, a quantum dot layer and a light-transmitting layer may be disposed on the touch sensing layer (TSL) as described above, at positions corresponding to each pixel. For example, a second color quantum dot layer is disposed on the second light-emitting element located at the second pixel (PX2). That is, the second color quantum dot layer is located on the second pixel electrode of the second light-emitting element located at the second pixel (PX2). Accordingly, when viewed from a direction perpendicular to the substrate (100) (z-axis direction), the second color quantum dot layer overlaps with the second pixel electrode. The second color quantum dot layer can convert light of the first wavelength band generated from the intermediate layer (222) on the second pixel electrode into light of the second wavelength band.

[0125] A third color quantum dot layer is located on the third light-emitting element located in the third pixel (PX3). That is, the third color quantum dot layer is located on the upper portion of the third pixel electrode of the third light-emitting element located in the third pixel (PX3). Accordingly, when viewed from a direction perpendicular to the substrate (100) (z-axis direction), the third color quantum dot layer overlaps with the third pixel electrode. The third color quantum dot layer can convert light of the second wavelength band generated from the intermediate layer (222) on the third pixel electrode into light of the third wavelength band. At this time, the first wavelength band and the second wavelength band may be different from or the same as each other.

[0126] Each of the second color quantum dot layer and the third color quantum dot layer may have a form in which quantum dots are dispersed within a resin. In the present embodiment, the embodiments described below, and variations thereof, the quantum dots refer to crystals of a semiconductor compound and may include any material capable of emitting light of various emission wavelengths depending on the size of the crystals. The diameter of such quantum dots may be, for example, approximately 1 nm to 10 nm.

[0127] Quantum dots can be synthesized by wet chemical processes, organometallic chemical vapor deposition (MOCVD), molecular beam epitaxy, or similar processes. A wet chemical process is a method of growing quantum dot crystals after mixing an organic solvent and a precursor material. In the case of wet chemical processes, the organic solvent naturally acts as a dispersant coordinated to the surface of the quantum dot crystals during crystal growth and controls crystal growth, making it easier than vapor deposition methods such as Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). Furthermore, wet chemical processes are low-cost processes that allow for the control of quantum dot particle growth.

[0128] These quantum dots may include group III-VI semiconductor compounds, group II-VI semiconductor compounds, group III-V semiconductor compounds, group III-VI semiconductor compounds, group I-III-VI semiconductor compounds, group IV-VI semiconductor compounds, group IV elements or compounds, or any combination thereof.

[0129] Examples of group III-VI semiconductor compounds may include binary compounds such as In2S3, ternary compounds such as AgInS, AgInS2, CuInS, or CuInS2, or any combination thereof.

[0130] Examples of group II-VI semiconductor compounds include binary compounds such as CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, or MgS, or ternary compounds such as CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, or MgZnS, or compounds such as CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, or HgZnSTe. It may include four-element compounds or any combination thereof.

[0131] Examples of III-V semiconductor compounds may include binary compounds such as GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, or InSb; ternary compounds such as GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb, or GaAlNP; quaternary compounds such as GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, or InAlPSb; or any combination thereof. Meanwhile, III-V semiconductor compounds may further include a Group II element. Examples of III-V semiconductor compounds containing additional group II elements may include InZnP, InGaZnP, or InAlZnP.

[0132] Examples of group III-VI semiconductor compounds may include binary compounds such as GaS, GaSe, Ga2Se3, GaTe, InS, InSe, In2Se3, or InTe, ternary compounds such as InGaS3 or InGaSe3, or any combination thereof.

[0133] Examples of group I-III-VI semiconductor compounds may include ternary compounds such as AgInS, AgInS2, CuInS, CuInS2, CuGaO2, AgGaO2, or AgAlO2, or any combination thereof.

[0134] Examples of group IV-VI semiconductor compounds may include binary compounds such as SnS, SnSe, SnTe, PbS, PbSe, or PbTe; ternary compounds such as SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, or SnPbTe; quaternary compounds such as SnPbSSe, SnPbSeTe, or SnPbSTe; or any combination thereof.

[0135] Group IV elements or compounds may include single-element compounds such as Si or Ge, binary compounds such as SiC or SiGe, or any combination thereof.

[0136] Each element contained in polyelement compounds, such as binary, ternary, and quaternary compounds, can exist within the particle at a uniform or non-uniform concentration.

[0137] Meanwhile, quantum dots can have a single structure in which the concentration of each element contained within the quantum dot is uniform, or a core-shell dual structure. For example, the material contained in the core and the material contained in the shell may be different from each other. The shell of the quantum dot can serve as a protective layer to maintain semiconductor properties by preventing chemical degradation of the core, and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell can be a single layer or a multilayer. The interface between the core and the shell may have a concentration gradient in which the concentration of elements present in the shell decreases towards the center.

[0138] Examples of the shell of a quantum dot include oxides of metals or nonmetals, semiconductor compounds, or combinations thereof. Examples of oxides of metals or nonmetals may include binary compounds such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, or NiO, ternary compounds such as MgAl2O4, CoFe2O4, NiFe2O4, or CoMn2O4, or any combination thereof. Examples of semiconductor compounds may include group III-VI semiconductor compounds, group II-VI semiconductor compounds, group III-V semiconductor compounds, group III-VI semiconductor compounds, group I-III-VI semiconductor compounds, group IV-VI semiconductor compounds, or any combination thereof as described above. For example, the semiconductor compound may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, or any combination thereof.

[0139] Quantum dots can have a full width of half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less, specifically about 40 nm or less, and more specifically about 30 nm or less, and color purity or color reproducibility can be improved in this range. In addition, since the light emitted through these quantum dots is emitted in all directions, the wide viewing angle can be improved.

[0140] In addition, the shape of the quantum dots can specifically be spherical, pyramidal, multi-arm, or cubic, and can be in the form of nanoparticles, nanotubes, nanowires, nanofibers, or nanoplate particles.

[0141] Since the energy band gap can be controlled by adjusting the size of the quantum dots, light of various wavelengths can be obtained from the quantum dot emissive layer. Therefore, by using quantum dots of different sizes, a light-emitting device that emits light of various wavelengths can be realized. Specifically, the size of the quantum dots can be selected to emit red, green, and / or blue light. Additionally, the size of the quantum dots can be configured to emit white light by combining light of various colors.

[0142] The second color quantum dot layer and the third color quantum dot layer may also include scatterers. Furthermore, any material that is transparent and has excellent dispersion properties for scatterers can be used as the resin included in the second color quantum dot layer and the third color quantum dot layer. For example, polymer resins such as acrylic resin, imide resin, or epoxy resin can be used as the resin included in the second color quantum dot layer (520) and the third color quantum dot layer (530).

[0143] The scattering material included in the second-color quantum dot layer and the third-color quantum dot layer may be a particle having a different refractive index from the transparent resin included in the second-color quantum dot layer and the third-color quantum dot layer, such as a light-scattering particle. The scattering material is not particularly limited as long as it is a material capable of partially scattering transmitted light by forming an optical interface between the scattering material and the transparent resin, such as a metal oxide particle or an organic particle. Examples of metal oxides for the scattering material include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of organic materials for the scattering material include acrylic resin or urethane resin. The scattering material can scatter light in various directions regardless of the angle of incidence without substantially changing the wavelength of the incident light. Through this, the scattering material can improve the side visibility of the display device. In addition, scatterers included in the second-color quantum dot layer and the third-color quantum dot layer can increase light conversion efficiency by increasing the probability that incident light incident on the second-color quantum dot layer and the third-color quantum dot layer meets the quantum dots.

[0144] In the first pixel (PX1), light of the first wavelength generated in the intermediate layer (222) is emitted externally without wavelength conversion. Therefore, the first pixel (PX1) does not have a quantum dot layer. Consequently, a light-transmitting layer formed of a light-transmitting resin is located on the first light-emitting element located in the first pixel (PX1). That is, the light-transmitting layer is located on the upper part of the first pixel electrode of the first light-emitting element located in the first pixel (PX1). Accordingly, when viewed from a direction perpendicular to the substrate (100) (z-axis direction), the light-transmitting layer (510) overlaps with the first pixel electrode.

[0145] The light-transmitting layer may also include a scatterer, and any resin containing the light-transmitting layer that is transparent and has excellent dispersion properties for scatterers can be used. For example, polymeric resins such as acrylic resins, imide resins, or epoxy resins can be used as the resin containing the light-transmitting layer.

[0146] The scattering material included in the light-transmitting layer may be a particle having a different refractive index from the light-transmitting resin included in the light-transmitting layer, such as a light-scattering particle. The scattering material is not particularly limited as long as it is a material capable of partially scattering transmitted light by forming an optical interface between the scattering material and the light-transmitting resin, such as a metal oxide particle or an organic particle. Examples of metal oxides for the scattering material include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of organic materials for the scattering material include acrylic resin or urethane resin. The scattering material can scatter light in various directions regardless of the angle of incidence without substantially changing the wavelength of the incident light (Lambertian reflection). Through this, the scattering material can improve the side visibility of the display device.

[0147] The light-transmitting layer, the second color quantum dot layer, and the third color quantum dot layer are positioned to correspond to the first pixel electrode, the second pixel electrode, and the third pixel electrode as described above. To this end, a bank layer having aperture regions corresponding to the first pixel electrode, the second pixel electrode, and the third pixel electrode may be disposed on the thin film encapsulation layer (300). That the aperture regions of the bank layer correspond to the first to third pixel electrodes means that when viewed from a direction perpendicular to the substrate (100) (z-axis direction), the aperture regions overlap with the first pixel electrode, the second pixel electrode, and the third pixel electrode. Such a bank layer may include various materials, for example, inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride. As another embodiment, the bank layer may include a photoresist material, which allows the bank layer to be easily formed through processes such as exposure and development.

[0148] A color filter may be disposed on the bank layer, the second color quantum dot layer, the third color quantum dot layer, and the light-transmitting layer as described above. At this time, the color filter may be disposed to correspond to each pixel. For example, a first color filter layer may be disposed to correspond to the first organic light-emitting element (OLED1), a second color filter layer may be disposed to correspond to the second organic light-emitting element (OLED2), and a color filter layer may be disposed to correspond to the third organic light-emitting element (OLED3).

[0149] The first color filter layer allows only light of wavelengths ranging from 450 nm to 495 nm to pass through, the second color filter layer allows only light of wavelengths ranging from 495 nm to 570 nm to pass through, and the third color filter layer allows only light of wavelengths ranging from 630 nm to 780 nm to pass through. The first to third color filter layers can serve to reduce external light reflection in a display device.

[0150] For example, when external light reaches the first color filter layer, only light of a preset wavelength as described above passes through the first color filter layer, while light of other wavelengths is absorbed by the first color filter layer. Therefore, among the external light incident on the display device, only light of a preset wavelength as described above passes through the first color filter layer, and a portion of it is reflected from the lower counter electrode (223) or the first pixel electrode and emitted outward. Consequently, since only a portion of the external light incident on the location where the first pixel (PX1) is situated is reflected outward, it can serve to reduce external light reflection. This explanation can also be applied to the second color filter layer and the third color filter layer.

[0151] In FIG. 5, the transistors of the pixel circuit are illustrated as P-type transistors, but the embodiments of the present invention are not limited thereto. For example, various embodiments are possible, such as the transistors of the pixel circuit being N-type transistors, or some being P-type transistors and others being N-type transistors.

[0152] The above-described display panel (20) may include a control groove. This control groove can control the position of at least one end of the organic encapsulation layer (320) and the high-refractive index layer (700). Specifically, the control groove may include a first control groove (CH1) positioned at the end of the organic encapsulation layer (320). The control groove may include a second control groove (CH2) positioned at the end of the high-refractive index layer (700).

[0153] The first control groove (CH1) described above can be placed in various locations. For example, the first control groove (CH1) can be placed between the dam (DAM) and the third organic light-emitting element (OLED3). As another embodiment, if there are multiple dams (DAM), the first control groove (CH1) may also be placed between multiple dams (DAM). As yet another embodiment, the first control groove (CH1) may be placed on the outer edge of the dam (DAM). In this case, the first control groove (CH1), the dam (DAM), and the third organic light-emitting element (OLED3) may be sequentially arranged in the x-axis direction based on FIG. 5.

[0154] The second control groove (CH2) can be placed in various locations. For example, the second control groove (CH2) can be placed on the first touch insulating layer (TNS1). As another embodiment, the second control groove (CH2) can also be placed on the touch wiring (CNM).

[0155] The first control groove (CH1) as described above can restrict the flow of the organic encapsulation layer (320). For example, the organic encapsulation layer (320) can be formed by supplying an organic material on the first inorganic encapsulation layer (310) using an inkjet method. At this time, the organic encapsulation layer (320) can flow on one side of the first inorganic encapsulation layer (310). In this case, if the organic encapsulation layer (320) moves too widely, a maximum point (320-2) and a minimum point (320-1) of the organic encapsulation layer (320) may occur near the end of the organic encapsulation layer (320), where the height measured from the bottom surface of the substrate (100) to the top surface of the organic encapsulation layer (320) is the highest. At this time, if there is a difference between the height of the lowest point (320-1) of the organic bag layer (320) and the height of the flat surface of the organic bag layer (320), a problem may occur in which the lowest point (320-1) of the organic bag layer (320) is visible. At this time, the plurality of first control grooves (CH1) as described above can prevent such a problem from occurring by obstructing the flow of the organic bag layer (320).

[0156] Specifically, when an organic encapsulation layer (320) in which a plurality of first control grooves (CH1) are arranged flows and comes into contact with the edges of the plurality of first control grooves (CH1), the movement of the organic encapsulation layer (320) may be obstructed. That is, each first control groove (CH1) can obstruct the movement of the organic encapsulation layer (320) by making the surface contact angle of the organic encapsulation layer (320) larger than in the case where there are no first control grooves (CH1). In this case, it is possible to form the height of the highest point (320-2) of the organic encapsulation layer (320) (measured from the lower surface of the substrate to the upper surface of the organic encapsulation layer) higher than in the case where there are no first control grooves (CH1), so the height of the lowest point (320-1) of the organic encapsulation layer (320) can be maintained higher than before. Through this, it is possible to make the height of the lowest point (320-1) of the organic bag layer (320) and the height of the flat part of the organic bag layer (320) almost the same.

[0157] In the above case, when the first control groove (CH1) is provided, the distance from a certain reference point to the end of the organic bag layer (320) can be reduced by approximately 10% compared to when the first control groove (CH1) is not provided.

[0158] The same principle as above can be applied to the second control groove (CH2). That is, the second control groove (CH2) can hinder the movement of the high refractive index layer (700) at the end of the high refractive index layer (700) when the high refractive index layer (700) is formed. Through this, the highest point of the high refractive index layer (700), which is the maximum height among the heights from the bottom surface of the substrate (100) to the top surface of the high refractive index layer (700) measured in a direction perpendicular to the bottom surface of the substrate (100) (e.g., the z-axis direction in FIG. 5), can be maintained at the highest possible height. In addition, it is possible to maintain the lowest point of the high refractive index layer (700), which is the lowest height among the heights from the bottom surface of the substrate (100) to the top surface of the high refractive index layer (700), at the same or nearly the same height as the flat top surface of the high refractive index layer (700).

[0159] The maximum length inside at least one of the first control groove (CH1) and second control groove (CH2) as described above may be approximately 100 μm or less. In this case, the length may refer to the length of a straight line connecting two points placed on the edge of at least one of the first control groove (CH1) and second control groove (CH2) that passes through the center of the planar shape.

[0160] The first control groove (CH1) and the second control groove (CH2) as described above can be formed in an intaglio shape.

[0161] Below, the first control home (CH1) and the second control home (CH2) will be explained in detail.

[0162] FIGS. 6a to 6e are schematic plan views showing the first control groove illustrated in FIG. 5. FIGS. 6a to 6e are enlarged plan views showing parts C and D of FIG. 5.

[0163] Referring to FIGS. 6a through 6e, the planar shape of the first control groove (CH1) may be of various forms. For example, the planar shape of the first control groove (CH1) may be a circle as shown in FIG. 6a. In another embodiment, the planar shape of the first control groove (CH1) may be a triangle as shown in FIG. 6b. In yet another embodiment, the planar shape of the first control groove (CH1) may be an ellipse as shown in FIG. 6c. In yet another embodiment, the planar shape of the first control groove (CH1) may be a polygon of square or larger shape as shown in FIG. 6d. In yet another embodiment, although not shown in the drawings, the planar shape of the first control groove (CH1) may include part of a circle, part of an ellipse, and / or part of a polygon. In yet another embodiment, the planar shape of the first control groove (CH1) may have an irregular shape, such as a star shape or a cross shape.

[0164] A plurality of first control grooves (CH1) as described above may be provided, and the plurality of first control grooves (CH1) may be arranged to be spaced apart from each other in a first direction (e.g., one of the x-axis direction or the y-axis direction in FIG. 6a) and a second direction (e.g., the other of the x-axis direction or the y-axis direction in FIG. 6a). At this time, the plurality of first control grooves (CH1) may be arranged to surround the edge of the organic encapsulation layer (320). For example, the plurality of first control grooves (CH1) may be arranged on the outer edge of the edge of the display area (DA) of the display panel (20) shown in FIG. 3 or on the edge of the display area (DA). In this case, the organic encapsulation layer (320) may be arranged to completely shield the display area (DA) of the display panel (20) shown in FIG. 3. At this time, at least some of the plurality of first control grooves (CH1) may be arranged to be covered by the organic encapsulation layer (320). For example, a plurality of first control grooves (CH1) may each be placed on a plurality of lines that form a closed loop while encircling the perimeter of the display area (DA). In this case, some of the plurality of first control grooves (CH1) may be placed spaced apart from each other along one of the plurality of lines to surround the outer edge of the display area (DA). Additionally, other parts of the plurality of second control grooves (CH2) may be placed spaced apart from each other along another of the plurality of lines. In this case, the other of the plurality of lines may be placed on the outer edge of one of the plurality of lines. For convenience of explanation, the following description will focus on the case where there are four of the plurality of lines.

[0165] In the above case, the planar shape of the first control groove (CH1) placed on different lines may differ from one another. For example, the first control groove (CH1) placed on the innermost first line among the multiple lines and the first control groove (CH1) placed on the outer side of the first line among the multiple lines may be triangular in shape as shown in FIG. 6d. The first control groove (CH1) placed on the third line, which is the outer side of the second line among the multiple lines, may be pentagonal in shape. In addition, the first control groove (CH1) placed on the outermost fourth line among the multiple lines may be circular in shape. That is, the planar shape of the first control groove (CH1) placed on each of the multiple lines may become closer to a circle as it moves further away from the display area (DA). Through this, it is possible to precisely control the position of the end of the organic encapsulation layer (320).

[0166] Meanwhile, referring to FIG. 6e, the first control grooves (CH1) placed on each line may be arranged in a zigzag shape in a second direction (e.g., the x-axis direction or the y-axis direction). For example, a plurality of first control grooves (CH1) placed on the side of the display area (DA) may be arranged in a zigzag shape (or serpentine shape) in the x-axis direction based on FIG. 6a to 6d, so that the first control grooves (CH1) placed on adjacent and different lines may not be placed on a straight line parallel to the x-axis direction. Specifically, the first control groove (CH1) placed on the first line and the second control groove (CH2) placed on the second line may be placed at different positions in the y-axis direction relative to the origin of the coordinate axes. In addition, the first control groove (CH1) placed on the third line and the first control groove (CH1) placed on the fourth line may also be placed at different positions in the y-axis direction relative to the origin of the coordinate axes. In this case, the first control groove (CH1) placed in the first and third lines can form a straight line parallel to the x-axis, and the first control groove (CH1) placed in the second and fourth lines can also form a straight line parallel to the x-axis. As another embodiment, it is also possible for the first control grooves (CH1) placed in each of the first, second, third, and fourth lines to be arranged diagonally. In this case, the first control grooves (CH1) placed in each line can be placed on different straight lines parallel to the x-axis.

[0167] FIGS. 7a to 7d are cross-sectional views schematically showing the first control groove illustrated in FIG. 5. FIGS. 7a to 7d are cross-sectional views showing an enlarged view of section C of FIG. 5.

[0168] Referring to FIGS. 7a through 7d, the first control groove (CH1) may be disposed on the third insulating layer (118). At this time, the first control groove (CH1) may have various shapes and various depths in the depth direction. Specifically, the first control groove (CH1) may be formed in at least a part of the first inorganic sealing layer (310) as shown in FIG. 7a. In this case, the first control groove (CH1) may have a shape that is drawn in from one side of the first inorganic sealing layer (310) in the thickness direction of the first inorganic sealing layer (310) (for example, the z-axis direction in FIG. 7a). In this case, some of the plurality of first control grooves (CH1) may have a part of the organic sealing layer (320) inserted into them.

[0169] The first control groove (CH1) may also be formed in the first inorganic sealing layer (310) and the third insulating layer (118) as shown in FIG. 7b. In this case, the first control groove (CH1) may be formed to completely penetrate the first inorganic sealing layer (310). For example, the first control groove (CH1) may include a first-1 portion (CH1-1) disposed in the first inorganic sealing layer (310) and a first-2 portion (CH1-2) disposed in the third insulating layer (118).

[0170] The cross-sectional shape of the first control groove (CH1) can be formed in various shapes. For example, the cross-sectional shape of the first control groove (CH1) may be U-shaped, as shown in FIG. 7a and 7b. As another embodiment, the cross-sectional shape of the first control groove (CH1) may be trapezoidal, as shown in FIG. 7c. In this case, the inner surface of the first control groove (CH1) may be formed at an angle. As yet another embodiment, the cross-sectional shape of the first control groove (CH1) may be formed with a step, as shown in FIG. 7d. In this case, the side surface of the first control groove (CH1) formed in the x-axis direction may be flat, and the side surface formed in the z-axis direction may be angled or straight. Additionally, the portion connecting the side surface of the first control groove (CH1) formed in the x-axis direction and the side surface formed in the z-axis direction may be formed at a pointed or rounded shape, as shown in FIG. 7d.

[0171] In the above case, when the side of the first control groove (CH1) is formed with a step, the planar shape of the first control groove (CH1) may be smaller than the same shape. For example, if the planar shape of the first control groove (CH1) is circular, the first circle with the largest diameter becomes the planar shape of the uppermost surface of the first control groove (CH1), and the second circle positioned below the first circle in the depth direction (e.g., opposite direction of the z-axis) from the upper surface of the first control groove (CH1) may have a smaller diameter than the first circle. This relationship continues in the depth direction of the first control groove (CH1), thereby allowing the side of the first control groove (CH1) to be formed with a step. As another embodiment, it is also possible for the planar shape of the upper surface of the first control groove (CH1) and the planar shape of the flat surface positioned in the depth direction of the first control groove (CH1) to be different. Specifically, the planar shape of the upper surface of the first control groove (CH1) is a circle, and the planar shape of the flat surface located below the upper surface of the first control groove (CH1) in the depth direction of the first control groove (CH1) may be a polygon, an ellipse, or an irregular shape.

[0172] FIGS. 8A and 8B are cross-sectional views schematically showing the second control groove illustrated in FIG. 5. Here, FIGS. 8A and 8B are cross-sectional views showing an enlarged view of section D of FIG. 5.

[0173] Referring to FIG. 8a and FIG. 8b, the second control groove (CH2) may be placed on the first touch insulating layer (TNS1) as shown in FIG. 8a. In another embodiment, the second control groove (CH2) may be placed on the second touch insulating layer (TNS2) as shown in FIG. 8b.

[0174] The second control groove (CH2) as described above may be arranged in the same or similar manner as the first control groove (CH1) shown in FIGS. 6a to 6d when viewed in a planar view. Additionally, the second control groove (CH2) may have a cross-sectional shape identical or similar to the first control groove (CH1) described in FIGS. 7a to 7c.

[0175] In the above case, the second control groove (CH2) can control the position of the end of the high-refractive index layer (700). Specifically, the high-refractive index layer (700) can be placed on the front of the display area (DA). At this time, the high-refractive index layer (700) can be supplied via an inkjet method similar to the organic encapsulation layer (320). In this case, the high-refractive index layer (700) can flow on the first touch insulating layer (TNS1) and the second touch insulating layer (TNS2), and the boundary may not be clearly defined.

[0176] However, when the second control groove (CH2) is arranged as described above, the position of the end of the high-refractive index layer (700) can be determined to some extent by the second control groove (CH2). In particular, in such a case, the second control groove (CH2) can control the flow of the high-refractive index layer (700) through a principle similar to the principle of controlling the end of the organic encapsulation layer (320) through the first control groove (CH1).

[0177] In this case, the highest point (710) of the high-refractive index layer (700) can be positioned at a higher location compared to the case where the second control groove (CH2) does not exist. Additionally, the lowest point (720) of the high-refractive index layer (700) can be positioned at a higher location than the case where the second control groove (CH2) does not exist.

[0178] In this case, after manufacturing the display panel (20), the stripes, etc., can be prevented from being visible from the outside due to the lowest point (720) of the high refractive index layer (700).

[0179] FIG. 9 is a cross-sectional view schematically showing a display device according to one embodiment of the present invention.

[0180] Referring to FIG. 9, the peripheral area (PA) may correspond to a part of the left or right side of the display area (DA) illustrated in FIG. 3. The first scan driving circuit (SDRV1) includes second thin-film transistors (TFT2) and may include wiring (not shown) connected to the second thin-film transistors (TFT2). The second thin-film transistor (TFT2) may be formed by the same process as the first thin-film transistor (TFT1) of the pixel circuit (PC), and therefore, a detailed description of the second thin-film transistor (TFT2) is omitted. Although not illustrated, a control signal line for applying a control signal to the first scan driving circuit (SDRV1) may be further disposed in the first sub-peripheral area (SPA1). The control signal line may include signal lines for applying a clock signal, an inverted clock signal, a carry signal, etc. The control signal line can be placed on the same layer as the semiconductor layer (ACT), the gate electrode (GE), the upper electrode (CE2) of the capacitor (Cst), or the driving voltage line (PL).

[0181] As illustrated in FIG. 3, a common voltage supply line (13) may be placed in the left, right, and upper peripheral areas (PA) of the display area (DA). The common voltage supply line (13) may be placed in the first sub-peripheral area (SPA1) and the second sub-peripheral area (SPA2). The common voltage supply line (13) may be placed between the first insulating layer (115) and the second insulating layer (116) in the first sub-peripheral area (SPA1), and placed on top of the interlayer insulating layer (113) in the second sub-peripheral area (SPA2).

[0182] A plurality of holes (13H) may be defined in the common voltage supply line (13) located in the first sub-peripheral area (SPA1). The holes (13H) can function as outgassing passages to release gas generated from the first insulating layer (115) to the outside, thereby preventing or reducing the problem of gas or moisture generated from the first insulating layer (115) penetrating into the display area (DA) and degrading the quality of the image implemented in the display device. Although not illustrated, holes (13H) may also be defined in the common voltage supply line (13) located on the upper side of the substrate (100) in an area adjacent to the display area (DA). The common voltage supply line (13) may include the same material as one of the wires placed between the first insulating layer (115) and the second insulating layer (116) in the display area (DA). For example, the common voltage supply line (13) may include the same material as the data line (DL) disposed on the first insulating layer (115) of the display area (DA). The common voltage supply line (13) may be disposed on the same layer as the driving voltage supply line (11) and may include the same material as the driving voltage supply line (11). The driving voltage supply line (11) and the common voltage supply line (13) may be provided on the same layer spaced apart from each other.

[0183] In the second sub-peripheral area (SPA2), a voltage line (17) may be further disposed between the common voltage supply line (13) and the interlayer insulation layer (113). A portion of the common voltage supply line (13) located in the second sub-peripheral area (SPA2) may overlap with the voltage line (17) and may be in direct contact with the voltage line (17). The voltage line (17) may contain the same material as one of the wires disposed between the interlayer insulation layer (113) and the first insulation layer (115) in the display area (DA). For example, the voltage line (17) may contain the same material as the driving voltage line (PL) disposed on the interlayer insulation layer (113) of the display area (DA). The common voltage supply line (13) may transmit the common voltage (ELVSS) applied from the voltage line (17) to the pixel electrode (221) through the auxiliary line (19).

[0184] The auxiliary line (19) may be placed in the first sub-peripheral area (SPA1) and the second sub-peripheral area (SPA2). The auxiliary line (19) may be located on the second insulating layer (116) in the first sub-peripheral area (SPA1) and on the common voltage supply line (13) in the second sub-peripheral area (SPA2). A portion of the auxiliary line (19) located in the first sub-peripheral area (SPA1) may be connected to the opposing electrode (223). For example, the opposing electrode (223) may make direct contact with the auxiliary line (19) exposed by a hole defined in the third insulating layer (118) located in the first sub-peripheral area (SPA1). In the second sub-peripheral area (SPA2), a portion of the auxiliary line (19) may overlap with the common voltage supply line (13) and make direct contact with the common voltage supply line (13). In the second sub-periphery area (SPA2), a portion of the auxiliary line (19) may be located between multiple layers constituting the dam of the dam portion (DAM). A hole (19H) that exposes a portion of the upper surface of the layer located below the auxiliary line (19) may be defined in the auxiliary line (19). The auxiliary line (19) may include the same material as one of the wires disposed between the second insulating layer (116) and the third insulating layer (118) in the display area (DA). For example, the auxiliary line (19) may include the same material as the pixel electrode (221) disposed on the second insulating layer (116) in the display area (DA).

[0185] The driving voltage supply line (11) and the common voltage supply line (13) may be located on top of the inorganic layer. For example, the driving voltage supply line (11) and the common voltage supply line (13) may be placed on top of an inorganic insulating layer comprising at least one of a buffer layer (110), a first gate insulating layer (111), a second gate insulating layer (112), and an interlayer insulating layer (113).

[0186] When forming the organic encapsulation layer (320), it is necessary to limit the material for forming the organic encapsulation layer (320) to be located within a pre-set area. To this end, a dam portion (DAM) including at least one dam may be provided in the surrounding area (PA). The dam portion (DAM) may be provided in the form of a line surrounding the display area (DA). That is, the dam portion (DAM) forms a closed loop, and the display area (DA) may be placed inside the dam portion (DAM) on a plane. FIG. 9 illustrates two first and second dams (DAM1, DAM2). The number of dams in the dam portion (DAM) may vary. The first and second dams (DAM1, DAM2) may be placed between the display area (DA) of the substrate (100) and the terminal portion (PAD, FIG. 3). The first and second dams (DAM1, DAM2) may be located on top of the inorganic layer. For example, the first and second dams (DAM1, DAM2) may be placed on top of an inorganic insulating layer comprising at least one of a buffer layer (110), a first gate insulating layer (111), a second gate insulating layer (112), and an interlayer insulating layer (113).

[0187] A first dam (DAM1) may be provided in the second sub-peripheral area (SPA2). In the second sub-peripheral area (SPA2), a second dam (DAM2) may be further provided between the first dam (DAM1) and the first sub-peripheral area (SPA1), which is relatively closer to the indication area (DA) than the first dam (DAM1).

[0188] The first inorganic sealing layer (310) and the second inorganic sealing layer (330) cover the first and second dams (DAM1, DAM2) and can be formed up to the outside of the first and second dams (DAM1, DAM2). The organic sealing layer (320) is positioned by the first and second dams (DAM1, DAM2) so that the material for forming the organic sealing layer (320) can be prevented from overflowing to the outside of the first and second dams (DAM1, DAM2).

[0189] At least a portion of the first and second dams (DAM1, DAM2) may be positioned above power supply lines, such as a driving voltage supply line (11) and / or a common voltage supply line (13). The first and second dams (DAM1, DAM2) may be positioned extending in the x-direction into the second sub-periphery area (SPA2) from the lower side of the display area (DA). The first and second dams (DAM1, DAM2) may be positioned extending in the y-direction into the second sub-periphery area (SPA2) from the left and right sides of the display area (DA). Although not illustrated, the first and second dams (DAM1, DAM2) may be positioned extending in the x-direction into the second sub-periphery area (SPA2) from the upper side of the display area (DA).

[0190] Each of the multiple dams (DAMs) may have a multilayer structure comprising multiple layers. In order for the dams (DAMs) to function as positioning devices for the organic encapsulation layer, it is preferable that the height of the first dam (DAM1) located at the outermost edge be relatively higher than that of the second dam (DAM2). A greater number of layers may be included so that the height of the first dam (DAM1) located at the outermost edge from the display area (DA) is higher than that of the second dam (DAM2). For example, the second dam (DAM2) may each include two layers: a first layer (116D), which is the lowest layer stacked in the direction away from the upper surface of the substrate (100), i.e., the z-direction, and a second layer (118D) on the first layer (116D). The first dam (DAM1) may include three layers, a first layer (116D) which is the lowest layer stacked in the z-direction, a second layer (118D) on the first layer (116D), and a third layer (119D) on the second layer (118D).

[0191] Each of the multiple dams (DAM) may include multiple organic insulating layers. For example, the first layer (116D) may be formed simultaneously with the same material when the second insulating layer (116) is formed in the display area (DA). The second layer (118D) may be formed simultaneously with the same material when the third insulating layer (118) is formed in the display area (DA). The third layer (119D) may be formed simultaneously with the same material when the spacer (SPC) is formed in the display area (DA).

[0192] As illustrated in FIG. 9, an auxiliary line (19) may be positioned between the first layer (116D) and the second layer (118D) of the first and second dams (DAM1, DAM2) to cover the first layer (116D). A hole (19H) may be defined in the auxiliary line (19) to expose a portion of the upper surface of the first layer (116D). The hole (19H) may function as an outgassing passage to release gas generated from the first layer (116D) to the outside.

[0193] In the above case, the first control groove (CH1) and the second control groove (CH2) may be arranged. At this time, the first control groove (CH1) may be placed on the second insulating layer (116). As another embodiment, the first control groove (CH1) may also be placed on the third insulating layer (118) as shown in FIG. 5. However, for convenience of explanation, the following description will focus on the case where the first control groove (CH1) is placed on the second insulating layer (116).

[0194] Additionally, the second control groove (CH2) may be placed in at least one of the first touch insulating layer (TNS1) and the second touch insulating layer (TNS2).

[0195] The first control groove (CH1) and the second control groove (CH2) as described above can each control the position of the boundary between the organic encapsulation layer (320) and the high-refractive index layer (700). At this time, the second control groove (CH2) placed in the J region is identical or similar to that described in FIGS. 5 and FIGS. 8, so a detailed description will be omitted. Below, the first control groove (CH1) will be described in detail.

[0196] FIGS. 10a to 10c are cross-sectional views schematically showing the first control groove illustrated in FIG. 9. FIGS. 10a to 10c are cross-sectional views showing an enlarged view of section E of FIG. 9.

[0197] Referring to FIGS. 10a to 10c, the first control groove (CH1) can be arranged on a plane similar to that shown in FIGS. 6a to 6e.

[0198] In the above case, the first control groove (CH1) can be formed in the first inorganic sealing layer (310) as shown in FIG. 10a.

[0199] The first control groove (CH1) may be formed in the first inorganic sealing layer (310) and the auxiliary line (19) as shown in FIG. 10b. In this case, the first control groove (CH1) may be formed to completely penetrate the first inorganic sealing layer (310). Additionally, the first control groove (CH1) may be formed only in a part of the auxiliary line (19). As another embodiment, although not shown in the drawings, it is also possible for the first control groove (CH1) to be formed to penetrate both the first inorganic sealing layer (310) and the auxiliary line (19). In this case, the first control groove (CH1) may be formed only in the first inorganic sealing layer (310) and the auxiliary line (19). In this case, the first control groove (CH1) may include a first-1 portion (CH1-1) disposed in the first inorganic sealing layer (310) and a first-2 portion (CH1-2) disposed in the auxiliary line (19). Part 1-1 (CH1-1) and Part 1-2 (CH1-2) can be connected to each other to form a single first control groove (CH1).

[0200] In another embodiment, the first control groove (CH1) may be formed in the first inorganic sealing layer (310), the auxiliary line (19), and the second insulating layer (116), respectively, as shown in FIG. 10c. In this case, the first control groove (CH1) may include a first-1 portion (CH1-1) penetrating the first inorganic sealing layer (310), a first-2 portion (CH1-2) penetrating the auxiliary line (19), and a first-3 portion (CH1-3) formed in the second insulating layer (116). At this time, the first-1 portion (CH1-1), the first-2 portion (CH1-2), and the first-3 portion (CH1-3) may be connected to each other.

[0201] In the above case, the cross-sectional shape of the first control groove (CH1) may be of various forms. For example, the cross-sectional shape of the first control groove (CH1) may be U-shaped as shown in FIG. 10a to 10c, trapezoidal as shown in FIG. 7b, or stepped on the inner surface as shown in FIG. 7c.

[0202] FIG. 11a is a cross-sectional view schematically showing a display device according to another embodiment of the present invention. FIG.S. 11b to 11d are cross-sectional views schematically showing the first control groove illustrated in FIG. 11a. FIG.S. 11b to 11d are cross-sectional views showing an enlarged view of portion G of FIG. 11a.

[0203] Referring to FIGS. 11a to 11d, the display device (1) may include a display panel (20) and an input sensing layer (40). In this case, since the display panel (20) is identical or similar to that described in FIGS. 3 to 5 and FIG. 9, a detailed description will be omitted. In this case, a detailed description will focus on the differences from FIGS. 3 to 5 and FIG. 9.

[0204] Based on FIG. 3, the first control groove (CH1) positioned in the lower part of the display area (DA) can be positioned between the dam (DAM) and the third organic light-emitting element (OLED3), as shown in FIG. 11a. As another embodiment, the first control groove (CH1) may also be positioned between adjacent dams (DAM). For convenience of explanation, the following description will focus on the case where the first control groove (CH1) is positioned between the dam (DAM) and the third organic light-emitting element (OLED3).

[0205] The first control groove (CH1) may be positioned between the end of the third insulating layer (118) and the second dam (DAM2), as shown in FIG. 11a. In this case, the first control groove (CH1) may be positioned inside the groove formed by the second insulating layer (116), the third insulating layer (118), and the second dam (DAM2). Multiple first control grooves (CH1) may be provided so as to be spaced apart from each other.

[0206] The second control groove (CH2) can be placed in the touch wiring (CNM). At this time, a plurality of second control grooves (CH2) may be provided, and the plurality of second control grooves (CH2) may be arranged spaced apart from each other.

[0207] The first control groove (CH1) as described above can control the position of the end of the organic encapsulation layer (320). Additionally, the second control groove (CH2) can control the position of the end of the high-refractive index layer (700).

[0208] Referring to FIG. 11b, the first control groove (CH1) can be formed on the first inorganic sealing layer (310). At this time, the first control groove (CH1) can be formed by removing a part of the first inorganic sealing layer (310) or by removing the entire first inorganic sealing layer (310).

[0209] Referring to FIG. 11c, the first control groove (CH1) may include a first-1 portion (CH1-1) formed to penetrate the first inorganic sealing layer (310) and a first-2 portion (CH1-2) from which at least a portion of the driving voltage supply line (11) is removed. In this case, the first-1 portion (CH1-1) and the first-2 portion (CH1-2) may be connected to each other to form a single first control groove (CH1).

[0210] In the above case, it is also possible for the first-2 part (CH1-2) to be formed to completely penetrate the driving voltage supply line (11).

[0211] Referring to FIG. 11d, the first control groove (CH1) may include a first-1 portion (CH1-1) formed to penetrate the first inorganic sealing layer (310), a first-2 portion (CH1-2) formed to penetrate the driving voltage supply line (11), and a first-3 portion (CH1-3) in which at least a portion of the interlayer insulation layer (113) is removed. At this time, the first-1 portion (CH1-1), the first-2 portion (CH1-2), and the interlayer insulation layer (113) may be connected to each other.

[0212] In the above case, the first control groove (CH1) may have various planar shapes as shown in FIGS. 6a to 6e, and may have various cross-sectional shapes as shown in FIGS. 7a to 7d.

[0213] FIG. 12a is a cross-sectional view schematically showing a display device according to another embodiment of the present invention. FIG. 12b to 12d are cross-sectional views schematically showing the first control groove shown in FIG. 12a. FIG. 12b to 12d are cross-sectional views showing an enlarged view of part I of FIG. 12a.

[0214] Referring to FIGS. 12a to 12d, the display device (1) may include a display panel (20) and an input sensing layer (40). In this case, since the display panel (20) is identical or similar to that described in FIGS. 3 to 5 and FIG. 9, a detailed description will be omitted. In this case, a detailed description will focus on the differences from FIGS. 3 to 5 and FIG. 9.

[0215] Based on FIG. 3, the first control groove (CH1), which is positioned on either the side or top surface of the display area (DA), can be positioned between the dam (DAM) and the third organic light-emitting element (OLED3), as shown in FIG. 12a. At this time, the first control groove (CH1) can be positioned between the end of the third insulating layer (118) and the second dam (DAM2), as shown in FIG. 11a. In this case, the first control groove (CH1) can be positioned inside the groove formed by the second insulating layer (116), the third insulating layer (118), and the second dam (DAM2). A plurality of first control grooves (CH1) may be provided so as to be spaced apart from each other.

[0216] The second control groove (CH2) can be placed in the touch wiring (CNM). At this time, a plurality of second control grooves (CH2) may be provided, and the plurality of second control grooves (CH2) may be arranged spaced apart from each other.

[0217] The first control groove (CH1) as described above can control the position of the end of the organic encapsulation layer (320). Additionally, the second control groove (CH2) can control the position of the end of the high-refractive index layer (700).

[0218] Referring to FIG. 12b, the first control groove (CH1) can be placed in the first inorganic sealing layer (310). At this time, the first control groove (CH1) may be provided in multiple numbers and arranged to be spaced apart from each other.

[0219] Referring to FIG. 12c, the first control groove (CH1) may include a first-1 portion (CH1-1) placed on the first inorganic sealing layer (310) and a first-2 portion (CH1-2) placed on the auxiliary line (19).

[0220] Referring to FIG. 12d, the first control groove (CH1) may include a first-1 portion (CH1-1) placed on the first inorganic sealing layer (310), a first-2 portion (CH1-2) placed on the auxiliary line (19), and a first-3 portion (CH1-3) placed on the common voltage supply line (13).

[0221] In the above case, the first control groove (CH1) may have various planar shapes as shown in FIGS. 6a to 6e, and may have various cross-sectional shapes as shown in FIGS. 7a to 7d.

[0222] FIGS. 13a to 13c are cross-sectional views schematically showing the second control groove illustrated in FIGS. 11a and FIGS. 12a. FIGS. 13a to 13c are cross-sectional views showing enlarged portion H of FIG. 11a and portion J of FIG. 12a.

[0223] Referring to FIGS. 13a to 13c, the second control groove (CH2) may be placed on one of the first touch insulating layer (TNS1), the second touch insulating layer (TNS2), and the touch wiring (CNM). At this time, although not shown in the drawings, the touch wiring (CNM) may have a structure in which it is shielded by the second touch insulating layer (TNS2). For convenience of explanation, the following description will focus on the case where the second touch insulating layer (TNS2) is not placed on the touch wiring (CNM) and the second control groove (CH2) is formed on the touch wiring (CNM).

[0224] In the above case, the second control home (CH2) can be placed on the touch wiring (CNM) as shown in FIG. 13a.

[0225] As another embodiment, the second control home (CH2) may include a second-1 portion (CH2-1) disposed on the touch wiring (CNM) as shown in FIG. 13b and a second-2 portion (CH2-2) disposed on the touch buffer layer (TBF) disposed on the dam portion (DAM).

[0226] As another embodiment, the second control groove (CH2) may include a second-1 portion (CH2-1) disposed on the touch wiring (CNM) as shown in FIG. 13c, a second-2 portion (CH2-2) disposed on the touch buffer layer (TBF) disposed on the dam portion (DAM), and a second-3 portion (CH2-3) disposed on the first inorganic encapsulation layer (310).

[0227] The second control groove (CH2) as described above may have various planar shapes as shown in FIGS. 6a to 6e, and may have various cross-sectional shapes as shown in FIGS. 7a to 7d.

[0228] Through this, the second control home (CH2) can not only control the position of the end of the high-refractive index layer (700), but also position the lowest point (720) of the high-refractive index layer (700) at a higher position than the existing one by positioning the highest point (710) of the high-refractive index layer (700) at a higher position than the existing one.

[0229] FIGS. 14a and 14b are cross-sectional views schematically showing a display device according to another embodiment of the present invention. FIGS. 15a and 15b are cross-sectional views schematically showing a first control groove illustrated in FIGS. 14a and 14b. Here, FIGS. 15a and 15b are cross-sectional views showing enlarged portion K of FIG. 14a and portion M of FIG. 14b.

[0230] Referring to FIGS. 14a and 14b, the display panel (20) may additionally include a valley (VA) in addition to the dam portion (DAM) to define the position of the end of the organic encapsulation layer (320). In this case, the valley (VA) may form a closed loop similar to the dam portion (DAM) and may be arranged to surround the outer edge of the display area (DA). The valley dam portion includes a first valley dam (VADAM1) and a second valley dam (VADAM2) arranged spaced apart from each other, and a valley (VA) may be formed between the first valley dam (VADAM1) and the second valley dam (VADAM2).

[0231] In the above case, the first valley dam (VADAM1) and the second valley dam (VADAM2) can be formed simultaneously when the dam section (DAM) is formed. In this case, the first valley dam (VADAM1) and the second valley dam (VADAM2) may contain a material identical to at least one of the first layer (116D), second layer (118D), and third layer (119D) of the dam section (DAM). For convenience of explanation, the following description will focus on the case where the first valley dam (VADAM1) and the second valley dam (VADAM2) are made of the same material as the first layer (116D).

[0232] Although the above-mentioned valley (VA) is not shown in the drawing, it may be placed between the dam section (DAM) and the display area (DA). As another embodiment, the valley (VA) may also be placed between adjacent dam sections (DAM). However, for the convenience of explanation, the following description will focus on the case where the valley (VA) is placed on the outer edge of the dam section (DAM).

[0233] The first control groove (CH1) can be placed in various locations. For example, as described above, the first control groove (CH1) can be placed on the second insulating layer (116) or the third insulating layer (118), or between the dam section (DAM) and the display area (DA). In another embodiment, the first control groove (CH1) can be placed in the valley (VA) or in the valley dam (DAM). For convenience of explanation, the following description will focus on the case where the first control groove (CH1) is placed on the second valley dam (VADAM2).

[0234] Referring to FIG. 15a, the first control groove (CH1) may be placed on the first inorganic sealing layer (310) placed on the second valley dam (VADAM2). Referring to FIG. 15b as another embodiment, the first control groove (CH1) may include a first-1 portion (CH1-1) placed on the first inorganic sealing layer (310) placed on the second valley dam (VADAM2) and a first-2 portion (CH1-2) placed on the second valley dam (VADAM2).

[0235] The first control groove (CH1) as described above can control the position of the end of the organic encapsulation layer (320). In particular, while it is true that the valley (VA) and the dam (DAM) restrict the flow of the organic encapsulation layer (320) throughout the entire display area (DA), the valley (VA) and the dam (DAM) cannot raise the lowest point (320-1) of the height of the organic encapsulation layer (320), which may cause problems such as stripes to be visible after manufacturing the display panel (20). However, when a plurality of first control grooves (CH1) are arranged spaced apart from each other as described above, it is possible to effectively restrict the flow of the organic encapsulation layer (320) and maintain the lowest point (320-1) of the organic encapsulation layer (320) at a height almost similar to the flat part of the organic encapsulation layer (320).

[0236] Meanwhile, in the above case, a second control groove (CH2) may be formed to control the position of the end of the high-refractive index layer (700). At this time, the second control groove (CH2) may be placed on the touch wiring (CNM) or the first touch insulating layer (TNS1) as described above. In this case, the second control groove (CH2) placed in the L region of FIG. 14a and the second control groove (CH2) placed in the N region of FIG. 14b may have the same or similar shape as described in FIG. 5, FIG. 8a and FIG. 8b or FIG. 13a to FIG. 13b.

[0237] Accordingly, the display device (1) can prevent the lowest point of the height of at least one of the organic encapsulation layer (320) and the high refractive index layer (700) from becoming too low by limiting the position of at least one end of the organic encapsulation layer (320) and the high refractive index layer (700).

[0238] The display device (1) can not only provide a clear image but also reduce image distortion caused by external light by reducing stripes caused by external light.

[0239] As such, the present invention has been described with reference to an embodiment illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims. Explanation of the symbols

[0240] 1: Display device 10: Display panel 100: Substrate 11: Driving voltage supply line 13: Common voltage supply line 17: Voltage line 19: Auxiliary line 20: Display panel 300: Thin film encapsulation layer 3l0: First inorganic encapsulation layer 320: Organic bag layer 330: Second Inorganic Seal Layer 40: Input detection layer 50: Optical functional layer

Claims

Claim 1 A display device comprising: a substrate, a display substrate including a display element disposed on the substrate; and a sealing film including an inorganic sealing layer and an organic sealing layer disposed on the display substrate and shielding the display element, wherein the inorganic sealing layer has a control groove that controls the position of the end of the organic sealing layer, wherein the end of the organic sealing layer does not overlap with the control groove or the organic sealing layer overlaps only partially with the control groove, and the control groove is formed in a shape that is drawn in the thickness direction of the inorganic sealing layer from one surface of the inorganic sealing layer in contact with the organic sealing layer or is formed in a shape that penetrates the inorganic sealing layer in the thickness direction of the inorganic sealing layer. Claim 2 A display device according to claim 1, wherein the control groove is formed to penetrate the inorganic encapsulation layer and extends to the upper surface of at least one of the inorganic layer, organic layer, and metal layer of the display substrate disposed below the inorganic encapsulation layer. Claim 3 A display device according to claim 1, wherein the control grooves are provided in plurality, and the plurality of control grooves are arranged to be spaced apart from each other in a first direction and a second direction on a plane. Claim 4 A display device according to claim 1, further comprising a damper disposed on the display substrate. Claim 5 In claim 4, a display device wherein one of the control groove and the dam part is positioned inwardly from the other of the control groove and the dam part. Claim 6 A display device according to claim 1, wherein the planar shape of the control groove is one of a circle, an ellipse, or a polygon. Claim 7 In claim 1, the control grooves are provided in plurality, and the planar shape of some of the plurality of control grooves and the planar shape of other of the plurality of control grooves are different from each other in the display device. Claim 8 In claim 1, the control grooves are provided in plurality, and the sides of some of the plurality of control grooves and the sides of other parts of the plurality of control grooves are different from each other in the display device. Claim 9 In claim 1, the side of the control groove is a slanted display device. Claim 10 In claim 1, the side of the control groove is a stepped display device. Claim 11 A display device according to claim 1, wherein the maximum width of the control groove passing through the center of the control groove is 100 μm or less. Claim 12 In claim 1, the control groove is a display device formed in different layers in the depth direction. Claim 13 A display device comprising: a substrate including a display area and a peripheral area; a display element disposed on the display area of ​​the substrate; a sealing film disposed on the display element to shield the display element; a touch layer disposed on the sealing film and receiving an external signal; a refractive layer disposed on the touch layer and refracting light emitted from the display element; and a damper disposed on the peripheral area of ​​the substrate; wherein the upper surface of the touch layer is formed to be recessed in the thickness direction of the touch layer and has a control groove for controlling the position of the end of the refractive layer, wherein the end of the refractive layer does not overlap with the control groove or the refractive layer overlaps only partially with the control groove, and the control groove is disposed closer to the display area than to the damper. Claim 14 In claim 13, the control grooves are provided in plurality, and the plurality of control grooves are arranged to be spaced apart from each other in a first direction and a second direction on a plane. Claim 15 In claim 13, a display device wherein the planar shape of the control groove is one of a circle, an ellipse, or a polygon. Claim 16 In claim 13, the control grooves are provided in plurality, and the planar shape of some of the plurality of control grooves and the planar shape of other of the plurality of control grooves are different from each other in the display device. Claim 17 In claim 13, the control grooves are provided in plurality, and the sides of some of the plurality of control grooves and the sides of other of the plurality of control grooves are different from each other in the display device. Claim 18 In claim 13, the side of the control groove is a slanted display device. Claim 19 In claim 13, the side of the control groove is a stepped display device. Claim 20 A display device according to claim 13, wherein the maximum width of the control groove passing through the center of the control groove is 100 μm or less.

Images