Semiconductor package

Abstract

According to embodiments, a semiconductor package comprises a substrate including substrate pads on an upper surface; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and first bonding wires provided on the upper surface of the first semiconductor chip and connected to the substrate pads, wherein the first semiconductor chip comprises: a first lower signal pad; a second lower signal pad spaced apart from the first lower signal pad; and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad, and any one of the first bonding wires may be connected to the first lower signal pad and none of the first bonding wires may be provided on the upper surface of the second lower signal pad.

Description

Technology Field

[0001] The present invention relates to a semiconductor package, specifically a semiconductor package comprising stacked semiconductor chips. Background Technology

[0002] A semiconductor package is an integrated circuit chip implemented in a form suitable for use in electronic products. Typically, semiconductor packages involve mounting semiconductor chips on a printed circuit board and electrically connecting them using bonding wires or bumps. The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor package with improved operational reliability and electrical characteristics. means of solving the problem

[0004] According to embodiments of the present invention, a semiconductor package comprises a substrate including substrate pads on an upper surface; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and first bonding wires provided on the upper surface of the first semiconductor chip and connected to the substrate pads, wherein the first semiconductor chip comprises: a first lower signal pad; a second lower signal pad spaced apart from the first lower signal pad; and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad, and any one of the first bonding wires may be connected to the first lower signal pad and none of the first bonding wires may be provided on the upper surface of the second lower signal pad.

[0005] According to embodiments of the present invention, a semiconductor package comprises: a substrate having substrate pads on an upper surface; a first semiconductor chip disposed on the substrate and having a first lower signal pad, a second lower signal pad, and a lower redistribution pattern; a second semiconductor chip provided on the first semiconductor chip and having a first upper signal pad, a second upper signal pad, and an upper redistribution pattern; first bonding wires provided on the upper surface of the first semiconductor chip and connected to the substrate; and second bonding wires provided on the upper surface of the second semiconductor chip and connected to the substrate, wherein the lower redistribution pattern is electrically connected to the first lower signal pad and the second lower signal pad, and the upper redistribution pattern is electrically connected to the first upper signal pad and the second upper signal pad, and the first bonding wires are spaced apart from the second lower signal pad, and the second bonding wires may be spaced apart from the first upper signal pad.

[0006] According to embodiments of the present invention, a semiconductor package comprises a substrate including substrate pads on an upper surface, wherein the substrate pads include signal substrate pads and ground / power substrate pads; solder balls disposed on a lower surface of the substrate; a first semiconductor chip disposed on the upper surface of the substrate; a second semiconductor chip on the upper surface of the first semiconductor chip; first bonding wires provided on the upper surface of the first semiconductor chip and connected to the substrate; second bonding wires provided on the upper surface of the second semiconductor chip and connected to the substrate; and a molding film provided on the upper surface of the substrate and covering the first and second semiconductor chips, wherein the first semiconductor chip includes: a first lower signal pad; a second lower signal pad spaced apart from the first lower signal pad; a lower redistribution pattern connected to the first and second lower signal pads; and a first ground / power pad insulated from the first and second lower signal pads, and the second semiconductor chip includes: a first upper signal pad; A second upper signal pad spaced apart from the first upper signal pad; an upper rewiring pattern connected to the first and second upper signal pads; and a second ground / power pad insulated from the first and second upper signal pads, wherein the second bonding wires include a second signal bonding wire, the second signal bonding wire is connected to the second upper signal pad, and the second bonding wires may be spaced apart from the first upper signal pad. Effects of the invention

[0007] According to the present invention, a ground / power bonding wire may be provided between signal bonding wires. The signal bonding wires may not overlap perpendicularly with one another. Accordingly, the occurrence of crosstalk between the signal bonding wires can be prevented. The semiconductor package may exhibit improved operational reliability and electrical characteristics. Brief explanation of the drawing

[0008] FIG. 1a is a plan view illustrating a semiconductor package according to embodiments. FIG. 1b is a plan view illustrating the arrangement of a substrate, a first semiconductor chip, and a first bonding wire according to embodiments. FIG. 1c is a plan view illustrating the arrangement of a substrate, a second semiconductor chip, and a second bonding wire according to embodiments. Figure 1d is a cross-section taken along the line I-I' of Figure 1a. Figure 1e is a cross-section taken along the line II-II' of Figure 1a. Figure 1f is a cross-section taken along the line III-III' of Figure 1a. FIG. 2a is a plan view illustrating a semiconductor package according to embodiments. FIG. 2b is a plan view illustrating the arrangement of a substrate, a first semiconductor chip, and a first bonding wire according to embodiments. FIG. 2c is a plan view illustrating the arrangement of a substrate, a second semiconductor chip, and a second bonding wire according to embodiments. FIG. 3 is a perspective view illustrating a part of a semiconductor package according to embodiments. FIG. 4a is a plan view illustrating a semiconductor package according to embodiments. Figure 4b is a cross-section taken along A-A' of Figure 4a. Figure 4c is a cross-section taken along B-B' of Figure 4a. Figure 4d is a cross-section taken along C-C' of Figure 4a. FIG. 5a is a plan view illustrating a semiconductor package according to embodiments. Figure 5b is a cross-section cut along the line D-D' of Figure 5a. FIG. 5c is a plan view illustrating a semiconductor package according to embodiments. FIG. 6a is a plan view illustrating a first semiconductor chip according to embodiments. FIG. 6b is a plan view illustrating a semiconductor package according to embodiments. FIG. 6c is a plan view illustrating a semiconductor package according to embodiments. Specific details for implementing the invention

[0009] In this specification, the same reference numerals throughout the text may refer to the same components. A semiconductor package according to the concept of the present invention is described.

[0011] FIG. 1a is a plan view illustrating a semiconductor package according to embodiments. FIG. 1b is a plan view illustrating the arrangement of a substrate, a first semiconductor chip, and a first bonding wire according to embodiments. FIG. 1c is a plan view illustrating the arrangement of a substrate, a second semiconductor chip, and a second bonding wire according to embodiments. FIG. 1d is a cross-section cut along line I-I' of FIG. 1a. FIG. 1e is a cross-section cut along line II-II' of FIG. 1a. FIG. 1f is a cross-section cut along line III-III' of FIG. 1a.

[0012] In the plan views of FIGS. 1a to 1c, FIGS. 2a to 2c, FIGS. 4a, FIGS. 5a, FIGS. 5c, FIGS. 6b, and FIGS. 6c of the present invention, the bonding wires connected to each of the signal substrate pads (550S) are shown as being spaced apart from each other for distinction, but the bonding wires connected to the same signal substrate pad (550S) may overlap each other in a planar view. Likewise, the bonding wires connected to each of the ground / power substrate pads (550PG) are shown as being spaced apart from each other, but the bonding wires connected to the same signal substrate pad (550S) may overlap each other in a planar view.

[0013] Referring to FIGS. 1a through 1f, the semiconductor package may include a substrate (500), a first semiconductor chip (100), a second semiconductor chip (200), first bonding wires (WB1), and second bonding wires (WB2).

[0014] As shown in FIGS. 1a and 1d, the substrate (500) may include signal substrate pads (550S), ground / power substrate pads (550PG), lower substrate pads (510), and substrate wiring (530). For example, the substrate (500) may be a printed circuit board (PCB). The signal substrate pads (550S) and the ground / power substrate pads (550PG) may be provided on the upper surface of the substrate (500). The signal substrate pads (550S) may function as a channel for inputting and outputting data signals to the first semiconductor chip (100) or the second semiconductor chip (200). The ground / power substrate pads (550PG) may be spaced apart laterally from the signal substrate pads (550S). Any components spaced apart laterally from each other may include being spaced horizontally. Horizontal may mean parallel to the upper surface of the substrate (500). Ground / power board pads (550PG) may be electrically insulated from signal board pads (550S). At least one of the ground / power board pads (550PG) may be provided between the signal board pads (550S). The ground / power board pads (550PG) may function as a channel to transmit voltage to the first semiconductor chip (100) or the second semiconductor chip (200). The voltage may be a ground voltage or a power voltage. The signal board pads (550S) and the ground / power board pads (550PG) may be aligned along a second direction (D2) in a planar view. Being electrically connected to the board (500) may mean being electrically connected to either the signal board pad (550S) or the ground / power board pads (550PG). Being electrically connected to the two components includes the components being connected directly or indirectly through other conductive components.

[0015] Board wiring (530) is provided within the board (500) and can be connected to signal board pads (550S) and ground / power board pads (550PG). The board wiring (530) may include vias and wirings. Lower board pads (510) may be provided on the lower surface of the board (500). Lower board pads (510) may be electrically connected to signal board pads (550S) and / or ground / power board pads (550PG) through the board wiring (530). The signal board pads (550S), ground / power board pads (550PG), board wiring (530), and lower board pads (510) may include metals such as aluminum, copper, tungsten, and / or titanium.

[0016] The first direction (D1) may be parallel to the upper surface of the substrate (500). The second direction (D2) may be parallel to the upper surface of the substrate (500) and substantially perpendicular to the first direction (D1). The third direction (D3) may be substantially perpendicular to the upper surface of the substrate (500).

[0017] The semiconductor package may further include solder balls (600). The solder balls (600) may be provided on the lower surface of the substrate (500). For example, the solder balls (600) may be connected to the lower surfaces of the lower substrate pads (510). The solder balls (600) may include a metal such as a solder material. The solder material may include, for example, tin, silver, zinc, and / or an alloy thereof.

[0018] A first semiconductor chip (100) may be disposed on the upper surface of a substrate (500). The first semiconductor chip (100) may include, for example, a memory chip such as DRAM and NAND. As another example, the first semiconductor chip (100) may be, for example, a logic chip or a buffer chip.

[0019] As shown in FIG. 1b, the first semiconductor chip (100) may have a first side (101), a second side (102), and a third side. The second side (102) of the first semiconductor chip (100) may be opposite to the first side (101). The first side (101) and the second side (102) of the first semiconductor chip (100) may be aligned in a first direction (D1). The third side of the first semiconductor chip (100) may be adjacent to the first side (101) and the second side (102). The third side of the first semiconductor chip (100) may be aligned in a second direction (D2).

[0020] As shown in FIGS. 1b, 1d, 1e, and 1f, the first semiconductor chip (100) may include a first semiconductor substrate (110), a first redistribution layer (120), a first lower signal pad (150S1), a second lower signal pad (150S2), and first ground / power pads (150PG). The first semiconductor chip (100) may further include first integrated circuits, a first wiring layer, and first metal pads. The first semiconductor substrate (110) may be a first semiconductor die. The first semiconductor substrate (110) may include silicon or silicon-germanium. The first integrated circuits may be provided on the first semiconductor substrate (110). The first wiring layer may be provided on the first semiconductor substrate (110) and may be connected to the first integrated circuits. The first wiring layer may include at least one of a front-end layer (FEOL) and a back-end layer (BEOL). The first metal pads may include a first signal metal pad (115S) and first ground / power metal pads (115PG). The first signal metal pad (115S) and the first ground / power metal pads (115PG) may be provided on the first wiring layer. The first signal metal pad (115S) and the first ground / power metal pads (115PG) may be center pads. For example, the first signal metal pad (115S) and the first ground / power metal pads (115PG) may overlap with the center region of the first semiconductor chip (100) in a planar view. The first signal metal pad (115S) and the first ground / power metal pads (115PG) may be electrically connected to the first integrated circuits through the first metal wiring within the first wiring layer. That a component is electrically connected to a semiconductor chip may mean that it is electrically connected to the integrated circuits of the semiconductor chip. The first signal metal pad (115S) is spaced apart from the first ground / power metal pads (115PG) and may be electrically insulated.

[0021] A first redistribution layer (120) may be provided on the upper surface of a first semiconductor substrate (110). A first wiring layer may be provided between the first semiconductor substrate (110) and the first redistribution layer (120). The first redistribution layer (120) may include a first insulating layer and first redistribution patterns. The first insulating layer may be a single layer or a multilayer. The first insulating layer may include a photo-imageable dielectric (PID) material or an insulating polymer. As another example, the first redistribution layer (120) may be at least part of a back-end layer. In this case, the first insulating layer may include a silicon-based insulating material.

[0022] The first redistribution patterns may be provided within the first insulating layer. The first redistribution pattern may include a first lower signal redistribution pattern (135S1), first lower ground / power redistribution patterns (135PG1), and a second lower ground / power redistribution pattern (135PG2). The first lower signal redistribution pattern (135S1) may be horizontally spaced apart from the first and second lower ground / power redistribution patterns (135PG1, 135PG2) and may be insulated from the first and second lower ground / power redistribution patterns (135PG1, 135PG2). The first lower signal redistribution pattern (135S1), the first lower ground / power redistribution patterns (135PG1), and the second lower ground / power redistribution patterns (135PG2) may include a metal such as copper, tungsten, titanium, and / or an alloy thereof.

[0023] The first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG) may be provided on the upper surface of the first semiconductor chip (100). For example, the first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG) may be provided on the upper surface of the first redistribution layer (120). The upper surface of the first semiconductor chip (100) may include the upper surface of the first redistribution layer (120). The first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG) may be provided adjacent to the third side of the first semiconductor chip (100) in a planar view. The first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG) can be aligned along the second direction (D2) in a planar view.

[0024] A first lower signal pad (150S1) may be provided between a second lower signal pad (150S2) and a first side (101) of a first semiconductor chip (100). For example, each of the first lower signal pad (150S1) and the second lower signal pad (150S2) may be a DQ signal transmission pad. The first lower signal pad (150S1) and the second lower signal pad (150S2) may transmit data signals relatively quickly. For another example, each of the first lower signal pad (150S1) and the second lower signal pad (150S2) may be used as a transmission path for a DQ signal and other types of signals.

[0025] Each of the first ground / power pads (150PG) can function as a channel for transmitting the voltage of the first semiconductor chip (100). The voltage may be a ground voltage or a power voltage. The voltage applied to any one of the first ground / power pads (150PG) may be the same or different from the voltage applied to the other of the first ground / power pads (150PG). At least one of the first ground / power pads (150PG) may be provided between the first lower signal pad (150S1) and the second lower signal pad (150S2). The at least one first ground / power pad (150PG) may shield the occurrence of noise between the first lower signal pad (150S1) and the second lower signal pad (150S2). The noise may be crosstalk.

[0026] From a planar perspective, the first lower signal pad (150S1) may be provided between the first ground / power pads (150PG). For example, another of the first ground / power pads (150PG) may be provided between the first lower signal pad (150S1) and the first side (101) of the first semiconductor chip (100). Accordingly, the occurrence of crosstalk of the first lower signal pad (150S1) can be further prevented.

[0027] A second lower signal pad (150S2) may be provided between the first ground / power pads (150PG). For example, another of the first ground / power pads (150PG) may be provided between the second lower signal pad (150S2) and the second side (102) of the second semiconductor chip (200). Accordingly, the occurrence of crosstalk of the second lower signal pad (150S2) may be further prevented.

[0028] The first lower signal pad (150S1) and the second lower signal pad (150S2) can be connected to the first lower signal redistribution pattern (135S1). Each of the first lower signal pad (150S1) and the second lower signal pad (150S2) can be connected to the first signal metal pad (115S) through the first lower signal redistribution pattern (135S1). The first lower signal pad (150S1) can be electrically connected to the second lower signal pad (150S2) through the first lower signal redistribution pattern (135S1).

[0029] The first ground / power pads (150PG) may be electrically connected to the first ground / power metal pads (115PG) through the first lower ground / power redistribution patterns (135PG1). The first ground / power pads (150PG) may include a first sub-ground / power pad and a second sub-ground / power pad. The first sub-ground / power pad may be in direct contact with either of the first lower ground / power redistribution patterns (135PG1). The second sub-ground / power pad may not be in direct contact with the first lower ground / power redistribution patterns (135PG1). The second lower ground / power redistribution pattern (135PG2) may be electrically connected to the first sub-ground / power pad and the second sub-ground / power pad. The second sub-ground / power pad can be electrically connected to the first sub-ground / power pad through the first lower ground / power rewiring pattern (135PG1). The same voltage can be applied to the first sub-ground / power pad and the second sub-ground / power pad.

[0030] First bonding wires (WB1) may be provided on the upper surface of the first semiconductor chip (100). The first bonding wires (WB1) may include a first signal bonding wire (sWB1) and first ground / power bonding wires (pgWB1). The first ground / power bonding wires (pgWB1) may each be provided on the first ground / power pads (150PG). The first ground / power bonding wires (pgWB1) may be connected to the first ground / power pads (150PG) and the ground / power substrate pads (550PG), respectively. For example, the first ground / power bonding wires (pgWB1) may be in direct contact with the first ground / power pads (150PG). Accordingly, voltage can be transmitted to the first ground / power pads (150PG) through the first ground / power bonding wires (pgWB1). The voltage may be a ground voltage or a power voltage.

[0031] A first signal bonding wire (sWB1) may be provided on a first lower signal pad (150S1). The first signal bonding wire (sWB1) may be connected to the first lower signal pad (150S1) and the signal substrate pad (550S). Accordingly, the first semiconductor chip (100) may be electrically connected to the substrate (500) through the first signal bonding wire (sWB1). The first signal bonding wire (sWB1) may not be provided on a second lower signal pad (150S2). For example, the first signal bonding wire (sWB1) may be spaced apart from the second lower signal pad (150S2) and may not be in direct contact with the second lower signal pad (150S2). However, the second lower signal pad (150S2) can be electrically connected to the first lower signal pad (150S1) or the first signal bonding wire (sWB1) through the first lower signal rewiring pattern (135S1).

[0032] When multiple signal transmission bonding wires are arranged adjacent to each other, crosstalk may occur between the signal transmission bonding wires. According to embodiments, none of the first bonding wires (WB1) may be provided on the upper surface of the second lower signal pad (150S2). Accordingly, other signal bonding wires horizontally adjacent to the first signal bonding wire (sWB1) may not be provided. Crosstalk of the first signal bonding wire (sWB1) may be prevented. According to embodiments, the first signal bonding wire (sWB1) may be provided between the first ground / power bonding wires (pgWB1). For example, other signal bonding wires may not be provided between the first signal bonding wire (sWB1) and the first ground / power bonding wires (pgWB1). Crosstalk of the first signal bonding wire (sWB1) can be further prevented by the first ground / power bonding wires (pgWB1). The electrical characteristics and operational reliability of the semiconductor package can be improved.

[0033] Each of the first bonding wires (WB1) may be substantially parallel to the first direction (D1) in a planar view. The first bonding wires (WB1) may be spaced apart from each other in the second direction (D2). Accordingly, the occurrence of an electrical short circuit between the first bonding wires (WB1) can be prevented. The spacing distance between two adjacent first bonding wires (WB1) may be uniform. For example, the maximum spacing distance between two adjacent first bonding wires (WB1) and the minimum spacing distance between said two first bonding wires (WB1) may be relatively small. Or said maximum spacing distance and minimum spacing distance may be substantially the same. Accordingly, electrical interference and physical contact between the first bonding wires (WB1) can be further prevented.

[0034] A second semiconductor chip (200) may be placed on the upper surface of the first semiconductor chip (100). As shown in FIG. 1c, the second semiconductor chip (200) may have a first side wall (201), a second side wall (202), and a third side wall. The second side wall (202) of the second semiconductor chip (200) may be opposite to the first side wall (201). The first side wall (201) and the second side wall (202) of the second semiconductor chip (200) may be parallel to the first direction (D1). The third side wall of the second semiconductor chip (200) may be adjacent to the first side wall (201) and the second side wall (202). The third side wall of the second semiconductor chip (200) may be parallel to the second direction (D2). The second semiconductor chip (200) may be vertically aligned with the first semiconductor chip (100). For example, the first sidewall (201), the second sidewall (202), and the third sidewall of the second semiconductor chip (200) may be vertically aligned with the first side (101), the second side (102), and the second side (102), respectively, of the first semiconductor chip (100). In this specification, "vertical" may mean parallel to the third direction (D3).

[0035] The second semiconductor chip (200) may include a second semiconductor substrate (210), a second redistribution layer (220), a first upper signal pad (250S1), second upper signal pads (250S2), and second ground / power pads (250PG). The second semiconductor chip (200) may further include second integrated circuits, a second wiring layer, and second metal pads. The second semiconductor substrate (210) may include silicon or silicon-germanium. The second integrated circuits may be provided on the second semiconductor substrate (210). The second wiring layer may be provided on the second semiconductor substrate (210) and may be connected to the second integrated circuits. The second wiring layer may include at least one of a front-end layer and a back-end layer. The second metal pads may be provided on the upper surface of the second wiring layer. The second metal pads may include a second signal metal pad (215S) and second ground / power metal pads (215PG). The second signal metal pad (215S) and the second ground / power metal pads (215PG) may be center pads. For example, the second signal metal pad (215S) and the second ground / power metal pads (215PG) may be provided on the center region of the second semiconductor chip (200) in a planar view. The second signal metal pad (215S) and the second ground / power metal pads (215PG) may be electrically connected to the second integrated circuits through the second metal wiring within the second wiring layer. The second signal metal pad (215S) may be spaced apart from the second ground / power metal pads (215PG) and may be electrically insulated.

[0036] A second redistribution layer (220) may be provided on the upper surface of the second semiconductor substrate (210). For example, the second wiring layer may be provided between the second semiconductor substrate (210) and the second redistribution layer (220). The second redistribution layer (220) may include a second insulating layer and second redistribution patterns. The second insulating layer may be a single layer or a multilayer. The second insulating layer may include a photosensitive insulating (PID) material or an insulating polymer. As another example, the second redistribution layer (220) may be at least part of a back-end layer. In this case, the second insulating layer may include a silicon-based insulating material.

[0037] The second redistribution patterns may be provided within the second insulating layer. The second redistribution patterns may include a first upper signal redistribution pattern (235S1), first upper ground / power redistribution patterns (235PG1), and a second upper ground / power redistribution pattern (235PG2). The first upper signal redistribution pattern (235S1) may be horizontally spaced apart from the first and second upper ground / power redistribution patterns (235PG1, 235PG2) and may be insulated from the first and second upper ground / power redistribution patterns (235PG1, 235PG2). The first upper signal redistribution pattern (235S1), the first upper ground / power redistribution patterns (235PG1), and the second upper ground / power redistribution patterns (235PG2) may include a metal such as copper, tungsten, titanium, and / or an alloy thereof.

[0038] The first upper signal pad (250S1), the second upper signal pad (250S2), and the second ground / power pads (250PG) may be provided on the upper surface of the second semiconductor chip (200). For example, the first upper signal pad (250S1), the second upper signal pad (250S2), and the second ground / power pads (250PG) may be provided on the upper surface of the second redistribution layer (220). The upper surface of the second semiconductor chip (200) may include the upper surface of the second redistribution layer (220). The first upper signal pad (250S1), the second upper signal pad (250S2), and the second ground / power pads (250PG) may be provided adjacent to the third sidewall of the second semiconductor chip (200) in a planar view. The first upper signal pad (250S1), the second upper signal pad (250S2), and the second ground / power pads (250PG) may be aligned along the second direction (D2) in a planar view. The first upper signal pad (250S1) may be provided between the second upper signal pad (250S2) and the first sidewall (201) of the second semiconductor chip (200). In one example, the first upper signal pad (250S1) and the second upper signal pad (250S2) may each be a DQ signal. For example, the first upper signal pad (250S1) and the second upper signal pad (250S2) may be required to transmit data signals relatively quickly. In another example, the first upper signal pad (250S1) and the second upper signal pad (250S2) may each be used as a signal transmission path for a type of signal other than the DQ signal.

[0039] Each of the second ground / power pads (250PG) can function as a channel for transmitting the voltage of the second semiconductor chip (200). The voltage may be a ground voltage or a power voltage. The voltage applied to any one of the second ground / power pads (250PG) may be the same or different from the voltage applied to the other of the second ground / power pads (250PG). At least one of the second ground / power pads (250PG) may be provided between the first upper signal pad (250S1) and the second upper signal pad (250S2). The at least one second ground / power pad (250PG) can prevent interference of crosstalk between the first upper signal pad (250S1) and the second upper signal pad (250S2).

[0040] From a planar perspective, the first upper signal pad (250S1) may be provided between the second ground / power pads (250PG). For example, the other of the second ground / power pads (250PG) may be provided between the first upper signal pad (250S1) and the first sidewall (201) of the second semiconductor chip (200). Accordingly, the occurrence of crosstalk of the first upper signal pad (250S1) can be further prevented.

[0041] A second upper signal pad (250S2) may be provided between the second ground / power pads (250PG). For example, another of the second ground / power pads (250PG) may be provided between the second upper signal pad (250S2) and the second sidewall (202) of the second semiconductor chip (200). Accordingly, the occurrence of crosstalk of the second upper signal pad (250S2) can be further prevented.

[0042] The first upper signal redistribution pattern (235S1) can be connected to the first upper signal pad (250S1) and the second upper signal pad (250S2). The first upper signal pad (250S1) and the second upper signal pad (250S2) can be electrically connected to each other through the first upper signal redistribution pattern (235S1). Each of the first upper signal pad (250S1) and the second upper signal pad (250S2) can be connected to the first signal metal pad (115S) through the first upper signal redistribution pattern (235S1).

[0043] The second ground / power pads (250PG) may be electrically connected to the second ground / power metal pads (215PG) through the first upper ground / power redistribution patterns (235PG1). The second ground / power pads (250PG) may include a third sub-ground / power pad and a fourth sub-ground / power pad. The third sub-ground / power pad may be in contact with any one of the first upper ground / power redistribution patterns (235PG1). The third sub-ground / power pad may not be in direct contact with the first upper ground / power redistribution patterns (235PG1). The second upper ground / power redistribution pattern (235PG2) may be electrically connected to the third sub-ground / power pad and the fourth sub-ground / power pad. The fourth sub-ground / power pad can be electrically connected to the third sub-ground / power pad through the second upper ground / power rewiring pattern (235PG2). The same voltage can be applied to the third sub-ground / power pad and the fourth sub-ground / power pad.

[0044] The second semiconductor chip (200) may be a semiconductor chip of the same type as the first semiconductor chip (100). The second semiconductor chip (200) may have the same size and the same storage capacity as the first semiconductor chip (100). The second semiconductor chip (200) may include memory chips such as DRAM and NAND, for example. The components of the second semiconductor chip (200) may be substantially the same as the components of the first semiconductor chip (100). For example, as shown in FIG. 1a, the first upper signal pad (250S1), the second upper signal pad (250S2), and the second ground / power pads (250PG) may overlap with the first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG), respectively, from a planar perspective. The shape and arrangement of the first upper signal pad (250S1), the second upper signal pad (250S2), and the second ground / power pads (250PG) may be substantially the same as the shape and arrangement of the first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG). The electrical connection and function of the first upper signal pad (250S1), the second upper signal pad (250S2), and the second ground / power pads (250PG) may be the same or similar to the electrical connection and function of the first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG).

[0045] The shape and arrangement of the first upper signal redistribution pattern (235S1), the first upper ground / power redistribution patterns (235PG1), and the second upper ground / power redistribution patterns (235PG2) may be substantially the same as the shape and arrangement of the first lower signal redistribution pattern (135S1), the first lower ground / power redistribution patterns (135PG1), and the second lower ground / power redistribution pattern (135PG2). For example, in a planar view, the first upper signal redistribution pattern (235S1), the first upper ground / power redistribution patterns (235PG1), and the second upper ground / power redistribution pattern (235PG2) may overlap with the first lower signal redistribution pattern (135S1), the first lower ground / power redistribution patterns (135PG1), and the second lower ground / power redistribution pattern (135PG2), respectively. The functions and electrical connections of the first upper signal redistribution pattern (235S1), the first upper ground / power redistribution patterns (235PG1), and the second upper ground / power redistribution patterns (235PG2) may be the same or similar to the functions and electrical connections of the first lower signal redistribution pattern (135S1), the first lower ground / power redistribution patterns (135PG1), and the second lower ground / power redistribution pattern (135PG2).

[0046] The shape and arrangement of the second signal metal pad (215S) and the second ground / power metal pads (215PG) may be substantially the same as the shape and arrangement of the first signal metal pad (115S) and the first ground / power metal pads (115PG). For example, from a planar perspective, the second signal metal pad (215S) and the second ground / power metal pads (215PG) may overlap with the first signal metal pad (115S) and the first ground / power metal pads (115PG), respectively. The role of the second signal metal pad (215S) and the second ground / power metal pads (215PG) may be substantially the same as the role of the first signal metal pad (115S) and the first ground / power metal pads (115PG).

[0047] As another example, the second semiconductor chip (200) may be a logic chip or a buffer chip.

[0048] Second bonding wires (WB2) may be provided on the upper surface of the second semiconductor chip (200). The second bonding wires (WB2) may include a second signal bonding wire (sWB2) and second ground / power bonding wires (pgWB2). The second ground / power bonding wires (pgWB2) may each be provided on the second ground / power pads (250PG). The second ground / power bonding wires (pgWB2) may be connected to the second ground / power pads (250PG) and the ground / power substrate pads (550PG). Accordingly, voltage may be transmitted from the substrate (500) to the second ground / power pads (250PG) through the second ground / power bonding wires (pgWB2). The voltage may be a ground voltage or a power voltage. The second ground / power bonding wires (pgWB2) and the first ground / power bonding wires (pgWB1) may share ground / power board pads (550PG). For example, any one of the ground / power board pads (550PG) and any one of the second ground / power bonding wires (pgWB2) and any one of the first ground / power bonding wires (pgWB1) may be connected to the same one.

[0049] A second signal bonding wire (sWB2) may be provided on a second upper signal pad (250S2). The second signal bonding wire (sWB2) may be connected to the second upper signal pad (250S2) and the signal substrate pad (550S). A second semiconductor chip (200) may be electrically connected to a substrate (500) through the second signal bonding wire (sWB2). The second signal bonding wire (sWB2) may overlap with the second lower signal pad (150S2) in a planar view. The second signal bonding wire (sWB2) may be vertically spaced from the second lower signal pad (150S2). Since the first signal bonding wire (sWB1) is not provided on the upper surface of the second lower signal pad (150S2), the second signal bonding wire (sWB2) may not overlap vertically with the first signal bonding wire (sWB1) as in FIG. 1e. For example, the first bonding wires (BW1) may not be provided between the second signal bonding wire (sWB2) and the second lower signal pad (150S2). Accordingly, the occurrence of crosstalk between the first signal bonding wire (sWB1) and the second signal bonding wire (sWB2) can be prevented.

[0050] None of the second bonding wires (WB2) may be provided on the first upper signal pad (250S1). For example, the second signal bonding wire (sWB2) may not be provided on the first upper signal pad (250S1). The second signal bonding wire (sWB2) may be spaced apart from the upper surface of the first upper signal pad (250S1) and may not be in direct contact with the first upper signal pad (250S1). Accordingly, as shown in FIG. 1d, the first signal bonding wire (sWB1) may not overlap vertically with the second signal bonding wire (sWB2). The first signal bonding wire (sWB1) may not overlap vertically with any of the second bonding wires (WB2). The occurrence of crosstalk between the first signal bonding wire (sWB1) and the second signal bonding wire (sWB2) may be further prevented.

[0051] The first upper signal pad (250S1) can be electrically connected to the second lower signal pad (150S2) or the second signal bonding wire (sWB2) through the first upper signal rewiring pattern (235S1).

[0052] According to embodiments, a second signal bonding wire (sWB2) may be provided between the second ground / power bonding wires (pgWB2). For example, no other signal bonding wire may be provided between the second signal bonding wire (sWB2) and the second ground / power bonding wires (pgWB2). Accordingly, the occurrence of crosstalk of the second signal bonding wire (sWB2) can be further prevented. Electrical characteristics of the semiconductor package and movement Reliability can be improved.

[0053] Each of the second bonding wires (WB2) may be substantially parallel to the first direction (D1) in a planar view. Accordingly, the occurrence of an electrical short circuit between the second bonding wires (WB2) can be prevented. The spacing between two adjacent second bonding wires (WB2) may be uniform. For example, the difference between the maximum spacing between two adjacent second bonding wires (WB2) and the minimum spacing between the two second bonding wires (WB2) may be small. Or, the maximum spacing and the minimum spacing may be substantially the same. Accordingly, electrical interference and physical contact between the second bonding wires (WB2) can be further prevented.

[0054] The semiconductor package may further include a molding film (700). The molding film (700) may be provided on the upper surface of the substrate (500) to cover the first semiconductor chip (100) and the second semiconductor chip (200). The molding film (700) may seal the first and second bonding wires (WB1, WB2). The outer walls of the molding film (700) may be vertically aligned with the side walls of the substrate (500). The molding film (700) may include an insulating polymer such as an epoxy-based molding compound.

[0055] The semiconductor package may further include adhesive layers (710). The adhesive layers (710) may be provided on the lower surface of the first semiconductor chip (100) and the lower surface of the second semiconductor chip (200). The adhesive layers (710) may be die attach films. The adhesive layers (710) may include, for example, an insulating polymer. The adhesive layers (710) may include a material different from the molding film (700). The ends of the first bonding wires (WB1) may be covered by the adhesive layer (710).

[0056] Hereinafter, for the sake of simplification, in drawings excluding FIGS. 1a to 1e, FIGS. 2b, FIGS. 2c, and FIGS. 6a, the illustration of the first signal metal pad (115S), the first ground / power metal pad (115PG), the second signal metal pad (215S), the second ground / power metal pad (215PG), the first lower signal redistribution pattern (135S1), the first lower ground / power redistribution patterns (135PG1), the second lower ground / power redistribution pattern (135PG2), the first upper signal redistribution pattern (235S1), the first upper ground / power redistribution patterns (235PG1), and the second upper ground / power redistribution patterns (235PG2) is omitted.

[0058] FIG. 2a is a plan view illustrating a semiconductor package according to embodiments. FIG. 2b is a plan view for explaining the arrangement of a substrate, a first semiconductor chip, and a first bonding wire according to embodiments. FIG. 2c is a plan view for explaining the arrangement of a substrate, a second semiconductor chip, and a second bonding wire according to embodiments. Hereinafter, in describing FIG. 2a to 2c, FIG. 1d to 1f will be used in conjunction with FIG. 1f.

[0059] Referring to FIGS. 2a through 2c, the semiconductor package may include a substrate (500), a first semiconductor chip (100), a second semiconductor chip (200), first bonding wires (WB1), and second bonding wires (WB2). The substrate (500), the first semiconductor chip (100), the second semiconductor chip (200), the first bonding wires (WB1), and the second bonding wires (WB2) may be substantially the same as those previously described in the examples of FIGS. 1a through 1f. The semiconductor package may further include solder balls (600), adhesive layers (710), and a molding film (700) as described in the examples of FIGS. 1d through 1f.

[0060] As shown in FIG. 2b, the first semiconductor chip (100) may further include a plurality of first signal metal pads (115S), first ground / power metal pads (115PG), a first lower signal redistribution pattern (135S1), first and second lower ground / power redistribution patterns (135PG1, 135PG2), a first lower signal pad (150S1), a second lower signal pad (150S2), and in addition to the first ground / power pads (150PG), a second lower signal redistribution pattern (135S2) and a third lower signal pad (150S3). The first lower signal pad (150S1) may be connected to any one of the first signal metal pads (115S) through the first lower signal redistribution pattern (135S1).

[0061] The second lower signal redistribution pattern (135S2) may be provided within the first redistribution layer (120) described in the examples of FIGS. 1d through 1f. The second lower signal redistribution pattern (135S2) may be spaced apart from the first lower signal redistribution pattern (135S1) and the first and second lower ground / power redistribution patterns (135PG1, 135PG2) and may be electrically isolated. The second lower signal redistribution pattern (135S2) may include the metallic material described in the example of the first lower signal redistribution pattern (135S1). The second lower signal redistribution pattern (135S2) may be electrically connected to the other of the first signal metal pads (115S).

[0062] The third lower signal pad (150S3) may be disposed on the upper surface of the first semiconductor chip (100). For example, the third lower signal pad (150S3) may be provided on the upper surface of the first redistribution layer (120) described in the examples of FIGS. 1d to 1f. The third lower signal pad (150S3) may include the same metal as the first and second lower signal pads (150S1, 150S2). The third lower signal pad (150S3) may be spaced apart from the first and second lower signal pads (150S1, 150S2) and the first ground / power pads (150PG), and may be electrically insulated from the first and second lower signal pads (150S1, 150S2) and the first ground / power pads (150PG). The third lower signal pad (150S3) can be connected to the other first signal metal pad (115S) through the second lower signal rewiring pattern (135S2).

[0063] The third lower signal pad (150S3) can transmit an electrical signal of a different type than the first lower signal pad (150S1) and the second lower signal pad (150S2). For example, the signal transmission speed required for the third lower signal pad (150S3) may be slower than the signal transmission speed required for the first lower signal pad (150S1) or the second lower signal pad (150S2). That is, the signal transmission speeds of the first and second lower signal pads (150S1, 150S2) may be faster than the signal transmission speed of the third lower signal pad (150S3). For example, the first and second lower signal pads (150S1, 150S2) may transmit a DQ signal, and the third lower signal pad (150S3) may transmit an electrical signal of a different type than the DQ signal.

[0064] A corresponding one of the first signal bonding wires (sWB1) can be connected to a third lower signal pad (150S3). The first semiconductor chip (100) may include a plurality of third lower signal pads (150S3), but the present invention is not limited thereto.

[0065] As shown in FIG. 2c, the second semiconductor chip (200) may further include a plurality of second signal metal pads (215S), second ground / power metal pads (215PG), a first upper signal redistribution pattern (235S1), first and second upper ground / power redistribution patterns (235PG1, 235PG2), a first upper signal pad (250S1), a second upper signal pad (250S2), and second ground / power pads (250PG), in addition to a second upper signal redistribution pattern (235S2) and third upper signal pads (250S3). The first upper signal pad (250S1) may be connected to any one of the second signal metal pads (215S) through the first upper signal redistribution pattern (235S1).

[0066] The second upper signal redistribution pattern (235S2) may be provided within the second redistribution layer (220) described in the examples of FIGS. 1d through 1f. The second upper signal redistribution pattern (235S2) may include the same material as the first upper signal redistribution pattern (235S1). The arrangement and shape of the second upper signal redistribution pattern (235S2) may be substantially the same as the arrangement and shape of the second lower signal redistribution pattern (135S2) of FIG. 2b. For example, the second semiconductor chip (200) may be provided on the first semiconductor chip (100) so that the second upper signal redistribution pattern (235S2) overlaps with the second lower signal redistribution pattern (135S2) in a planar view. The second upper signal redistribution pattern (235S2) may be spaced apart from the first upper signal redistribution pattern (235S1) and the first and second upper ground / power redistribution patterns (235PG1, 235PG2). The role and electrical connection of the second upper signal redistribution pattern (235S2) may be the same or similar to the role and electrical connection of the second lower signal redistribution pattern (135S2). For example, the second upper signal redistribution pattern (235S2) may be electrically connected to the other of the first signal metal pads (115S). The second upper signal redistribution pattern (235S2) may be electrically isolated from the first upper signal redistribution pattern (235S1) and the first and second upper ground / power redistribution patterns (235PG1, 235PG2).

[0067] The third upper signal pads (250S3) may be disposed on the upper surface of the second semiconductor chip (200). For example, the third upper signal pads (250S3) may be provided on the upper surface of the second redistribution layer (220) described in the examples of FIGS. 1d to 1f.

[0068] The arrangement and shape of the third upper signal pads (250S3) may be substantially the same as the arrangement and shape of the third lower signal pad (150S3). For example, the third upper signal pads (250S3) may overlap with the third lower signal pad (150S3) in a planar view. The third upper signal pads (250S3) may be spaced apart from the first and second upper signal pads (250S1, 250S2) and the second ground / power pads (250PG). The role and electrical connection of the third upper signal pads (250S3) may be the same or similar to the role and electrical connection of the third lower signal pad (150S3). For example, the third upper signal pads (250S3) may be electrically isolated from the first and second upper signal pads (250S1, 250S2) and the second ground / power pads (250PG). The third upper signal pads (250S3) may be connected to the other second signal metal pad (215S) through the second upper signal rewiring pattern (235S2).

[0069] The third upper signal pads (250S3) can transmit electrical signals of a different type than the first and second upper signal pads (250S1, 250S2). For example, the signal transmission speed required for the third upper signal pads (250S3) may be slower than the signal transmission speed required for the first and second upper signal pads (250S1, 250S2). That is, the signal transmission speed of the first and second upper signal pads (250S1, 250S2) may be faster than the signal transmission speed of the third upper signal pads (250S3). For example, the second upper signal pad (250S2) can transmit a DQ signal, and the third upper signal pads (250S3) can transmit electrical signals of a different type than the DQ signal.

[0070] A corresponding second signal bonding wire (sWB2) can be connected to a third upper signal pad (250S3). The second semiconductor chip (200) may include a plurality of third upper signal pads (250S3), but the present invention is not limited thereto.

[0072] FIG. 3 is a perspective view illustrating a portion of a semiconductor package according to embodiments. FIG. 4a is a plan view illustrating a semiconductor package according to embodiments. FIG. 4b is a cross-section taken along A-A' of FIG. 4a. FIG. 4c is a cross-section taken along B-B' of FIG. 4a. FIG. 4d is a cross-section taken along C-C' of FIG. 4a. The following descriptions that overlap with those previously explained are omitted.

[0073] Referring to FIGS. 3, 4a, 4b, 4c, and 4d, the semiconductor package may include a substrate (500), a first semiconductor chip (100), a second semiconductor chip (200), first bonding wires (WB1), and second bonding wires (WB2). The semiconductor package may further include solder balls (600), adhesive layers (710), and a molding film (700) as described in the examples of FIGS. 1d through 1f.

[0074] The second semiconductor chip (200) may be a semiconductor chip of the same type as the first semiconductor chip (100). The second semiconductor chip (200) may be provided on the upper surface of the first semiconductor chip (100). However, the second semiconductor chip (200) may be shifted and positioned in the opposite direction of the first direction (D1) from the first semiconductor chip (100). The second semiconductor chip (200) is spaced apart from the first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG), and may expose the first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG). As shown in FIGS. 4b to 4d, the molding film (700) can cover the first lower signal pad (150S1), the second lower signal pad (150S2), and the first ground / power pads (150PG).

[0075] A plurality of first signal bonding wires (sWB1) may contact the first lower signal pad (150S1) and the third lower signal pad (150S3). The first signal bonding wires (sWB1) may not be provided on the upper surface of the second lower signal pad (150S2) and may not contact the second lower signal pad (150S2) directly. The first ground / power bonding wires (pgWB1) may be connected to the first ground / power pads (150PG).

[0076] A plurality of second signal bonding wires (sWB2) may contact the second upper signal pad (250S2) and the third upper signal pads (250S3). The second signal bonding wires (sWB2) may not be provided on the upper surface of the first lower signal pad (150S1) and may not contact the first upper signal pad (250S1) directly. The second ground / power bonding wires (pgWB2) may be connected to the second ground / power pads (250PG).

[0077] From a planar perspective, the first lower signal pad (150S1) may be positioned between any one of the signal substrate pads (550S) and the first upper signal pad (250S1). Any one of the signal substrate pads (550S) may be connected to the first lower signal pad (150S1) through a first signal bonding wire (sWB1) corresponding to it.

[0078] From a planar perspective, the second lower signal pad (150S2) may be positioned between the other of the signal substrate pads (550S) and the second upper signal pad (250S2). The other of the signal substrate pads (550S) may be connected to the second upper signal pad (250S2) via a second signal bonding wire (sWB2) corresponding to it.

[0080] FIG. 5a is a plan view illustrating a semiconductor package according to embodiments. FIG. 5b is a cross-sectional view taken along the line D-D' of FIG. 5a.

[0081] Referring to FIGS. 5a and 5b, the semiconductor package may include a substrate (500), a first semiconductor chip (100), a second semiconductor chip (200), first bonding wires (WB1), and second bonding wires (WB2). The semiconductor package may further include solder balls (600), adhesive layers (710), and a molding film (700) as described in the examples of FIGS. 1d through 1f. The substrate (500), the first semiconductor chip (100), the second semiconductor chip (200), and the first bonding wires (WB1) may be substantially the same as those previously described in the examples of FIGS. 1a through 1f or FIGS. 2a through 2c.

[0082] However, the first lower signal pad (150S1) and the second lower signal pad (150S2) may be adjacent to each other. None of the first ground / power pads (150PG) may be provided between the first lower signal pad (150S1) and the second lower signal pad (150S2). The first semiconductor chip (100) may not include the second lower ground / power rewiring pattern (135PG2) described in the example of FIG. 1a and FIG. 1b, but is not limited thereto.

[0083] The first upper signal pad (250S1) and the second upper signal pad (250S2) may be adjacent to each other. The second ground / power pads (250PG) may not be provided between the first upper signal pad (250S1) and the second upper signal pad (250S2). The second semiconductor chip (200) may not include the second upper ground / power rewiring pattern (235PG2) described in the example of FIG. 1a and FIG. 1c, but is not limited thereto.

[0084] The substrate (500) may include signal substrate pads (550S) and ground / power substrate pads (550PG). The ground / power substrate pads (550PG) may include a first ground / power substrate pad (551PG) and a second ground / power substrate pad (552PG). The first ground / power substrate pad (551PG) may be provided between the signal substrate pads (550S) (e.g., the first signal substrate pads). Among the signal substrate pads (550S), the first signal substrate pads may include a signal substrate pad (550S) connected to a first lower signal pad (150S1) and a signal substrate pad (550S) connected to a second upper signal pad (250S2). Among the signal substrate pads (550S), the first signal substrate pads may be adjacent to each other. Among the signal substrate pads (550S), the first signal substrate pads can transmit the DQ signal.

[0085] The second ground / power board pad (552PG) may be spaced apart from the first ground / power board pad (551PG). The second ground / power board pad (552PG) may not be provided between the first signal board pads among the signal board pads (550S).

[0086] As shown in FIG. 5b, the second ground / power board pad (552PG) and the second ground / power board pad (552PG) can be electrically connected to each other through corresponding board wiring (530). The first ground / power board pad (551PG) can receive a ground voltage or a power voltage through the board wiring (530).

[0087] Any one of the first ground / power bonding wires (pgWB1) and any one of the second ground / power bonding wires (pgWB2) can be connected to the second ground / power board pad (552PG). Neither the first ground / power bonding wire (pgWB1) nor the second ground / power bonding wire (pgWB2) may be provided on the upper surface of the first ground / power board pad (551PG). According to the embodiments, since the first ground / power board pad (551PG) is provided, the occurrence of crosstalk between the first signal board pads among the signal board pads (550S) can be prevented. Accordingly, the electrical characteristics of the semiconductor package can be improved.

[0088] Each of the first bonding wires (WB1) and the second bonding wires (WB2) can be substantially parallel to the first direction (D1).

[0090] FIG. 5c is a plan view illustrating a semiconductor package according to embodiments. In describing FIG. 5c, FIG. 5b is also referenced. Content that overlaps with what has been previously described is omitted.

[0091] Referring to FIG. 5c, the semiconductor package may include a substrate (500), a first semiconductor chip (100), a second semiconductor chip (200), first bonding wires (WB1), and second bonding wires (WB2). The semiconductor package may further include solder balls (600), adhesive layers (710), and a molding film (700) as described in the examples of FIG. 1d to 1f.

[0092] The substrate (500), the first semiconductor chip (100), the second semiconductor chip (200), the first bonding wires (WB1), and the second bonding wires (WB2) may be substantially the same as described in the examples of FIG. 5a and 5b. For example, as in FIG. 5b, the first ground / power substrate pad (551PG) and the second ground / power substrate pad (552PG) may be electrically connected to each other through corresponding substrate wiring (530 in FIG. 5b).

[0093] However, the first signal bonding wire (sWB1) connected to the first lower signal pad (150S1) may not be parallel to the first direction (D1) in a planar view. The second signal bonding wire (sWB2) connected to the second upper signal pad (250S2) may not be parallel to the first direction (D1) in a planar view.

[0095] FIG. 6a is a plan view illustrating a first semiconductor chip according to embodiments.

[0096] Referring to FIG. 6a, the first semiconductor chip (100) may include first signal metal pads (115S), first ground / power metal pads (115PG), a first lower signal redistribution pattern (135S1), first and second lower ground / power redistribution patterns (135PG1, 135PG2), a plurality of first signal pads (150S), and first ground / power pads (150PG). The first semiconductor chip (100) may further include a second lower signal redistribution pattern (135S2) and a third lower signal pad (150S3). The first semiconductor chip (100) may be similar to the one described above. For example, the first signal pads (150S) may include a first lower signal pad (150S1) and a second lower signal pad (150S2) as described in the examples of FIG. 1a, FIG. 1b, FIG. 1d, FIG. 1e, and FIG. 1f. That is, the first signal pads (150S) may be similar to the first lower signal pad (150S1) and the second lower signal pad (150S2) of FIG. 1a, FIG. 1b, FIG. 1d, FIG. 1e, and FIG. 1f. The first lower signal rewiring pattern (135S1) may be connected to a plurality of first signal pads (150S). For example, the first lower signal rewiring pattern (135S1) may be connected to at least four first signal pads (150S), but the present invention is not limited thereto. The first signal pads (150S) can be electrically connected to the first signal metal pad (115S) through the first lower signal redistribution pattern (135S1). The first signal pads (150S) can be electrically connected to each other through the first lower signal redistribution patterns (135S1).

[0097] First ground / power pads (150PG) may be provided between each of the first signal pads (150S).

[0099] FIG. 6b is a plan view illustrating a semiconductor package according to embodiments. In describing FIG. 6b, FIG. 6a is referenced together.

[0100] Referring to FIG. 6b, the semiconductor package may include a substrate (500), a first semiconductor chip (100), a second semiconductor chip (200), a third semiconductor chip (300), a fourth semiconductor chip (400), first bonding wires (WB1), second bonding wires (WB2), third bonding wires (WB3), and fourth bonding wires (WB4). The semiconductor package may further include solder balls (600), adhesive layers (710), and a molding film (700) as described in the examples of FIG. 1d and FIG. 1e.

[0101] The first semiconductor chip (100) may be mounted on the upper surface of the substrate (500). The first semiconductor chip (100) may be substantially the same as described in the example of FIG. 6a. The second semiconductor chip (200), the third semiconductor chip (300), and the fourth semiconductor chip (400) may be stacked on the first semiconductor chip (100). The first semiconductor chip (100), the second semiconductor chip (200), the third semiconductor chip (300), and the fourth semiconductor chip (400) may be aligned vertically with each other.

[0102] The second semiconductor chip (200), the third semiconductor chip (300), and the fourth semiconductor chip (400) may be semiconductor chips of the same type as the first semiconductor chip (100). Each of the second semiconductor chip (200), the third semiconductor chip (300), and the fourth semiconductor chip (400) may be identical or similar to the first semiconductor chip (100) of FIG. 6a. For example, the second semiconductor chip (200) may include a plurality of second signal pads (250S) and second ground / power pads (250PG). For example, the second signal pads (250S) may include a first upper signal pad (250S1) and a second upper signal pad (250S2) as described in the examples of FIG. 1a, FIG. 1c, FIG. 1d, FIG. 1e, and FIG. 1f. The second semiconductor chip (200) may further include third upper signal pads (250S3). The second semiconductor chip (200) may further include the second signal metal pads (215S), second ground / power metal pads (215PG), first upper signal redistribution pattern (235S1), second upper signal redistribution pattern (235S2), and first and second upper ground / power redistribution patterns (235PG1, 235PG2) described in the examples of FIGS. 2a to 2c.

[0103] The arrangement, shape, and electrical connection of the plurality of second signal pads (250S), second ground / power pads (250PG), and third upper signal pads (250S3) may be substantially the same as the arrangement, shape, and electrical connection of the plurality of first signal pads (150S), first ground / power pads (150PG), and third lower signal pads (150S3) of FIG. 6A, respectively. For example, the plurality of second signal pads (250S) may be electrically connected to each other through the first upper signal redistribution pattern (235S1 in FIG. 2C). The plurality of second signal pads (250S) may be electrically connected to any one of the second signal metal pads (215S in FIG. 2C) through the first upper signal redistribution pattern (235S1 in FIG. 2C). A plurality of second signal pads (250S), second ground / power pads (250PG), and third upper signal pads (250S3) can each overlap with a plurality of first signal pads (150S), first ground / power pads (150PG), and second lower signal pads (150S2) in a planar view.

[0104] The third semiconductor chip (300) may include third signal metal pads, third ground / power metal pads, a third signal redistribution pattern, third and fourth upper ground / power redistribution patterns, a plurality of third signal pads (350S), fourth upper signal pads (350S3), and third ground / power pads (350PG). The arrangement, shape, and electrical connection of the third signal metal pads, third ground / power metal pads, third signal redistribution pattern, third and fourth upper ground / power redistribution patterns, plurality of third signal pads (350S), third ground / power pads (350PG), and fourth upper signal pads (350S3) may be substantially the same as the arrangement, shape, and electrical connection of the first signal metal pads (115S), first ground / power metal pads (115PG), first lower signal redistribution pattern (135S1), first and second lower ground / power redistribution patterns (135PG1, 135PG2), plurality of first signal pads (150S), first ground / power pads (150PG), and third lower signal pads (150S3) of FIG. 6A. For example, a plurality of third signal pads (350S) may be electrically connected to each other through a third signal rewiring pattern. A plurality of third signal pads (350S) may be electrically connected to any one of the third signal metal pads through a third signal rewiring pattern. Fourth upper signal pads (350S3) may be electrically isolated from the third signal pads (350S). The signal transmission speed of the fourth upper signal pads (350S3) may be slower than the signal transmission speed of the third signal pads (350S).The third signal metal pads, third ground / power metal pads, third signal redistribution pattern, third and fourth upper ground / power redistribution patterns, a plurality of third signal pads (350S), third ground / power pads (350PG), and fourth upper signal pads (350S3) can each overlap with the first signal metal pads (115S), first ground / power metal pads (115PG), first lower signal redistribution pattern (135S1), first and second lower ground / power redistribution patterns (135PG1, 135PG2), a plurality of first signal pads (150S), first ground / power pads (150PG), and third lower signal pads (150S3) of FIG. 6A in a planar view.

[0105] The fourth semiconductor chip (400) may include fourth signal metal pads, fourth ground / power metal pads, a fourth signal redistribution pattern, fifth and sixth upper ground / power redistribution patterns, a plurality of fourth signal pads (450S), fourth ground / power pads (450PG), and fifth upper signal pads (450S3). The arrangement, shape, and function of the fourth signal metal pads, fourth ground / power metal pads, fourth signal redistribution pattern, fifth and sixth upper ground / power redistribution patterns, plurality of fourth signal pads (450S), fourth ground / power pads (450PG), and fifth upper signal pads (450S3) may be substantially the same as the arrangement, shape, and function of the first signal metal pads (115S), first ground / power metal pads (115PG), first lower signal redistribution pattern (135S1), first and second lower ground / power redistribution patterns (135PG1, 135PG2), plurality of first signal pads (150S), first ground / power pads (150PG), and third lower signal pads (150S3) of FIG. 6A. For example, the plurality of fourth signal pads (450S) may be electrically connected to each other through the fourth signal redistribution pattern. Multiple fourth signal pads (450S) may be electrically connected to any one of the fourth signal metal pads through a third signal rewiring pattern. The fifth upper signal pads (450S3) may be electrically isolated from the fourth signal pads (450S). The fifth upper signal pads (450S3) may be electrically isolated from each other. The signal transmission speed of the fifth upper signal pads (450S3) may be slower than the signal transmission speed of the fourth signal pads (450S).The fourth signal metal pads, the fourth ground / power metal pads, the fourth signal redistribution pattern, the fifth and sixth upper ground / power redistribution patterns, the plurality of fourth signal pads (450S), the fourth ground / power pads (450PG), and the fifth upper signal pads (450S3) can each overlap with the first signal metal pads (115S), the first ground / power metal pads (115PG), the first lower signal redistribution pattern (135S1), the first and second lower ground / power redistribution patterns (135PG1, 135PG2), the plurality of first signal pads (150S), the first ground / power pads (150PG), and the third lower signal pads (150S3) in a planar view.

[0106] The first bonding wires (WB1) are provided on the upper surface of the first semiconductor chip (100) and can be electrically connected to the substrate (500). Any one of the first signal bonding wires (sWB1) (e.g., a first sub-signal bonding wire) is provided on any one of the first signal pads (150S) (e.g., a contact signal pad) and can be in contact with said first signal pad (150S). The first signal bonding wires (sWB1) can be spaced apart from the upper surface of the remaining first signal pads (150S) (e.g., blank signal pads). The remaining first signal pads (150S) can be connected to the contact signal pad and the corresponding first signal metal pad (115S) among the first signal pads (150S) through the first lower signal rewiring pattern (135S1). The remaining first signal bonding wires (sWB1) (e.g., second sub-signal bonding wire) can be electrically connected to the third lower signal pads (150S3). The first ground / power bonding wires (pgWB1) can be in contact with the first ground / power pads (150PG).

[0107] The second bonding wires (WB2) are provided on the upper surface of the second semiconductor chip (200) and can be electrically connected to the substrate (500). Any one of the second signal bonding wires (sWB2) (e.g., the first sub-signal bonding wire) can be in contact with the upper surface of any one of the second signal pads (250S) (e.g., the contact signal pad). The second signal bonding wires (sWB2) can be spaced apart from the upper surface of the remaining second signal pads (250S) (e.g., the blank signal pads). The blank signal pads among the second signal pads (250S) can be connected to the contact signal pad or the corresponding second signal metal pad (215S in FIG. 2A) among the second signal pads (250S) through the second upper signal rewiring pattern (235S2 in FIG. 2A). The remaining of the second signal bonding wires (sWB2) (e.g., the second sub-signal bonding wire) can each be connected to the third upper signal pads (250S3). The second ground / power bonding wires (pgWB2) can be connected to the second ground / power pads (250PG).

[0108] The third bonding wires (WB3) are provided on the upper surface of the third semiconductor chip (300) and can be electrically connected to the substrate (500). Any one of the third signal bonding wires (sWB3) (e.g., the first sub-signal bonding wire) can be in contact with the upper surface of any one of the third signal pads (350S) (e.g., the contact signal pad). The third signal bonding wires (sWB3) may not be provided on the upper surface of the remaining third signal pads (350S) (e.g., the blank signal pads). The blank signal pads among the third signal pads (350S) can be connected to the contact signal pads among the third signal pads (350S) or the corresponding third signal metal pads through the third upper signal rewiring pattern. The remaining of the third signal bonding wires (sWB3) (e.g., the second sub-signal bonding wire) can each be connected to the fourth upper signal pads (350S3). The third ground / power bonding wires (pgWB3) can be connected to the third ground / power pads (350PG).

[0109] The fourth bonding wires (WB4) are provided on the upper surface of the fourth semiconductor chip (400) and can be electrically connected to the substrate (500). Any one of the fourth signal bonding wires (sWB4) (e.g., the first sub-signal bonding wire) can be in contact with the upper surface of any one of the fourth signal pads (450S) (e.g., the contact signal pad). The fourth signal bonding wires (sWB4) can be spaced apart from the upper surface of the remaining fourth signal pads (450S) (e.g., the blank signal pads). The remaining fourth signal pads (450S) can be connected to any one of the third signal pads (350S) or the corresponding fourth signal metal pad through the fourth upper signal rewiring pattern. The remaining of the fourth signal bonding wires (sWB4) (e.g., the second sub-signal bonding wire) can be connected to the fifth upper signal pads (450S3), respectively. The fourth ground / power bonding wires (pgWB4) can be connected to the fourth ground / power pads (450PG).

[0110] The first signal pads (150S) may overlap with the second signal pads (250S), the third signal pads (350S), and the fourth signal pads (450S) in a planar view. The contact signal pad among the first signal pads (150S) may overlap with the corresponding blank signal pad among the second signal pads (250S), the corresponding blank signal pad among the third signal pads (350S), and the corresponding blank signal pad among the fourth signal pads (45S) in a planar view. Accordingly, the first sub-signal bonding wire among the first signal bonding wires (sWB1) may not overlap with the second signal bonding wires (sWB2), the third signal bonding wires (sWB3), and the fourth signal bonding wires (sWB4) in a planar view. Accordingly, the occurrence of crosstalk between the first to fourth signal bonding wires (sWB1, sWB2, sWB3, sWB4) can be prevented.

[0111] The contact signal pad among the second signal pads (250S) may overlap in a planar view with the corresponding blank signal pad among the first signal pads (150S), the corresponding blank signal pad among the third signal pads (350S), and the corresponding blank signal pad among the fourth signal pads (450S). Accordingly, the first sub-signal bonding wire among the second signal bonding wires (sWB2) may not overlap in a planar view with the first signal bonding wires (sWB1), the third signal bonding wires (sWB3), and the fourth signal bonding wires (sWB4).

[0112] The contact signal pad among the third signal pads (350S) may overlap in a planar view with the corresponding blank signal pad among the first signal pads (150S), the corresponding blank signal pad among the second signal pads (250S), and the corresponding blank signal pad among the fourth signal pads (450S). Accordingly, the first sub-signal bonding wire among the third signal bonding wires (sWB3) may not overlap in a planar view with the first signal bonding wires (sWB1), the second signal bonding wires (sWB2), and the fourth signal bonding wires (sWB4).

[0113] The contact signal pad among the fourth signal pads (450S) may overlap in a planar view with the corresponding blank signal pad among the first signal pads (150S), the corresponding blank signal pad among the second signal pads (250S), and the corresponding blank signal pad among the third signal pads (350S). Accordingly, the first sub-signal bonding wire among the fourth signal bonding wires (sWB4) may not overlap in a planar view with the first signal bonding wires (sWB1), the second signal bonding wires (sWB2), and the third signal bonding wires (sWB3). Accordingly, the occurrence of crosstalk between the first to fourth signal bonding wires (sWB1, sWB2, sWB3, sWB4) may be further prevented. The semiconductor package is improved movement It can have reliability.

[0114] A semiconductor package may include first to fourth semiconductor chips (100, 200, 300, 400), and as shown in FIG. 6a, at least four first signal pads (150S) may be electrically connected to each other by a first lower signal redistribution pattern (135S1). At least four second signal pads (250S) may be electrically connected to each other by a first upper redistribution pattern. At least four second signal pads (250S) may be electrically connected to each other by a second upper redistribution pattern. At least four fourth signal pads (450S) may be electrically connected to each other by a fourth upper redistribution pattern.

[0115] First to fourth ground / power bonding wires (pgWB1, pgWB2, pgWB3, pgWB4) may each be provided between two adjacent wires among the first sub-signal bonding wire of the first signal bonding wires (sWB1), the first sub-signal bonding wire of the second signal bonding wires (sWB2), the first sub-signal bonding wire of the third signal bonding wires (sWB3), and the first sub-signal bonding wire of the fourth signal bonding wires (sWB4). Accordingly, the occurrence of crosstalk between the first to fourth signal bonding wires (sWB1, sWB2, sWB3, sWB4) may be further reduced. The semiconductor package may have improved electrical characteristics.

[0116] Each of the ground / power board pads (550PG) can be connected to a corresponding first ground / power bonding wire (pgWB1), a corresponding second ground / power bonding wire (pgWB2), a corresponding third ground / power bonding wire (pgWB3), and a corresponding fourth ground / power bonding wire (pgWB4).

[0117] The number of stacked semiconductor chips (100, 200, 300, 400) is not limited to what is shown and can be varied in many ways. The semiconductor package may further include solder balls (600), adhesive layers (710), and molding film (700) as described in the examples of FIG. 1d and FIG. 1e.

[0119] FIG. 6c is a plan view illustrating a semiconductor package according to embodiments. In describing FIG. 6c, FIG. 6a is referenced together.

[0120] Referring to FIG. 6c, the semiconductor package may include a substrate (500), a first semiconductor chip (100), a second semiconductor chip (200), a third semiconductor chip (300), a fourth semiconductor chip (400), first bonding wires (WB1), second bonding wires (WB2), third bonding wires (WB3), and fourth bonding wires (WB4). The substrate (500), the first to fourth semiconductor chips (100, 200, 300, 400), and the first to fourth bonding wires (WB1, WB2, WB3, WB4) may be substantially the same as those described in the examples of FIG. 6a and 6b. However, the second semiconductor chip (200) may be shifted in the opposite direction of the first direction (D1) from the first semiconductor chip (100). The first signal pads (150S), the first ground / power pads (150PG), and the third lower signal pads (150S3) can be spaced apart from the second semiconductor chip (200).

[0121] The third semiconductor chip (300) can be shifted and positioned in the opposite direction of the first direction (D1) from the second semiconductor chip (200). The third semiconductor chip (300) can expose the second signal pads (250S), the second ground / power pads (250PG), and the third upper signal pads (250S3).

[0122] The fourth semiconductor chip (400) can be shifted and positioned in the opposite direction of the first direction (D1) from the third semiconductor chip (300). The fourth semiconductor chip (400) can expose fourth signal pads (450S), fourth ground / power pads (450PG), and fourth upper signal pads (350S3).

[0123] The semiconductor package may further include solder balls (600), adhesive layers (710), and molding film (700) as described in the examples of FIG. 1d and FIG. 1e.

[0125] The above detailed description of the invention is not intended to limit the invention to the disclosed embodiments, and may be used in various other combinations, modifications, and environments without departing from the essence of the invention.

Claims

Claim 1 A semiconductor package comprising: a substrate including substrate pads on an upper surface; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and first bonding wires provided on the upper surface of the first semiconductor chip and connected to the substrate pads, wherein the first semiconductor chip comprises: a first lower signal pad; a second lower signal pad spaced apart from the first lower signal pad; and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad, wherein any one of the first bonding wires is connected to the first lower signal pad and none of the first bonding wires are provided on the upper surface of the second lower signal pad, and the first lower signal pad and the second lower signal pad are provided on the upper surface of the lower signal redistribution pattern. Claim 2 In claim 1, the first semiconductor chip further includes a first power / ground pad on an upper surface, and the first power / ground pad is a semiconductor package disposed between the first lower signal pad and the second lower signal pad. Claim 3 A semiconductor package according to claim 1, further comprising second bonding wires provided on the upper surface of the second semiconductor chip and connected to the substrate, wherein the second semiconductor chip comprises: a first upper signal pad; a second upper signal pad spaced apart from the first upper signal pad; and an upper signal rewiring pattern electrically connected to the first upper signal pad and the second upper signal pad, and wherein the second bonding wires include a second signal bonding wire connected to the second upper signal pad, and none of the second bonding wires are provided on the upper surface of the first upper signal pad. Claim 4 In claim 3, the second signal bonding wire overlaps with the first lower signal pad in a planar view and is a semiconductor package vertically spaced from the first lower signal pad. Claim 5 A semiconductor package according to claim 3, wherein none of the first bonding wires overlap vertically with the second signal bonding wire. Claim 6 In claim 3, the second semiconductor chip further includes a second power / ground pad on an upper surface, and the second power / ground pad is a semiconductor package disposed between the first upper signal pad and the second upper signal pad. Claim 7 A semiconductor package according to claim 3, wherein the first upper signal pad overlaps with the first lower signal pad in a planar view, and the second upper signal pad overlaps with the second lower signal pad in a planar view. Claim 8 In claim 1, the first semiconductor chip comprises: a first semiconductor substrate; a first signal metal pad on the first semiconductor substrate; and a first redistribution layer provided on the first semiconductor substrate and including the lower signal redistribution pattern, wherein the lower signal redistribution pattern is connected to the first signal metal pad, and the first lower signal pad and the second lower signal pad are provided on the upper surface of the first redistribution layer. Claim 9 A semiconductor package comprising: a substrate including substrate pads on an upper surface; a first semiconductor chip disposed on the substrate and including a first lower signal pad, a second lower signal pad, and a lower redistribution pattern; a second semiconductor chip provided on the first semiconductor chip and including a first upper signal pad, a second upper signal pad, and an upper redistribution pattern; first bonding wires provided on the upper surface of the first semiconductor chip and connected to the substrate; and second bonding wires provided on the upper surface of the second semiconductor chip and connected to the substrate, wherein the lower redistribution pattern is electrically connected to the first lower signal pad and the second lower signal pad, the upper redistribution pattern is electrically connected to the first upper signal pad and the second upper signal pad, the first bonding wires are spaced apart from the second lower signal pad, the second bonding wires are spaced apart from the first upper signal pad, and the first lower signal pad and the second lower signal pad are provided on the upper surface of the lower redistribution pattern. Claim 10 In claim 9, the semiconductor package wherein the first bonding wires include a first signal bonding wire connected to the first lower signal pad, and the second bonding wires include a second signal bonding wire connected to the second upper signal pad. Claim 11 In claim 10, the second signal bonding wire is a semiconductor package spaced vertically apart from the upper surface of the first lower signal pad. Claim 12 In claim 10, the semiconductor package in which the first signal bonding wire does not vertically overlap with the second bonding wires. Claim 13 In claim 9, the first semiconductor chip further includes a power / ground pad on an upper surface, and the power / ground pad is a semiconductor package disposed between the first lower signal pad and the second lower signal pad. Claim 14 A semiconductor package according to claim 9, wherein the first bonding wires do not contact the upper surface of the second lower signal pad, and the second bonding wires do not contact the upper surface of the first upper signal pad. Claim 15 In claim 9, the second upper semiconductor chip is shifted in one direction from the first upper semiconductor chip in a planar view, and the substrate pads include a signal substrate pad connected to the first lower signal pad, and in a planar view, the first lower signal pad is a semiconductor package interposed between the first upper signal pad and the signal substrate pad. Claim 16 A substrate comprising substrate pads on an upper surface, wherein the substrate pads include signal substrate pads and ground / power substrate pads; solder balls disposed on a lower surface of the substrate; a first semiconductor chip disposed on the upper surface of the substrate; a second semiconductor chip on the upper surface of the first semiconductor chip; first bonding wires provided on the upper surface of the first semiconductor chip and connected to the substrate; second bonding wires provided on the upper surface of the second semiconductor chip and connected to the substrate; and a molding film provided on the upper surface of the substrate and covering the first and second semiconductor chips, wherein the first semiconductor chip comprises: a first lower signal pad; a second lower signal pad spaced laterally from the first lower signal pad; a lower redistribution pattern connected to the first and second lower signal pads; and a first ground / power pad insulated from the first and second lower signal pads, and the second semiconductor chip comprises: a first upper signal pad; a second upper signal pad spaced laterally from the first upper signal pad; A semiconductor package comprising: an upper rewiring pattern connected to the first and second upper signal pads; and a second ground / power pad insulated from the first and second upper signal pads, wherein the second bonding wires include a second signal bonding wire, the second signal bonding wire is connected to the second upper signal pad, and the second bonding wires are spaced apart from the first upper signal pad. Claim 17 In claim 16, the second signal bonding wire is vertically spaced from the upper surface of the first lower signal pad, and the first bonding wires are not provided between the second signal bonding wire and the first lower signal pad in a semiconductor package. Claim 18 A semiconductor package according to claim 16, wherein the first bonding wires include a first signal bonding wire, the first signal bonding wire is connected to the first lower signal pad, and none of the first bonding wires come into contact with the upper surface of the second lower signal pad. Claim 19 In claim 16, the first ground / power pad is disposed between the first lower signal pad and the second lower signal pad, and the second ground / power pad is disposed between the first upper signal pad and the second upper signal pad in a semiconductor package. Claim 20 In claim 16, the first semiconductor chip comprises: a first signal metal pad on a first semiconductor substrate; and a first redistribution layer provided on the first semiconductor substrate and comprising the lower redistribution pattern, wherein the lower redistribution pattern is connected to the first signal metal pad, and the second semiconductor chip comprises: a second signal metal pad on a second semiconductor substrate; and a second redistribution layer provided on the second semiconductor substrate and comprising the upper redistribution pattern, wherein the upper redistribution pattern is connected to the second signal metal pad.

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