Circuit board and package substrate including the same

Abstract

A circuit board according to an embodiment comprises an insulating layer; a pad disposed on the insulating layer; and a protective layer disposed on the insulating layer and exposing the upper surface of the pad, wherein the pad comprises a seed layer disposed on the insulating layer; a first pattern disposed on the seed layer; a second pattern disposed on the first pattern and comprising a metal material identical to the first pattern, the upper surface of which is exposed through the protective layer; and a surface treatment layer disposed on the upper surface of the second pattern exposed through the protective layer, wherein the width of the first pattern is greater than the width of the second pattern, the thickness of the first pattern is thicker than the thickness of the second pattern, and the upper surface of the protective layer is located on the same plane as or lower than the upper surface of the second pattern.

Description

Technology Field

[0001] The embodiment relates to a circuit board, and in particular to a circuit board including a pad with improved bonding properties with an adhesive member, and a package board including the same. Background Technology

[0002] As the miniaturization, lightweighting, and integration of electronic components accelerate, circuit linewidths are becoming finer. In particular, as semiconductor chip design rules are integrated to the nanometer scale, the circuit linewidths of package substrates or circuit boards on which semiconductor chips are mounted are being reduced to a few micrometers or less.

[0003] Various processes have been proposed to increase the circuit integration density of circuit boards (i.e., to miniaturize circuit line widths). For example, the semi-additive process (SAP) and modified semi-additive process (MSAP) have been proposed to prevent the loss of circuit line width during the etching step used to form patterns after copper plating.

[0004] Subsequently, the embedded trace substrate (ETS) method, in which copper foil is embedded within an insulating layer to implement finer circuit patterns, has been used in the industry. Since the ETS method manufactures copper foil circuits by embedding them within the insulating layer instead of forming them by protruding them from the surface, it eliminates circuit loss caused by etching, making it advantageous for finer circuit pitches.

[0005] Meanwhile, to meet the demand for wireless data traffic, improved 5G (5 thEfforts are being made to develop a generational communication system or a pre-5G communication system. Here, 5G communication systems use high frequency (mmWave) bands (e.g., 6 GHz, 28 GHz, 35 GHz) or higher frequencies to achieve high data transmission rates.

[0006] In addition, to mitigate path loss of radio waves in the ultra-high frequency band and increase the transmission distance of radio waves, integration technologies such as beamforming, massive MIMO, and array antennas are being developed in 5G communication systems. Various chips constituting AP modules are mounted on circuit boards applied to these 5G and higher (6G, 7G, etc.) communication systems, and the circuit boards include pads for mounting these chips. Furthermore, the performance of the 5G and higher communication system can be determined according to the characteristics of the chips mounted on the circuit board. Additionally, the performance improvement of the final product can be determined by the bonding properties between the mounted chips and the pads of the circuit board connected thereto.

[0007] Therefore, there is a need for a circuit board with a structure capable of improving the bonding properties of the pads connected to the chip. The problem to be solved

[0008] In an exemplary embodiment, a circuit board of a new structure and a package board including the same are to be provided.

[0009] Specifically, the embodiment aims to provide a circuit board including a pad with improved bonding properties with a chip and a package board including the same.

[0010] In addition, the embodiment aims to provide a circuit board with improved bonding strength between the protective layer and the pad, and a package board including the same.

[0011] The technical problems to be solved in the proposed embodiments are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the proposed embodiments belong from the description below. means of solving the problem

[0012] A circuit board according to an embodiment comprises an insulating layer; a pad disposed on the insulating layer; and a protective layer disposed on the insulating layer and exposing the upper surface of the pad, wherein the pad comprises a seed layer disposed on the insulating layer; a first pattern disposed on the seed layer; a second pattern disposed on the first pattern and comprising a metal material identical to the first pattern, the upper surface of which is exposed through the protective layer; and a surface treatment layer disposed on the upper surface of the second pattern exposed through the protective layer, wherein the width of the first pattern is greater than the width of the second pattern, the thickness of the first pattern is thicker than the thickness of the second pattern, and the upper surface of the protective layer is located on the same plane as or lower than the upper surface of the second pattern.

[0013] In addition, the first pattern has a width greater than the width of the surface treatment layer.

[0014] In addition, the thickness of the first pattern is thicker than the thickness of the surface treatment layer.

[0015] Additionally, the upper surface of the protective layer is positioned lower than the upper surface of the second pattern, and the second pattern includes a protruding area protruding from the upper surface of the protective layer, and the surface treatment layer includes a first portion disposed on the upper surface of the second pattern and a second portion extending from the first portion and disposed on the side of the protruding area of ​​the second pattern.

[0016] Additionally, the surface treatment layer comprises a first portion disposed on the upper surface of the second pattern and a second portion extending from the first portion and disposed on the upper surface of the protective layer.

[0017] In addition, at least one side of the first pattern and the second pattern includes a curved surface.

[0018] Additionally, the insulating layer comprises a first insulating layer and a second insulating layer on the first insulating layer, the seed layer is disposed on the second insulating layer and comprises a first circuit pattern layer disposed between the first insulating layer and the second insulating layer, and the surface roughness (Ra) of the first circuit pattern layer is greater than the surface roughness (Ra) of the second pattern.

[0019] In addition, the surface roughness (Ra) of the protective layer is smaller than the surface roughness (Ra) of the first circuit pattern layer and larger than the surface roughness (Ra) of the second pattern.

[0020] Meanwhile, a package substrate according to an embodiment comprises: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first protective layer disposed on the first surface of the insulating layer and exposing the upper surface of the first pad; a first adhesive member disposed on the upper surface of the first pad exposed through the first protective layer; a chip disposed on the first adhesive member; and a molding layer disposed on the first protective layer and molding the chip, wherein the first pad comprises: a seed layer disposed on the first surface of the insulating layer; a first pattern disposed on the seed layer; and a second pattern disposed on the first pattern, comprising a metal material identical to the first pattern, and having its upper surface exposed through the first protective layer. It includes a surface treatment layer disposed on the upper surface of the second pattern exposed through the first protective layer, wherein the width of the first pattern is greater than the width of the second pattern, the thickness of the first pattern is thicker than the thickness of the second pattern, and the upper surface of the first protective layer is located on the same plane as or lower than the upper surface of the second pattern.

[0021] In addition, the first pad is formed in plurality on the first surface of the insulating layer, and the chip includes a first AP chip and a second AP chip disposed on the plurality of first pads, the first AP chip corresponds to a central processor (CPU), and the second AP chip corresponds to a graphics processor (GPU).

[0022] Additionally, it includes a second pad disposed on a second surface opposite to the first surface of the insulating layer; a second protective layer disposed on the second surface of the insulating layer and exposing the lower surface of the second pad; and a second adhesive member disposed on the lower surface of the second pad exposed through the second protective layer.

[0023] Additionally, the insulating layer comprises an inner insulating layer; a first outermost insulating layer disposed on a first surface of the inner insulating layer; and a second outermost insulating layer disposed on a second surface opposite to the first surface of the inner insulating layer, wherein the first pad is disposed on the first surface of the first outermost insulating layer and the second pad is disposed on the second surface of the second outermost insulating layer, and the package substrate comprises a first via disposed on the inner insulating layer; a second via disposed on the first outermost insulating layer and connecting the first pad and the first via; and a third via disposed on the second outermost insulating layer and connecting the first via and the second pad, wherein the first to third vias have different widths.

[0024] Additionally, the first via has a width greater than the second via and a width smaller than the third via, and the second via has a width smaller than the third via. A circuit board according to an embodiment includes a build-up insulating layer comprising a plurality of insulating layers stacked along a vertical direction; a protective layer disposed on the build-up insulating layer; and a pad portion disposed on the build-up insulating layer and penetrating the upper and lower surfaces of the protective layer, wherein the pad portion comprises a lower pad disposed on the build-up insulating layer and having a first width along a horizontal direction; The pad portion further comprises an upper pad disposed on the lower pad and having a second width along the horizontal direction that is smaller than the first width, wherein the upper surface of the upper pad and the upper surface of the protective layer are located on the same plane. Additionally, the pad portion further comprises a seed layer disposed between the upper surface of the build-up insulating layer and the lower pad, and the thickness in the vertical direction from the lower surface of the seed layer to the upper surface of the upper pad is equal to the thickness in the vertical direction from the upper surface of the protective layer to the lower surface of the protective layer. Additionally, the pad portion further comprises a surface treatment layer disposed on the pad portion, wherein the thickness of the lower pad is thicker than the thickness of the surface treatment layer. Additionally, the surface treatment layer has a third width that is smaller than the first width and larger than the second width. Additionally, the surface treatment layer comprises a first portion disposed on the upper surface of the upper pad and a second portion extending from the first portion and disposed on the upper surface of the protective layer. Additionally, at least one of the side of the lower pad and the side of the upper pad comprises a curved surface in which the width in the horizontal direction increases toward the upper surface of the build-up insulating layer.Additionally, the build-up insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer, and the seed layer is disposed on the second insulating layer and includes a circuit pattern layer disposed between the first insulating layer and the second insulating layer, wherein the surface roughness (Ra) of the circuit pattern layer is greater than the surface roughness (Ra) of the upper pad. Additionally, the surface roughness (Ra) of the protective layer is smaller than the surface roughness (Ra) of the circuit pattern layer and greater than the surface roughness (Ra) of the upper pad. Meanwhile, a package substrate according to an embodiment comprises a build-up insulating layer including a plurality of insulating layers stacked along a vertical direction; a first protective layer disposed on the build-up insulating layer; a first pad disposed on the build-up insulating layer and penetrating the first protective layer along the vertical direction; a surface treatment layer disposed on the first pad; a first adhesive member disposed on the surface treatment layer; and a chip disposed on the first adhesive member. The apparatus comprises a molding layer disposed on the first protective layer and molding the chip, wherein the first pad comprises a lower pad disposed on the build-up insulating layer and having a first width along the horizontal direction; and an upper pad disposed on the lower pad and having a second width along the horizontal direction that is smaller than the first width, and the upper surface of the upper pad and the upper surface of the first protective layer are located on the same plane. Additionally, the first pad further comprises a seed layer disposed between the upper surface of the build-up insulating layer and the lower pad, and the thickness in the vertical direction from the lower surface of the seed layer to the upper surface of the upper pad is the same as the thickness in the vertical direction from the upper surface of the first protective layer to the lower surface of the first protective layer. Additionally, the surface treatment layer has a third width that is smaller than the first width and larger than the second width, and the surface treatment layer comprises a first portion disposed on the upper surface of the upper pad and a second portion extending from the first portion and disposed on the upper surface of the first protective layer.Additionally, the build-up insulating layer comprises an inner insulating layer; a first outermost insulating layer disposed on the inner insulating layer; and a second outermost insulating layer disposed below the inner insulating layer, wherein the first pad is disposed on the first outermost insulating layer, and the package substrate comprises a second pad disposed on the second outermost insulating layer; a first via penetrating at least a portion of the inner insulating layer along the vertical direction; a second via penetrating at least a portion of the first outermost insulating layer along the vertical direction and connected to the first pad; and a third via penetrating at least a portion of the second outermost insulating layer along the vertical direction and connected to the second pad, wherein the first to third vias have different widths in the horizontal direction. Additionally, the first via has a width greater than the width of the second via and a width smaller than the width of the third via, and the second via has a width smaller than the width of the third via. Effects of the invention

[0025] In the embodiment, the circuit pattern layer comprises a pad composed of a seed layer, a first pattern, a second pattern, and a surface treatment layer. At this time, the surface treatment layer comprises a first portion disposed on the upper surface of the second pattern and a second portion extending from the first portion and disposed on the upper surface of the protective layer. Accordingly, in the embodiment, the surface treatment layer including the second portion as described above can secure a large placement space for an adhesive member (not shown) for mounting a chip, and thereby improve chip bonding performance. That is, in the embodiment, the width of the surface treatment layer is made larger than the width of the second pattern, and accordingly, the contact area with the adhesive member is widened, thereby improving bonding performance with an adhesive member such as a solder ball or wire.

[0026] In addition, since the second part is positioned on the upper surface of the protective layer, the protective layer can support the second part when an adhesive member (not shown) for mounting the chip is positioned, so unlike a conventional overhang structure (a structure in which the end of the surface treatment layer is spaced apart from the first and second pads and the protective layer), the surface treatment layer can be prevented from being damaged by the adhesive member.

[0028] In addition, in the embodiment, the upper surface of the second pattern is positioned higher than the upper surface of the protective layer. Accordingly, in the embodiment, the resin of the protective layer can be prevented from remaining on the upper surface of the second pattern, thereby exposing the entire upper surface of the pad from the protective layer. Consequently, the entire upper surface of the pad can be used for connection with the chip, which increases circuit integration density and improves reliability. Furthermore, in the embodiment, the surface treatment layer is positioned on a part of the side of the protruding second pattern to improve the contact area between the surface treatment layer and the second pattern.

[0029] In addition, in the embodiment, at least one side of the seed layer, the first pattern, and the second pattern constituting the pad is made to have a rounded curved surface. Accordingly, in the embodiment, as at least one side of the seed layer, the first pattern, and the second pattern has a rounded curved surface, the contact area between the interface with the protective layer can be increased, and the adhesion with the protective layer can be improved accordingly. Furthermore, when forming the protective layer, lifting (forming an air layer between the protective layer and the pad) between the pad and the protective layer can be prevented, thereby preventing the detachment of the protective layer. Brief explanation of the drawing

[0030] FIG. 1 is a drawing showing a circuit board according to a first embodiment. Figure 2 is an enlarged view of the pad of the third circuit pattern layer of Figure 1. FIGS. 3 to 15 are drawings showing the first manufacturing method of the circuit board illustrated in FIG. 1 in process order. FIGS. 16 and FIGS. 17 are drawings for explaining a second method of manufacturing a circuit board illustrated in FIGS. 1. FIG. 18 is a drawing showing a circuit board according to a second embodiment. FIG. 19 is a drawing showing a circuit board according to a third embodiment. FIG. 20 is a drawing showing a package substrate according to an embodiment. Specific details for implementing the invention

[0031] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the attached drawings. Identical or similar components regardless of drawing symbols are assigned the same reference number, and redundant descriptions thereof will be omitted. The suffixes "module" and "part" for components used in the following description are assigned or used interchangeably solely for the ease of drafting the specification and do not inherently possess distinct meanings or roles. Furthermore, in describing the embodiments disclosed in this specification, if it is determined that a detailed description of related prior art could obscure the essence of the embodiments disclosed in this specification, such detailed description will be omitted. Additionally, the attached drawings are intended only to facilitate easy understanding of the embodiments disclosed in this specification; the technical concept disclosed in this specification is not limited by the attached drawings and should be understood to include all modifications, equivalents, and substitutions that fall within the spirit and technical scope of the present invention.

[0032] Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. These terms are used solely for the purpose of distinguishing one component from another.

[0033] When it is stated that one component is "connected" or "connected" to another component, it should be understood that while it may be directly connected or connected to that other component, there may also be other components in between. On the other hand, when it is stated that one component is "directly connected" or "directly connected" to another component, it should be understood that there are no other components in between.

[0034] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0035] In this application, terms such as “comprising” or “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0036] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0038] FIG. 1 is a drawing showing a circuit board according to a first embodiment, and FIG. 2 is an enlarged view of the third circuit pattern layer of FIG. 1.

[0039] Referring to FIGS. 1 and 2, the circuit board includes an insulating layer (110), a circuit pattern layer, vias, and a protective layer.

[0040] The insulating layer (110) may have a plurality of layer structures. For example, the insulating layer (110) may include a first insulating layer (111), a second insulating layer (112), and a third insulating layer (113). In this case, the circuit board is shown in the drawing as having a three-layer structure based on the number of insulating layers, but it is not limited thereto. For example, the circuit board may have a structure of two layers or fewer based on the number of insulating layers, or it may have a structure of four layers or more.

[0041] For example, the first insulating layer (111) may be an inner insulating layer positioned on the inside in a multilayer structure. Also, the second insulating layer (112) may be a first outermost insulating layer positioned on the first outermost side in a multilayer structure. Additionally, the third insulating layer (113) may be a second outermost insulating layer positioned on the second outermost side in a multilayer structure. Furthermore, although the inner insulating layer is depicted as being composed of one layer, it may be composed of two or more layers.

[0042] The insulating layer (110) is a substrate on which an electrical circuit capable of changing wiring is organized, and may include a printed circuit board and an insulating substrate made of an insulating material capable of forming circuit patterns on its surface.

[0043] For example, at least one of the insulating layers (110) may be rigid or flexible. For example, at least one of the insulating layers (110) may include glass or plastic. Specifically, at least one of the insulating layers (110) may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG) polycarbonate (PC), or sapphire.

[0044] Additionally, at least one of the insulating layers (110) may include an optically isotropic film. For example, at least one of the insulating layers (110) may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), optically isotropic polycarbonate (PC), or optically isotropic polymethyl methacrylate (PMMA).

[0045] In addition, at least one of the insulating layers (110) may be formed from a material comprising an inorganic filler and an insulating resin. For example, as a material constituting the insulating layer (110), a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, and a resin containing reinforcing materials such as inorganic fillers such as silica and alumina may be used, specifically ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), PID (Photo Imagable Dielectric Resin), BT, etc.

[0046] Additionally, at least one of the insulating layers (110) may be partially curved and bent. That is, at least one of the insulating layers (110) may be partially flat and partially curved and bent. Specifically, at least one of the insulating layers (110) may be bent or bent with a curved end or a surface including random curvature.

[0047] A circuit pattern layer can be placed on the surface of the insulating layer (110).

[0048] For example, a first circuit pattern layer (120) may be disposed on the first surface of the first insulating layer (111). For example, a second circuit pattern layer (130) may be disposed on the second surface of the first insulating layer (111). For example, a third circuit pattern layer (140) may be disposed on the first surface of the second insulating layer (112). For example, a fourth circuit pattern layer (150) may be disposed on the second surface of the third insulating layer (113). The first circuit pattern layer (120) and the second circuit pattern layer (130) may be described as inner circuit pattern layers disposed on the surface of the inner insulating layer. Furthermore, the third circuit pattern layer (140) and the fourth circuit pattern layer (150) may be described as outer or outermost circuit pattern layers disposed on the outermost insulating layer.

[0049] The first circuit pattern layer (120), the second circuit pattern layer (130), the third circuit pattern layer (140), and the fourth circuit pattern layer (150) are wirings that transmit electrical signals and can be formed from a metal material with high electrical conductivity. To this end, the first circuit pattern layer (120), the second circuit pattern layer (130), the third circuit pattern layer (140), and the fourth circuit pattern layer (150) can be formed from at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Additionally, the first circuit pattern layer (120), the second circuit pattern layer (130), the third circuit pattern layer (140), and the fourth circuit pattern layer (150) may be formed from a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first circuit pattern layer (120), the second circuit pattern layer (130), the third circuit pattern layer (140), and the fourth circuit pattern layer (150) may be formed from copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0050] The first circuit pattern layer (120), second circuit pattern layer (130), third circuit pattern layer (140), and fourth circuit pattern layer (150) can be manufactured using conventional printed circuit board manufacturing processes such as the additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process), and a detailed description is omitted here.

[0051] Meanwhile, each of the third circuit pattern layer (140) and the fourth circuit pattern layer (150) includes a trace and a pad.

[0052] Specifically, the third circuit pattern layer (140) may include a pad (140P) and a trace (140T). Additionally, the fourth circuit pattern layer (150) may include a pad (150P) and a trace (150T). The trace (140T, 150T) refers to a long line-shaped wiring that transmits an electrical signal. Furthermore, the pad (140P, 150P) may be a mounting pad on which a component such as a chip is mounted, or a core pad or BGA pad for connection with an external board. Accordingly, the pad (140P) may also be referred to as the 'first pad', and the pad (150P) may also be referred to as the 'second pad'.

[0053] Specifically, the pad (140P) of the third circuit pattern layer (140) may be a mounting pad on which a component such as a chip is mounted. Additionally, the pad (150P) of the fourth circuit pattern layer (140) may be a core pad or a BGA pad for connection with an external board, but is not limited thereto. Meanwhile, the pad (140P) of the third circuit pattern layer (140) may be narrower than the pad (150P) of the fourth circuit pattern layer (150).

[0054] The surface of the pad (140P) of the third circuit pattern layer (140) may be exposed by the first protective layer (160) disposed on the first surface of the second insulating layer (112). Additionally, the surface of the pad (150P) of the fourth circuit pattern layer (150) may be exposed by the second protective layer (170) disposed on the second surface of the third insulating layer (113).

[0055] The third circuit pattern layer (140) may have a plurality of layer structures. In this case, the pads (140P) and traces (140T) of the third circuit pattern layer (140) may have different layer structures. For example, the number of layers of the pads (140P) may be greater than the number of layers of the traces (140T). For example, the traces (140T) may include only some of the layers among the plurality of layers constituting the pads (140P).

[0056] For example, the pad (140P) of the third circuit pattern layer (140) includes a first pattern (142) disposed on the first surface of the second insulating layer (112) and a second pattern (143) disposed on the first pattern (142). In the embodiment, the pad (140P) of the third circuit pattern layer (140) is configured to have a two-layer structure. Accordingly, in the embodiment, the pad (140P) of the third circuit pattern layer (140) is configured to protrude above a certain height relative to the first surface of the second insulating layer (112). Accordingly, in the embodiment, as the pad (140P) of the third circuit pattern layer (140) has above a certain height, ease of the chip mounting process can be improved.

[0057] The first pattern (142) and the second pattern (143) may each contain the same metallic material. For example, the first pattern (142) may contain copper. And, the second pattern (143) may contain copper, which is the same metallic material as the first pattern (142).

[0058] Additionally, the pad (140P) of the third circuit pattern layer (140) may include a seed layer (141) disposed between the first surface of the second insulating layer (112) and the first pattern (142). The seed layer (141) may be a seed layer used to form the first pattern (142) and the second pattern (143). For example, the first pattern (142) and the second pattern (143) may be formed by an electroplating process. Accordingly, the seed layer (141) may be a seed layer for electroplating the first pattern (142) and the second pattern (143), respectively.

[0059] The pad (140P) of the third circuit pattern layer (140) may include a surface treatment layer (144) disposed on the second pattern (143). The surface treatment layer (144) may be formed to protect the surface of the pad (140P) or to increase the bonding properties of the pad (140P). The surface treatment layer (144) may include gold (Au). For example, the surface treatment layer (144) may include only a gold metal layer. And, the gold metal layer may be formed directly on the second pattern (143) which includes copper. Alternatively, the surface treatment layer (144) may be an ENEPIG layer. For example, the surface treatment layer (144) may include a nickel metal layer, a palladium metal layer, and a gold metal layer.

[0060] Meanwhile, the trace (140T) of the third circuit pattern layer (140) may include only some of the layers constituting the pad (140P). For example, the trace (140T) of the third circuit pattern layer (140) may include the seed layer (141) and the first pattern (142). Accordingly, in the embodiment, the seed layer (141) and the first pattern (142) may be formed to form a part of the pad (140P) of the third circuit pattern layer (140) and the trace (140T). In addition, in the embodiment, the pad (140P) may be formed by forming a second pattern (143) and a surface treatment layer (144) on the area corresponding to the pad (140P) among the formed first pattern (142).

[0061] The pad (150P) of the fourth circuit pattern layer (150) may have a structure substantially identical to the pad (140P) of the third circuit pattern layer (140). For example, the pad (150P) of the fourth circuit pattern layer (150) may include a seed layer (151), a first pattern (152), a second pattern (153), and a surface treatment layer (154). At this time, the seed layer (151), the first pattern (152), the second pattern (153), and the surface treatment layer (154) constituting the pad (150P) of the fourth circuit pattern layer (150) have a layer structure substantially identical to the seed layer (141), the first pattern (142), the second pattern (143), and the surface treatment layer (144) constituting the pad (140P) of the third circuit pattern layer (140), and accordingly, a detailed description thereof is omitted.

[0062] Additionally, the trace (150T) of the fourth circuit pattern layer (150) may include a seed layer (151) and a first pattern (152) which are part of the layer constituting the pad (150P), corresponding to the trace (140T) of the third circuit pattern layer (140).

[0063] The third circuit pattern layer may be a mounting pad on which a component such as a chip is mounted. The fourth circuit pattern layer may be a core pad or a BGA pad for connection with an external board. The pad of the fourth circuit pattern layer (150) may be wider than the pad of the third circuit pattern layer.

[0064] A first protective layer (160) may be disposed on the first surface of the second insulating layer (112). The first protective layer (160) may include a solder resist. The first protective layer (160) may include an opening (not shown) that exposes the surface of the pad (140P) of the third circuit pattern layer (140). For example, the first protective layer (160) may expose the surface of the second pattern (143) constituting the pad (140P) of the third circuit pattern layer (140).

[0065] The first protective layer (160) may be positioned to cover the side of the seed layer (141) of the third circuit pattern layer (140). Additionally, the first protective layer (160) may be positioned to cover the side of the first pattern (142) of the pad (140P). Additionally, the first protective layer (160) may be positioned to cover a portion of the upper surface of the first pattern (142) of the pad (140P). Additionally, the first protective layer (160) may be positioned to cover the side of the second pattern (143) of the pad (140P).

[0066] In the first embodiment, the upper surface of the first protective layer (160) may be located on the same plane as the upper surface of the second pattern (143) of the third circuit pattern layer (140).

[0067] Correspondingly, a second protective layer (170) may be disposed on the second surface of the third insulating layer (113). The second protective layer (170) may include a solder resist. The second protective layer (170) may include an opening (not shown) that exposes the surface of the pad (150P) of the fourth circuit pattern layer (150). For example, the second protective layer (170) may expose the surface of the second pattern (153) constituting the pad (150P) of the fourth circuit pattern layer (150).

[0068] The second protective layer (170) may be positioned to cover the side of the seed layer (151). Additionally, the second protective layer (170) may be positioned to cover the side of the first pattern (152) of the pad (150P) of the fourth circuit pattern layer (150). Additionally, the second protective layer (170) may cover a portion of the lower surface of the first pattern (152) of the pad (150P) of the fourth circuit pattern layer (150). Additionally, the second protective layer (170) may be positioned to cover the side of the second pattern (153) of the pad (150P) of the fourth circuit pattern layer (150).

[0069] In addition, in the first embodiment, the lower surface of the second protective layer (170) may be located on the same plane as the lower surface of the second pattern (153) of the pad (150P) of the fourth circuit pattern layer (150).

[0070] Meanwhile, the circuit board of the embodiment includes vias. The vias can electrically connect circuit pattern layers disposed on different layers. For example, a first via (V1) may be formed in the first insulating layer (111). The first via (V1) penetrates the first insulating layer (111) and, accordingly, can electrically connect the first circuit pattern layer (120) and the second circuit pattern layer (130). For example, a second via (V2) may be formed in the second insulating layer (112). The second via (V2) penetrates the second insulating layer (112) and, accordingly, can electrically connect the first circuit pattern layer (120) and the third circuit pattern layer (140). For example, a third via (V3) may be formed in the third insulating layer (113). The third via (V3) penetrates the third insulating layer (113), thereby electrically connecting the second circuit pattern layer (130) and the fourth circuit pattern layer (150).

[0071] The vias (V1, V2, V3) described above can be formed by filling the inside of the via holes formed within each insulating layer with a metallic material. The via holes can be formed by any one of mechanical, laser, and chemical processing methods. When the via holes are formed by mechanical processing, methods such as milling, drilling, and routing can be used; when they are formed by laser processing, UV or CO2 laser methods can be used; and when they are formed by chemical processing, the insulating layer can be opened using a chemical containing aminosilanes, ketones, etc.

[0072] When the via hole is formed, the inside of the via hole can be filled with a conductive material to form the vias (V1, V2, V3). The vias (V1, V2, V3) can be formed from any one of the metal materials selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). Additionally, the filling of the conductive material can be performed using any one of electroless plating, electroplating, screen printing, sputtering, evaporation, inkjetting, and dispensing, or a combination thereof.

[0073] As described above, each pad (140P, 150P) of the third circuit pattern layer (140) and the fourth circuit pattern layer (150) includes a seed layer, a first pattern, a second pattern, and a surface treatment layer. The structure thereof will be described in detail below. However, since the pad (150P) of the fourth circuit pattern layer (150) has substantially the same layer structure as the pad (140P) of the third circuit pattern layer (140), the description will focus on the structure of the pad (140P) of the third circuit pattern layer (140).

[0075] As illustrated in FIG. 2, the third circuit pattern layer (140) includes a pad (140P) and a trace (140T). The pad (140P) includes a seed layer (141), a first pattern (142), a second pattern (143), and a surface treatment layer (144). The trace (140T) may include the seed layer (141) and the first pattern (142). For example, the pad (140P) and the trace (140T) of the third circuit pattern layer (140) may have different layer structures.

[0076] The first pattern (142) may have a first thickness (T1). For example, the first thickness (T1) of the first pattern (142) may satisfy a range of 7 µm to 17 µm. For example, the first thickness (T1) of the first pattern (142) may satisfy a range of 9 µm to 15 µm. For example, the first thickness (T1) of the first pattern (142) may satisfy a range of 10 µm to 13 µm. Here, the first pattern (142) may be a pattern constituting a pad (140P) and a trace (140T).

[0077] The second pattern (143) may be placed on the first pattern (142) having a second thickness (T2) that is thinner than the first thickness (T1) of the first pattern (142). For example, the second thickness (T2) of the second pattern (143) may satisfy a range of 5 µm to 15 µm. For example, the second thickness (T2) of the second pattern (143) may satisfy a range of 7 µm to 13 µm. For example, the second thickness (T2) of the second pattern (143) may satisfy a range of 8 µm to 11 µm.

[0078] Through this, in the embodiment, the overall thickness of the circuit board can be reduced, and the distance from the uppermost surface of the second insulating layer (112), which is the outermost insulating layer of the circuit board, to the lowermost surface mounted on the circuit board can be reduced, thereby reducing the overall thickness of the chip package.

[0079] The surface treatment layer (144) may be disposed on the second pattern (143) having a third thickness (T3) that is thinner than the first thickness (T1) and the second thickness (T2). For example, the third thickness (T3) of the surface treatment layer (144) may satisfy a range of 0.1 μm to 10 μm. For example, the third thickness (T3) of the surface treatment layer (144) may satisfy a range of 0.5 μm to 8 μm. For example, the third thickness (T3) of the surface treatment layer (144) may satisfy a range of 1 μm to 5 μm. However, the third thickness (T3) is the thickness range of the surface treatment layer (144) when the surface treatment layer (144) is composed of the ENEPIG layer described above. For example, the surface treatment layer (144) may include a nickel (Ni) metal layer with a thickness range of 0.002 μm to 0.244 μm formed on the second pattern (143), a palladium (Pd) metal layer with a thickness range of 0.049 μm to 4.878 μm formed on the nickel (Ni) metal layer, and a gold (Au) metal layer with a thickness range of 0.049 μm to 4.478 μm formed on the palladium (Pd) metal layer. However, the embodiment is not limited thereto, and the surface treatment layer (144) may include only a gold (Au) metal layer containing gold (Au). In this case, the third thickness (T3) of the surface treatment layer (144) may have a thickness range lower than the thickness range described above. For example, the thickness of the gold (Au) metal layer may have a range of 0.049 μm to 4.478 μm. For example, the thickness of the gold (Au) metal layer may range from 0.244 μm to 3.902 μm. For example, the thickness of the gold (Au) metal layer may range from 0.488 μm to 2.439 μm.

[0080] The seed layer (141) is disposed between the second insulating layer (112) and the first pattern (142) with a fourth thickness (T4). For example, the fourth thickness (T4) of the seed layer (141) may satisfy a range of 0.5 μm to 5 μm. For example, the fourth thickness (T4) of the seed layer (141) may satisfy a range of 0.8 μm to 3.5 μm. For example, the fourth thickness (T4) of the seed layer (141) may satisfy a range of 1.0 μm to 2.5 μm. Here, the seed layer (141) may be a pattern constituting a pad (140P) and a trace (140T).

[0081] Meanwhile, the first circuit pattern layer (120) corresponding to the inner circuit pattern layer of the circuit board may have a fifth thickness (T5). The fifth thickness (T5) of the first circuit pattern layer (120) may correspond to the first thickness (T1) of the first pattern (142). For example, the fifth thickness (T5) of the first circuit pattern layer (120) may satisfy a range of 7 µm to 17 µm. For example, the fifth thickness (T5) of the first circuit pattern layer (120) may satisfy a range of 9 µm to 15 µm. For example, the fifth thickness (T5) of the first circuit pattern layer (120) may satisfy a range of 10 µm to 13 µm. However, if the first circuit pattern layer (120) includes a seed layer, the first circuit pattern layer (120) may correspond to the sum of the fourth thickness (T4) of the seed layer (141) and the fifth thickness (T5) described above.

[0082] The second insulating layer (112) may have a sixth thickness (T6). The sixth thickness (T6) of the second insulating layer (112) may correspond to the distance from the upper surface of the first circuit pattern layer (120) to the upper surface of the second insulating layer (112). For example, the sixth thickness (T6) of the second insulating layer (112) may satisfy a range of 10 µm to 30 µm. For example, the sixth thickness (T6) of the second insulating layer (112) may satisfy a range of 15 µm to 25 µm. For example, the sixth thickness (T6) of the second insulating layer (112) may satisfy a range of 18 µm to 23 µm.

[0083] Meanwhile, the seed layer (141), first pattern (142), second pattern (143), and surface treatment layer (144) of the pad (140P) constituting the third circuit pattern layer (140) may have different widths.

[0084] The first pattern (142) of the pad (140P) may have a first width (W1). For example, the first width (W1) of the first pattern (142) of the pad (140P) may satisfy a range of 5 µm to 300 µm. For example, the first width (W1) of the first pattern (142) of the pad (140P) may satisfy a range of 70 µm to 200 µm. For example, the first width (W1) of the first pattern (142) of the pad (140P) may satisfy a range of 100 µm to 150 µm.

[0085] The second pattern (143) of the pad (140P) may be disposed on the first pattern (142) of the pad (140P) having a second width (W2) that is smaller than the first width (W1) of the first pattern (142). For example, the second width (W2) of the second pattern (143) of the pad (140P) may satisfy a range of 3 µm to 250 µm. For example, the second width (W2) of the second pattern (143) of the pad (140P) may satisfy a range of 50 µm to 150 µm. For example, the second width (W2) of the second pattern (143) of the pad (140P) may satisfy a range of 60 µm to 100 µm.

[0086] Accordingly, the upper surface of the first pattern (142) of the pad (140P) may include a first portion that is in direct contact with the lower surface of the second pattern (143) and a second portion other than the first portion. Additionally, the second portion of the upper surface of the first pattern (142) may be in direct contact with the first protective layer (160).

[0087] Additionally, the width of the first part of the first pattern (142) of the pad (140P) may be greater than the width of the second part. Because a portion of the pad (140P) is formed on the lower part of the first protective layer (160) through the second part, it is possible to prevent the pad (140P) from being separated and detached from the circuit board. Furthermore, because the thickness of the first pattern (142) is formed to be thicker than the thickness of the second pattern (143), adhesive strength can be secured so that the pad is not separated from the circuit board even if the width of the second part is smaller than the first part. For example, if the thickness of the first pattern (142) is thinner than the thickness of the second pattern (143), when connecting with a chip mounted on the circuit board, the first pattern (142) cannot support the second pattern (143) when it is detached, and thus the pad (140P) may be detached from the circuit board. In addition, in the embodiment, by forming the width of the first part larger than the width of the second part, it is possible to facilitate connection with the chip mounted on the circuit board.

[0088] The surface treatment layer (144) may be disposed on the second pattern (143) having a third width (W3) that is smaller than the first width (W1) of the first pattern (142) of the pad (140P) and larger than the second width (W2) of the second pattern (143). For example, the third width (W3) of the surface treatment layer (144) may satisfy a range of 4 µm to 280 µm. For example, the third width (W3) of the surface treatment layer (144) may satisfy a range of 70 µm to 180 µm. For example, the third width (W3) of the surface treatment layer (144) may satisfy a range of 80 µm to 120 µm.

[0089] Meanwhile, the first pattern (142) of the trace (140T) may have a different width from the first pattern of the pad (140P). For example, the first pattern (142) of the trace (140T) may have a fourth width (W4) that is narrower than the first width (W1) of the first pattern of the pad (140P). The fourth width (W4) of the first pattern (142) of the trace (140T) may satisfy a range of 0.5㎛ to 20㎛. For example, the fourth width (W4) of the first pattern (142) of the trace (140T) may satisfy a range of 0.8㎛ to 15㎛. For example, the fourth width (W4) of the first pattern (142) of the trace (140T) may satisfy a range of 1.0㎛ to 10㎛.

[0090] Meanwhile, the traces (140T) may be formed in multiple numbers spaced apart from each other on the second insulating layer (112). At this time, among the multiple traces, adjacent traces (140T) may be spaced apart by a fifth width (W5). The fifth width (W5) corresponding to the spacing of the traces (140T) may satisfy a range of 0.5 μm to 20 μm. For example, the fifth width (W5) may satisfy a range of 0.8 μm to 15 μm. For example, the fifth width (W5) may satisfy a range of 1.0 μm to 10 μm.

[0091] Meanwhile, in the first embodiment, the upper surface of the second pattern (143) may be located on the same plane as the upper surface of the first protective layer (160).

[0092] Accordingly, the surface treatment layer (144) may include a first portion disposed on the upper surface of the second pattern (143) and a second portion extending from the first portion. For example, the lower surface of the surface treatment layer (144) may include a first portion of the surface treatment layer (144) in direct contact with the upper surface of the second pattern (143) and a second portion of the surface treatment layer (144) in direct contact with the upper surface of the first protective layer (160). In this case, when forming the surface treatment layer (144) in the embodiment, the opening of the mask (not shown) is configured to have the third width (W3) between the first width (W1) and the second width (W2). Accordingly, in the embodiment, the surface treatment layer (144) may be formed in part on the upper surface of the first protective layer (160) by extending from the upper surface of the second pattern (143).

[0093] In addition, in the embodiment, the surface treatment layer (144) may be plated using the seed layer (141), the second pattern (142), and the second pattern (142) without a mask. At this time, the width of the first portion of the surface treatment layer (144) may be larger than the width of the second portion of the surface treatment layer (144). Accordingly, by forming a wide width of the first portion of the surface treatment layer (144) where the surface treatment layer (144) and the second pattern (143) are in direct contact with each other, the surface treatment layer (144) may be prevented from detaching from the second pattern (143), thereby improving the adhesion between the protective layer and the pad (140P). Accordingly, in the embodiment, a wider placement space for an adhesive member (not shown) for mounting a chip may be secured, and the chip bonding performance may be improved. That is, in the embodiment, the width of the surface treatment layer (144) is made larger than the width of the second pattern (143), and accordingly, the contact area with the adhesive member (not shown) is widened, thereby improving bonding performance with an adhesive member such as a solder ball or wire.

[0094] Meanwhile, the first circuit pattern layer (120) and the third circuit pattern layer (140) may have different surface roughness (Ra). For example, the inner circuit pattern layer in the embodiment may have a different surface roughness (Ra) than the outer circuit pattern layer.

[0095] For example, the first circuit pattern layer (120) may have a first surface roughness (Ra). The first surface roughness (Ra) may have a range between 0.83 μm and 1.0 μm. That is, the first circuit pattern layer (120) is roughened to improve adhesion with the second insulating layer (112), and accordingly, may have a first surface roughness (Ra) in the range of 0.83 μm to 1.0 μm.

[0096] The third circuit pattern layer (140) may have a second surface roughness (Ra) smaller than that of the first circuit pattern layer (120). For example, the second surface roughness (Ra) may satisfy a range of 0.70 μm to 0.82 μm. For example, the second surface roughness (Ra) of the first pattern (141) may satisfy a range of 0.70 μm to 0.82 μm. For example, the second surface roughness (Ra) of the second pattern (142) may satisfy a range of 0.70 μm to 0.82 μm. For example, the second surface roughness (Ra) of the surface treatment layer (144) may satisfy a range of 0.70 μm to 0.82 μm.

[0097] That is, in the embodiment, the second surface roughness (Ra) may be greater than the first surface roughness (Ra). The first circuit pattern layer (120) must be treated with a larger roughness to improve adhesion with the second insulating layer (112), and the pad (140P) of the third circuit pattern layer (140) may be treated with a relatively smaller roughness because it requires a roughness to make contact with a contact member for connection with the protective layer or a chip or main printed circuit board mounted on the circuit board. Furthermore, the pad (140P) of the third circuit pattern layer (140) may be formed with only the roughness generated by the etching process of the seed layer (141) as shown in FIG. 12, without any separate roughness treatment.

[0098] Meanwhile, the first protective layer (160) may have a third surface roughness (Ra) between the first surface roughness (Ra) and the second surface roughness (Ra). For example, the third surface roughness (Ra) of the first protective layer (160) may satisfy a range between 0.80 μm and 0.90 μm. The surface roughness of the first protective layer (160) is not specifically limited, but it is sufficient to ensure adhesion with the molding layer during the process of mounting and molding a chip on the first protective layer (160).

[0100] FIGS. 3 to 15 illustrate a first manufacturing method of a circuit board illustrated in FIG. 1 in process order, and FIGS. 16 and 17 are drawings for explaining a second manufacturing method of a circuit board illustrated in FIG. 1.

[0101] Hereinafter, with reference to the attached drawings, a method for manufacturing a circuit board illustrated in FIG. 1 will be described in detail.

[0102] Referring to FIG. 3, in the embodiment, a first insulating layer (111) is prepared. Then, in the embodiment, once the first insulating layer (111) is prepared, a process of forming a first circuit pattern layer (120), a second circuit pattern layer (130), and a first via (V1) on the first insulating layer (111) can be carried out. Briefly, once the first insulating layer (111) is prepared, a process of forming a seed layer (not shown) on one or both surfaces of the first insulating layer (111) can be carried out. At this time, the first insulating layer (111) may be a Copper Clad Laminate (CCL), and accordingly, the seed layer may be a copper foil layer constituting the CCL. Alternatively, the seed layer may be formed on at least one of the first surface and the second surface of the first insulating layer (111) through electroless plating. Next, in the embodiment, a process of forming a first via hole in the first insulating layer (111) on which the seed layer is formed may be carried out. Subsequently, in the embodiment, a mask (not shown) including an opening may be formed on at least one of the first surface and the second surface of the first insulating layer (111), and plating may be carried out within the opening of the mask to form at least one circuit pattern layer among the first circuit pattern layer (120) and the second circuit pattern layer (130), and a first via (V1).

[0103] Next, referring to FIG. 4, in the embodiment, a process may be performed to laminate a second insulating layer (112) on the first surface of the first insulating layer (111) and to laminate a third insulating layer (113) on the second surface of the first insulating layer (111). At this time, a metal layer (141, 151) may be formed on the first surface of the second insulating layer (112) and the second surface of the third insulating layer (113), respectively. The metal layer (141, 151) may be used as a seed layer for forming the third circuit pattern layer (140) and the fourth circuit pattern layer (150). Accordingly, the metal layer (141, 151) may also be referred to as a seed layer.

[0104] Next, referring to FIG. 5, in the embodiment, a process can be carried out to form a second via hole (VH2) penetrating the second insulating layer (112) and the seed layer (141) disposed on the first surface thereof, and to form a third via hole (VH3) penetrating the third insulating layer (113) and the seed layer (151) disposed on the second surface thereof.

[0105] Next, referring to FIG. 6, in an embodiment, a process of forming a first mask (M1) on the seed layer (141, 151) can be carried out. At this time, the first mask (M1) placed on the seed layer (141) on the second insulating layer (112) may include an opening (not shown) that opens an area where the second via (V2) and the third circuit pattern layer (140) are to be formed. Additionally, the first mask (M1) placed on the seed layer (151) on the third insulating layer (113) may include an opening (not shown) that opens an area where the third via (V3) and the fourth circuit pattern layer (150) are to be formed.

[0106] Next, referring to FIG. 7, in the embodiment, electroplating can be performed using the seed layers (141, 151). Specifically, in the embodiment, a metal material can be filled into the opening of the first mask (M1) to form a first-1 plating layer (142a), a first-2 plating layer (152a), a second via (V2), and a third via (V3).

[0107] The first-1 plating layer (142a) and the second via (V2) can be formed simultaneously. In addition, the first-1 plating layer (142a) and the second via (V2) can be formed simultaneously from the same material.

[0108] At this time, the first-1 plating layer (142a) may correspond to the first pattern (142) of the pad (140P) and trace (140T) of the third circuit pattern layer (140) described above, and the first-2 plating layer (152a) may correspond to the first pattern (152) of the pad (150P) and trace (150T) of the fourth circuit pattern layer (150). However, the first-1 plating layer (142a) may be thicker than the thickness of the first pattern (142) of the third circuit pattern layer (140), and the first-2 plating layer (152a) may be thicker than the thickness of the first pattern (152) of the fourth circuit pattern layer (150).

[0109] Next, referring to FIGS. 8 and 9, a first grinding process may be performed in the embodiment. The first grinding process can prevent warpage or poor connection between vias from occurring when forming multiple insulating layers, as the upper surface of the first-1 plating layer (142a) is not flat due to a dimple phenomenon (a phenomenon in which the central part in the width direction of the first-1 plating layer (142a) or the second via (V2) is formed indented (not shown)) caused by the second via hole (VH2) when forming the first-1 plating layer (142a) and the second via (V2) through plating.

[0110] At this time, the first grinding process may include a first process of grinding the first mask (M1) and the first-1 plating layer (142a) together to form a first pattern (142) of the third circuit pattern layer (140), and a second process of grinding the first mask (M1) and the first-2 plating layer (152a) together to form a first pattern (152) of the fourth circuit pattern layer (150). By the first grinding process, the first pattern (142) of the third circuit pattern layer (140) and the first pattern (152) of the fourth circuit pattern layer (150) each have the first thickness (T1) described above. In the embodiment, when the first grinding process is completed, a process of peeling off the first mask (M1) may be performed. However, the embodiments are not limited thereto, and the next process can be carried out without the peeling process of the first mask (M1).

[0111] That is, referring to FIG. 10, when the first grinding process is completed, the embodiment may proceed with the process of forming a second mask (M2). At this time, the second mask (M2) may be formed after removing the first mask (M1), or alternatively, it may be formed on the first mask (M1). However, the second mask (M2) may have an opening smaller than the opening of the first mask (M1). Accordingly, at least a portion of the second mask (M2) may be placed on the first pattern (142) of the third circuit pattern layer (140) and the first pattern (142) of the fourth circuit pattern layer (150).

[0112] Next, referring to FIG. 11, in the embodiment, electroplating can be performed using the seed layers (141, 151). Specifically, in the embodiment, a metal material can be filled into the opening of the second mask (M2) to form a second-1 plating layer (143a) and a second-2 plating layer (153a).

[0113] At this time, the second-1 plating layer (143a) may correspond to the second pattern (143) of the pad (140P) of the third circuit pattern layer (140) described above, and the second-2 plating layer (153a) may correspond to the second pattern (153) of the pad (150P) of the fourth circuit pattern layer (150). However, the second-1 plating layer (143a) may be thicker than the thickness of the second pattern (143) of the third circuit pattern layer (140), and the second-2 plating layer (153a) may be thicker than the thickness of the second pattern (153) of the fourth circuit pattern layer (150).

[0114] Next, referring to FIG. 12, in the embodiment, a process of removing the second mask (M2) can be performed. Then, in the embodiment, when the second mask (M2) is removed, a process of etching the seed layer (141, 151) can be performed. Specifically, in the embodiment, among the seed layer (141) disposed on the first surface of the second insulating layer (112), the area that does not overlap in a vertical direction with the first pattern (141) can be etched and removed. Additionally, in the embodiment, among the seed layer (151) disposed on the second surface of the third insulating layer (113), the area that does not overlap in a vertical direction with the first pattern (151) can be etched and removed.

[0115] Next, referring to FIG. 13, in an embodiment, a first solder resist layer (160a) can be formed on the second insulating layer (112). At this time, the first solder resist layer (160a) may have the same height as the second-1 plating layer (143a). Additionally, in an embodiment, a second solder resist layer (170a) may be formed on the third insulating layer (113). At this time, the second solder resist layer (170a) may have the same height as the second-2 plating layer (153a).

[0116] Next, referring to FIG. 14, a second grinding process may be performed in the embodiment. That is, the embodiment may include a first process of grinding the first solder resist layer (160a) and the second-1 plating layer (143a), and a second process of grinding the second solder resist layer (170a) and the second-2 plating layer (153a). Accordingly, in the embodiment, the first solder resist layer (160a) and the second-1 plating layer (143a) may be ground to form a second pattern (143) of the pad (140P) of the first protective layer (160) and the third circuit pattern layer (140). Additionally, in the embodiment, the second solder resist layer (170a) and the second-2 plating layer (153a) can be ground to form the second pattern (153) of the pad (150P) of the second protective layer (170) and the fourth circuit pattern layer (150).

[0117] However, the above second grinding process may be omitted. For example, the second-1 plating layer (143a) may be formed with a thickness corresponding to the second pattern (143) of the pad (140P) of the third circuit pattern layer (140), and the second-2 plating layer (153a) may be formed with a thickness corresponding to the second pattern (153) of the pad (150P) of the fourth circuit pattern layer (150), and in such cases, the above second grinding process may be omitted. However, the above second grinding process may be added to improve reliability in case the thickness control of the second pattern (143, 153) is incorrect due to difficulty in controlling process conditions when forming the second pattern (143, 153) of the pad (140P, 150P).

[0118] Next, referring to FIG. 15, in the embodiment, a process of forming a surface treatment layer (144) on the first protective layer (160) and the second pattern (143) of the pad (140P) of the third circuit pattern layer (140) can be carried out. Additionally, in the embodiment, a process of forming a surface treatment layer (154) on the second protective layer (170) and the second pattern (153) of the pad (150P) of the fourth circuit pattern layer (150) can be carried out.

[0119] Meanwhile, in the above, when manufacturing the circuit board, a secondary grinding process was performed after the solder resist layer forming the first protective layer (160) and the second protective layer (170) was formed. Accordingly, the first protective layer (160) and the second protective layer (170) could have the same height as the second pattern (143, 153) by the secondary grinding process.

[0120] Alternatively, referring to FIG. 16, in another embodiment, after the manufacturing of FIG. 11 is completed, a secondary grinding process can be performed to grind the second mask (M2), the second-1 plating layer (143a), and the second-2 plating layer (153a). Accordingly, referring to FIG. 16, the second pattern (143, 153) of the pads (140P, 150P) of the third circuit pattern layer (140) and the fourth circuit pattern layer (150) can be formed before the solder resist layer is formed.

[0121] Next, referring to FIG. 17, in the embodiment, first and second solder resist layers (160a, 170a) covering the second pattern (143, 153) can be formed on the second insulating layer (112) and the third circuit pattern layer (140). In the embodiment, the height of the first and second solder resist layers (160a, 170a) can be adjusted by performing a dipping process. That is, as shown in FIG. 17, the first protective layer (160) and the second protective layer (170) can have the same height as the second pattern (142, 153) through an exposure and development process rather than a grinding process.

[0123] FIG. 18 is a drawing showing a circuit board according to a second embodiment.

[0124] Referring to FIG. 18, the circuit board according to the second embodiment is identical to the circuit board of the first embodiment of FIG. 1 and FIG. 2 except for the structure of the second pad and the surface treatment layer, and accordingly, only the second pad and the surface treatment layer will be described.

[0125] The circuit board includes an insulating layer (212), a first circuit pattern layer (212) corresponding to an inner circuit pattern layer, vias (V2), pads, and a first protection layer (260).

[0126] And, the circuit board includes a third circuit pattern layer (240) corresponding to the first outermost circuit pattern layer. Additionally, the third circuit pattern layer (240) includes pads (240P) and traces (240T).

[0127] The trace (240T) of the third circuit pattern layer (240) may include a seed layer (241) and a first pattern (242). Additionally, the pad (240P) of the third circuit pattern layer (240) includes a seed layer (241), a first pattern (242), a second pattern (243), and a surface treatment layer (244).

[0128] At this time, the upper surface of the second pattern (143) of the pad (140P) in the first embodiment and the upper surface of the first protective layer (160) were located on the same plane.

[0129] Alternatively, the upper surface of the second pattern (243) of the pad (240P) in the second embodiment may be located on a different plane from the upper surface of the first protective layer (260). Specifically, the upper surface of the first protective layer (260) may be located lower than the upper surface of the second pattern (243).

[0130] That is, the first protective layer (260) is formed by removing the solder resist layer through grinding or dipping as described above. At this time, when the first protective layer (260) is formed through grinding, the solder resist layer may be polished more than the second pattern (243) due to the difference in hardness between the second pattern (243) and the solder resist layer. Accordingly, the upper surface of the first protective layer (260) may be positioned lower than the upper surface of the second pattern (243) as described above.

[0131] In contrast, in the embodiment, to increase the reliability of the surface of the second pattern (243), the upper surface of the first protective layer (260) is positioned lower than the upper surface of the second pattern (243) as described above. That is, the first protective layer (260) is formed by removing the solder resist layer covering the surface of the second pattern (243) as described above. At this time, if a grinding or dipping process is performed so that the upper surface of the first protective layer (260) has the same height as the upper surface of the second pattern (243), a reliability problem may occur in which the upper surface of the second pattern (243) is not completely exposed depending on the process capability. Furthermore, even if the upper surface of the second pattern (243) is completely exposed, the resin that constituted the solder resist layer may remain on the upper surface of the second pattern (243). Accordingly, in the embodiment, to solve the above problem, the upper surface of the first protective layer (260) is positioned lower than the upper surface of the second pattern (243).

[0132] Accordingly, the surface treatment layer (244) in the second embodiment is formed not only on the upper surface of the second pattern (243) but also on a part of its side. That is, the second pattern (243) includes a protruding area that protrudes from the upper surface of the first protective layer (260).

[0133] And, the surface treatment layer (244) may include a first portion disposed on the upper surface of the protruding area of ​​the second pattern (243) and a second portion disposed on the side of the protruding area of ​​the second pattern (243). And, similar to the first embodiment, a portion of the second portion of the second pattern (243) may be in contact with the upper surface of the first protective layer (260).

[0134] At this time, the protruding area of ​​the second pattern (243) may be smaller than the area where the second pattern (243) and the first protective layer (260) meet. That is, the upper surface of the first protective layer (260) may be positioned slightly lower than the upper surface of the second pattern (243). If the protruding area protrudes too much from the upper surface of the first protective layer (260), a problem may occur where the adhesive members between the chips mounted on the circuit board become connected to each other and break, and a break may occur between the solder balls when forming solder balls to connect the main printed circuit board to the circuit board.

[0136] FIG. 19 is a drawing showing a circuit board according to a third embodiment.

[0137] Referring to FIG. 19, the circuit board according to the third embodiment is identical to the circuit board of the first embodiment except for the shape of the seed layer, first pattern, and second pattern constituting the pad of the third circuit pattern layer, which is the outermost circuit pattern layer. Accordingly, only the shape of the seed layer, first pattern, and second pattern constituting the pad will be described.

[0138] First, in the first embodiment, the sides of the seed layer (141), the first pattern (142), and the second pattern (152) of the pad (140P) were planes perpendicular to the upper surface of the first protective layer (160).

[0139] In contrast, in the third embodiment, at least one side of the seed layer (341), the first pattern (342), and the second pattern (343) of the pad (340P) may include a rounded curved surface. That is, referring to FIG. 12, the embodiment includes a process of etching the seed layer in the manufacturing process of the circuit board. At this time, in the embodiment, the etching process time or etching conditions (e.g., etching rate) of the seed layer are adjusted so that not only the seed layer but also a part of the side of the first pattern (342) and / or the side of the second pattern (343) are etched together.

[0140] Accordingly, in the embodiment, at least one of the side of the seed layer (341), the side of the first pattern (342), and the side of the second pattern (343) can be formed into a rounded curved surface by the etching.

[0141] Meanwhile, as in the first embodiment, when the sides of the seed layer (141), the first pattern (142), and the second pattern (152) of the pad (140P) are perpendicular to the upper surface of the first protective layer (160), a problem of air filling the interface between them occurs during the process of forming the first protective layer (160), and a void problem corresponding to the air space occurs.

[0142] In contrast, as in the third embodiment, if at least one side of the seed layer (341), the first pattern (342), and the second pattern (343) of the pad (340P) has a rounded curved surface, the problem of air filling can be solved, and reliability problems such as the void can be solved accordingly.

[0143] Meanwhile, if at least one side of the seed layer (341), first pattern (342), and second pattern (343) of the pad (340P) has a rounded curved surface, the contact area between the interface with the first protective layer can be increased compared to when the side is formed as a flat surface, and the adhesion to the first protective layer (360) can be improved accordingly, thereby preventing the detachment of the first protective layer (360).

[0144] In the embodiment, a pad is included that comprises a seed layer, a first pattern, a second pattern, and a surface treatment layer. At this time, the surface treatment layer includes a first portion disposed on the upper surface of the second pattern and a second portion extending from the first portion and disposed on the upper surface of the protective layer. Accordingly, in the embodiment, the surface treatment layer including the second portion as described above can secure a large placement space for an adhesive member (not shown) for mounting a chip, and thereby improve chip bonding performance. That is, in the embodiment, the width of the surface treatment layer is made larger than the width of the second pattern, and accordingly, the contact area with the adhesive member is widened, thereby improving bonding performance with an adhesive member such as a solder ball or wire.

[0145] In addition, in the embodiment, the upper surface of the second pattern is positioned higher than the upper surface of the protective layer. Accordingly, in the embodiment, the resin of the protective layer can be prevented from remaining on the upper surface of the second pattern, thereby improving reliability. Furthermore, in the embodiment, the surface treatment layer is positioned on a part of the side of the protruding second pattern as well, so that the contact area between the surface treatment layer and the second pattern can be improved.

[0146] In addition, in the embodiment, at least one side of the seed layer, the first pattern, and the second pattern constituting the pad is made to have a rounded curved surface. Accordingly, in the embodiment, as at least one side of the seed layer, the first pattern, and the second pattern has a rounded curved surface, the contact area between the interface with the protective layer can be increased, and the adhesion to the protective layer can be improved accordingly, thereby preventing the protective layer from peeling off.

[0148] FIG. 20 is a drawing showing a package substrate according to an embodiment.

[0149] Referring to FIG. 20, the package substrate (200) includes a circuit board illustrated in at least one of FIG. 1, FIG. 18, and FIG. 19. For convenience of explanation, the following description will focus on a package substrate including the circuit board illustrated in FIG. 1. However, the embodiments are not limited thereto, and the package substrate described below may include the circuit board illustrated in FIG. 18 or FIG. 19.

[0150] Additionally, the package substrate (200) includes an adhesive member disposed on a pad of the circuit board.

[0151] Specifically, the package substrate (200) may include a first adhesive member (210) disposed on a pad (140P) of a third circuit pattern layer (140) of the circuit board. Additionally, the package substrate (200) may include a second adhesive member (240) disposed on a pad (150P) of a fourth circuit pattern layer (150) of the circuit board.

[0152] The first adhesive member (210) and the second adhesive member (240) may have different shapes. For example, the first adhesive member (210) may have a cuboid shape. For example, the cross-section of the first adhesive member (210) may include a rectangular shape. For example, the cross-section of the first adhesive member (210) may include a rectangular or square shape. The second adhesive member (240) may include a spherical shape. For example, the cross-section of the second adhesive member (240) may include a circular or semicircular shape. For example, the cross-section of the second adhesive member (240) may include a partially or entirely rounded shape. As an example, the cross-sectional shape of the second adhesive member (240) may include a flat surface on one side and a curved surface on the other side opposite to the one side. Meanwhile, the second adhesive member (240) may be a solder ball, but is not limited thereto.

[0153] A chip (220) may be mounted on the first adhesive member (210). For example, the chip (220) may include a drive IC chip. For example, the chip (220) may refer to various chips including sockets or components other than a drive IC chip. For example, the chip (220) may include at least one of a diode chip, a power IC chip, a touch sensor IC chip, an MLCC chip, a BGA chip, or a chip capacitor. For example, the chip (220) may be a power management integrated circuit (PMIC). For example, the chip (220) may be a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory. For example, the chip (220) may be an application processor (AP) chip such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, or a microcontroller, or a logic chip such as an analog-to-digital converter or an ASIC (application-specific IC). Here, although the drawing shows only one chip mounted on the package substrate (200), it is not limited thereto. For example, the third circuit pattern layer (140) of the circuit board may include a plurality of mutually spaced pads. And, a chip may be mounted on each of the plurality of pads. For example, the plurality of chips may include a first AP chip corresponding to a central processor (CPU) and a second AP chip corresponding to a graphics processor (GPU).

[0154] A molding layer (230) may be formed on the circuit board. The molding layer (230) may be placed over the mounted chip (220). For example, the molding layer (230) may be an EMC (Epoxy Mold Compound) formed to protect the mounted chip (220), but is not limited thereto.

[0155] Meanwhile, in the embodiment, the first spacing of the plurality of pads (140P) of the third circuit pattern layer (140) may differ from the second spacing of the plurality of pads (150P) of the fourth circuit pattern layer (150). For example, the first spacing of the plurality of pads (140P) of the third circuit pattern layer (140) may correspond to a terminal (not shown) of the chip (220). Additionally, the second spacing of the plurality of pads (150P) of the fourth circuit pattern layer (150) may correspond to a terminal (not shown) of an external board (not shown) attached through the second adhesive member (240). At this time, the first spacing of the plurality of pads (140P) of the third circuit pattern layer (140) may be smaller than the second spacing of the plurality of pads (150P) of the fourth circuit pattern layer (150). For example, the third circuit pattern layer (140) may be a fine pattern corresponding to a terminal (not shown) of the chip (220).

[0156] The vias (V1, V2, V3), the first circuit pattern layer (120), and the second circuit pattern layer (130) of the circuit board can connect the plurality of pads (140P) of the third circuit pattern layer (140) having different spacing and the plurality of pads (150P) of the fourth circuit pattern layer (150).

[0157] At this time, the vias (V1, V2, V3) may have different widths to connect a pad (140P) having a smaller first gap and a pad (150P) having a larger second gap.

[0158] For example, the second via (V2) may have a width corresponding to the first gap of the pad (140P). For example, the third via (V2) may have a width corresponding to the second gap of the pad (150P). For example, the width of the first via (V1) may be between the width of the second via (V2) and the width of the third via (V3). For example, the width of the vias (V1, V2, V3) in the embodiment may gradually decrease as they get closer to the pad (140P) or as they get further away from the pad (150P). For example, the second via (V2) in the embodiment may have the smallest width, the third via (V3) may have the largest width, and the first via (V1) may have a width between the second via (V2) and the third via (V3).

[0160] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment may be combined or modified and implemented in other embodiments by a person skilled in the art to which the embodiments belong. Therefore, details regarding such combinations and modifications should be interpreted as being included within the scope of the embodiments.

[0161] Although the above description has focused on the embodiments, this is merely an example and is not intended to limit the embodiments. A person skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For instance, each component specifically shown in the embodiments may be modified and implemented. Furthermore, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

Claim 1 A circuit board comprising: a build-up insulating layer including a plurality of insulating layers stacked along a vertical direction; a protective layer disposed on the build-up insulating layer; and a pad portion disposed on the build-up insulating layer and penetrating the upper and lower surfaces of the protective layer, wherein the pad portion comprises: a lower pad disposed on the build-up insulating layer and having a first width along a horizontal direction; and an upper pad disposed on the lower pad and having a second width along the horizontal direction that is smaller than the first width, wherein the upper surface of the upper pad and the upper surface of the protective layer are located on the same plane. Claim 2 A circuit board according to claim 1, wherein the pad portion further comprises a seed layer disposed between the upper surface of the build-up insulating layer and the lower pad, and the thickness in the vertical direction from the lower surface of the seed layer to the upper surface of the upper pad is the same as the thickness in the vertical direction from the upper surface of the protective layer to the lower surface of the protective layer. Claim 3 A circuit board according to claim 1, further comprising a surface treatment layer disposed on the pad portion, wherein the thickness of the lower pad is thicker than the thickness of the surface treatment layer. Claim 4 In paragraph 3, the surface treatment layer has a third width that is smaller than the first width and larger than the second width, on a circuit board. Claim 5 In paragraph 4, the surface treatment layer comprises a first portion disposed on the upper surface of the upper pad and a second portion extending from the first portion and disposed on the upper surface of the protective layer, the circuit board. Claim 6 A circuit board according to claim 1, wherein at least one of the side of the lower pad and the side of the upper pad includes a curved surface whose width increases in the horizontal direction toward the upper surface of the build-up insulating layer. Claim 7 In paragraph 2, the build-up insulating layer comprises a first insulating layer and a second insulating layer disposed on the first insulating layer, the seed layer disposed on the second insulating layer and the circuit pattern layer disposed between the first insulating layer and the second insulating layer, wherein the surface roughness (Ra) of the circuit pattern layer is greater than the surface roughness (Ra) of the upper pad. Claim 8 In claim 7, the surface roughness (Ra) of the protective layer is smaller than the surface roughness (Ra) of the circuit pattern layer and larger than the surface roughness (Ra) of the upper pad, in a circuit board. Claim 9 A package substrate comprising: a build-up insulating layer including a plurality of insulating layers stacked along a vertical direction; a first protective layer disposed on the build-up insulating layer; a first pad disposed on the build-up insulating layer and penetrating the first protective layer along the vertical direction; a surface treatment layer disposed on the first pad; a first adhesive member disposed on the surface treatment layer; a chip disposed on the first adhesive member; and a molding layer disposed on the first protective layer and molding the chip, wherein the first pad comprises: a lower pad disposed on the build-up insulating layer and having a first width along a horizontal direction; and an upper pad disposed on the lower pad and having a second width along the horizontal direction that is smaller than the first width, wherein the upper surface of the upper pad and the upper surface of the first protective layer are located on the same plane. Claim 10 In claim 9, the first pad further comprises a seed layer disposed between the upper surface of the build-up insulating layer and the lower pad, and the thickness in the vertical direction from the lower surface of the seed layer to the upper surface of the upper pad is the same as the thickness in the vertical direction from the upper surface of the first protective layer to the lower surface of the first protective layer, the package substrate. Claim 11 In claim 9, the surface treatment layer has a third width smaller than the first width and larger than the second width, and the surface treatment layer comprises a first portion disposed on the upper surface of the upper pad and a second portion extending from the first portion and disposed on the upper surface of the first protective layer, a package substrate. Claim 12 In claim 11, the build-up insulating layer comprises: an inner insulating layer; a first outermost insulating layer disposed on the inner insulating layer; and a second outermost insulating layer disposed below the inner insulating layer, wherein the first pad is disposed on the first outermost insulating layer, and the package substrate comprises: a second pad disposed in the second outermost insulating layer; a first via penetrating at least a portion of the inner insulating layer along the vertical direction; a second via penetrating at least a portion of the first outermost insulating layer along the vertical direction and connected to the first pad; and a third via penetrating at least a portion of the second outermost insulating layer along the vertical direction and connected to the second pad, wherein the first to third vias have different widths in the horizontal direction. Claim 13 A package substrate according to claim 12, wherein the first via has a width greater than the width of the second via and a width smaller than the width of the third via, and the second via has a width smaller than the width of the third via.

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