Image sensing device

Abstract

An image sensing device and a method of operating the image sensing device are provided. An image sensing device comprises: a photoelectric element that generates an electric charge in response to light; a first floating diffusion in which the electric charge generated by the photoelectric element is stored; a second floating diffusion (FD2) in which the electric charge generated by the photoelectric element is stored; a transfer gate having one end connected to the photoelectric element and the other end connected to the first floating diffusion (FD1); a reset transistor that resets the voltages of the first and second floating diffusions based on a reset signal; a first DCG (Dual Conversion Gain) transistor having one end connected to the first floating diffusion and the other end connected to the second floating diffusion, a first DCG transistor that connects the first floating diffusion and the second floating diffusion based on a first DCG control signal; a first pixel circuit that generates a first output voltage based on the voltage of the first floating diffusion; a second pixel circuit that generates a second output voltage based on the voltage of the second floating diffusion; a first analog-to-digital converter that receives the first output voltage and converts it into a first digital signal; and a first analog-to-digital converter. It may include a second analog-to-digital converter that is positioned separately from the converter and receives a second output voltage to convert it into a second digital signal.

Description

Technology Field

[0001] The present invention relates to an image sensing device. Background Technology

[0002] An image sensing device is one of the semiconductor devices that converts optical information into electrical signals. Such image sensing devices include Charge Coupled Device (CCD) image sensing devices and Complementary Metal-Oxide Semiconductor (CMOS) image sensing devices, and CMOS image sensors are abbreviated as CIS (CMOS image sensor).

[0003] Methods for implementing HDR (High Dynamic Range) scenes using CIS include the Multiple Exposure method and the Multiple Conversion Gain (MCG) method. However, these methods have the problem of reduced frame rate because they involve the process of reading data multiple times and compositing it. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide an image sensing device equipped with multiple floating diffusion and an analog-to-digital converter.

[0005] Another technical problem that the present invention aims to solve is to provide a method of operation for an image sensing device that can implement an HDR scene with a single read operation.

[0006] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] An image sensing device according to the technical concept of the present invention for solving the above problem comprises: a photoelectric element that generates an electric charge in response to light; a first floating diffusion in which the electric charge generated by the photoelectric element is stored; a second floating diffusion (FD2) in which the electric charge generated by the photoelectric element is stored; a transfer gate having one end connected to the photoelectric element and the other end connected to the first floating diffusion (FD1); a reset transistor that resets the voltages of the first and second floating diffusions based on a reset signal; a first DCG (Dual Conversion Gain) transistor having one end connected to the first floating diffusion and the other end connected to the second floating diffusion, wherein the first DCG transistor connects the first floating diffusion and the second floating diffusion based on a first DCG control signal; a first pixel circuit that generates a first output voltage based on the voltage of the first floating diffusion; a second pixel circuit that generates a second output voltage based on the voltage of the second floating diffusion; and a device that receives the first output voltage and converts it into a first digital signal. It may include a first analog-to-digital converter and a second analog-to-digital converter disposed separately from the first analog-to-digital converter and receiving a second output voltage to convert into a second digital signal.

[0008] An image sensing device according to the technical concept of the present invention for solving the above problem comprises: a first pixel circuit that generates a first output voltage in a high-conversion manner based on a charge generated by one photoelectric element and outputs the same; a first analog-to-digital converter that receives the first output voltage and converts it into a first digital signal; a second pixel circuit that generates a second output voltage different from the first output voltage in a low-conversion manner based on a charge generated by one photoelectric element (PD) and outputs the same; and a second analog-to-digital converter that receives the second output voltage and converts it into a second digital signal, wherein the first analog-to-digital converter is disposed on a first plate and the second analog-to-digital converter may be disposed on a second plate different from the first plate.

[0009] A method of operation of an image sensing device according to the technical concept of the present invention for solving the above problem may include connecting a first floating diffusion and a second floating diffusion based on a first DCG control signal, resetting the voltage levels of the first floating diffusion and the second floating diffusion to a reset level, transitioning the voltage level of the first floating diffusion from the reset level to a first signal level based on a charge generated from a photoelectric element, transitioning the voltage level of the second floating diffusion from the reset level to a second signal level different from the first signal level based on a charge generated from a photoelectric element, separating the first floating diffusion and the second floating diffusion based on the first DCG control signal, generating a first digital signal based on the level difference between the reset level of the first floating diffusion and the first signal level, and generating a second digital signal based on the level difference between the reset level of the second floating diffusion and the second signal level.

[0010] Other specific details of the present invention are included in the detailed description and drawings. Brief explanation of the drawing

[0011] FIG. 1 is an exemplary block diagram of an image sensing device according to some embodiments of the present invention. FIG. 2 is a diagram illustrating the stack structure of an image sensing device according to some embodiments of the present invention. Figure 3 is a circuit diagram for explaining the structure of a pixel included in the pixel array of Figure 1. FIGS. 4 to 7 are drawings for explaining the operation of the circuit of FIG. 3. FIGS. 8 and 9 are drawings for explaining the charge potentials of the photoelectric element and the first and second floating diffusions. Figure 10 is a diagram illustrating the waveform of a signal applied to a pixel and the change in output voltage during one sensing cycle. FIG. 11 is a diagram illustrating the operation of a pixel circuit that does not include the technical concept of the present invention. FIG. 12 is a drawing for explaining the stacked structure of an image sensing device according to another embodiment of the present invention. FIG. 13 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 14 is a drawing for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 15 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 16 is an exemplary block diagram of an image sensing device according to another embodiment of the present invention. FIG. 17a is a circuit diagram for explaining the structure of a pixel included in the pixel array of FIG. 16. FIG. 17b is a diagram illustrating the waveform of a signal applied to a pixel and the change in output voltage during one sensing cycle of FIG. 17a. FIG. 18 is a diagram illustrating the stacked structure of the image sensing device shown in FIG. 17a. FIG. 19 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 20 is a drawing for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 21 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 22 is a drawing for explaining the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 23 is an exemplary block diagram of an image sensing device according to another embodiment of the present invention. FIG. 24 is a circuit diagram for explaining the structure of a pixel included in the pixel array of FIG. 23. FIG. 25 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 26 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 27 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. FIG. 28 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. FIGS. 29 and FIGS. 30 are block diagrams of an electronic device including a multi-camera module. FIG. 31 is a detailed block diagram of the camera module of FIG. 29 and FIG. 30. Specific details for implementing the invention

[0012] Embodiments according to the technical concept of the present invention will be described below with reference to the attached drawings.

[0013] FIG. 1 is an exemplary block diagram of an image sensing device according to some embodiments of the present invention.

[0014] An image sensing device (1) may include a pixel array (100), a logic circuit (200), an analog-to-digital converter circuit (300), and a memory (400). The pixel array (100) includes a plurality of pixels (110), and the pixels (110) may be connected to row lines extending in a first direction and column lines extending along a second direction intersecting the first direction, and may be arranged in a matrix form. Each of the pixels (110) may include at least one photoelectric element that generates an electric charge in response to light, and a pixel circuit that generates an output voltage using the electric charge generated by the photoelectric element. In FIG. 1, the pixel array (100) is shown as being in the form of a 6x8 matrix, but this is exemplary and the present embodiment is not limited thereto, and the pixel array (100) may include various numbers of pixels.

[0015] The logic circuit (200) may include circuits for driving a pixel array. For example, the logic circuit (200) may include a row driver for driving row lines, a readout circuit for obtaining output voltage from pixels (110) through column lines, control logic for controlling the row driver and the readout circuit, a power circuit, an input / output interface, and an image signal processor.

[0016] The analog-to-digital converter circuit (300) may include a plurality of analog-to-digital converters. The analog-to-digital converter may receive an image signal in an analog form and convert it into a digital signal. The analog-to-digital converter may convert the analog signal into a digital signal using the Correlated Double Sampling (CDS) method. The analog-to-digital converter circuit (300) may be disposed separately from the logic circuit (200), or it may be structured to be included inside the logic circuit (200).

[0017] The memory (400) may include storage elements, and the storage elements may be implemented as at least one of a Metal-Insulator-Metal (MIM) capacitor, a charge trap element, a Magnetic Tunnel Junction (MTJ) element, and a Germanium (Ge)-Antimony (Sb)-Tellurium (Te) element. The memory (400) may be connected to pixels (110) and / or a logic circuit (200).

[0018] FIG. 2 is a diagram illustrating the stack structure of an image sensing device according to some embodiments of the present invention.

[0019] Referring to FIGS. 1 and 2, the image sensing device may be formed as a stacked structure including a first plate (P1) and a second plate (P2). The second plate (P2) may be formed parallel to the first plate (P1). Specifically, the second plate (P2) may be formed parallel to the first plate (P1) on top of the first plate (P1). The first plate may include a pixel array area (PA) and a pixel peripheral area (PS). A pixel array (100) may be placed in the pixel array area (PA). A logic circuit (200) may be placed in the pixel peripheral area (PS) or on the second plate (P2).

[0020] The second plate may include a first zone (P2_1) and a second zone (P2_2). The second zone (P2_2) may be formed physically separated from the first zone (P2_1). In some embodiments, when the analog-to-digital converter circuit (300) illustrated in FIG. 1 includes a plurality of analog-to-digital converters (310, 320), the first analog-to-digital converter (310) may be placed in the first zone (P2_1), and the second analog-to-digital converter (320) may be placed in the second zone (P2_2).

[0021] Figure 3 is a circuit diagram for explaining the structure of a pixel included in the pixel array of Figure 1.

[0022] Referring to FIG. 3, the pixel (110) may include a photovoltaic element (PD), a reset transistor (RT) that resets the voltage levels of the first and second floating diffusions (FD1, FD2) to a reset level (V_RST), a transfer gate (TG) that transfers the charge generated in the photovoltaic element (PD) to the first and second floating diffusions (FD1, FD2), a DCG transistor (DCG) that connects the first floating diffusion (FD1) and the second floating diffusion (FD2), a first pixel circuit (111), and a second pixel circuit (112).

[0023] A photoelectric device (PD) can generate an electric charge by sensing an external image (or light). For example, the photoelectric device (PD) may include an organic photodiode. If the photoelectric device (PD) is an organic photodiode, the photoelectric device (PD) may include first and second electrodes arranged parallel to each other and an organic photoconversion layer provided between them, wherein the organic photoconversion layer can receive light of a predetermined wavelength band and generate an electric charge. The photoelectric device (PD) may be a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof, but the embodiments are not limited thereto.

[0024] One end of the transfer gate (TG) can be connected to the photoelectric element (PD), and the other end can be connected to the first floating diffusion (FD1). The transfer gate (TG) can connect the photoelectric element (PD), the first floating diffusion (FD1), and the second floating diffusion (FD2) based on the transfer gate signal (S_TG).

[0025] The first pixel circuit (111) may include a first source follower transistor (SF1) and a first select transistor (ST1). The gate terminal of the first source follower transistor (SF1) is connected to the first floating diffusion (FD1), and a pixel voltage (V_PIX) may be provided to the source terminal. The first source follower transistor (SF1) may operate as a source follower buffer amplifier by means of the charge delivered to the first floating diffusion (FD1). That is, the first source follower transistor (SF1) may amplify the charge generated in the photovoltaic element (PD) and delivered to the first floating diffusion (FD1) using the pixel voltage (V_PIX) and deliver it to the first select transistor (ST1). The first select transistor (ST1) may be controlled by a select signal (SEL) provided from a row driver and may perform switching and addressing operations. The source terminal of the first select transistor (ST1) can be connected to the drain terminal of the first source follower transistor (SF1), and the first output voltage (V_OUT1) can be output to a column connected to the first select transistor (ST1). The first output voltage (V_OUT1) can be provided to the first analog-to-digital converter (310).

[0026] The second pixel circuit (112) may include a second source follower transistor (SF2) and a second select transistor (ST2). The gate terminal of the second source follower transistor (SF2) is connected to the second floating diffusion (FD2), and a pixel voltage (V_PIX) may be provided to the source terminal. The second source follower transistor (SF2) may operate as a source follower buffer amplifier by the charge delivered to the second floating diffusion (FD2). That is, the second source follower transistor (SF2) may use the pixel voltage (V_PIX) to amplify the charge generated in the photovoltaic element (PD) and delivered to the second floating diffusion (FD2), and deliver it to the second select transistor (ST2). The second select transistor (ST2) may be controlled by a select signal (SEL) provided from a low driver and may perform switching and addressing operations. The source terminal of the second select transistor (ST2) can be connected to the drain terminal of the second source follower transistor (SF2), and the second output voltage (V_OUT2) can be output to a column connected to the second select transistor (ST2). The second output voltage (V_OUT2) can be provided to the second analog-to-digital converter (320).

[0027] In some embodiments, the first and second floating diffusions (FD1, FD2) may be MIM capacitors or may be in the form of cylindrical capacitors used in DRAM cells. Referring further to FIG. 2, if the first and second floating diffusions (FD1, FD2) are in the form of MIM capacitors, they may be formed between the first plate (P1) and the second plate (P2), and if they are cylindrical capacitors, they may be formed on the second plate (P2).

[0028] One end of the DCG transistor (DCG) may be connected to the first floating diffusion (FD1) and the photoelectric element (PD), and the other end may be connected to the second floating diffusion (FD2). The DCG transistor (DCG) may control the amount of charge supplied from the photoelectric element (PD) and / or the first floating diffusion (FD1) to the second floating diffusion (FD2) based on the DCG control signal (S_DCG).

[0029] Although FIG. 3 is illustrated as having only the first and second pixel circuits (111, 112) connected to a single photovoltaic element (PD), the embodiment is not limited thereto and may further include a plurality of pixel circuits similar to the first and second pixel circuits (111, 112).

[0030] Next, the operation of the pixel (110) circuit of FIG. 3 will be explained with reference to FIG. 4 to FIG. 10.

[0031] FIGS. 4 to 7 are drawings for explaining the operation of the circuit of FIG. 3. FIGS. 8 to 9 are drawings for explaining the charge potential of the photoelectric element and the first and second floating diffusions. FIG. 10 is a drawing showing the waveform of a signal applied to a pixel and the change in output voltage during one sensing cycle.

[0032] The operation of the pixel circuit described below is merely an example, and its detailed configuration can be modified as needed.

[0033] First, referring to FIGS. 4 and FIGS. 10, prior to the first time point (t1), the DCG control signal (S_DCG) transitions from a logical low level (hereinafter L level) to a logical high level (hereinafter H level). That is, the DCG control signal (S_DCG) can be enabled. Accordingly, the DCG transistor (DCG) can be turned on. That is, the first floating diffusion (FD1) and the second floating diffusion (FD2) can be electrically connected.

[0034] At the first time point (t1), the reset signal (RESET) can transition from an L level to an H level. That is, the reset signal (RESET) can be enabled. Accordingly, the reset transistor (RT) can be turned on. Meanwhile, the DCG control signal (S_DCG) can remain at the H level. That is, the DCG control signal (S_DCG) can remain in the enabled state. As the DCG control signal (S_DCG) remains at the H level, the DCG transistor (DCG) remains in the turned-on state, and accordingly, the first floating diffusion (FD1) and the second floating diffusion (FD2) can remain electrically connected. Therefore, as the reset transistor (RT) is turned on, both the first floating diffusion (FD1) and the second floating diffusion (FD2) can be reset to the pixel voltage (V_PIX).

[0035] Next, referring to FIGS. 5 and FIGS. 10, after the first time point (t1) and before the second time point (t2), the reset signal (RESET) can transition from an H level to an L level. That is, the reset signal (RESET) can be disabled. Accordingly, the reset transistor (RT) can be turned off. Meanwhile, the DCG control signal (S_DCG) can remain at an H level. That is, the DCG control signal (S_DCG) can remain in an enabled state. As the DCG control signal (S_DCG) remains at an H level, the DCG transistor (DCG) remains in a turned-on state, and accordingly, the first floating diffusion (FD1) and the second floating diffusion (FD2) can remain electrically connected.

[0036] Before the second time point (t2) after the reset transistor (RT) is turned off, the select signal (SEL) can transition from an L level to an H level. That is, the select signal (SEL) can be enabled. Accordingly, the first and second select transistors (ST1, ST2) can be turned on. The first source follower transistor (SF1) can output the charge level of the first floating diffusion (FD1) as the first output voltage (V_OUT1) using the pixel voltage (V_PIX). In this case, the first output voltage (V_OUT1) may be the reset voltage (V_RST). The second source follower transistor (SF2) can output the charge level of the second floating diffusion (FD2) as the second output voltage (V_OUT2) using the pixel voltage (V_PIX). In this case, since the DCG transistor (DCG) remains in the turned-on state, the charge level of the first floating diffusion (FD1) can be equal to the charge level of the second floating diffusion (FD2). That is, the second output voltage (V_OUT2) can also be the reset voltage (V_RST).

[0037] Next, referring to FIGS. 6 and FIGS. 10, at a second time point (t2), the transfer gate signal (S_TG) can transition from an L level to an H level. That is, the transfer gate signal (S_TG) can be enabled. Accordingly, the transfer gate (TG) can be turned on. Meanwhile, the DCG control signal (S_DCG) can remain at an H level. That is, the DCG control signal (S_DCG) can remain in an enabled state. As the DCG control signal (S_DCG) remains at an H level, the DCG transistor (DCG) remains in a turned-on state, and accordingly, the first floating diffusion (FD1) and the second floating diffusion (FD2) can remain electrically connected. Accordingly, as the transfer gate (TG) is turned on, the charges stored in the photovoltaic device (PD) can be transferred to the first floating diffusion (FD1) and the second floating diffusion (FD2). That is, the charge levels of the first floating diffusion (FD1) and the second floating diffusion (FD2) can be increased.

[0038] Referring further to FIG. 8, prior to the second time point (t2), the photovoltaic device (PD) may store a charge generated by sensing an external image (or light). Subsequently, at the second time point (t2), the transfer gate control signal (S_TG) may transition from the L level to the H level, and accordingly, charge may be transferred from the photovoltaic device (PD) to the first and second floating diffusions (FD2) which have a relatively low charge potential. That is, the charge level of the photovoltaic device (PD) (H1 in FIG. 8) may be lowered.

[0039] Referring further to FIG. 9, in some embodiments, as described above, the first floating diffusion (FD1) and the second floating diffusion (FD2) may have different capacitances, so the degree to which the charge level of the first floating diffusion (FD1) rises may differ from the degree to which the charge level of the second floating diffusion (FD2) rises. In some embodiments, the capacitance of the first floating diffusion (FD1) may be smaller than the capacitance of the second floating diffusion (FD2). Therefore, the degree to which the charge level of the first floating diffusion (FD1) rises (H2) may be smaller than the degree to which the charge level of the second floating diffusion (FD2) rises (H3). Although FIGS. 8 and 9 show that as the transfer gate control signal (S_TG) transitions from the L level to the H level, the charge level of the photovoltaic device (PD) is shown to decrease from H1 to 0, this is exemplary and the embodiments are not limited thereto.

[0040] Referring to FIGS. 7 and FIGS. 10, at the third time point (t3), the transfer gate signal (S_TG) can transition from an H level to an L level. That is, the transfer gate signal (S_TG) can be disabled. Accordingly, the transfer gate (TG) can be turned off. Also, at the third time point (t3), the DCG control signal (S_DCG) can transition from an H level to an L level. That is, the DCG control signal (S_DCG) can be disabled. Accordingly, the DCG transistor (DCG) can be turned off, and the first floating diffusion (FD1) and the second floating diffusion (FD2) can be electrically separated.

[0041] After the third time point (t3), the selection signal (SEL) can transition from an L level to an H level. That is, the selection signal (SEL) can be enabled. Accordingly, the first and second selection transistors (ST1, ST2) can be turned on. Meanwhile, the transfer gate signal (S_TG) and the DCG control signal (S_DCG) can remain at an L level. That is, the transfer gate signal (S_TG) and the DCG control signal (S_DCG) can remain in a disabled state. As the transfer gate signal (S_TG) and the DCG control signal (S_DCG) remain at an L level, the transfer gate (TG) and the DCG transistor (DCG) can remain in a turned-off state. Accordingly, the photoelectric device (PD) and the first floating diffusion (FD1), and the first floating diffusion (FD1) and the second floating diffusion (FD2) can each remain electrically separated.

[0042] The first source follower transistor (SF1) can output the charge level of the first floating diffusion (FD1) as a first output voltage (V_OUT1) using the pixel voltage (V_PIX). In this case, the first output voltage (V_OUT1) may be the first signal voltage (V_S1). The second source follower transistor (SF2) can output the charge level of the second floating diffusion (FD2) as a second output voltage (V_OUT2) using the pixel voltage (V_PIX). In this case, since the DCG transistor (DCG) remains in a turned-off state, the second output voltage (V_OUT2) may be different from the first output voltage (V_OUT1). Specifically, the second output voltage (V_OUT2) may be the second signal voltage (V_S2). The first signal voltage (V_S1) may have a higher level than the second signal voltage (V_S2).

[0043] Depending on the difference in capacitance between the first and second floating diffusions (FD1, FD2) or the charge transfer control of the DCG transistor (DCG), the method of converting the charge of the floating diffusion into an output voltage may differ. That is, the charge-voltage conversion coefficients of the first pixel circuit (111) and the second pixel circuit (112) may differ. In some embodiments, the method by which the first pixel circuit (111) generates the first output voltage (V_OUT1) may be a high conversion method, and the method by which the second pixel circuit (112) generates the second output voltage (V_OUT2) may be a low conversion method.

[0044] The first and second output voltages (V_OUT1, V_OUT2) output through the process described above are converted into first and second digital signals, respectively, through first and second analog-to-digital converters (ADC1, ADC2). Each analog-to-digital converter (ADC1, ADC2) generates a digital signal based on the level difference (DV1, DV2 in FIG. 10) by comparing the level of the reset voltage (V_RST) and each signal voltage (V_S1, V_S2) using the CDS method. That is, the first and second digital signals can be generated simultaneously.

[0045] Next, the effects of the present invention will be explained with reference to FIG. 11.

[0046] FIG. 11 is a diagram illustrating the operation of a pixel circuit that does not include the technical concept of the present invention.

[0047] Specifically, unlike that illustrated in FIG. 3, this describes an image sensing device that includes first and second floating diffusions connected by a DCG transistor, but includes one pixel circuit and an analog-to-digital converter to sense the voltage of each floating diffusion. Referring to FIG. 11, if the technical concept of the present invention is not included, two voltage lead processes may be required to generate two different output voltages. That is, compared to FIG. 10, the voltage of the first floating diffusion with the DCG transistor turned off must be sensed between the fourth time point (t4) and the fifth time point (t5), and then the voltages of the first and second floating diffusions with the DCG transistor turned on must be sensed after the fifth time point (t5). Therefore, the first and second digital signals cannot be generated simultaneously, and consequently, the sensing period (T) of the image signal is increased.

[0048] The image sensing device according to the present embodiment can simultaneously read two analog image signals generated by different CG (Conversion Gain) for implementing an HDR scene. Therefore, the sensing period (T) of the image signal can be shortened compared to the case of FIG. 11 (a in FIG. 10 < b in FIG. 11).

[0049] However, including an additional analog-to-digital converter in the image sensing device may present design problems related to integration limits. These design limitations can be resolved by forming the image sensing device into a stacked structure composed of multiple plates, as described with reference to FIG. 2, and by placing additional analog-to-digital converters on the multiple plates.

[0050] FIG. 12 is a diagram illustrating the stacked structure of an image sensing device according to another embodiment of the present invention. The differences from FIG. 2 will be explained in detail below.

[0051] Referring to FIG. 12, the image sensing device may be formed as a stacked structure including a first plate (P1) and a second plate (P2). The second plate (P2) may be formed parallel to the first plate (P1). Specifically, the second plate (P2) may be formed parallel to the first plate (P1) on the upper side of the first plate (P1). The first plate (P1) may include a pixel array area (PA) and a pixel peripheral area (PS). A pixel array (100) may be placed in the pixel array area (PA). A first analog-to-digital converter (510) may be placed in the pixel peripheral area (PS). Additionally, a second analog-to-digital converter (520) may be placed on the second plate (P2).

[0052] FIG. 13 is a diagram illustrating the stacked structure of an image sensing device according to another embodiment of the present invention. The differences from FIG. 2 will be explained in detail below.

[0053] Referring to FIG. 13, the image sensing device may be formed as a stacked structure including a first plate (P1), a second plate (P2), and a third plate (P3). Each of the plates (P1, P2, P3) may be formed parallel to each other. Specifically, the second plate (P2) may be formed on top of the first plate (P1) parallel to the first plate (P1), and the third plate (P3) may be formed between the first plate (P1) and the second plate (P2) parallel to the first and second plates (P1, P2). The first plate (P1) may include a pixel array area (PA) and a pixel peripheral area (PS). A pixel array (100) may be placed in the pixel array area (PA). A first analog-to-digital converter (510) may be placed on the second plate (P2). Additionally, a second analog-to-digital converter (520) may be placed on the third plate (P3).

[0054] FIG. 14 is a diagram illustrating the stacked structure of an image sensing device according to another embodiment of the present invention. The differences from FIG. 2 will be explained in detail below.

[0055] Referring to FIG. 14, the image sensing device may be formed as a stacked structure including a first plate (P1), a second plate (P2), and a third plate (P3). Each of the plates (P1, P2, P3) may be formed parallel to each other. Specifically, the second plate (P2) may be formed on top of the first plate (P1) parallel to the first plate (P1), and the third plate (P3) may be formed between the first plate (P1) and the second plate (P2) parallel to the first and second plates (P1, P2). The third plate (P3) may include a first zone (P3_1) and a second zone (P3_2). The second zone (P3_2) may be formed physically separated from the first zone (P3_1). In this case, the first analog-to-digital converter (510) may be placed in the first zone (P3_1), and the second analog-to-digital converter (520) may be placed in the second zone (P3_2).

[0056] FIG. 15 is a diagram illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. The differences from FIG. 14 will be explained in detail below.

[0057] Referring to FIG. 15, the second plate (P2) may include a first zone (P2_1) and a second zone (P2_2). The second zone (P2_2) may be formed physically separated from the first zone (P2_1). In this case, the first analog-to-digital converter (510) may be placed in the first zone (P2_1), and the second analog-to-digital converter (520) may be placed in the second zone (P2_2).

[0058] FIG. 16 is an exemplary block diagram of an image sensing device according to another embodiment of the present invention. The differences from FIG. 1 will be explained in detail below.

[0059] Referring to FIG. 16, the image sensing device (2) may include a pixel array (100), a logic circuit (200), an analog-to-digital converter circuit (500), and a memory (400). The pixel array (100) may include a plurality of pixels (120). The analog-to-digital converter circuit (500) may include a plurality of analog-to-digital converters (510, 520, 530).

[0060] FIG. 17a is a circuit diagram illustrating the structure of a pixel included in the pixel array of FIG. 16. FIG. 17b is a diagram showing the waveform of a signal applied to a pixel and the change in output voltage during one sensing cycle of FIG. 17a. The differences from FIG. 3 will be explained in detail below.

[0061] Referring to FIG. 17a, the pixel (120) may include a photovoltaic element (PD), a reset transistor (RT) that resets the voltage level of the first to third floating diffusions (FD1, FD2, FD3) to a reset level (V_RST), a transfer gate (TG) that transfers the charge generated in the photovoltaic element (PD) to the first to third floating diffusions (FD1, FD2, FD3), a first DCG transistor (DCG1) that connects the first floating diffusion (FD1) and the second floating diffusion (FD2), a second DCG transistor (DCG2) that connects the second floating diffusion (FD2) and the third floating diffusion (FD3), and first to third pixel circuits (121, 122, 123). The first and second pixel circuits (121, 122) may each be similar to the first and second pixel circuits (111, 112) of FIG. 3.

[0062] One end of the transfer gate (TG) may be connected to the photoelectric element (PD), and the other end may be connected to the first floating diffusion (FD1). The transfer gate (TG) may connect the photoelectric element (PD) and the first to third floating diffusions (FD1, FD2, FD3) based on the transfer gate signal (S_TG).

[0063] The third pixel circuit (123) may include a third source follower transistor (SF3) and a third select transistor (ST3). The gate terminal of the third source follower transistor (SF3) is connected to the third floating diffusion (FD3), and a pixel voltage (V_PIX) may be provided to the source terminal. The third source follower transistor (SF3) may operate as a source follower buffer amplifier by the charge delivered to the third floating diffusion (FD3). That is, the third source follower transistor (SF3) may use the pixel voltage (V_PIX) to amplify the charge generated in the photovoltaic element (PD) and delivered to the third floating diffusion (FD3), and deliver it to the third select transistor (ST3). The third select transistor (ST3) may be controlled by a select signal (SEL) provided from a low driver and may perform switching and addressing operations. The source terminal of the third select transistor (ST3) can be connected to the drain terminal of the third source follower transistor (SF3), and the third output voltage (V_OUT3) can be output to a column connected to the third select transistor (ST3). The third output voltage (V_OUT3) can be provided to the third analog-to-digital converter (530).

[0064] In some embodiments, the first to third floating diffusions (FD1, FD2, FD3) may be MIM capacitors or may be in the form of cylindrical capacitors used in DRAM cells. Referring further to FIG. 18, if the first to third floating diffusions (FD1, FD2, FD3) are in the form of MIM capacitors, they may be formed between the second plate (P2) and the third plate (P3), and if they are cylindrical capacitors, they may be formed on the second plate (P2) or the third plate (P3).

[0065] One end of the first DCG transistor (DCG1) is connected to the first floating diffusion (FD1) and the photoelectric element (PD), and the other end can be connected to the second and third floating diffusions (FD2, FD3). The first DCG transistor (DCG1) can control the amount of charge provided from the photoelectric element (PD) and / or the first floating diffusion (FD1) to the second and third floating diffusions (FD2, FD3) based on the first DCG control signal (S_DCG1).

[0066] One end of the second DCG transistor (DCG2) is connected to the first and second floating diffusions (FD1, FD2) and the photoelectric element (PD), and the other end can be connected to the third floating diffusion (FD3). The second DCG transistor (DCG2) can control the amount of charge supplied to the third floating diffusion (FD3) from the photoelectric element (PD) and / or the first and second floating diffusions (FD1, FD2) based on the second DCG control signal (S_DCG2).

[0067] Although FIG. 17a is illustrated as having only the first to third pixel circuits (121, 122, 123) connected to a single photovoltaic element (PD), the embodiment is not limited thereto and may further include a plurality of pixel circuits similar to the first to third pixel circuits (121, 122, 123).

[0068] Next, with reference to FIG. 17b, the operation of the pixel circuit illustrated in FIG. 17a will be described. The operation of the pixel circuit illustrated in FIG. 17a may be similar to the contents of FIG. 4 to FIG. 10.

[0069] Referring to FIG. 17b, first, prior to the first time point (t1), the first and second DCG control signals (S_DCG1, S_DCG2) transition from an L level to an H level. That is, the first and second DCG control signals (S_DCG1, S_DCG2) can be enabled. Accordingly, the first and second DCG transistors (DCG1, DCG2) can be turned on. That is, the first floating diffusion (FD1) and the second floating diffusion (FD2), and the second floating diffusion (FD2) and the third floating diffusion (FD3) can be electrically connected.

[0070] At the first time point (t1), the reset signal (RESET) can transition from an L level to an H level. That is, the reset signal (RESET) can be enabled. Accordingly, the reset transistor (RT) can be turned on. Meanwhile, the first and second DCG control signals (S_DCG1, S_DCG2) can remain at an H level. That is, the first and second DCG control signals (S_DCG1, S_DCG2) can remain in an enabled state. As the first and second DCG control signals (S_DCG1, S_DCG2) remain at an H level, the first and second DCG transistors (DCG1, DCG2) remain in a turned-on state, and accordingly, the first to third floating diffusions (FD1, FD2, FD3) can remain electrically connected. Accordingly, as the reset transistor (RT) is turned on, the first to third floating diffusions (FD1, FD2, FD3) can all be reset to the pixel voltage (V_PIX).

[0071] Next, after the first time point (t1) and before the second time point (t2), the reset signal (RESET) can transition from an H level to an L level. That is, the reset signal (RESET) can be disabled. Accordingly, the reset transistor (RT) can be turned off. Meanwhile, the first and second DCG control signals (S_DCG1, S_DCG2) can remain at an H level. That is, the first and second DCG control signals (S_DCG1, S_DCG2) can remain in an enabled state. As the first and second DCG control signals (S_DCG1, S_DCG2) remain at an H level, the first and second DCG transistors (DCG1, DCG2) remain in a turned-on state, and accordingly, the first to third floating diffusions (FD1, FD2, FD3) can remain electrically connected.

[0072] Before the second time point (t2) after the reset transistor (RT) is turned off, the selection signal (SEL) can transition from an L level to an H level. That is, the selection signal (SEL) can be enabled. Accordingly, the first to third selection transistors (ST1, ST2, ST3) can be turned on. The first source follower transistor (SF1) can output the charge level of the first floating diffusion (FD1) as the first output voltage (V_OUT1) using the pixel voltage (V_PIX). In this case, the first output voltage (V_OUT1) may be the reset voltage (V_RST). The second and third source follower transistors (SF2, SF3) can output the charge levels of the second and third floating diffusions (FD2, FD3), respectively, as the second and third output voltages (V_OUT2, V_OUT3) using the pixel voltage (V_PIX). In this case, since the first and second DCG transistors (DCG1, DCG2) remain in the turned-on state, the charge levels of the first to third floating diffusions (FD1, FD2, FD3) can all be the same. That is, the second and third output voltages (V_OUT2, V_OUT3) can also be the reset voltage (V_RST).

[0073] Next, at the second time point (t2), the transfer gate signal (S_TG) can transition from an L level to an H level. That is, the transfer gate signal (S_TG) can be enabled. Accordingly, the transfer gate (TG) can be turned on. Meanwhile, the first and second DCG control signals (S_DCG1, S_DCG2) can remain at an H level. That is, the first and second DCG control signals (S_DCG1, S_DCG2) can remain in an enabled state. As the first and second DCG control signals (S_DCG1, S_DCG2) remain at an H level, the first and second DCG transistors (DCG1, DCG2) remain in a turned-on state, and accordingly, the first to third floating diffusions (FD1, FD2, FD3) can remain electrically connected. Accordingly, as the transfer gate (TG) is turned on, charges stored in the photovoltaic device (PD) can be transferred to the first to third floating diffusions (FD1, FD2, FD3). That is, the charge level of each floating diffusion (FD1, FD2, FD3) can be increased.

[0074] Before the second time point (t2), the photoelectric device (PD) may store a charge generated by sensing an external image (or light). Then, at the second time point (t2), the transfer gate control signal (S_TG) may transition from the L level to the H level, and accordingly, charge may be transferred from the photoelectric device (PD) to the first and second floating diffusions (FD1, FD2, FD3) which have a relatively low charge potential. That is, the charge level of the photoelectric device (PD) may be lowered.

[0075] Since the first to third floating diffusions (FD1, FD2, FD3) may each have different capacitances, the degree to which the charge level of the floating diffusions (FD1, FD2, FD3) rises may each be different.

[0076] At the third time point (t3), the transfer gate signal (S_TG) can transition from an H level to an L level. That is, the transfer gate signal (S_TG) can be disabled. Accordingly, the transfer gate (TG) can be turned off. Also, at the third time point (t3), the first and second DCG control signals (S_DCG1, S_DCG2) can transition from an H level to an L level. That is, the first and second DCG control signals (S_DCG1, S_DCG2) can be disabled. Accordingly, the first and second DCG transistors (DCG1, DCG2) can be turned off, and the first to third floating diffusions can each be electrically isolated.

[0077] After the third time point (t3), the selection signal (SEL) can transition from an L level to an H level. That is, the selection signal (SEL) can be enabled. Accordingly, the first to third selection transistors (ST1, ST2, ST3) can be turned on. Meanwhile, the transfer gate signal (S_TG) and the first and second DCG control signals (S_DCG1, S_DCG2) can remain at an L level. That is, the transfer gate signal (S_TG) and the first and second DCG control signals (S_DCG1, S_DCG2) can remain in a disabled state. As the transfer gate signal (S_TG) and the first and second DCG control signals (S_DCG1, S_DCG2) remain at an L level, the transfer gate (TG) and the first and second DCG transistors (DCG1, DCG2) can remain in a turned-off state. Accordingly, the photoelectric element (PD) and the first to third floating diffusions (FD1, FD2, FD3) can each be maintained in an electrically separated state.

[0078] The first source follower transistor (SF1) can output the charge level of the first floating diffusion (FD1) as the first output voltage (V_OUT1) using the pixel voltage (V_PIX). In this case, the first output voltage (V_OUT1) may be the first signal voltage (V_S1). The second source follower transistor (SF2) can output the charge level of the second floating diffusion (FD2) as the second output voltage (V_OUT2) using the pixel voltage (V_PIX). The third source follower transistor (SF3) can output the charge level of the third floating diffusion (FD3) as the third output voltage (V_OUT3) using the pixel voltage (V_PIX). In this case, since the first and second DCG transistors (DCG1, DCG2) remain in a turned-off state, each output voltage (V_OUT1, V_OUT2, V_OUT3) may differ depending on the capacitance difference of each floating diffusion (FD1, FD2, FD3) or the charge transfer control of the first and second DCG transistors (DCG1, DCG2). That is, the method of converting the charge of the floating diffusion into an output voltage may differ for each pixel circuit. In some embodiments, the method by which the first pixel circuit (121) generates the first output voltage (V_OUT1) may be a high conversion method, and the method by which the second pixel circuit (122) generates the second output voltage (V_OUT2) may be a low conversion method. The method by which the third pixel circuit (123) generates the third output voltage (V_OUT3) may be yet another method.

[0079] The first to third output voltages (V_OUT1, V_OUT2, V_OUT3) produced through the process described above are each converted into first to third digital signals through first to third analog-to-digital converters (ADC1, ADC2, ADC3). Each analog-to-digital converter (ADC1, ADC2, ADC3) generates a digital signal based on the level difference (DV1, DV2, DV3 in FIG. 17b) by comparing the level of the reset voltage (V_RST) and each signal voltage (V_S1, V_S2, V_S3) through the CDS method. That is, the first to third floating diffusions (FD1, FD2, FD3) are each electrically isolated, and different output voltages (V_OUT1, V_OUT2, V_OUT3) can be simultaneously output by simultaneously sensing the voltage of each floating diffusion using the first to third pixel circuits (121, 122, 123).

[0080] FIG. 18 is a diagram illustrating the stacked structure of the image sensing device shown in FIG. 17a.

[0081] Referring to FIG. 18, the image sensing device may be formed as a stacked structure including a first plate (P1), a second plate (P2), and a third plate (P3). Each of the plates (P1, P2, P3) may be formed parallel to each other. Specifically, the second plate (P2) may be formed on top of the first plate (P1) parallel to the first plate (P1), and the third plate (P3) may be formed between the first plate (P1) and the second plate (P2) parallel to the first and second plates (P1, P2). The first plate (P1) may include a pixel array area (PA) and a pixel peripheral area (PS). A pixel array (100) may be placed in the pixel array area (PA). A logic circuit (200) may be placed in the pixel peripheral area (PS), or may be placed on the second plate (P2) or the third plate (P3). The first analog-to-digital converter (510) may be placed on the second plate (P2). Additionally, the second and third analog-to-digital converters (520, 530) may be placed on the third plate (P3).

[0082] The third plate (P3) may include a first zone (P3_1) and a second zone (P3_2). The second zone (P3_2) may be formed physically separated from the first zone (P3_1). In this case, the second analog-to-digital converter (520) may be placed in the first zone (P3_1), and the third analog-to-digital converter (530) may be placed in the second zone (P3_2).

[0083] FIG. 19 is a diagram illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. The differences from FIG. 18 will be explained in detail below.

[0084] Referring to FIG. 19, the second plate (P2) may include a first zone (P2_1) and a second zone (P2_2). The second zone (P2_2) may be formed physically separated from the first zone (P2_1). In this case, the first analog-to-digital converter (510) may be placed in the first zone (P2_1), and the second analog-to-digital converter (520) may be placed in the second zone (P2_2). The third analog-to-digital converter (530) may be placed in the third plate (P3).

[0085] FIG. 20 is a drawing illustrating the stacked structure of an image sensing device according to some other embodiments of the present invention. The differences from FIG. 18 will be explained in detail below.

[0086] The first analog-to-digital converter (510) may be placed in the pixel peripheral area (PS) of the first plate (P1). The logic circuit (200) may be placed in the pixel peripheral area (PS) or in the second plate (P2).

[0087] FIG. 21 is a diagram illustrating the stacked structure of an image sensing device according to another embodiment of the present invention. The differences from FIG. 19 will be explained in detail below.

[0088] The first analog-to-digital converter (510) may be placed in the pixel area (PS) of the first plate (P1). The logic circuit (200) may be placed in the pixel area (PS) or in the third plate (P3).

[0089] FIG. 22 is a diagram illustrating the stacked structure of an image sensing device according to another embodiment of the present invention. The differences from FIG. 19 will be explained in detail below.

[0090] The first analog-to-digital converter (510) may be placed in the pixel peripheral area (PS) of the first plate (P1). The second analog-to-digital converter (520) may be placed in the second plate (P2). The third analog-to-digital converter (530) may be placed in the third plate (P3). The logic circuit (200) may be placed in the pixel peripheral area (PS), or in the second plate (P2) or the third plate (P3).

[0091] FIG. 23 is an exemplary block diagram of an image sensing device according to another embodiment of the present invention. The differences from FIG. 1 will be explained in detail below.

[0092] Referring to FIG. 23, the image sensing device may include a pixel array (100), a logic circuit (200), an analog-to-digital converter circuit (600), and a memory (400). The pixel array (100) may include a plurality of pixels (130). The analog-to-digital converter circuit (600) may include a plurality of analog-to-digital converters (610, 620).

[0093] FIG. 24 is a circuit diagram for explaining the structure of a pixel included in the pixel array of FIG. 23. The differences from FIG. 3 and FIG. 17a will be explained in detail below.

[0094] Referring to FIG. 24, the pixel (130) may include a photovoltaic element (PD), a reset transistor (RT) that resets the voltage level of the first to third floating diffusions (FD1, FD2, FD3) to a reset level (V_RST), a transfer gate (TG) that transfers the charge generated in the photovoltaic element (PD) to the first to third floating diffusions (FD1, FD2, FD3), a first DCG transistor (DCG1) that connects the first floating diffusion (FD1) and the second floating diffusion (FD2), a second DCG transistor (DCG2) that connects the second floating diffusion (FD2) and the third floating diffusion (FD3), and first to third pixel circuits (131, 132, 133). The first to third pixel circuits (131, 132, 133) may be similar to the first to third pixel circuits (121, 122, 123) of FIG. 17a.

[0095] The first output voltage (V_OUT1) output from the output terminal of the first pixel circuit (131) can be provided to the first analog-to-digital converter (610). The second and third output voltages (V_OUT2, V_OUT3) output from the output terminals of the second and third pixel circuits (132, 133) can be provided to the second analog-to-digital converter (620).

[0096] The operation of FIG. 24 may be similar to the operation of FIG. 3 described with reference to FIG. 4 to 10. That is, the first to third floating diffusions (FD1, FD2, FD3) are each electrically separated, and different output voltages (V_OUT1, V_OUT2, V_OUT3) can be simultaneously output by using the first to third pixel circuits (131, 132, 133) to simultaneously sense the voltage of each floating diffusion.

[0097] FIG. 25 is a drawing for illustrating a stacked structure of an image sensing device according to some other embodiments of the present invention. The stacked structure of FIG. 25 may be similar to the stacked structure of the image sensing device of FIG. 15.

[0098] Referring to FIG. 25, the second plate (P2) may include a first zone (P2_1) and a second zone (P2_2). The second zone (P2_2) may be formed physically separated from the first zone (P2_1). In this case, the first analog-to-digital converter (610) may be placed in the first zone (P2_1), and the second analog-to-digital converter (620) may be placed in the second zone (P2_2). The logic circuit (200) may be placed in the pixel peripheral zone (PS) or in the third plate (P3).

[0099] FIG. 26 is a drawing for illustrating a stacked structure of an image sensing device according to some other embodiments of the present invention. The stacked structure of FIG. 26 may be similar to the stacked structure of the image sensing device of FIG. 14.

[0100] Referring to FIG. 26, the third plate (P3) may include a first zone (P3_1) and a second zone (P3_2). The second zone (P3_2) may be formed physically separated from the first zone (P3_1). In this case, the first analog-to-digital converter (610) may be placed in the first zone (P3_1), and the second analog-to-digital converter (620) may be placed in the second zone (P3_2). The logic circuit (200) may be placed in the pixel peripheral zone (PS) or in the second plate (P2).

[0101] FIG. 27 is a drawing for illustrating a stacked structure of an image sensing device according to some other embodiments of the present invention. The stacked structure of FIG. 27 may be similar to the stacked structure of the image sensing device of FIG. 22.

[0102] Referring to FIG. 27, the first analog-to-digital converter (610) may be placed in the pixel area (PS) of the first plate (P1). The second analog-to-digital converter (620) may be placed in the second plate (P2). The logic circuit (200) may be placed in the pixel area (PS) or in the third plate (P3).

[0103] FIG. 28 is a drawing for illustrating a stacked structure of an image sensing device according to some other embodiments of the present invention. The stacked structure of FIG. 28 may be similar to the stacked structure of the image sensing device of FIG. 27.

[0104] Referring to FIG. 28, the first analog-to-digital converter (610) may be placed in the pixel area (PS) of the first plate (P1). The second analog-to-digital converter (620) may be placed in the third plate (P3). The logic circuit (200) may be placed in the pixel area (PS) or in the second plate (P2).

[0105] FIGS. 29 and FIGS. 30 are block diagrams of an electronic device including a multi-camera module. FIG. 31 is a detailed block diagram of the camera module of FIGS. 29 and FIGS. 30. In the following, the image sensing device (1140) may be similar to the image sensing device (1) shown in FIG. 1, the image sensing device (2) shown in FIG. 16, and the image sensing device (3) shown in FIG. 23.

[0106] Referring to FIG. 29, the electronic device (1000) may include a camera module group (1100), an application processor (1200), a PMIC (1300), and an external memory (1400).

[0107] The camera module group (1100) may include a plurality of camera modules (1100a, 1100b, 1100c). Although an embodiment in which three camera modules (1100a, 1100b, 1100c) are arranged is illustrated in the drawings, the embodiments are not limited thereto. In some embodiments, the camera module group (1100) may be modified to include only two camera modules or to include n camera modules (where n is a natural number greater than or equal to 4).

[0108] Hereinafter, with reference to FIG. 31, the detailed configuration of the camera module (1100b) will be described in more detail, but the following description may be applied equally to other camera modules (1100a, 1100b) according to the embodiment.

[0109] Referring to FIG. 31, the camera module (1100b) may include a prism (1105), an optical path folding element (hereinafter, ½OPFE½) (1110), an actuator (1130), an image sensing device (1140), and a storage unit (1150).

[0110] The prism (1105) can modify the path of light (L) incident from the outside by including a reflective surface (1107) of a light-reflecting material.

[0111] In some embodiments, the prism (1105) can change the path of light (L) incident in a first direction (X) to a second direction (Y) perpendicular to the first direction (X). Additionally, the prism (1105) can change the path of light (L) incident in the first direction (X) to a second direction (Y) perpendicular to the first direction (X) by rotating the reflective surface (1107) of the light-reflecting material in direction A around the central axis (1106) or by rotating the central axis (1106) in direction B. At this time, the OPFE (1110) can also move in a third direction (Z) perpendicular to the first direction (X) and the second direction (Y).

[0112] In some embodiments, as illustrated, the maximum rotation angle in the A direction of the prism (1105) may be 15 degrees or less in the plus (+) A direction and greater than 15 degrees in the minus (-) A direction, but the embodiments are not limited thereto.

[0113] In some embodiments, the prism (1105) can move in the plus (+) or minus (-) B direction by about 20 degrees, or between 10 and 20 degrees, or between 15 and 20 degrees, where the angle of movement can be moved by the same angle in the plus (+) or minus (-) B direction, or by a nearly similar angle within a range of about 1 degree.

[0114] In some embodiments, the prism (1105) can move the reflective surface (1106) of the light-reflecting material in a third direction (e.g., Z direction) parallel to the extension direction of the central axis (1106).

[0115] In some embodiments, the camera module (1100b) may be composed of two or more prisms, thereby allowing the path of light (L) incident in a first direction (X) to be varied to a second direction (Y) perpendicular to the first direction (X), then to the first direction (X) or a third direction (Z), and then to the second direction (Y).

[0116] OPFE (1110) may include, for example, groups of m (where m is a natural number) optical lenses. The m lenses can be moved in a second direction (Y) to change the optical zoom ratio of the camera module (1100b). For example, when the basic optical zoom ratio of the camera module (1100b) is Z, moving the m optical lenses included in the OPFE (1110) may change the optical zoom ratio of the camera module (1100b) to 3Z or 5Z or an optical zoom ratio of 5Z or more.

[0117] The actuator (1130) can move the OPFE (1110) or the optical lens (hereinafter referred to as the optical lens) to a specific position. For example, the actuator (1130) can adjust the position of the optical lens so that the image sensor (1142) is positioned at the focal length of the optical lens for accurate sensing.

[0118] The image sensing device (1140) may include an image sensor (1142), control logic (1144), and memory (1146). The image sensor (1142) can sense an image of a sensing target using light (L) provided through an optical lens. The control logic (1144) can control the overall operation of the camera module (1100b) and process the sensed image. For example, the control logic (1144) can control the operation of the camera module (1100b) according to a control signal provided through a control signal line (CSLb) and can extract image data corresponding to a specific image (e.g., a person's face, arm, leg, etc. within the image) from the sensed image.

[0119] In some embodiments, the control logic (1144) can perform image processing such as encoding and noise reduction of the sensed image.

[0120] The memory (1146) can store information necessary for the operation of the camera module (1100b), such as calibration data (1147). Calibration data (1147) is information necessary for the camera module (1100b) to generate image data using light (L) provided from the outside, and may include, for example, information regarding the degree of rotation, information regarding the focal length, information regarding the optical axis, etc. If the camera module (1100b) is implemented in the form of a multi-state camera in which the focal length changes according to the position of the optical lens, the calibration data (1147) may include focal length values ​​for each position (or state) of the optical lens and information related to auto-focusing.

[0121] The storage unit (1150) can store image data sensed through the image sensor (1142). The storage unit (1150) may be placed outside the image sensing device (1140) and may be implemented in a stacked form with the sensor chip constituting the image sensing device (1140). In some embodiments, the image sensor (1142) may be composed of a first plate, and the control logic (1144), the storage unit (1150), and the memory (1146) may be composed of a first plate or a second plate, so that a plurality of plates are stacked. The stacked structure of the image sensing device (1140) is as described above.

[0122] In some embodiments, the storage unit (1150) may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory), but the embodiments are not limited thereto. In some embodiments, the image sensor (1142) is composed of a pixel array, and the control logic (1144) may include an analog-to-digital converter and an image signal processing unit for processing the sensed image.

[0123] Referring to FIG. 29 and FIG. 31 together, in some embodiments, each of the plurality of camera modules (1100a, 1100b, 1100c) may include an actuator (1130). Accordingly, each of the plurality of camera modules (1100a, 1100b, 1100c) may include identical or different calibration data (1147) according to the operation of the actuator (1130) included therein.

[0124] In some embodiments, one of the plurality of camera modules (1100a, 1100b, 1100c) camera module (e.g., 1100b) is a camera module in the form of a folded lens including the previously described prism (1105) and OPFE (1110), and the remaining camera modules (e.g., 1100a, 1100c) may be camera modules in the form of a vertical camera module that do not include the prism (1105) and OPFE (1110), but are not limited thereto.

[0125] In some embodiments, one of the plurality of camera modules (1100a, 1100b, 1100c) (e.g., 1100c) may be a vertical depth camera that extracts depth information using, for example, IR (Infrared Ray). In this case, the application processor (1200) may generate a 3D depth image by merging image data provided from this depth camera with image data provided from another camera module (e.g., 1100a or 1100b).

[0126] In some embodiments, at least two of the plurality of camera modules (1100a, 1100b, 1100c) may have different field of view angles. In this case, for example, the optical lenses of at least two of the plurality of camera modules (1100a, 1100b, 1100c) may be different from each other, but are not limited thereto.

[0127] Additionally, in some embodiments, the field of view of each of the plurality of camera modules (1100a, 1100b, 1100c) may be different from one another. For example, camera module (1100a) may be an ultrawide camera, camera module (1100b) may be a wide camera, and camera module (1100c) may be a tele camera, but is not limited thereto. In this case, the optical lenses included in each of the plurality of camera modules (1100a, 1100b, 1100c) may also be different from one another, but are not limited thereto.

[0128] In some embodiments, each of the plurality of camera modules (1100a, 1100b, 1100c) may be physically separated from one another. That is, instead of the plurality of camera modules (1100a, 1100b, 1100c) dividing and using the sensing area of ​​a single image sensor (1142), an independent image sensor (1142) may be placed inside each of the plurality of camera modules (1100a, 1100b, 1100c).

[0129] Referring again to FIG. 29, the application processor (1200) may include an image processing device (1210), a memory controller (1220), and an internal memory (1230). The application processor (1200) may be implemented separated from each other, for example, by a plurality of camera modules (1100a, 1100b, 1100c) and a separate semiconductor chip.

[0130] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c), an image generator (1214), and a camera module controller (1216).

[0131] The image processing device (1210) may include a plurality of sub-image processors (1212a, 1212b, 1212c) corresponding to the number of camera modules (1100a, 1100b, 1100c).

[0132] Image data generated from the camera module (1100a) may be provided to the sub-image processor (1212a) via the image signal line (ISLa), image data generated from the camera module (1100b) may be provided to the sub-image processor (1212b) via the image signal line (ISLb), and image data generated from the camera module (1100c) may be provided to the sub-image processor (1212c) via the image signal line (ISLc). Such image data transmission may be performed, for example, using a Camera Serial Interface (CSI) based on the Mobile Industry Processor Interface (MIPI), but is not limited thereto.

[0133] Meanwhile, in some embodiments, a single sub-image processor may be arranged to correspond to a plurality of camera modules. For example, the sub-image processor (1212a) and the sub-image processor (1212c) are not implemented separately as illustrated, but are integrated into a single sub-image processor, and image data provided from the camera module (1100a) and the camera module (1100c) may be selected through a selection element (e.g., a multiplexer) and then provided to the integrated sub-image processor. At this time, the sub-image processor (1212b) is not integrated and may receive image data from the camera module (1100b).

[0134] Additionally, in some embodiments, image data generated from a camera module (1100a) may be provided to a sub-image processor (1212a) via an image signal line (ISLa), image data generated from a camera module (1100b) may be provided to a sub-image processor (1212b) via an image signal line (ISLb), and image data generated from a camera module (1100c) may be provided to a sub-image processor (1212c) via an image signal line (ISLc). Furthermore, image data processed by the sub-image processor (1212b) may be provided directly to an image generator (1214), but image data processed by the sub-image processor (1212a) and image data processed by the sub-image processor (1212c) may be provided to the image generator (1214) after one of them is selected through a selection element (e.g., a multiplexer).

[0135] Each sub-image processor (1212a, 1212b, 1212c) can perform image processing such as bad pixel correction, 3A adjustment (Auto-focus correction, Auto-white balance, Auto-exposure), noise reduction, sharpening, gamma control, and remosaic on image data provided from the camera module (1100a, 1100b, 1100c).

[0136] In some embodiments, remosaic signal processing may be performed in each camera module (1100a, 1100b, 1100c) and then provided to a sub-image processor (1212a, 1212b, 1212c).

[0137] Image data processed by each sub-image processor (1212a, 1212b, 1212c) can be provided to an image generator (1214). The image generator (1214) can generate an output image using image data provided from each sub-image processor (1212a, 1212b, 1212c) according to image generating information or a mode signal.

[0138] Specifically, the image generator (1214) can generate an output image by merging at least some of the image data generated from the image processors (1212a, 1212b, 1212c) according to image generation information or a mode signal. Additionally, the image generator (1214) can generate an output image by selecting any one of the image data generated from the image processors (1212a, 1212b, 1212c) according to image generation information or a mode signal.

[0139] In some embodiments, the image generation information may include a zoom signal (or zoom factor). Additionally, in some embodiments, the mode signal may be a signal based, for example, on a mode selected by a user.

[0140] When the image generation information is a zoom signal (zoom factor) and each camera module (1100a, 1100b, 1100c) has a different viewing angle (angle of view), the image generator (1214) can perform different operations depending on the type of zoom signal. For example, when the zoom signal is a first signal, among the image data output from the sub-image processor (1212a) and the image data output from the sub-image processor (1212c), the image data output from the sub-image processor (1212a) and the image data output from the sub-image processor (1212b) can be used to generate an output image. If the zoom signal is a second signal different from the first signal, the image generator (1214) can generate an output image by using the image data output from the sub-image processor (1212c) and the image data output from the sub-image processor (1212b), among the image data output from the sub-image processor (1212a) and the image data output from the sub-image processor (1212c). If the zoom signal is a third signal different from the first and second signals, the image generator (1214) can generate an output image by selecting any one of the image data output from each sub-image processor (1212a, 1212b, 1212c) without performing such image data merging. However, the embodiments are not limited thereto, and the method of processing image data can be modified as needed.

[0141] Referring to FIG. 30, in some embodiments, the image processing device (1210) may further include a selection unit (1213) that selects the output of sub-image processors (1212a, 1212b, 1212c) and transmits it to an image generator (1214).

[0142] In this case, the selection unit (1213) can perform different operations depending on the zoom signal or zoom factor. For example, when the zoom signal is the fourth signal (e.g., the zoom magnification is the first magnification), the selection unit (1213) can select one of the outputs of the sub-image processors (1212a, 1212b, 1212c) and transmit it to the image generator (1214).

[0143] Additionally, the selection unit (1213) can sequentially transmit p outputs (p is a natural number greater than or equal to 2) among the outputs of sub-image processors (1212a, 1212b, 1212c) to the image generator (1214) when the zoom signal is a fifth signal different from the fourth signal (e.g., the zoom magnification is the second magnification). For example, the selection unit (1213) can sequentially transmit the outputs of sub-image processor (1212b) and sub-image processor (1212c) to the image generator (1214). Additionally, the selection unit (1213) can sequentially transmit the outputs of sub-image processor (1212a) and sub-image processor (1212b) to the image generator (1214). The image generator (1214) can generate a single output image by merging the p outputs received sequentially.

[0144] Here, image processing such as demosaicing, downscaling to a video / preview resolution size, gamma correction, and HDR (High Dynamic Range) processing is performed in advance in sub-image processors (1212a, 1212b, 1212c), and then the processed image data is transmitted to the image generator (1214). Therefore, even if the processed image data is provided to the image generator (1214) as a single signal line through the selection unit (1213), the image merging operation of the image generator (1214) can be performed at high speed.

[0145] In some embodiments, the image generator (1214) receives multiple image data with different exposure times from at least one of a plurality of sub-image processors (1212a, 1212b, 1212c) and performs HDR (high dynamic range) processing on the multiple image data to generate merged image data with increased dynamic range.

[0146] The camera module controller (1216) can provide control signals to each camera module (1100a, 1100b, 1100c). The control signals generated from the camera module controller (1216) can be provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0147] One of the plurality of camera modules (1100a, 1100b, 1100c) may be designated as a master camera (e.g., 1100b) according to image generation information including a zoom signal or a mode signal, and the remaining camera modules (e.g., 1100a, 1100c) may be designated as slave cameras. This information may be included in a control signal and provided to the corresponding camera modules (1100a, 1100b, 1100c) through separate control signal lines (CSLa, CSLb, CSLc).

[0148] The camera module operating as a master and slave may be changed according to the zoom factor or operation mode signal. For example, if the field of view of the camera module (1100a) is wider than the field of view of the camera module (1100b) and the zoom factor indicates a low zoom magnification, the camera module (1100a) may operate as a master and the camera module (1100b) may operate as a slave. Conversely, if the zoom factor indicates a high zoom magnification, the camera module (1100b) may operate as a master and the camera module (1100a) may operate as a slave.

[0149] In some embodiments, the control signal provided from the camera module controller (1216) to each camera module (1100a, 1100b, 1100c) may include a sync enable signal. For example, if the camera module (1100b) is a master camera and the camera modules (1100a, 1100c) are slave cameras, the camera module controller (1216) may transmit a sync enable signal to the camera module (1100b). The camera module (1100b) that receives this sync enable signal may generate a sync signal based on the received sync enable signal and provide the generated sync signal to the camera modules (1100a, 1100c) through a sync signal line (SSL). The camera module (1100b) and camera modules (1100a, 1100c) can be synchronized with this sync signal to transmit image data to the application processor (1200).

[0150] In some embodiments, a control signal provided from a camera module controller (1216) to a plurality of camera modules (1100a, 1100b, 1100c) may include mode information according to a mode signal. Based on this mode information, the plurality of camera modules (1100a, 1100b, 1100c) may operate in a first operation mode and a second operation mode with respect to the sensing speed.

[0151] A plurality of camera modules (1100a, 1100b, 1100c) can, in a first operating mode, generate an image signal at a first speed (e.g., generate an image signal at a first frame rate) and encode it at a second speed higher than the first speed (e.g., encode an image signal at a second frame rate higher than the first frame rate), and transmit the encoded image signal to an application processor (1200). At this time, the second speed may be 30 times or less of the first speed.

[0152] The application processor (1200) stores the received image signal, that is, the encoded image signal, in a memory (1230) provided internally or in a storage (1400) outside the application processor (1200), and subsequently reads the encoded image signal from the memory (1230) or the storage (1400) to decode it, and can display image data generated based on the decoded image signal. For example, a corresponding sub-image processor among a plurality of sub-image processors (1212a, 1212b, 1212c) of the image processing device (1210) can perform decoding and can also perform image processing on the decoded image signal.

[0153] A plurality of camera modules (1100a, 1100b, 1100c) can generate an image signal at a third speed lower than a first speed in a second operation mode (e.g., generate an image signal at a third frame rate lower than a first frame rate) and transmit the image signal to an application processor (1200). The image signal provided to the application processor (1200) may be an unencoded signal. The application processor (1200) may perform image processing on the received image signal or store the image signal in memory (1230) or storage (1400).

[0154] The PMIC (1300) can supply power, such as power voltage, to each of the plurality of camera modules (1100a, 1100b, 1100c). For example, the PMIC (1300) can supply first power to the camera module (1100a) through a power signal line (PSLa), supply second power to the camera module (1100b) through a power signal line (PSLb), and supply third power to the camera module (1100c) through a power signal line (PSLc), under the control of the application processor (1200).

[0155] The PMIC (1300) can generate power corresponding to each of the plurality of camera modules (1100a, 1100b, 1100c) and adjust the power level in response to a power control signal (PCON) from the application processor (1200). The power control signal (PCON) may include power adjustment signals for each operating mode of the plurality of camera modules (1100a, 1100b, 1100c). For example, the operating mode may include a low power mode, and in this case, the power control signal (PCON) may include information about the camera module operating in the low power mode and the power level being set. The power levels provided to each of the plurality of camera modules (1100a, 1100b, 1100c) may be the same or different from each other. Additionally, the power level may be changed dynamically.

[0156] Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical concept or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0157] Pixel array (100) First plate (P1) Second plate (P2) Third plate (P3) Pixel Array Area (PA) Pixel surrounding area (PS) Photovoltaic device (PD) Transfer Gate (TG) / Transfer Gate Signal (S_TG) 1st, 2nd, and 3rd floating diffusions (FD1, FD2, FD3) First analog-to-digital converter (310) DCG Transistor (DCG) / DCG Control Signal (S_DCG) Reset Transistor (RT) / Reset Signal (RESET) Pixel voltage (V_PIX)

Claims

Claim 1 A photoelectric element that generates charge in response to light; a first floating diffusion in which the charge generated by the photoelectric element is stored; a second floating diffusion in which the charge generated by the photoelectric element is stored; a third floating diffusion in which the charge generated by the photoelectric element is stored; a transfer gate, one end of which is connected to the photoelectric element and the other end of which is connected to the first floating diffusion; a reset transistor that resets the voltages of the first and second floating diffusions based on a reset signal; a first DCG (Dual Conversion Gain) transistor, one end of which is directly connected to the first floating diffusion and the other end of which is directly connected to the second floating diffusion, and a first DCG transistor that connects the first floating diffusion and the second floating diffusion based on a first DCG control signal; a second DCG transistor, one end of which is directly connected to the second floating diffusion and the other end of which is directly connected to the third floating diffusion, and the second floating diffusion based on a second DCG control signal A second DCG transistor connecting the diffusion and the third floating diffusion; a first pixel circuit generating a first output voltage based on the voltage of the first floating diffusion; a second pixel circuit generating a second output voltage based on the voltage of the second floating diffusion; a third pixel circuit generating a third output voltage based on the voltage of the third floating diffusion; a first analog-to-digital converter receiving the first output voltage and converting it into a first digital signal; and a second analog-to-digital converter disposed separately from the first analog-to-digital converter, receiving the second output voltage and converting it into a second digital signal.An image sensing device comprising a third analog-digital converter that is disposed separately from the first and second analog-digital converters and receives the third output voltage and converts it into a third digital signal, wherein the first pixel circuit includes a first source follower transistor and the second pixel circuit includes a second source follower transistor, the gate of the first source follower transistor is directly connected to the first floating diffusion and the gate of the second source follower transistor is directly connected to the second floating diffusion, the reset transistor is directly connected to the first floating diffusion but not directly connected to the second floating diffusion, the first analog-digital converter is disposed on a first plate and the second analog-digital converter is disposed on a second plate different from the first plate. Claim 2 In claim 1, the threshold voltages of the first and second source follower transistors are different image sensing devices. Claim 3 delete Claim 4 delete Claim 5 An image sensing device according to claim 1, wherein the photoelectric element is disposed on the first plate, and the first floating diffusion is disposed on a third plate formed parallel to the first and second plates. Claim 6 An image sensing device comprising: a first pixel circuit that generates a first output voltage in a high-conversion manner based on a charge generated by one photoelectric element and outputs the same; a first analog-to-digital converter that receives the first output voltage and converts it into a first digital signal; a second pixel circuit that generates a second output voltage different from the first output voltage in a low-conversion manner based on a charge generated by the one photoelectric element and outputs the same; a second analog-to-digital converter that receives the second output voltage and converts it into a second digital signal; a third pixel circuit that generates a third output voltage different from the first and second output voltages in a manner different from the high-conversion and low-conversion methods based on a charge received from the one photoelectric element and outputs the same; and a third analog-to-digital converter that receives the third output voltage and converts it into a third digital signal, wherein the first analog-to-digital converter is disposed on a first plate and the second analog-to-digital converter is disposed on a second plate different from the first plate. Claim 7 delete Claim 8 Based on a first DCG control signal, a first floating diffusion and a second floating diffusion are connected, and a reset transistor directly connected to the first floating diffusion and not directly connected to the second floating diffusion resets the voltage levels of the first floating diffusion and the second floating diffusion to a reset level, based on a charge generated from a photoelectric element, the voltage level of the first floating diffusion is transitioned from the reset level to a first signal level, and based on a charge generated from the photoelectric element, the voltage level of the second floating diffusion is transitioned from the reset level to a second signal level different from the first signal level, and based on the charge generated from the photoelectric element, the first floating diffusion and the second floating diffusion are separated based on the first DCG control signal, a first digital signal is generated based on the level difference between the reset level of the first floating diffusion and the first signal level, and based on the level difference between the reset level of the second floating diffusion and the second signal level A method of operating an image sensing device comprising generating a second digital signal, connecting the second floating diffusion and the third floating diffusion based on a second DCG control signal, resetting the voltage level of the third floating diffusion to a reset level, transitioning the voltage level of the third floating diffusion from the reset level to a third signal level based on a charge generated from the photoelectric element, separating the second floating diffusion and the third floating diffusion based on the second DCG control signal, and generating a third digital signal based on the level difference between the reset level and the third signal level of the third floating diffusion. Claim 9 delete Claim 10 A method of operation of an image sensing device according to claim 8, wherein, before the first to third digital signals are generated, the first floating diffusion and the second floating diffusion are separated based on the first DCG control signal, and the second floating diffusion and the third floating diffusion are separated based on the second DCG control signal. Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 delete Claim 18 delete Claim 19 delete Claim 20 delete

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