Semiconductor memory device

Abstract

A semiconductor memory device according to the concept of the present invention comprises: a substrate including a memory cell region and a test region; an active pattern provided on the memory cell region; a source / drain pattern provided on the active pattern; a dummy pattern provided on the test region; a first gate electrode extending in a first direction on the dummy pattern; a first shared contact in contact with the dummy pattern and the first gate electrode; and a first wiring layer on the first shared contact, wherein the first wiring layer includes a first test wiring electrically connected to the first shared contact, and the first shared contact includes a first contact pattern in contact with the dummy pattern and a first gate contact electrically connected to the first gate electrode, and the first gate contact includes a body portion connected to the first gate electrode and a protrusion extending from the body portion into the first contact pattern, and the lowest level of the upper surface of the active pattern may be lower than the lowest level of the upper surface of the dummy pattern.

Description

Technology Field

[0001] The present invention relates to a semiconductor memory device, and more specifically, to a semiconductor memory device including an SRAM cell. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements. As the electronics industry advances, demands regarding the characteristics of semiconductor devices are steadily increasing. For example, there is a growing demand for high reliability, high speed, and / or multifunctionality. To meet these requirements, the internal structures of semiconductor devices are becoming increasingly complex, and semiconductor devices are becoming more highly integrated. Prior art literature

[65535] US Patent Publication 2021 / 0210479 (Published July 8, 2021) US Patent Publication 6,465,266 (Published October 15, 2002) The problem to be solved

[0003] The problem that the present invention aims to solve is to provide a semiconductor memory device that facilitates defect detection. means of solving the problem

[0004] A semiconductor memory device according to the concept of the present invention comprises: a substrate including a memory cell region and a test region; an active pattern provided on the memory cell region; a source / drain pattern provided on the active pattern; a dummy pattern provided on the test region; a first gate electrode extending in a first direction on the dummy pattern; a first shared contact in contact with the dummy pattern and the first gate electrode; and a first wiring layer on the first shared contact, wherein the first wiring layer includes a first test wiring electrically connected to the first shared contact, and the first shared contact includes a first contact pattern in contact with the dummy pattern and a first gate contact electrically connected to the first gate electrode, and the first gate contact includes a body portion connected to the first gate electrode and a protrusion extending from the body portion into the first contact pattern, and the lowest level of the upper surface of the active pattern may be lower than the lowest level of the upper surface of the dummy pattern.

[0005] According to another concept of the present invention, a semiconductor memory device comprises: a memory cell region and a test region on a substrate; a dummy pattern provided on the test region; a first gate electrode extending in a first direction on the dummy pattern; a first shared contact in contact with the dummy pattern and the first gate electrode; a second gate electrode spaced apart from the first gate electrode in a second direction intersecting the first direction; and a second shared contact spaced apart from the first shared contact in the first direction. and a first wiring layer provided on the first and second shared contacts and connected thereto, wherein the first wiring layer includes a first test wiring and a second test wiring that extend in the second direction and are electrically connected to the first and second shared contacts, respectively, and the first shared contact includes a first contact pattern that contacts the dummy pattern and a first gate contact that is electrically connected to the first gate electrode, and the second shared contact includes a second contact pattern that contacts the dummy pattern and a second gate contact that is electrically connected to the second gate electrode, wherein the first gate contact may include a first body portion connected to the first gate electrode and a first protrusion extending from the first body portion into the first contact pattern.

[0006] According to another concept of the present invention, a semiconductor memory device comprises: a substrate including a memory cell region and a test region; an active pattern provided on the memory cell region; a source / drain pattern provided on the active pattern; a dummy pattern provided on the test region; a device isolation film provided on the substrate and covering the lower sidewalls of each of the active pattern and the dummy pattern, wherein the upper portions of each of the active pattern and the dummy pattern protrude over the device isolation film; a first gate electrode provided on the active pattern and extending in a first direction, wherein the first gate electrode and the source / drain pattern are adjacent to each other in a second direction intersecting the first direction; a first shared contact connected to the source / drain pattern and the first gate electrode to electrically connect them; a second gate electrode extending in the first direction on the dummy pattern; a second shared contact in contact with the dummy pattern and the second gate electrode; a gate spacer on the sidewalls of each of the first and second gate electrodes; a gate capping pattern on the upper surface of each of the first and second gate electrodes; and an interlayer insulating film on the gate capping pattern.A first wiring layer, a second wiring layer, and a third wiring layer are sequentially stacked on the interlayer insulating film, wherein the first shared contact includes an active contact electrically connected to the source / drain pattern by penetrating the interlayer insulating film and a first gate contact electrically connected to the first gate electrode by penetrating the gate capping pattern, and the second shared contact includes a first contact pattern contacting the dummy pattern by penetrating the interlayer insulating film and a second gate contact electrically connected to the second gate electrode by penetrating the gate capping pattern, wherein the first gate contact includes a first body portion connected to the first gate electrode and a first protrusion extending from the first body portion into the active pattern, and the second gate contact includes a second body portion connected to the second gate electrode and a second protrusion extending from the second body portion into the first contact pattern, and the first wiring layer is electrically connected to the second shared contact and extends in the second direction It includes a first test wiring, and the lowest level of the upper surface of the active pattern may be lower than the lowest level of the upper surface of the dummy pattern.; Effects of the invention

[0007] According to the present invention, short-circuit defects can be measured in a non-destructive manner by using a voltage ramping method in which different voltages are applied to each of the first test wiring and the second test wiring to gradually increase the difference. Accordingly, the time required to detect short-circuit defects between the active contact and the gate electrode, which occur as the size of the semiconductor device decreases, can be reduced, and costs can be reduced by preventing wafer loss due to destructive analysis. As a result, defect detection in semiconductor memory devices can be made easier. Brief explanation of the drawing

[0008] FIG. 1 is an equivalent circuit diagram of an SRAM cell according to embodiments of the present invention. FIG. 2 is a perspective view showing wiring layers of a semiconductor memory device according to embodiments of the present invention. Figure 3 is a plan view showing the memory cell of Figure 2. FIG. 4 is a plan view for illustrating a semiconductor memory device according to embodiments of the present invention. FIGS. 5a to 5j are cross-sectional views along the lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', H-H', I-I', and J-J' of FIG. 4, respectively. Figure 6a is an enlarged cross-sectional view of the M region of Figure 5b. FIG. 6b is a simplified perspective view of the first shared contact of FIG. 6a. FIGS. 7a to 11h are cross-sectional views for explaining a method for manufacturing a semiconductor memory device according to embodiments of the present invention. FIGS. 12a to 12c are cross-sectional views along the G-G', I-I', and J-J' lines of FIG. 4, respectively, for illustrating semiconductor memory devices according to embodiments of the present invention. FIGS. 13a to 13c are cross-sectional views along the lines A-A', B-B', and D-D' of FIG. 4, respectively, for illustrating semiconductor memory devices according to embodiments of the present invention. Specific details for implementing the invention

[0009] FIG. 1 is an equivalent circuit diagram of an SRAM cell according to embodiments of the present invention.

[0010] Referring to FIG. 1, an SRAM cell according to embodiments of the present invention may include a first pull-up transistor (TU1), a first pull-down transistor (TD1), a second pull-up transistor (TU2), a second pull-down transistor (TD2), a first pass-gate transistor (TA1), and a second pass-gate transistor (TA2). The first and second pull-up transistors (TU1, TU2) may be PMOS transistors. The first and second pull-down transistors (TD1, TD2) and the first and second pass-gate transistors (TA1, TA2) may be NMOS transistors.

[0011] The first source / drain of the first pull-up transistor (TU1) and the first source / drain of the first pull-down transistor (TD1) can be connected to the first node (N1). The second source / drain of the first pull-up transistor (TU1) can be connected to the power line (VDD), and the second source / drain of the first pull-down transistor (TD1) can be connected to the ground line (VSS). The gate of the first pull-up transistor (TU1) and the gate of the first pull-down transistor (TD1) can be electrically connected to each other. The first pull-up transistor (TU1) and the first pull-down transistor (TD1) can constitute the first inverter. The interconnected gates of the first pull-up and first pull-down transistors (TU1, TD1) can correspond to the input terminal of the first inverter, and the first node (N1) can correspond to the output terminal of the first inverter.

[0012] The first source / drain of the second pull-up transistor (TU2) and the first source / drain of the second pull-down transistor (TD2) can be connected to the second node (N2). The second source / drain of the second pull-up transistor (TU2) can be connected to the power line (VDD), and the second source / drain of the second pull-down transistor (TD2) can be connected to the ground line (VSS). The gate of the second pull-up transistor (TU2) and the gate of the second pull-down transistor (TD2) can be electrically connected to each other. Thus, the second pull-up transistor (TU2) and the second pull-down transistor (TD2) can constitute a second inverter. The interconnected gates of the second pull-up and second pull-down transistors (TU2, TD2) can correspond to the input terminal of the second inverter, and the second node (N2) can correspond to the output terminal of the second inverter.

[0013] The first and second inverters mentioned above can be combined to form a latch structure. That is, the gates of the first pull-up and first pull-down transistors (TU1, TD1) can be electrically connected to the second node (N2), and the gates of the second pull-up and second pull-down transistors (TU2, TD2) can be electrically connected to the first node (N1). The first source / drain of the first pass-gate transistor (TA1) can be connected to the first node (N1), and the second source / drain of the first pass-gate transistor (TA1) can be connected to the first bit line (BL1). The first source / drain of the second pass-gate transistor (TA2) can be connected to the second node (N2), and the second source / drain of the second pass-gate transistor (TA2) can be connected to the second bit line (BL2). The gates of the first and second pass-gate transistors (TA1, TA2) can be electrically connected to the word line (WL). Thus, an SRAM cell according to embodiments of the present invention can be implemented.

[0015] FIG. 2 is a perspective view showing wiring layers of a semiconductor memory device according to embodiments of the present invention. FIG. 3 is a plan view showing a memory cell of FIG. 2.

[0016] Referring to FIGS. 2 and FIGS. 3, a memory cell (CE) may be provided on a substrate (100). Referring to FIG. 3, the memory cell (CE) may include first to fourth bit cells (CE1-CE4) arranged in a 2x2 configuration. Each of the first to fourth bit cells (CE1-CE4) may be an SRAM cell as described above with reference to FIG. 1. Typically, a specific structure regarding the first bit cell (CE1) will be described later with reference to FIGS. 4 and FIGS. 5a to 5e. Each of the second to fourth bit cells (CE2, CE3, CE4) may have a symmetrical structure with respect to the first bit cell (CE1).

[0017] A first wiring layer (M1), a second wiring layer (M2), and a third wiring layer (M3) may be provided on a memory cell (CE). The first to third wiring layers (M1, M2, M3) may be stacked sequentially. The first to third wiring layers (M1, M2, M3) may include at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0018] The first wiring layer (M1) may include a first bit line (BL1), a second bit line (BL2), and a power line (VDD) extending in a second direction (D2). The power line (VDD) may be interposed between the first bit line (BL1) and the second bit line (BL2). In a planar view, the first bit line (BL1), the second bit line (BL2), and the power line (VDD) may have a line shape. The width of the power line (VDD) in the first direction (D1) may be greater than the width of each of the first and second bit lines (BL1, BL2) in the first direction (D1).

[0019] The first wiring layer (M1) may further include a first lower landing pad (LLP1) and a second lower landing pad (LLP2) adjacent to the first and second bit lines (BL1, BL2). The first and second lower landing pads (LLP1, LLP2) may be arranged along a second direction (D2). In a planar view, the first and second lower landing pads (LLP1, LLP2) may have an island shape.

[0020] The first wiring layer (M1) may further include first vias provided under the first bit line (BL1), the second bit line (BL2), the power line (VDD), the first lower landing pad (LLP1), and the second lower landing pad (LLP2), respectively. Through the first vias, the memory cell (CE) and the first wiring layer (M1) may be electrically connected.

[0021] The second wiring layer (M2) may include a ground line (VSS) and an upper landing pad (ULP). The ground line (VSS) may be a mesh-shaped conductive structure. The ground line (VSS) may have at least one first opening (OP1). Specifically, the ground line (VSS) may include a first part (P1) extending in a second direction (D2) and a second part (P2) extending in the first direction (D1). The width of the first part (P1) may be greater than the width of the second part (P2). The first opening (OP1) may be defined by a pair of first parts (P1) adjacent to each other and a pair of second parts (P2) adjacent to each other.

[0022] A pair of upper landing pads (ULP) may be disposed within the first opening (OP1). The pair of upper landing pads (ULP) within the first opening (OP1) may be arranged in a second direction (D2). In a planar view, the upper landing pads (ULP) may have an island shape.

[0023] The second portions (P2) of the ground line (VSS) may each be vertically overlapped with the first lower landing pads (LLP1). The upper landing pads (ULP) may each be vertically overlapped with the second lower landing pads (LLP2).

[0024] The second wiring layer (M2) may further include second vias (VI2) provided below the ground line (VSS) and the upper landing pad (ULP), respectively. The ground line (VSS) may be electrically connected to the first lower landing pad (LLP1) of the first wiring layer (M1) through the second vias (VI2). Since multiple second vias (VI2) are provided below the ground line (VSS), multiple first lower landing pads (LLP1) may be commonly connected to a single ground line (VSS). The upper landing pad (ULP) may be electrically connected to the second lower landing pad (LLP2) of the first wiring layer (M1) through the second vias (VI2).

[0025] According to embodiments of the present invention, the second wiring layer (M2) may consist only of a ground line (VSS), upper landing pads (ULP), and second vias (VI2). In other words, the second wiring layer (M2) may not include other lines (e.g., bit line, power line, and word line) other than the ground line (VSS).

[0026] The third wiring layer (M3) may include word lines (WL) extending in a first direction (D1). The word lines (WL) may be arranged in a second direction (D2). In a planar view, the word lines (WL) may have a line shape.

[0027] The third wiring layer (M3) may further include a third via (VI3) provided below the word line (WL). The word line (WL) may be electrically connected to the upper landing pad (ULP) of the second wiring layer (M2) through the third via (VI3). In other words, the word line (WL) may be electrically connected to the second lower landing pad (LLP2) of the first wiring layer (M1) through the third via (VI3), the upper landing pad (ULP), and the second via (VI2).

[0028] According to embodiments of the present invention, the third wiring layer (M3) may be composed only of word lines (WL) and third vias (VI3). In other words, the third wiring layer (M3) may not include other lines (e.g., bit lines, power lines, and ground lines) other than the word lines (WL).

[0030] FIG. 4 is a plan view for illustrating a semiconductor memory device according to embodiments of the present invention. FIGS. 5a to 5j are cross-sectional views along lines A-A', B-B', C-C', D-D', E-E', F-F', G-G', H-H', I-I', and J-J' of FIG. 4, respectively. FIG. 6a is an enlarged cross-sectional view of region M of FIG. 5b. FIG. 6b is a simplified perspective view of the first shared contact of FIG. 6a.

[0031] Referring to FIGS. 1, FIGS. 3, FIGS. 4 and FIGS. 5a through 5j, a substrate (100) including a memory cell region (MCR) and a test region (TSR) may be provided. The memory cell region (MCR) may include a first bit cell (CE1) and a second bit cell (CE2). The test region (TSR) may include a first test cell (TC1) and a second test cell (TC2). Each of the first bit cell (CE1) and the second bit cell (CE2) on the substrate (100) may include an SRAM cell of FIG. 1. That is, the memory cell region (MCR) may be an area on the substrate (100) where an SRAM cell is placed. In one example, the test region (TSR) may be an area on the substrate (100) where an SRAM cell is not placed. In another example, the test region (TSR) may be an area where a scribe line is formed.

[0032] The second bit cell (CE2) may be disposed adjacent to the first bit cell (CE1) in the second direction (D2). First and second active patterns (AP1, AP2), gate electrodes (GE), active contacts (AC), and gate contacts (GC) may be provided on the first and second bit cells (CE1, CE2). Hereinafter, the first bit cell (CE1) will be described in detail as a representative example with reference to FIGS. 1, 3, 4 and FIGS. 5a through 5e.

[0033] A device isolation layer (ST) may be provided on a substrate (100). The device isolation layer (ST) may define first and second active patterns (AP1, AP2). The substrate (100) may be a semiconductor substrate including silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. The device isolation layer (ST) may include an insulating material such as a silicon oxide film.

[0034] The first and second active patterns (AP1, AP2) may be part of the substrate (100). A trench (TR) may be defined between the first and second active patterns (AP1, AP2) that are adjacent to each other. A device isolation layer (ST) may fill the trench (TR). The upper portions of the first and second active patterns (AP1, AP2) may protrude vertically relative to the device isolation layer (ST). Each of the upper portions of the first and second active patterns (AP1, AP2) may have a fin shape protruding vertically over the device isolation layer (ST). In other words, each of the first and second active patterns (AP1, AP2) may be an active fin.

[0035] The upper surface of the device isolation layer (ST) may include a recess region (RSR) that is recessed toward one of the trenches (TR). The recess region (RSR) may be formed only on the memory cell region (MCR) where the first and second source / drain patterns (SD1, SD2) are formed.

[0036] According to the present embodiment, the first bit cell (CE1) may include a pair of first active patterns (AP1) and two pairs of second active patterns (AP2). One pair of the two pairs of second active patterns (AP2) may form the body of the first pass-gate transistor (TA1) and the body of the first pull-down transistor (TD1). The other pair of the two pairs of second active patterns (AP2) may form the body of the second pass-gate transistor (TA2) and the body of the second pull-down transistor (TD2). One of the pair of first active patterns (AP1) may form the body of the first pull-up transistor (TU1). The other of the pair of first active patterns (AP1) may form the body of the second pull-up transistor (TU2). The spacing between a pair of adjacent first active patterns (AP1) may be larger than the spacing between a pair of adjacent second active patterns (AP2).

[0037] According to another embodiment of the present invention, instead of two pairs of second active patterns (AP2), two second active patterns (AP2) may be provided. In other words, a pair of adjacent second active patterns (AP2) may be merged to be provided as a single second active pattern (AP2).

[0038] First channel patterns (CH1) and first source / drain patterns (SD1) may be provided on top of first active patterns (AP1). Second channel patterns (CH2) and second source / drain patterns (SD2) may be provided on top of second active patterns (AP2). The first source / drain patterns (SD1) may be p-type impurity regions. The second source / drain patterns (SD2) may be n-type impurity regions. Each of the first channel patterns (CH1) may be interposed between a pair of first source / drain patterns (SD1), and each of the second channel patterns (CH2) may be interposed between a pair of second source / drain patterns (SD2).

[0039] The first and second source / drain patterns (SD1, SD2) may be epitaxial patterns formed by an optional epitaxial growth process. The upper surfaces of the first and second source / drain patterns (SD1, SD2) may be located at a higher level than the upper surfaces of the first and second channel patterns (CH1, CH2). The first and second source / drain patterns (SD1, SD2) may include semiconductor elements that are the same as or different from the substrate (100). For example, the first source / drain patterns (SD1) may include a semiconductor element having a lattice constant greater than the lattice constant of the semiconductor element of the substrate (100). Thus, the first source / drain patterns (SD1) may provide compressive stress to the first channel patterns (CH1). For example, the second source / drain patterns (SD2) may include a semiconductor element identical to the semiconductor element of the substrate (100).

[0040] Second source / drain patterns (SD2) on a pair of adjacent second active patterns (AP2) can be merged to form a single second source / drain pattern (SD2). This is because the spacing between the pair of second active patterns (AP2) is relatively small (see FIG. 5c).

[0041] The gate electrodes (GE) may include first to fourth gate electrodes (GE1-GE4) on the first bit cell (CE1). The first to fourth gate electrodes (GE1-GE4) may extend in a first direction (D1) across the first and second active patterns (AP1, AP2). The first to fourth gate electrodes (GE1-GE4) may be vertically overlapped with the first and second channel patterns (CH1, CH2). The first gate electrode (GE1) may be symmetrical with the fourth gate electrode (GE4), and the second gate electrode (GE2) may be symmetrical with the third gate electrode (GE3).

[0042] The second gate electrode (GE2) and the fourth gate electrode (GE4) can be aligned side by side in the first direction (D1). An insulating pattern (SP) can be interposed between the second gate electrode (GE2) and the fourth gate electrode (GE4) to separate them from each other. The first gate electrode (GE1) and the third gate electrode (GE3) can be aligned side by side in the first direction (D1). An insulating pattern (SP) can be interposed between the first gate electrode (GE1) and the third gate electrode (GE3) to separate them from each other.

[0043] A pair of gate spacers (GS) may be disposed on both sidewalls of the gate electrode (GE). The pair of gate spacers (GS) may extend along the gate electrode (GE) in a first direction (D1). The upper surfaces of the pair of gate spacers (GS) may be higher than the upper surface of the gate electrode (GE). The upper surfaces of the pair of gate spacers (GS) may be covered by a gate capping pattern (GP) to be described later.

[0044] The gate spacer (GS) may include at least one of SiO, SiCN, SiCON, and SiN. As another example, the gate spacer (GS) may include a multi-layer composed of at least two of SiO, SiCN, SiCON, and SiN.

[0045] A gate insulating film (GI) may be interposed between the gate electrode (GE) and the first and second active patterns (AP1, AP2). The gate insulating film (GI) may extend along the bottom surface of the gate electrode (GE).

[0046] In one embodiment of the present invention, the gate insulating film (GI) may include a high dielectric film or a combination of a silicon oxide film and a high dielectric film. The high dielectric film may include a high dielectric constant material having a higher dielectric constant than that of a silicon oxide film. As an example, the high dielectric constant material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0047] In another embodiment, the semiconductor device of the present invention may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating film (GI) may include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0048] Ferroelectric film materials can have negative capacitance, while paraelectric film materials can have positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be smaller than the capacitance of each individual capacitor. Conversely, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance will have a positive value and may be greater than the absolute value of each individual capacitance.

[0049] When a ferroelectric material film with negative capacitance and a paraelectric material film with positive capacitance are connected in series, the total capacitance value of the series-connected ferroelectric material film and paraelectric material film can increase. By utilizing the increase in the total capacitance value, a transistor containing a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0050] Ferroelectric material films may have ferroelectric properties. Ferroelectric material films may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0051] The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). Depending on which ferroelectric material the ferroelectric material film contains, the type of dopant included in the ferroelectric material film may vary.

[0052] When the ferroelectric material film contains hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0053] When the dopant is aluminum (Al), the ferroelectric material film may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be the ratio of aluminum to the sum of hafnium and aluminum.

[0054] When the dopant is silicon (Si), the ferroelectric material film may contain 2 to 10 at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may contain 2 to 10 at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may contain 1 to 7 at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may contain 50 to 80 at% zirconium.

[0055] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0056] Ferroelectric and paraelectric film layers may contain the same material. Ferroelectric film layers possess ferroelectric properties, whereas paraelectric film layers may not. For example, if both ferroelectric and paraelectric film layers contain hafnium oxide, the crystal structure of the hafnium oxide contained in the ferroelectric film layer is different from the crystal structure of the hafnium oxide contained in the paraelectric film layer.

[0057] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example, 0.5 to 10 nm, but is not limited thereto. Since the critical thickness at which ferroelectric properties are exhibited may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0058] For example, the gate insulating film (GI) may include a single ferroelectric material film. For another example, the gate insulating film (GI) may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film (GI) may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0059] The gate electrode (GE) may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on a gate insulating film (GI) and adjacent to first and second channel patterns (CH1, CH2). The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. A desired threshold voltage can be achieved by controlling the thickness and composition of the first metal pattern.

[0060] The first metal pattern may include a metal nitride film. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). The first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal films.

[0061] The second metal pattern may include a metal having lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0062] Referring again to FIG. 5d, the second gate electrode (GE2) may be provided on the first upper surface (TS1) of the first channel pattern (CH1) and on at least one first sidewall (SW1) of the first channel pattern (CH1). The fourth gate electrode (GE4) may be provided on the second upper surface (TS2) of the second channel pattern (CH2) and on at least one second sidewall (SW2) of the second channel pattern (CH2). In other words, the transistor according to the present embodiment may be a three-dimensional field-effect transistor (e.g., FinFET) in which the gate electrode surrounds the channel three-dimensionally.

[0063] Gate capping patterns (GP) may each be provided on the gate electrodes (GE). The gate capping pattern (GP) may extend along the gate electrode (GE) in a first direction (D1). The gate capping pattern (GP) may include a material having etch selectivity with respect to the first to fourth interlayer insulating films (110, 120, 130, 140) described later. Specifically, the gate capping pattern (GP) may include at least one of SiON, SiCN, SiCON, and SiN.

[0064] A first interlayer insulating film (110) may be provided on a substrate (100). The first interlayer insulating film (110) may cover gate spacers (GS) and first and second source / drain patterns (SD1, SD2).

[0065] The first interlayer insulating film (110) may include a lower insulating film (LIL) and an upper insulating film (UIL). The upper insulating film (UIL) may cover the gate capping patterns (GP) and the recessed portion (RSP) of the active contact (AC) to be described later. The upper insulating film (UIL) may include an insulating material that is the same as or different from the lower insulating film (LIL). For example, the lower insulating film (LIL) may include SiO, and the upper insulating film (UIL) may include SiO, SiOC, or SiC.

[0066] Active contacts (AC) can penetrate the first interlayer insulating film (110) and be connected to the first and second source / drain patterns (SD1, SD2). The upper surfaces of the active contacts (AC) can co-plane with the upper surface of the first interlayer insulating film (110). The active contacts (AC) may include first to eighth active contacts (AC1-AC8) on the first bit cell (CE1). As the size of the semiconductor memory device decreases, a short circuit defect may occur between the active contact (AC) and the adjacent gate electrode (GE). Whether a short circuit defect occurs may be determined by the distance between the active contact (AC) and the adjacent gate electrode (GE).

[0067] The active contact (AC) may be a self-aligned contact. In other words, the active contact (AC) may be self-aligned by the gate capping pattern (GP) and the gate spacer (GS). For example, the active contact (AC) may cover at least a portion of the sidewall of the gate capping pattern (GP).

[0068] The active contact (AC) may include a connection portion (CNP) and a recess portion (RSP). The upper surface of the connection portion (CNP) of the active contact (AC) may be higher than the upper surface of the recess portion (RSP). The upper surface of the connection portion (CNP) of the active contact (AC) may form a co-surface with the upper surface of the first interlayer insulating film (110). An upper insulating film (UIL) may be provided on the upper surface of the recess portion (RSP) of the active contact (AC).

[0069] A first via (VI1) may be disposed on the connection portion (CNP). In other words, the connection portion (CNP) may be extended in a vertical direction, i.e., a third direction (D3), to contact the first via (VI1). The active contact (AC) may be electrically connected to the first wiring layer (M1) through the connection portion (CNP) and the first via (VI1).

[0070] The connection portion (CNP) of the second active contact (AC2) among the active contacts (AC) can be in contact with the first gate contact (GC1) (see FIG. 5b). The second active contact (AC2) can be electrically connected to the first gate contact (GC1) through the connection portion (CNP). The connection portion (CNP) of the fifth active contact (AC5) among the active contacts (AC) can be in contact with the second gate contact (GC2) (see FIG. 5b). The fifth active contact (AC5) can be electrically connected to the second gate contact (GC2) through the connection portion (CNP).

[0071] A silicide pattern (SC) may be interposed between an active contact (AC) and source / drain patterns (SD1, SD2) connected thereto. The active contact (AC) may be electrically connected to the source / drain patterns (SD1, SD2) through the silicide pattern (SC). The silicide pattern (SC) may include a metal-silicide, and may include, for example, at least one of titanium-silicide, tantalum-silicide, tungsten-silicide, nickel-silicide, and cobalt-silicide.

[0072] A gate contact (GC) electrically connected thereto may be provided on the gate electrode (GE). The gate contact (GC) may be connected to the gate electrode (GE) by penetrating the first interlayer insulating film (110), gate spacers (GS), and gate capping pattern (GP).

[0073] The upper surface of the gate contact (GC) and the upper surface of the connection portion (CNP) of the active contact (AC) may co-plane with the upper surface of the first interlayer insulating film (110). The bottom surface of the gate contact (GC) may be higher than the bottom surface of the active contact (AC). The bottom surface of the gate contact (GC) may be higher than the upper surface of the recess portion (RSP) of the active contact (AC) and lower than the upper surface of the connection portion (CNP).

[0074] Each of the active contact (AC) and the gate contact (GC) may include a conductive pattern (FM) and a barrier pattern (BM) surrounding the conductive pattern (FM). For example, the conductive pattern (FM) may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern (BM) may cover the sidewalls and bottom surface of the conductive pattern (FM). The barrier pattern (BM) may include a metal nitride film or a metal film / metal nitride film. The metal film may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride film may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0075] The gate contacts (GC) may include first and second gate contacts (GC1, GC2) on the first bit cell (CE1). The first gate contact (GC1) may be connected to the third gate electrode (GE3), and the second gate contact (GC2) may be connected to the second gate electrode (GE2).

[0076] Referring again to FIGS. 4 and FIGS. 5b, on the first bit cell (CE1), the first gate contact (GC1) and the second active contact (AC2) in contact with it can form a first shared contact (SHC1). Through the first shared contact (SHC1), the third gate electrode (GE3) can be electrically connected to the first source / drain pattern (SD1) adjacent thereto. The second gate contact (GC2) and the fifth active contact (AC5) in contact with it can form a second shared contact (SHC2).

[0077] A second interlayer insulating film (120), a third interlayer insulating film (130), and a fourth interlayer insulating film (140) may be provided sequentially stacked on a first interlayer insulating film (110). As an example, the second to fourth interlayer insulating films (120, 130, 140) may include silicon oxide films.

[0078] A first wiring layer (M1) may be provided within the second interlayer insulating film (120). The first wiring layer (M1) may include a first bit line (BL1), a second bit line (BL2), a power line (VDD), a first lower landing pad (LLP1), a second lower landing pad (LLP2), and first vias (VI1), as previously described with reference to FIG. 2.

[0079] A second wiring layer (M2) may be provided within the third interlayer insulating film (130). The second wiring layer (M2) may include a ground line (VSS), an upper landing pad (ULP), and second vias (VI2), as previously described with reference to FIG. 2.

[0080] A third wiring layer (M3) may be provided within the fourth interlayer insulating film (140). The third wiring layer (M3) may include word lines (WL) and third vias (VI3), as previously described with reference to FIG. 2. The second wiring layer (M2) and the third wiring layer (M3) may be provided only on the memory cell region (MCR) and not on the test region (TSR).

[0081] In the first bit cell (CE1), the first and second active patterns (AP1, AP2) and the first to fourth gate electrodes (GE1-GE4) may constitute memory transistors. The memory transistors of the first bit cell (CE1) may include the first pull-up transistor (TU1), the first pull-down transistor (TD1), the second pull-up transistor (TU2), the second pull-down transistor (TD2), the first pass-gate transistor (TA1), and the second pass-gate transistor (TA2) described above with reference to FIG. 1.

[0082] The first gate electrode (GE1) may be the gate of the first pass-gate transistor (TA1). The first gate electrode (GE1) may be electrically connected to the word line (WL). The second gate electrode (GE2) may be the common gate of the first pull-down and first pull-up transistors (TD1, TU1). The third gate electrode (GE3) may be the common gate of the second pull-down and second pull-up transistors (TD2, TU2). The fourth gate electrode (GE4) may be the gate of the second pass-gate transistor (TA2). The fourth gate electrode (GE4) may be electrically connected to the word line (WL).

[0083] The first active contact (AC1) can be electrically connected to the second source / drain of the first pull-down transistor (TD1). The first active contact (AC1) can be electrically connected to the ground line (VSS).

[0084] The second active contact (AC2) can be electrically connected to the common source / drain (first source / drain) of the first pull-down transistor (TD1) and the first pass-gate transistor (TA1). The second active contact (AC2) can be extended in the first direction (D1) and electrically connected to the first source / drain of the first pull-up transistor (TU1).

[0085] The first gate contact (GC1) and the second active contact (AC2) can form a first shared contact (SHC1). Through the first shared contact (SHC1), the second active contact (AC2) and the third gate electrode (GE3) can be electrically connected to each other. In other words, through the first shared contact (SHC1), the common source / drain of the first pull-up and first pull-down transistors (TU1, TD1) can be electrically connected to the common gate of the second pull-up and second pull-down transistors (TU2, TD2). The first shared contact (SHC1) can correspond to the first node (N1) of FIG. 1.

[0086] The third active contact (AC3) can be electrically connected to the second source / drain of the first pass-gate transistor (TA1). The third active contact (AC3) can be electrically connected to the first bit line (BL1) through the first via (V1) (see FIG. 5a).

[0087] The fourth active contact (AC4) can be electrically connected to the second source / drain of the first pull-up transistor (TU1). The fourth active contact (AC4) can be electrically connected to the power line (VDD) through the first via (V1) (see FIG. 5b).

[0088] The fifth active contact (AC5) can be electrically connected to the first source / drain of the second pull-up transistor (TU2). The fifth active contact (AC5) can be extended in the first direction (D1) and electrically connected to the common source / drain (first source / drain) of the second pull-down transistor (TD2) and the second pass-gate transistor (TA2).

[0089] The second gate contact (GC2) and the fifth active contact (AC5) can form a second shared contact (SHC2). Through the second shared contact (SHC2), the fifth active contact (AC5) and the second gate electrode (GE2) can be electrically connected to each other. In other words, through the second shared contact (SHC2), the common source / drain of the second pull-up and second pull-down transistors (TU2, TD2) can be electrically connected to the common gate of the first pull-up and first pull-down transistors (TU1, TD1). The second shared contact (SHC2) can correspond to the second node (N2) of FIG. 1.

[0090] The sixth active contact (AC6) can be electrically connected to the second source / drain of the second pull-up transistor (TU2). The sixth active contact (AC6) can be electrically connected to the power line (VDD) through the first via (V1) (see FIG. 5c).

[0091] The seventh active contact (AC7) can be electrically connected to the second source / drain of the second pass-gate transistor (TA2). The seventh active contact (AC7) can be electrically connected to the second bit line (BL2) through the first via (V1).

[0092] The eighth active contact (AC8) can be electrically connected to the second source / drain of the second pull-down transistor (TD2). The eighth active contact (AC8) can be electrically connected to the ground line (VSS).

[0093] A first test cell (TC1) and a second test cell (TC2) may be provided on a test area (TSR). The second test cell (TC2) may be arranged adjacent to the first test cell (TC1) in a second direction (D2). The test cells (TC1, TC2) may be provided in an array form. First and second dummy patterns (DP1, DP2), gate electrodes (GE), contact patterns (CP), and gate contacts (GC) may be provided on the first and second test cells (TC1, TC2). Hereinafter, the first test cell (TC1) will be described in detail as a representative example with reference to FIGS. 4 and FIGS. 5f through 5j.

[0094] A device isolation layer (ST) can define first and second dummy patterns (DP1, DP2). The first and second dummy patterns (DP1, DP2) may be part of a substrate (100). A trench (TR) may be defined between adjacent first and second dummy patterns (DP1, DP2). The device isolation layer (ST) may fill the trench (TR). The upper portions of the first and second dummy patterns (DP1, DP2) may protrude vertically relative to the device isolation layer (ST). Each of the upper portions of the first and second dummy patterns (DP1, DP2) may have a fin shape protruding vertically over the device isolation layer (ST).

[0095] The upper surface of the device isolation film (ST) on the test area (TSR) may have a flat profile. That is, on the test area (TSR), a recess area (RSR) in the memory cell area (MCR) may not be formed on the upper surface of the device isolation film (ST).

[0096] According to the present embodiment, the first test cell (TC1) may include a pair of first dummy patterns (DP1) and two pairs of second dummy patterns (DP2). The spacing between adjacent pairs of first dummy patterns (DP1) may be greater than the spacing between adjacent pairs of second dummy patterns (DP2).

[0097] Unlike in the memory cell region (MCR), the first and second source / drain patterns (SD1, SD2) may not be provided on the upper portions of the first and second dummy patterns (DP1, DP2). Since the first and second source / drain patterns (SD1, SD2) are not formed on the test region (TSR), a short circuit between the first and second source / drain patterns (SD1, SD2) and the adjacent gate electrode (GE) can be prevented. This prevents errors from occurring during the detection of short circuit defects, which will be described later.

[0098] The gate electrodes (GE) may include first to fourth gate electrodes (GE1-GE4) on the first test cell (TC1). The first to fourth gate electrodes (GE1-GE4) may extend in a first direction (D1) across the first and second dummy patterns (DP1, DP2). The first gate electrode (GE1) may be symmetrical with respect to the fourth gate electrode (GE4), and the second gate electrode (GE2) may be symmetrical with respect to the third gate electrode (GE3).

[0099] The second gate electrode (GE2) and the fourth gate electrode (GE4) can be aligned side by side in the first direction (D1). An insulating pattern (SP) may be interposed between the second gate electrode (GE2) and the fourth gate electrode (GE4) to separate them from each other. The first gate electrode (GE1) and the third gate electrode (GE3) can be aligned side by side in the first direction (D1). An insulating pattern (SP) may be interposed between the first gate electrode (GE1) and the third gate electrode (GE3) to separate them from each other. That is, the first to fourth gate electrodes (GE1-GE4) on the first test cell (TC1) may be substantially identical in structure to the first to fourth gate electrodes (GE1-GE4) on the first bit cell (CE1).

[0100] Insulating patterns (SP) may be disposed on the sidewalls toward the first direction (D1) of the gate electrode (GE) on the test area (TSR) (see FIG. 5i). The gate electrode (GE) on the test area (TSR) may be interposed between the insulating patterns (SP).

[0101] A pair of gate spacers (GS) may be disposed on both sidewalls of the gate electrode (GE). The pair of gate spacers (GS) may extend along the gate electrode (GE) in a first direction (D1). The upper surfaces of the pair of gate spacers (GS) may be higher than the upper surface of the gate electrode (GE). The upper surfaces of the pair of gate spacers (GS) may be covered by a gate capping pattern (GP) to be described later. A gate insulating film (GI) may be interposed between the gate electrode (GE) and the first and second dummy patterns (DP1, DP2).

[0102] The first interlayer insulating film (110) may include a lower insulating film (LIL) and an upper insulating film (UIL). The upper insulating film (UIL) may cover the gate capping patterns (GP) and the recessed portion (RSP) of the contact pattern (CP) to be described later. The upper insulating film (UIL) may include an insulating material that is the same as or different from the lower insulating film (LIL). For example, the lower insulating film (LIL) may include SiO, and the upper insulating film (UIL) may include SiO, SiOC, or SiC.

[0103] The contact patterns (CP) can penetrate the first interlayer insulating film (110) and contact the upper surfaces of the first and second dummy patterns (DP1, DP2), respectively. The upper surfaces of the contact patterns (CP) can co-face with the upper surface of the first interlayer insulating film (110). The contact patterns (CP) may include first to eighth contact patterns (CP1-CP8) on the first test cell (TC1).

[0104] The contact pattern (CP) may be a self-aligned contact. In other words, the contact pattern (CP) may be self-aligned by the gate capping pattern (GP) and the gate spacer (GS). For example, the contact pattern (CP) may cover at least a portion of the sidewall of the gate capping pattern (GP).

[0105] The contact pattern (CP) may include a connection portion (CNP) and a recess portion (RSP). The upper surface of the connection portion (CNP) of the contact pattern (CP) may be higher than the upper surface of the recess portion (RSP). The upper surface of the connection portion (CNP) of the contact pattern (CP) may be co-planar with the upper surface of the first interlayer insulating film (110). An upper insulating film (UIL) may be provided on the upper surface of the recess portion (RSP) of the contact pattern (CP). That is, the contact pattern (CP) may have a structure substantially identical to that of the active contact (AC). In other words, the first to eighth contact patterns (CP1-CP8) of the first test cell (TC1) may have a structure substantially identical to that of the first to eighth active contacts (AC1-AC8) of the first bit cell (CE1).

[0106] A first via (VI1) may be disposed on the connection portion (CNP). In other words, the connection portion (CNP) may be extended in a vertical direction, i.e., a third direction (D3), to contact the first via (VI1). Any one of the contact patterns (CP) may be electrically connected to the first wiring layer (M1) through the connection portion (CNP) and the first via (VI1).

[0107] The connection portion (CNP) of the second contact pattern (CP2) among the contact patterns (CP) can be in contact with the first gate contact (GC1) (see FIG. 5g). The second contact pattern (CP2) can be electrically connected to the first gate contact (GC1) through the connection portion (CNP). The connection portion (CNP) of the fifth contact pattern (CP5) among the contact patterns (CP) can be in contact with the second gate contact (GC2) (see FIG. 5g). The fifth contact pattern (CP5) can be electrically connected to the second gate contact (GC2) through the connection portion (CNP).

[0108] A gate contact (GC) electrically connected thereto may be provided on the gate electrode (GE). The gate contact (GC) may be connected to the gate electrode (GE) by penetrating the first interlayer insulating film (110), gate spacers (GS), and gate capping pattern (GP).

[0109] The upper surface of the gate contact (GC) and the upper surface of the connection portion (CNP) of the contact pattern (CP) may form a co-surface with the upper surface of the first interlayer insulating film (110). The bottom surface of the gate contact (GC) may be higher than the bottom surface of the contact pattern (CP). The bottom surface of the gate contact (GC) may be higher than the upper surface of the recess portion (RSP) of the contact pattern (CP) and lower than the upper surface of the connection portion (CNP).

[0110] Referring again to FIGS. 4 and 5g, on the first test cell (TC1), the first gate contact (GC1) and the second contact pattern (CP2) in contact with it can form a third shared contact (SHC3). The second gate contact (GC2) and the fifth contact pattern (CP5) in contact with it can form a fourth shared contact (SHC4).

[0111] A first wiring layer (M1) may be provided within the second interlayer insulating film (120). The first wiring layer (M1) may include a first test wiring (M1_T1), a second test wiring (M1_T2), and first vias (VI1) on a test area (TSR).

[0112] Each of the first test wire (M1_T1) and the second test wire (M1_T2) may extend in a second direction (D2) parallel to each other. The first test wire (M1_T1) and the second test wire (M1_T2) may be spaced apart from the second wire layer (M2) and the third wire layer (M3). The first test wire (M1_T1) may be connected to the third shared contact (SHC3). The second test wire (M1_T2) may be connected to the fourth shared contact (SHC4). First vias (VI1) may be interposed between the first test wire (M1_T1) and the third shared contact (SHC3), and between the second test wire (M1_T2) and the fourth shared contact (SHC4), respectively.

[0113] The first via (VI1) connected to the third shared contact (SHC3) may be vertically overlapped with the connection portion (CNP) of the second contact pattern (CP2). The first via (VI1) connected to the fourth shared contact (SHC4) may be vertically overlapped with the connection portion (CNP) of the fifth contact pattern (CP5).

[0114] The lowest level on the upper surface of each of the first and second active patterns (AP1, AP2) may be the first level (LV1). The lowest level on the lower surface of the first interlayer insulating film (110) on the memory cell region (MCR) may be the third level (LV3) (see FIG. 5c and FIG. 5e). The lowest level on the upper surface of each of the dummy patterns (DP) may be the second level (LV2). The lowest level on the lower surface of the first interlayer insulating film (110) on the test region (TSR) may be the fourth level (LV4) (see FIG. 5h and FIG. 5j). The first level (LV1) may be lower than the second level (LV2). The third level (LV3) may be lower than the fourth level (LV4). This is because, as will be described later, the first and second source / drain patterns (SD1, SD2) are not formed on the test region (TSR).

[0115] Different voltages can be applied to the first test wiring (M1_T1) and the second test wiring (M1_T2). By gradually increasing the difference between the voltage applied to the first test wiring (M1_T1) and the voltage applied to the second test wiring (M1_T2), the breakdown of the insulating material between the second contact pattern (CP2) and the adjacent second gate electrode (GE2) (or the fifth contact pattern (CP5) and the third gate electrode (GE3)) can be induced, thereby allowing the breakdown voltage to be measured. The distance between the second contact pattern (CP2) and the adjacent second gate electrode (GE2) can be quantified based on the magnitude of the measured breakdown voltage. Accordingly, short-circuit defects between the active contact (AC) and the adjacent gate electrode (GE) in the memory cell region (MCR), which has a structure substantially identical to the test region (TSR), can also be measured in a non-destructive manner.

[0116] Conventionally, to identify short circuit defects between a gate electrode and an active contact, electron beam inspection and nano probing were used to locate the short circuit area, and the area was cut to perform destructive analysis. According to embodiments of the present invention, short circuit defects can be measured in a non-destructive manner by using a voltage ramping method in which different voltages are applied to each of the first test wiring (M1_T1) and the second test wiring (M1_T2) to gradually increase the difference. Accordingly, costs can be reduced by reducing the detection time for short circuit defects between the active contact and the gate electrode that occur as the size of the semiconductor device decreases, and by preventing wafer loss due to destructive analysis. As a result, defect detection in semiconductor memory devices can be made easier.

[0117] Referring to FIGS. 6a and 6b, the first gate contact (GC1) and the second active contact (AC2) of the first shared contact (SHC1) may each include a barrier pattern (BM) and a conduction pattern (FM). The barrier pattern (BM) of the first gate contact (GC1) may be interposed between the conduction pattern (FM) of the first gate contact (GC1) and the conduction pattern (FM) of the second active contact (AC2).

[0118] The first gate contact (GC1) may include a body portion (BDP) connected to the third gate electrode (GE3) and a protrusion (PRP) horizontally protruding from the body portion (BDP) in a second direction (D2). The protrusion (PRP) may be vertically overlapped with the second active contact (AC2). The body portion (BDP) may be offset without overlapping with the second active contact (AC2). The protrusion (PRP) may be in direct contact with the second active contact (AC2). In other words, the first gate contact (GC1) may be connected to the second active contact (AC2) through the protrusion (PRP).

[0119] The protrusion (PRP) may extend from the body portion (BDP) toward the center of the second active contact (AC2). The protrusion (PRP) may have a shape that penetrates the upper part of the second active contact (AC2). The protrusion (PRP) may have a shape that is embedded inside the second active contact (AC2).

[0120] The protrusion (PRP) may be located at a higher level than the bottom surface of the body portion (BDP). In other words, the lowest part of the protrusion (PRP) may be higher than the upper surface of the third gate electrode (GE3). In one embodiment, the upper surface of the protrusion (PRP) may be co-plane with the upper surface of the body portion (BDP). In another embodiment, the upper surface of the protrusion (PRP) may be lower than the upper surface of the body portion (BDP).

[0121] By having a shape in which the protrusion (PRP) of the first gate contact (GC1) is embedded inside the second active contact (AC2), the contact area between the first gate contact (GC1) and the second active contact (AC2) can be relatively increased. As a result, the contact resistance between the first gate contact (GC1) and the second active contact (AC2) can be relatively reduced.

[0122] The protrusion (PRP) of the first gate contact (GC1) can be provided to overlap with the second active contact (AC2). This allows for securing an alignment margin between the first gate contact (GC1) and the second active contact (AC2) through the protrusion (PRP) when the first gate contact (GC1) is formed. In other words, misalignment between the first gate contact (GC1) and the second active contact (AC2) can be prevented through the protrusion (PRP). Consequently, the reliability of the semiconductor memory device can be improved.

[0123] The second to fourth shared contacts (SHC2-SHC4) may also each have a structure substantially identical to the first shared contact (SHC1).

[0125] FIGS. 7a to 11h are cross-sectional views illustrating a method for manufacturing a semiconductor memory device according to embodiments of the present invention. FIGS. 7a, 8a, 9a, 10a, and 11a are cross-sectional views along line A-A' of FIG. 4. FIGS. 7b, 8b, 9b, 10b, and 11b are cross-sectional views along line B-B' of FIG. 4. FIGS. 7c, 8c, 9c, 10c, and 11c are cross-sectional views along line C-C' of FIG. 4. FIGS. 7d, 8d, 9d, 10d, and 11d are cross-sectional views along line D-D' of FIG. 4. FIGS. 7e, 8e, 9e, 10e, and 11e are cross-sectional views along line F-F' of FIG. 4. FIGS. 7f, 8f, 9f, 10f, and 11f are cross-sectional views along the line G-G' of FIG. 4. FIGS. 7g, 8g, 9g, 10g, and 11g are cross-sectional views along the line H-H' of FIG. 4. FIGS. 7h, 8h, 9h, 10h, and 11h are cross-sectional views along the line I-I' of FIG. 4.

[0126] Referring to FIGS. 4 and FIGS. 7a through 7h, a substrate (100) including a memory cell region (MCR) and a test region (TSR) may be provided. By patterning the substrate (100), trenches (TR) defining first and second active patterns (AP1, AP2) and first and second dummy patterns (DP1, DP2) may be formed. In other words, trenches (TR) may be formed between the first and second active patterns (AP1, AP2) and between the first and second dummy patterns (DP1, DP2).

[0127] A device isolation layer (ST) that fills trenches (TR) on a substrate (100) may be formed. The device isolation layer (ST) may include an insulating material such as a silicon oxide film. The device isolation layer (ST) may be recessed until the tops of the first and second active patterns (AP1, AP2) and the first and second dummy patterns (DP1, DP2) are exposed. Thus, the tops of the first and second active patterns (AP1, AP2) may protrude vertically over the device isolation layer (ST).

[0128] Referring to FIGS. 4 and FIGS. 8a through 8h, sacrificial patterns (PP) can be formed across first and second active patterns (AP1, AP2) and first and second dummy patterns (DP1, DP2). The sacrificial patterns (PP) can be formed in a line shape extending in a first direction (D1). Specifically, forming the sacrificial patterns (PP) may include forming a sacrificial film on the front surface of a substrate (100), forming hard mask patterns (MA) on the sacrificial film, and patterning the sacrificial film using the hard mask patterns (MA) as an etching mask. The sacrificial film may include polysilicon.

[0129] A pair of gate spacers (GS) may be formed on both sidewalls of each of the sacrifice patterns (PP). Forming the gate spacers (GS) may include conformally forming a gate spacer film on the front surface of the substrate (100) and anisotropically etching the gate spacer film. The gate spacer film may include at least one of SiCN, SiCON, and SiN. As another example, the gate spacer film may be a multi-layer film including at least two of SiCN, SiCON, and SiN.

[0130] A mask film (MK) covering the test region (TSR) may be formed. The mask film (MK) may cover only the test region (TSR) and not the memory cell region (MCR). That is, the memory cell region (MCR) may be exposed by the mask film (MK).

[0131] First source / drain patterns (SD1) may be formed on top of a first active pattern (AP1). A pair of first source / drain patterns (SD1) may be formed on both sides of each of the sacrifice patterns (PP). Specifically, first recesses (RS1) may be formed by etching the top of the first active pattern (AP1) using hard mask patterns (MA) and gate spacers (GS) as etching masks. While etching the top of the first active pattern (AP1), the device isolation layer (ST) between the first active patterns (AP1) may be recessed. Thus, a recessed region (RSR) may be formed on the upper surface of the device isolation layer (ST) on the memory cell region (MCR).

[0132] A first source / drain pattern (SD1) can be formed by performing an optional epitaxial growth process in which the inner wall of the first recess (RS1) of the first active pattern (AP1) serves as a seed layer. As the first source / drain patterns (SD1) are formed, a first channel pattern (CH1) can be defined between a pair of first source / drain patterns (SD1). For example, the first source / drain patterns (SD1) may include a semiconductor element (e.g., SiGe) having a lattice constant greater than the lattice constant of the semiconductor element of the substrate (100). Each of the first source / drain patterns (SD1) may be formed of multiple semiconductor layers.

[0133] In one embodiment, impurities may be injected in-situ during a selective epitaxial growth process to form first source / drain patterns (SD1). In another embodiment, impurities may be injected into the first source / drain patterns (SD1) after the first source / drain patterns (SD1) are formed. The first source / drain patterns (SD1) may be doped to have a first conductivity type (e.g., p-type).

[0134] Second source / drain patterns (SD2) may be formed on top of the second active pattern (AP2). A pair of second source / drain patterns (SD2) may be formed on both sides of each of the sacrifice patterns (PP). Specifically, second recesses (RS2) may be formed by etching the top of the second active pattern (AP2) using hard mask patterns (MA) and gate spacers (GS) as etching masks.

[0135] A second source / drain pattern (SD2) can be formed by performing an optional epitaxial growth process in which the inner wall of the second recess (RS2) of the second active pattern (AP2) serves as a seed layer. As the second source / drain patterns (SD2) are formed, a second channel pattern (CH2) can be defined between a pair of second source / drain patterns (SD2). For example, the second source / drain patterns (SD2) may contain the same semiconductor element (e.g., Si) as the substrate (100). The second source / drain patterns (SD2) may be doped to have a second conductivity type (e.g., n-type).

[0136] The first source / drain patterns (SD1) and the second source / drain patterns (SD2) can be formed sequentially through different processes. In other words, the first source / drain patterns (SD1) and the second source / drain patterns (SD2) may not be formed simultaneously.

[0137] The first and second source / drain patterns (SD1, SD2) may not be formed on the test region (TSR) by the mask film (MK). The upper surface of the device isolation film (ST) on the test region (TSR) may have a flat profile by the mask film (MK).

[0138] Referring to FIGS. 4 and FIGS. 9a through 9h, a lower insulating layer (LIL) can be formed covering first and second source / drain patterns (SD1, SD2), hard mask patterns (MA), and gate spacers (GS). For example, the lower insulating layer (LIL) may include a silicon oxide film.

[0139] The lower insulating film (LIL) can be flattened until the upper surfaces of the sacrificial patterns (PP) are exposed. Flattening of the first interlayer insulating film (110) can be performed using an etch back or chemical mechanical polishing (CMP) process. During the flattening process, all hard mask patterns (MA) can be removed. Consequently, the upper surface of the first interlayer insulating film (110) can be co-planar with the upper surfaces of the sacrificial patterns (PP) and the upper surfaces of the gate spacers (GS).

[0140] A portion of the exposed sacrificial pattern (PP) can be removed and an insulating material filled to form an insulating pattern (SP). By the insulating pattern (SP), the subsequently formed gate electrode (GE) can be divided into first to fourth gate electrodes (GE1-GE4).

[0141] Sacrificial patterns (PP) can be replaced with gate electrodes (GE). Specifically, the exposed sacrificial pattern (PP) can be selectively removed. A void space can be formed by removing the sacrificial pattern (PP). A gate insulating film (GI) and a gate electrode (GE) can be sequentially formed within the void space from which the sacrificial pattern (PP) has been removed.

[0142] A gate electrode (GE) and a gate spacer (GS) may be recessed, and a gate capping pattern (GP) may be formed on the recessed gate electrode (GE) and the recessed gate spacer (GS). The gate capping pattern (GP) may include a material having an etch selectivity with respect to the lower insulating film (LIL).

[0143] Active contacts (AC) and contact patterns (CP) electrically connected to first and second source / drain patterns (SD1, SD2) can be formed by penetrating the lower insulating layer (LIL). Specifically, first contact holes can be formed within the lower insulating layer (LIL) through a first photolithography process. The first contact holes can define the active contacts (AC) and contact patterns (CP). The first contact holes can expose the first and second source / drain patterns (SD1, SD2) and the first and second dummy patterns (DP1, DP2). The first contact holes can be formed self-aligned using the gate capping patterns (GP) as a mask.

[0144] Silicide patterns (SC) may be formed on first and second source / drain patterns (SD1, SD2) exposed through first contact holes. An active contact (AC) may be formed by sequentially forming a barrier pattern (BM) and a conductive pattern (FM) within the first contact hole. The upper surface of the active contact (AC) may co-plane with the upper surface of the gate capping pattern (GP) and the upper surface of the lower insulating film (LIL).

[0145] A contact pattern (CP) may be formed on first and second dummy patterns (DP1, DP2) exposed through first contact holes. Forming the contact pattern (CP) may include sequentially forming a barrier pattern (BM) and a conductive pattern (FM) within the first contact hole. The upper surface of the contact pattern (CP) may be co-plane with the upper surface of the gate capping pattern (GP) and the upper surface of the lower insulating film (LIL).

[0146] Referring to FIG. 4 and FIG. 10a through FIG. 10h, a mask pattern (MAP) may be formed on a portion of an active contact (AC) and a portion of a contact pattern (CP). The mask pattern (MAP) may define the area where the connection portion (CNP) of the active contact (AC) and the connection portion (CNP) of the contact pattern (CP) are to be formed.

[0147] A recess hole (RSH) can be formed by using a mask pattern (MAP) as an etching mask and etching the area excluding the mask pattern (MAP). During the etching process for forming the recess hole (RSH), the upper portion of the gate capping pattern (GP) can be recessed. During the etching process, the remaining area of ​​the active contact (AC) and the remaining area of ​​the contact pattern (CP) that are not covered by the mask pattern (MAP) can be recessed to form a recess portion (RSP), respectively. The upper surface of the recess portion (RSP) of the active contact (AC) and the upper surface of the recess portion (RSP) of the contact pattern (CP) can be lower than the upper surface of the gate electrode (GE). During the etching process, the upper portion of the lower insulating film (LIL) can also be recessed.

[0148] Referring to FIG. 4 and FIG. 11a through FIG. 11h, an upper insulating film (UIL) can be formed to fill a recess hole (RSH). The upper insulating film (UIL) may include an insulating material that is the same as or different from that of the lower insulating film (LIL). The upper insulating film (UIL) may cover the upper surface of the recess portion (RSP) of the active contact (AC) and the upper surface of the recess portion (RSP) of the contact pattern (CP). The upper insulating film (UIL) and the lower insulating film (LIL) may form a first interlayer insulating film (110).

[0149] A sacrificial insulating layer (SAL) may be formed on the first interlayer insulating layer (110). A gate contact (GC) electrically connected to a gate electrode (GE) may be formed by penetrating the sacrificial insulating layer (SAL) and the gate capping pattern (GP).

[0150] Specifically, second contact holes penetrating the sacrificial insulating layer (SAL) can be formed through a second photolithography process. The second contact holes can define a gate contact (GC). The second contact holes can expose the upper surface of the gate electrode (GE). The gate contact (GC) can be formed by sequentially forming a barrier pattern (BM) and a conductive pattern (FM) within the second contact holes. The upper surface of the gate contact (GC) can co-plane with the upper surface of the sacrificial insulating layer (SAL).

[0151] Among the gate contacts (GC), the first gate contact (GC1) can be formed to partially overlap with the second active contact (AC2). Thus, the first gate contact (GC1) can be connected to the upper surface of the third gate electrode (GE3) while penetrating the upper part of the second active contact (AC2). The first gate contact (GC1) can form the first shared contact (SHC1) by making direct contact with the second active contact (AC2). The second to fourth shared contacts (SHC2-SHC4) can also be formed by substantially the same process.

[0152] According to the method for manufacturing a semiconductor memory device of the present invention, after forming an active contact (AC), a gate contact (GC) can be formed such that a part thereof overlaps the active contact (AC). This allows a protrusion (PRP, see FIG. 6) embedded within the active contact (AC) to be formed on the gate contact (GC). As a result, the electrical resistance of the shared contact (SHC), i.e., the first node (N1), is reduced, and the operating speed and electrical characteristics of the SRAM cell can be improved.

[0153] Referring again to FIGS. 4 and FIGS. 5a through 5j, a planarization process can be performed on the gate contacts (GC) and the sacrificial insulating film (SAL) until the upper surfaces of the active contacts (AC) and contact patterns (CP) are exposed. In this way, the sacrificial insulating film (SAL) can be completely removed. The upper surface of the gate contact (GC) can be co-plane with the upper surface of the active contact (AC) and the upper surface of the contact pattern (CP).

[0154] Second to fourth interlayer insulating films (120, 130, 140) may be sequentially formed on the first interlayer insulating film (110). Through a BEOL (Back end of line) process, a first wiring layer (M1) may be formed within the second interlayer insulating film (120), a second wiring layer (M2) may be formed within the third interlayer insulating film (130), and a third wiring layer (M3) may be formed within the fourth interlayer insulating film (140). The second wiring layer (M2) and the third wiring layer (M3) may be formed only on the memory cell region (MCR). The first wiring layer (M1) may include first and second test wirings (M1_T1, M1_T2) on the test region (TSR).

[0156] FIGS. 12a to 12c are cross-sectional views along the G-G', I-I', and J-J' lines of FIG. 4, respectively, for illustrating semiconductor memory devices according to embodiments of the present invention. In this embodiment, details that overlap with those described with reference to FIGS. 4 and FIGS. 5a to 5j are omitted, and the differences are described in detail.

[0157] Referring to FIG. 4 and FIG. 12a through 12c, the first via (VI1) between the first test wire (M1_T1) and the third shared contact (SHC3) can be horizontally offset from the second contact pattern (CP2). The first via (VI1) between the second test wire (M1_T2) and the fourth shared contact (SHC4) can be horizontally offset from the fifth contact pattern (CP5).

[0158] The first via (VI1) between the first test wire (M1_T1) and the third shared contact (SHC3) may be vertically overlapped with the third gate electrode (GE). The first via (VI1) between the second test wire (M1_T2) and the fourth shared contact (SHC4) may be vertically overlapped with the second gate electrode (GE2). That is, the position of the first via (VI1) on the third shared contact (SHC3) or the fourth shared contact (SHC4) can be freely changed.

[0160] FIGS. 13a to 13c are cross-sectional views taken along lines A-A', B-B', and D-D' of FIG. 4, respectively, to illustrate semiconductor memory devices according to embodiments of the present invention. In this embodiment, details that overlap with those described with reference to FIGS. 4 and FIGS. 5a to 5j are omitted, and the differences are described in detail.

[0161] Referring to FIG. 4 and FIG. 13a through 13c, first and second active patterns (AP1, AP2) may be provided on a substrate (100). The first active pattern (AP1) may include first channel patterns (CH1) that are vertically stacked. The stacked first channel patterns (CH1) may be spaced apart from each other in a third direction (D3). The stacked first channel patterns (CH1) may be vertically overlapped with each other. The second active pattern (AP2) may include second channel patterns (CH2) that are vertically stacked. The stacked second channel patterns (CH2) may be spaced apart from each other in a third direction (D3). The stacked second channel patterns (CH2) may be vertically overlapped with each other. The first and second channel patterns (CH1, CH2) may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0162] The first active pattern (AP1) may further include first source / drain patterns (SD1). Stacked first channel patterns (CH1) may be interposed between a pair of adjacent first source / drain patterns (SD1). The stacked first channel patterns (CH1) may connect a pair of adjacent first source / drain patterns (SD1).

[0163] The second active pattern (AP2) may further include second source / drain patterns (SD2). Stacked second channel patterns (CH2) may be interposed between a pair of adjacent second source / drain patterns (SD2). The stacked second channel patterns (CH2) may connect a pair of adjacent second source / drain patterns (SD2).

[0164] Gate electrodes (GE) extending in a first direction (D1) across the first and second channel patterns (CH1, CH2) may be provided. Each gate electrode (GE) may be perpendicularly overlapped with the first and second channel patterns (CH1, CH2).

[0165] A gate electrode (GE) may surround each of the first channel patterns (CH1). Specifically, the gate electrode (GE) may be provided on the first top surface (TS1), first sidewalls (SW1), and first bottom surface (BS1) of each of the first channel patterns (CH1) (see FIG. 13c). A gate electrode (GE) may surround each of the second channel patterns (CH2). Specifically, the gate electrode (GE) may be provided on the second top surface (TS2), second sidewalls (SW2), and second bottom surface (BS2) of each of the second channel patterns (CH2) (see FIG. 13c). The transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., a Multi-Bridge Channel Field Effect Transistor (MBCFET) or a Gate All Around Field Effect Transistor (GAAFET)) in which the gate electrode (GE) surrounds the channels (CH1, CH2) in three dimensions.

[0166] A gate insulating film (GI) may be provided between each of the first and second channel patterns (CH1, CH2) and the gate electrode (GE). The gate insulating film (GI) may surround each of the first and second channel patterns (CH1, CH2).

[0167] On the second active pattern (AP2), an inner spacer (IP) may be interposed between the gate insulating film (GI) and the second source / drain pattern (SD2). The gate electrode (GE) may be separated from the second source / drain pattern (SD2) by the gate insulating film (GI) and the inner spacer (IP). On the other hand, on the first active pattern (AP1), the inner spacer (IP) may be omitted.

[0169] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

Claim 1 A semiconductor memory device comprising: a substrate including a memory cell region and a test region; an active pattern provided on the memory cell region; a source / drain pattern provided on the active pattern; a dummy pattern provided on the test region; a first gate electrode extending in a first direction on the dummy pattern; a first shared contact in contact with the dummy pattern and the first gate electrode; and a first wiring layer on the first shared contact, wherein the first wiring layer includes a first test wiring electrically connected to the first shared contact, the first shared contact includes a first contact pattern in contact with the dummy pattern and a first gate contact electrically connected to the first gate electrode, and the first gate contact includes a body portion connected to the first gate electrode and a protrusion extending from the body portion into the first contact pattern, wherein the lowest level of the upper surface of the active pattern is lower than the lowest level of the upper surface of the dummy pattern. Claim 2 A semiconductor memory device according to claim 1, wherein the protrusion is vertically superimposed with the first contact pattern and the body is horizontally offset from the first contact pattern. Claim 3 A semiconductor memory device according to claim 1, wherein the upper surface of the body portion forms a co-plane with the upper surface of the first contact pattern. Claim 4 A semiconductor memory device according to claim 1, wherein the first contact pattern comprises a connecting portion and a recess portion excluding the connecting portion, the connecting portion contacts the protrusion portion, and the upper surface of the recess portion is lower than the upper surface of the connecting portion. Claim 5 A semiconductor memory device according to claim 1, further comprising: a second gate electrode spaced apart from the first gate electrode in a second direction intersecting the first direction; and a second shared contact spaced apart from the first shared contact in the first direction, wherein the second shared contact comprises a second contact pattern extending in the first direction in contact with the dummy pattern and a second gate contact electrically connected to the second gate electrode. Claim 6 In claim 5, the first wiring layer further comprises a second test wiring electrically connected to the second shared contact, wherein the voltage applied to the second test wiring is different from the voltage applied to the first test wiring. Claim 7 In claim 1, the semiconductor memory device further comprises a second wiring layer on the first wiring layer, wherein the second wiring layer is spaced apart from the first test wiring. Claim 8 A semiconductor memory device according to claim 1, further comprising a first via between the first test wiring and the first shared contact, wherein the first via is vertically superimposed with the first contact pattern. Claim 9 A semiconductor memory device according to claim 1, further comprising a first via between the first test wiring and the first shared contact, wherein the first via is horizontally offset from the first contact pattern. Claim 10 In claim 1, the first gate electrode is a semiconductor memory device interposed between insulating patterns.

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