Display device

Abstract

The present invention relates to a display device capable of resolving the shortage of placement space for fan-out wiring due to a reduction in the area of ​​a non-display area. A display device according to one embodiment comprises a display area including an optical hole, a plurality of first data wirings disposed on one side of the optical hole in the display area and extending in a second direction intersecting a first direction, a plurality of second data wirings disposed on the other side of the optical hole in the display area and extending in the second direction, and a plurality of bypass wirings that bypass the optical hole in the display area and respectively connect the first data wirings and the second data wirings. Each of the plurality of bypass wirings includes a first sub-bypass wiring that extends in the first direction and is connected to one of the first data wirings among the plurality of first data wirings, a second sub-bypass wiring that extends in the second direction and is connected to the first sub-bypass wiring, and a third sub-bypass wiring that extends in the first direction and connects the second sub-bypass wiring to one of the second data wirings among the plurality of second data wirings.

Description

Technology Field

[0001] The present invention relates to a display device. Background Technology

[0002] As the information society develops, the demand for display devices to show images is increasing in various forms. For example, display devices are being applied to a wide range of electronic devices, such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may further include pixels emitting a predetermined light, scan lines for driving the pixels, data lines, power lines, a scan driving unit for outputting scan signals to the scan lines, and a display driving unit for outputting data voltages to the data lines.

[0004] A display device includes a display area that displays an image, including pixels, and a non-display area located around the display area. Recently, the area of ​​the non-display area in display devices has been minimized; however, this may result in insufficient space for fan-out lines connecting the display driver and data wiring within the non-display area. The problem to be solved

[0005] The problem that the present invention aims to solve is to provide a display device capable of resolving the shortage of placement space for fan-out wiring caused by the reduction of the non-display area.

[0006] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0007] A display device according to an embodiment for solving the above problem comprises a display area including subpixels that display a hole and an image, a plurality of first data lines disposed on one side of the hole in the display area and extending in a second direction intersecting a first direction, a plurality of second data lines disposed on the other side of the hole in the display area and extending in the second direction, and a plurality of bypass lines that bypass the hole in the display area and respectively connect the first data lines and the second data lines. Each of the plurality of bypass lines includes a first sub-bypass line that extends in the first direction and is connected to one of the first data lines among the plurality of first data lines, a second sub-bypass line that extends in the second direction and is connected to the first sub-bypass line, and a third sub-bypass line that extends in the first direction and connects the second sub-bypass line and one of the second data lines among the plurality of second data lines.

[0008] The device may further comprise a plurality of first horizontal power lines extending in the first direction in the display area and to which a first power voltage is applied, a plurality of second horizontal power lines extending in the first direction in the display area and to which a second power voltage higher than the first power voltage is applied, and a first vertical power line extending in the second direction in the display area and disposed apart from one end of the second sub-bypass line.

[0009] The first vertical power line can be connected to any one of the plurality of first horizontal power lines.

[0010] Among the plurality of bypass lines, the first separation portion in which the second sub-bypass line of the first bypass line and the first vertical power line are separated may overlap with any one of the plurality of second horizontal power lines.

[0011] The second sub-bypass wiring of the first bypass wiring and the first vertical power wiring may include a first wiring section having a first width and a second wiring section having a second width greater than the first width. The first separation section may be defined as a gap between the first wiring section of the second sub-bypass wiring of the first bypass wiring and the first wiring section of the first vertical power wiring.

[0012] Among the plurality of bypass lines, the second separation portion in which the second sub-bypass line of the second bypass line and the first vertical power line are separated may not overlap with the plurality of second horizontal power lines.

[0013] The second sub-bypass wiring of the second bypass wiring and the first vertical power wiring may include a first wiring section having a first width and a second wiring section having a second width greater than the first width.

[0014] The second gap may be defined as a gap between the first wiring portion of the second sub-bypass wiring of the second bypass wiring and the second wiring portion of the first vertical power wiring, or a gap between the second wiring portion of the second sub-bypass wiring and the first wiring portion of the first vertical power wiring.

[0015] The second separation portion can be defined as the gap between the second wiring portion of the second sub-bypass wiring of the second bypass wiring and the second wiring portion of the first vertical power wiring.

[0016] A vertical dummy pattern may be further provided that extends in the second direction from the above-mentioned display area and is positioned apart from the other end of the second sub-bypass wiring.

[0017] The device further comprises a second power line to which the second power voltage is applied, which is positioned in a non-display area surrounding the display area, and the vertical dummy pattern can be connected to the second power line in the non-display area.

[0018] Among the plurality of bypass lines, the second sub-bypass lines and third sub-bypass lines of some of the bypass lines may be placed in the display area, and the second sub-bypass lines and third sub-bypass lines of the remaining bypass lines may be placed in the non-display area.

[0019] The device further comprises a first power line to which the first power voltage is applied, which is disposed in a non-display area disposed around the display area, and the second sub-bypass lines and third sub-bypass lines of the remaining bypass lines may be disposed between the first power line and the second power line.

[0020] Among the second sub-bypass lines and third sub-bypass lines of the remaining bypass lines mentioned above, adjacent second sub-bypass lines and third sub-bypass lines may be placed on different layers.

[0021] An optical device that is positioned in the hole and detects light incident through the hole may be further provided.

[0022] A display device further comprising a plurality of first horizontal dummy patterns extending in the first direction from the above display area and positioned apart from one end of the first sub-bypass wiring.

[0023] The first horizontal dummy patterns can each be connected to the first vertical power wiring through the first power holes.

[0024] The first power holes mentioned above can be arranged in the second direction.

[0025] The first power holes above may overlap with the center of the hole in the second direction.

[0026] A plurality of second horizontal dummy patterns may be further provided, extending in the first direction from the above-mentioned display area and positioned apart from one end of the third sub-bypass wiring.

[0027] A second vertical power line extending in the second direction in the above-mentioned display area is further provided, and the second horizontal dummy patterns can be connected to the second vertical power line through the second power holes.

[0028] The above second power holes can be arranged in the above second direction.

[0029] The above second power holes can overlap with the center of the hole in the above second direction.

[0030] The first vertical power wiring above receives a first power voltage, and the second vertical power wiring above can receive a second power voltage higher than the first power voltage.

[0031] The apparatus may further comprise a plurality of active patterns, at least one insulating film disposed on the plurality of active patterns, and an exposure hole that penetrates the at least one insulating film to expose any one of the plurality of active patterns.

[0032] A dummy pattern disposed on the active pattern in the above exposure hole may be further provided.

[0033] The above dummy pattern may be positioned apart from the sidewall of the at least one insulating film in the above exposed hole.

[0034] The above active pattern can be placed between the hole and the subpixels.

[0035] The above active pattern can be placed in a non-display area surrounding the above display area.

[0036] Among the plurality of bypass lines, the second sub-bypass lines and third sub-bypass lines of some of the bypass lines are placed in the display area, and the second sub-bypass lines and third sub-bypass lines of the remaining bypass lines are placed in the non-display area, and the active pattern may be placed between adjacent second sub-bypass lines and third sub-bypass lines among the second sub-bypass lines and third sub-bypass lines of the remaining bypass lines.

[0037] A display device according to one embodiment for solving the above problem comprises a plurality of first data lines extending in a second direction intersecting a first direction, a plurality of second data lines extending in the second direction, a plurality of bypass lines connecting the first data lines and the second data lines respectively, a plurality of first horizontal power lines extending in the first direction to which a first power voltage is applied, and a plurality of vertical power lines extending in the second direction to which a second power voltage is applied. Each of the plurality of bypass lines includes a first sub-bypass line extending in the first direction and connected to one of the first data lines among the plurality of first data lines, a second sub-bypass line extending in the second direction and connected to the first sub-bypass line, and a third sub-bypass line extending in the first direction and connecting the second sub-bypass line and one of the second data lines among the plurality of second data lines. The first separation portion in which the second sub-bypass wiring of the first bypass wiring among the plurality of bypass wirings and any one of the vertical power wirings are separated overlaps with any one of the first horizontal power wirings among the plurality of first horizontal power wirings.

[0038] Among the plurality of bypass lines, the second bypass line of the second bypass line and another vertical power line among the vertical power lines are spaced apart, and the second spaced portion may not overlap with the plurality of first horizontal power lines.

[0039] The apparatus further comprises a plurality of second horizontal power lines that extend in the first direction and to which a second power voltage lower than the first power voltage is applied, and the vertical power line may be connected to any one of the plurality of second horizontal power lines.

[0040] A display device according to one embodiment for solving the above problem comprises a plurality of first data lines extending in a second direction intersecting a first direction, a plurality of second data lines extending in the second direction, a plurality of bypass lines connecting the first data lines and the second data lines respectively, a plurality of horizontal power lines extending in the first direction to which a first power voltage is applied, and a plurality of vertical power lines extending in the second direction to which a second power voltage is applied. Each of the plurality of bypass lines includes a first sub-bypass line extending in the first direction and connected to one of the first data lines among the plurality of first data lines, a second sub-bypass line extending in the second direction and connected to the first sub-bypass line, and a third sub-bypass line extending in the first direction and connecting the second sub-bypass line and one of the second data lines among the plurality of second data lines. The first separation portion in which the second sub-bypass wiring of the first bypass wiring among the plurality of bypass wirings and one of the vertical power wirings among the vertical power wirings are separated does not overlap with the plurality of horizontal power wirings.

[0041] The second separation portion, in which the second sub-bypass wiring of the second bypass wiring among the plurality of bypass wirings and another vertical power wiring among the vertical power wirings are spaced apart, can overlap with any one of the horizontal power wirings among the plurality of horizontal power wirings.

[0042] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0043] According to the display device of the embodiments, a plurality of data lines disposed on one side of a hole are connected to a plurality of data lines disposed on the other side of the hole through a plurality of bypass lines. As a result, a bypass line section disposed adjacent to the hole and bypassing the hole can be omitted, thereby minimizing the distance between the hole and the area where subpixels are disposed. Accordingly, the distance between the hole and the subpixels can be improved so that it is not visible to the user as a non-display area.

[0044] According to the display device of the embodiments, by positioning the spacing portion between the second sub-bypass wiring of the bypass wiring and the vertical power wiring so as to overlap with the horizontal power wiring or not to overlap with the horizontal power wiring, it is possible to prevent the pattern caused by the step difference of the pixel electrode from being visible to the user.

[0045] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification. Brief explanation of the drawing

[0046] FIG. 1 is a perspective view showing a display device according to one embodiment. FIG. 2 is a layout diagram showing a display device according to one embodiment. FIG. 3 is a side view showing a display device according to one embodiment. Figure 4 is a layout diagram showing area A of Figure 2 in detail. FIG. 5 is a circuit diagram showing a subpixel according to one embodiment. FIG. 6 is a circuit diagram showing a subpixel according to another embodiment. Figure 7 is a layout diagram showing a part of the first display area of ​​Figure 2. FIG. 8 is a layout diagram showing in detail a part of the first sub-display area of ​​FIG. 7. FIG. 9 is a layout diagram showing in detail a part of the second sub-display area of ​​FIG. 7. FIG. 10 is an enlarged layout diagram showing in detail an example of the first separation portion of FIG. 9. FIG. 11 is an enlarged layout diagram showing in detail an example of the second separation portion of FIG. 9. FIG. 12 is an enlarged layout diagram showing in detail another example of the second separation portion of FIG. 9. FIG. 13 is a cross-sectional view showing an example of a display panel cut along A-A' of FIG. 10. FIG. 14 is a cross-sectional view showing a first comparative example of a display panel. FIG. 15 is a cross-sectional view showing a second comparative example of a display panel. FIG. 16 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 11. FIG. 17 is a layout diagram showing a part of the second display area of ​​FIG. 2. FIG. 18 is a layout diagram showing a part of the third display area of ​​FIG. 2. FIG. 19 is a layout diagram showing in detail a part of the fourth display area of ​​FIG. 2. FIG. 20 is a layout diagram showing in detail a part of the fifth display area of ​​FIG. 2. FIG. 21 is a layout diagram showing in detail a part of the sixth display area of ​​FIG. 2. FIG. 22 is a layout diagram showing in detail an example of the seventh display area of ​​FIG. 2. FIG. 23 is a layout diagram showing in detail a part of the first area and the third area of ​​the seventh display area of ​​FIG. 22. FIG. 24 is a layout diagram showing in detail the second area, the fourth area, and a part of the non-display area of ​​the seventh display area of ​​FIG. 22. Fig. 25 is a layout diagram showing the hole of Fig. 22 in detail. FIG. 26 is a layout diagram showing in detail an example of area B of FIG. 9. Figure 27 is a layout diagram showing in detail an example of area B of Figure 9. FIG. 28 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 26 and FIG. 27. FIG. 29 is a cross-sectional view showing an example of a display panel cut along D-D' of FIG. 27. FIG. 30 is a cross-sectional view showing an example of a display panel cut along E-E' of FIG. 27. FIG. 31 is a cross-sectional view showing an example of a display panel cut along F-F' of FIG. 27. FIG. 32 is a cross-sectional view showing an example of a display panel cut along G-G' of FIG. 24. FIG. 33 is a cross-sectional view showing an example of a display panel cut along H-H' of FIG. 25. FIG. 34 is a layout diagram showing a display device according to another embodiment. FIG. 35 is a layout diagram showing a display device according to another embodiment. FIG. 36 is a layout diagram showing a display device according to another embodiment. FIG. 37 is a layout diagram showing a display device according to another embodiment. FIG. 38 is a layout diagram showing a display device according to another embodiment. Specific details for implementing the invention

[0047] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0048] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and the invention is not limited to the depicted details.

[0049] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0050] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0051] Specific embodiments will be described below with reference to the attached drawings.

[0052] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0053] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0054] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Although the following description focuses on the display device (10) being an organic light-emitting display device, the present invention is not limited thereto.

[0055] The display device (10) includes a display panel (100), a display driving circuit (200), and a circuit board (300).

[0056] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0057] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA). The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) which is a peripheral area of ​​the display area (DA). The display area (DA) may include subpixels (SPX in FIG. 5) that display an image. The display area (DA) may include a hole (OH) that can transmit light. The hole (OH) may be a physical hole that penetrates the display panel (100). Alternatively, the hole (OH) may be an optical hole that does not penetrate the display panel (100) but can transmit light.

[0058] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). Although FIG. 1 illustrates a sub-region (SBA) unfolded, the sub-region (SBA) may be bent, in which case it may be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it may overlap with the main region (MA) in the thickness direction (DR3) of the substrate (SUB). A display driving circuit (200) may be placed in the sub-region (SBA).

[0059] The display driving circuit (200) can generate signals and voltages to drive the display panel (100). The display driving circuit (200) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (200) may be attached to the circuit board (300) using a COF (chip on film) method.

[0060] A circuit board (300) can be attached to one end of a sub-region (SBA) of a display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100) and the display driving circuit (200). The display panel (100) and the display driving circuit (200) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0061] FIG. 2 is a layout diagram showing a display device according to one embodiment. FIG. 3 is a side view showing a display device according to one embodiment.

[0062] FIG. 2 illustrates a sub-region (SBA) that is unfolded without being bent. FIG. 3 illustrates a sub-region (SBA) that is bent toward the lower surface of the display device (10).

[0063] Referring to FIGS. 2 and FIGS. 3, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0064] The main area (MA) may include a display area (DA) for displaying an image and a non-display area (NDA) which is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0065] The display area (DA) may include the first to seventh display areas (DA1, DA2, DA3, DA4, DA5, DA7).

[0066] The first display area (DA1) and the fourth display area (DA4) are each areas where first data lines are placed, which are connected to data fan-out lines through data connection lines. The second display area (DA2) may be an area where second data lines are placed, which are directly connected to data fan-out lines. The third display area (DA3), the fifth display area (DA5), and the sixth display area (DA6) may be areas where power holes (PH) are placed, to which first horizontal power lines (HPL1) extending in the first direction (DR1) and first vertical power lines (HPL1) are connected. The seventh display area (DA7) may be an area where a hole (OH) is placed.

[0067] The first display area (DA1) and the third display area (DA3) may be positioned to the left of the display area (DA), and the fourth display area (DA4) and the fifth display area (DA5) may be positioned to the right of the display area (DA). The first display area (DA1) may be positioned below the third display area (DA3), and the fourth display area (DA4) may be positioned below the fifth display area (DA5). The second display area (DA2) may be positioned between the first display area (DA1) and the fourth display area (DA4). The sixth display area (DA6) and the seventh display area (DA7) may be positioned between the third display area (DA3) and the fifth display area (DA5). The sixth display area (DA6) may be positioned between the second display area (DA2) and the seventh display area (DA7).

[0068] The length of the first direction (DR1) of the first display area (DA1) may be substantially the same as the length of the first direction (DR1) of the third display area (DA3). Additionally, the length of the second direction (DR2) of the first display area (DA1) may be smaller than the length of the second direction (DR2) of the third display area (DA3).

[0069] The length of the first direction (DR1) of the first display area (DA1) may be longer than the length of the first direction (DR1) of the second display area (DA2). The length of the second direction (DR2) of the first display area (DA1) may be substantially the same as the length of the second direction (DR2) of the second display area (DA2).

[0070] The length of the first direction (DR1) of the third display area (DA3) may be longer than the length of the first direction (DR1) of the sixth display area (DA6). The length of the second direction (DR2) of the third display area (DA3) may be longer than the length of the second direction (DR2) of the sixth display area (DA6).

[0071] The length of the first direction (DR1) of the fourth display area (DA4) may be substantially the same as the length of the first direction (DR1) of the fifth display area (DA5). Additionally, the length of the second direction (DR2) of the fourth display area (DA4) may be smaller than the length of the second direction (DR2) of the fifth display area (DA5).

[0072] The length of the first direction (DR1) of the fourth display area (DA4) may be longer than the length of the first direction (DR1) of the second display area (DA2). The length of the second direction (DR2) of the fourth display area (DA4) may be substantially the same as the length of the second direction (DR2) of the second display area (DA2).

[0073] The length of the first direction (DR1) of the fifth display area (DA5) may be longer than the length of the first direction (DR1) of the sixth display area (DA6). The length of the second direction (DR2) of the fifth display area (DA5) may be longer than the length of the second direction (DR2) of the sixth display area (DA6).

[0074] The length of the first direction (DR1) of the first display area (DA1) may be substantially the same as the length of the first direction (DR1) of the fourth display area (DA4). Additionally, the length of the second direction (DR2) of the first display area (DA1) may be substantially the same as the second direction (DR2) of the fourth display area (DA4).

[0075] The length of the first direction (DR1) of the second display area (DA2) may be substantially the same as the length of the first direction (DR1) of the sixth display area (DA6). Additionally, the length of the second direction (DR2) of the second display area (DA2) may be smaller than the length of the second direction (DR2) of the sixth display area (DA6).

[0076] The length of the first direction (DR1) of the third display area (DA3) may be substantially the same as the length of the first direction (DR1) of the fifth display area (DA5). Additionally, the length of the second direction (DR2) of the third display area (DA3) may be substantially the same as the length of the second direction (DR2) of the fifth display area (DA5).

[0077] The length of the first direction (DR1) of the seventh display area (DA7) may be longer than the length of the first direction (DR1) of the sixth display area (DA6). The length of the second direction (DR2) of the seventh display area (DA7) may be shorter than the length of the second direction (DR2) of the sixth display area (DA6).

[0078] For example, if the display area (DA) contains 1080×2340 pixels, 484 pixels may be arranged in the first direction (DR1) in each of the first display area (DA1) and the third display area (DA3), 112 pixels may be arranged in the first direction (DR1) in each of the second display area (DA2) and the sixth display area (DA6), and 484 pixels may be arranged in each of the fourth display area (DA4) and the fifth display area (DA5).

[0079] In the display area (DA), first horizontal power lines (HPL1) and vertical power lines (VPL) connected to the first power line (PL1) can be arranged in a mesh form.

[0080] The first power wiring (PL1) is connected to the pads (PD) of the sub-region (SBA) and can receive the first power voltage. The first power wiring (PL1) can be positioned on the left, upper, and right sides of the display area (DA).

[0081] The first horizontal power lines (HPL1) can be extended in a first direction (DR1) and arranged in a second direction (DR2). The first horizontal power lines (HPL1) can be connected to the first power line (PL1) on the left and right sides of the display area (DA).

[0082] The first vertical power lines (VPL1) can be extended in the second direction (DR2) and arranged in the first direction (DR1). The first vertical power lines (VPL1) can be connected to the first power lines (PL1) at the upper and lower sides of the display area (DA).

[0083] A power hole (PH) may be disposed at each of some of the intersections of the first horizontal power lines (HPL1) and the vertical power lines (VPL). The power hole (PH) may be a hole for connecting the first horizontal power line (HPL1) and the vertical power line (VPL). The power holes (PH) may be arranged in a "∨" shape in the third display area (DA3) and the fifth display area (DA5), but the embodiments of this specification are not limited thereto. For example, the power holes (PH) may be arranged repeatedly in a "∧" shape, or arranged in a pattern other than "∨" and "∧".

[0084] Power holes (PH) may be arranged in a first diagonal direction (DD1) between a first direction (DR1) and a second direction (DR2) in the second display area (DA2) and the sixth display area (DA6). The first diagonal direction (DD1) may be a direction tilted at +45 degrees from the first direction (DR1) and a direction tilted at -45 degrees from the second direction (DR2). Alternatively, power holes (PH) may be arranged in a second diagonal direction (DD2) orthogonal to the first diagonal direction (DD1) in the second display area (DA2) and the sixth display area (DA6).

[0085] In each of the first display area (DA1) and the third display area (DA3), first connection holes (DCH1 in FIG. 4) to which first data wires (DL1 in FIG. 4) and data connection wires (DCL in FIG. 4) are connected, and second connection holes (DCH2 in FIG. 4) to which second data wires (DL2 in FIG. 4) and data connection wires (DCL2 in FIG. 4) are connected may be arranged in a "∨" shape. Alternatively, the first connection holes (DCH1 in FIG. 4) and the second connection holes (DCH2 in FIG. 4) may be arranged repeatedly in a "∧" shape, or arranged in a pattern other than "∨" and "∧".

[0086] A detailed description of the first display area (DA1) will be described later in conjunction with FIG. 7, a detailed description of the second display area (DA2) will be described later in conjunction with FIG. 17, and a detailed description of the third display area (DA3) will be described later in conjunction with FIG. 18. A detailed description of the fourth display area (DA4) will be described later in conjunction with FIG. 19, a detailed description of the fifth display area (DA5) will be described later in conjunction with FIG. 20, and a detailed description of the sixth display area (DA6) will be described later in conjunction with FIG. 21.

[0087] The non-display area (NDA) may be positioned adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0088] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and may be positioned at the bottom of the display panel (100). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0089] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0090] The connection area (CA) is an area protruding in a second direction (DR2) from one side of the main area (MA). The connection area (CA) may be positioned between the non-display area (NDA) and the bending area (BA) of the main area (MA) in the second direction (DR2).

[0091] The pad area (PA) is an area where pads (PDs) and a display driving circuit (200) are placed. The display driving circuit (200) can be attached to the driving pads of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive member such as an anisotropic conductive film.

[0092] The bending region (BA) is a bending region. When the bending region (BA) is bent, the pad region (PA) can be positioned below the connection region (CA) and below the main region (MA). The bending region (BA) can be positioned between the connection region (CA) and the pad region (PA) in the second direction (DR2).

[0093] As shown in FIG. 3, the display panel (100) may include a substrate (SUB), a thin film transistor layer (TFTL), a light-emitting element layer (EML), an encapsulation layer (TFEL), and a touch sensing unit (TDU).

[0094] The substrate (SUB) may be made of an insulating material such as a polymer resin. For example, the substrate (SUB) may be made of polyimide. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc.

[0095] A thin-film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin-film transistor layer (TFTL) may be disposed in a main region (MA) and a sub-region (SBA). The thin-film transistor layer (TFTL) includes thin-film transistors.

[0096] The light-emitting element layer (EML) can be disposed on the thin-film transistor layer (TFTL). The light-emitting element layer (EML) can be disposed in the display area (DA) of the main area (MA). The light-emitting element layer (EML) includes light-emitting elements disposed in the light-emitting parts.

[0097] The encapsulation layer (TFEL) may be disposed on the light-emitting element layer (EML). The encapsulation layer (TFEL) may be disposed in the display area (DA) and non-display area (NDA) of the main area (MA). The encapsulation layer (TFEL) comprises at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer.

[0098] The touch detection unit (TDU) can be placed on the encapsulation layer (TFEL). The touch detection unit (TDU) can be placed in the display area (DA) and non-display area (NDA) of the main area (MA). The touch detection unit (TDU) can detect a touch of a person or object using touch electrodes.

[0099] A cover window may be disposed on the touch sensing unit (TDU) to protect the upper portion of the display panel (100). The cover window may be attached to the touch sensing unit (TDU) by a transparent adhesive material such as an optically clear adhesive (OCA) film or an optically clear resin (OCR). The cover window may be an inorganic material such as glass, or an organic material such as plastic or polymer material.

[0100] Additionally, to prevent external light from reflecting off the display panel (100) and thereby reducing the visibility of the image displayed by the display panel (100), an anti-reflection member may be additionally disposed between the touch detection unit (TDU) and the cover window. The anti-reflection member may be a polarizing film. Alternatively, the anti-reflection member may include a light-blocking organic film such as a black matrix and a color filter, or a light-blocking organic film such as a black matrix and an anti-reflection organic film.

[0101] The touch driving circuit (400) can be placed on the circuit board (300). The touch driving circuit (400) can be formed as an integrated circuit (IC) and attached to the circuit board (300).

[0102] The touch driving circuit (400) can be electrically connected to a plurality of driving electrodes and a plurality of sensing electrodes of the touch sensing unit (TDU). The touch driving circuit (400) applies a touch driving signal to the plurality of driving electrodes and detects a touch sensing signal of each of the plurality of touch nodes, for example, a change in the charge of mutual capacitance, through the plurality of sensing electrodes. The touch driving circuit (400) can determine whether a user touches and whether there is proximity, etc., based on the touch sensing signal of each of the plurality of touch nodes. A user touch refers to an object such as a user's finger or a pen directly contacting the front surface of the display device (10) placed on the touch sensing unit (TDU). A user proximity refers to an object such as a user's finger or a pen being positioned away from the front surface of the display device (10), such as hovering.

[0103] The hole (OH) can penetrate the substrate (SUB), the thin-film transistor layer (TFTL), the encapsulation layer (TFEL), and the touch sensing unit (TDU). The hole (OH) can overlap with the optical device (510) in the third direction (DR3). The optical device (510) may be an optical sensor that detects light incident through the hole (OH), such as a proximity sensor, an illuminance sensor, and a camera sensor. The optical device (510) may be placed on an optical circuit board (520). The optical circuit board (520) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0104] FIG. 4 is a layout diagram showing area A of FIG. 2 in detail. FIG. 4 shows the first display area (DA1), the second display area (DA2), the fourth display area (DA4), the non-display area (NDA), and the sub-area (SBA) in detail.

[0105] Referring to FIG. 4, a plurality of first data lines (DL1), a plurality of second data lines (DL2), a plurality of data connection lines (DCL), and a plurality of first vertical power lines (VPL1) can be placed in a first display area (DA1).

[0106] A plurality of first data lines (DL1) may be extended in a second direction (DR2) and arranged in a first direction (DR1). A plurality of second data lines (DL2) may be extended in a second direction (DR2) and arranged in a first direction (DR1). A plurality of data connection lines (DCL) may include a first data connection line (DCL1) and a second data connection line (DCL2). A plurality of first vertical power lines (VPL1) may be extended in a second direction (DR2) and arranged in a first direction (DR1).

[0107] The first data connection wiring (DCL1) extends in a second direction (DR2) and can be connected to the first fan-out wiring (FL1) through the first connection hole (CH1). The second data connection wiring (DCL2) extends in a first direction (DR1) and can be connected to the first data connection wiring (DCL1) through the first data connection hole (DCH1).

[0108] Each of the plurality of first data wires (DL1) can be connected to the second data connection wire (DCL2) through the second data connection hole (DCH2). Each of the plurality of second data wires (DL2) can be connected to the second fan-out wire (FL2) through the second connection hole (CH2). Each of the plurality of first vertical power wires (VPL1) can be connected to the first power wire (PL1).

[0109] A plurality of second data lines (DL2) and a plurality of first vertical power lines (VPL1) can be placed in the second display area (DA2).

[0110] The first fan-out wires (FL1), the second fan-out wires (FL2), the first power wires (PL1), and the second power wires (PL2) may be placed in the non-display area (NDA). Each of the first fan-out wires (FL1) may be connected to the first data connection wire (DCL1) through the first connection hole (CH1). Each of the second fan-out wires (FL2) may be connected to the second data wire (DL2) through the second connection hole (CH2).

[0111] Among the first power lines (PL1), the first power line (PL1) positioned in the center can be connected to a plurality of first vertical power lines (VPL1). Among the first power lines (PL1), the first power lines (PL1) positioned on the left and right can be arranged to surround the second power lines (PL2). The second power lines (PL2) can be arranged to surround the display area (DA). A first power voltage is applied to each of the first power lines (PL1), and a second power voltage higher than the first power voltage can be applied to each of the second power lines (PL2).

[0112] The first bending wires (BL1), second bending wires (BL2), third bending wires (BL3), and fourth bending wires (BL4) can be placed in the bending area (BA). Each of the first bending wires (BL1) can be connected to the first fan-out wire (FL1) through the third connection hole (CH3). Each of the second bending wires (BL2) can be connected to the second fan-out wire (FL2) through the fourth connection hole (CH4). Each of the third bending wires (BL3) is connected to the first power wire (PL1), and each of the fourth bending wires (BL4) can be connected to the second power wire (PL2).

[0113] The first pad wires (PDL1), the second pad wires (PDL2), the first power pad wires (PPL1), and the second power pad wires (PPL2) can be placed in the pad area (PA). Each of the first pad wires (PDL1) can be connected to the first bending wire (BL1) through the fifth connection hole (CH5). Each of the second pad wires (PDL2) can be connected to the second bending wire (BL2) through the sixth connection hole (CH6). The first power pad wires (PPL1) can be connected to the third bending wires (BL3), and the second power pad wires (PPL2) can be connected to the fourth bending wires (BL4).

[0114] The first pad wires (PDL1) and the second pad wires (PDL2) can be electrically connected to the display driving circuit (200). The first power pad wires (PPL1) and the second power pad wires (PPL2) can be directly connected to the pads (PD). The display driving circuit (200) can be connected to the pads (PD) through the third pad wires (PDL3).

[0115] As shown in FIG. 4, a plurality of first data lines (DL1) positioned on the left and right sides of the display panel (100) are connected to first fan-out lines (FL1) through data connection lines (DCL). As a result, the first fan-out lines (FL1) do not need to be positioned in the non-display area (NDA) on the lower side of the display panel (100) to be connected to a plurality of first data lines (DL1) positioned adjacent to the left and right sides of the display area (DA). Therefore, even if the area of ​​the non-display area (NDA) on the lower side of the display panel (100) is reduced, there may not be a shortage of space for the placement of the fan-out lines (FL1, FL2).

[0116] FIG. 5 is a circuit diagram showing a subpixel of a display layer according to one embodiment.

[0117] Referring to FIG. 5, a subpixel (SPX) may be connected to at least one of the scan lines (GWL, GIL, GCL), any one of the light-emitting lines (EL), and any one of the data lines. For example, the subpixel (SPX) may be connected to the write scan line (GWL), the initial scan line (GIL), the control scan line (GCL), the light-emitting line (EL), and the data line (DL).

[0118] A subpixel (SPX) includes a light-emitting element (LE) and a pixel driver unit (PDU). The pixel driver unit (PDU) includes a driving transistor (DT), switching elements, and a capacitor (C1). The switching elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0119] The driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls the drain-source current (Ids, hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0120] The light-emitting element (LEL) emits light according to the driving current (Ids). The amount of light emitted by the light-emitting element (LEL) can be proportional to the driving current (Ids).

[0121] The light-emitting element (LEL) may be an organic light-emitting diode comprising an anode electrode, a cathode electrode, and an organic light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be an inorganic light-emitting element comprising an anode electrode, a cathode electrode, and an inorganic semiconductor disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be a quantum dot light-emitting element comprising an anode electrode, a cathode electrode, and a quantum dot light-emitting layer disposed between the anode electrode and the cathode electrode. Alternatively, the light-emitting element (LEL) may be a micro light-emitting diode.

[0122] The anode electrode of the light-emitting element (LEL) is connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode can be connected to the low potential wiring (VSL). A parasitic capacitance (Cel) may be formed between the anode electrode and the cathode electrode of the light-emitting element (LEL).

[0123] A capacitor (C1) is formed between the second electrode of the driving transistor (DT) and the high potential wiring (VSL). One electrode of the capacitor (C1) is connected to the second electrode of the driving transistor (DT), and the other electrode can be connected to the high potential wiring (VSL).

[0124] As shown in FIG. 5, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as P-type MOSFETs. The active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon or oxide semiconductor.

[0125] The gate electrode of the second transistor (ST2) may be connected to the write scan line (GWL), and the gate electrode of the first transistor (ST1) may be connected to the control scan line (GCL). The gate electrode of the third transistor (ST3) may be connected to the initial scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to the bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) are formed as P-type MOSFETs, they can be turned on when a scan signal of gate low voltage and a light emission signal are applied to the control scan line (GCL), initial scan line (GIL), write scan line (GWL), bias scan line (GBL), and light emission line (EL), respectively.

[0126] One electrode of the third transistor (ST3) may be connected to the first initialization voltage wire (VIL), while one electrode of the fourth transistor (ST4) may be connected to the second initialization voltage wire (VAIL). The first initialization voltage applied to the first initialization voltage wire (VIL) and the second initialization voltage applied to the second initialization voltage wire (VAIL) may be different voltages.

[0127] Alternatively, as shown in FIG. 6, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as P-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as N-type MOSFETs. The active layer of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as P-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor (ST1) and the third transistor (ST3) formed as N-type MOSFETs may be formed of an oxide semiconductor. In this case, since the transistors formed of polysilicon and the transistors formed of oxide semiconductors may be placed on different layers, the placement area of ​​each transistor in the pixels (PX) may be reduced.

[0128] Alternatively, the fourth transistor (ST4) in FIG. 6 may be formed as an N-type MOSFET. In this case, the active layer of each fourth transistor (ST4) may be formed as an oxide semiconductor.

[0129] The gate electrodes of the second transistor (ST2) and the fourth transistor (ST4) are connected to the write scan line (GWL), and the gate electrode of the first transistor (ST1) can be connected to the control scan line (GCL). The gate electrode of the third transistor (ST3) can be connected to the initial scan line (GIL). Since the first transistor (ST1) and the third transistor (ST3) are formed as N-type MOSFETs, they can be turned on when a scan signal with a gate high voltage is applied to the control scan line (GCL) and the initial scan line (GIL). In contrast, since the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as P-type MOSFETs, they can be turned on when a scan signal with a gate low voltage and a light emission signal are applied to the write scan line (GWL) and the light emission line (EL), respectively.

[0130] Alternatively, although not shown in FIGS. 5 and 6, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as N-type MOSFETs.

[0131] FIG. 7 is a layout diagram showing an example of the first display area of ​​FIG. 2. FIG. 8 is a layout diagram showing a part of the first sub-display area of ​​FIG. 7 in detail. FIG. 9 is a layout diagram showing a part of the second sub-display area of ​​FIG. 7 in detail.

[0132] Referring to FIGS. 7 through 9, the first display area (DA1) includes a first sub-display area (SDA1) and a second sub-display area (SDA2). The first sub-display area (SDA1) is an area where second data connection holes (DCH2), to which the second data connection wires (DCL2) and the first data wires (DL1) are respectively connected, are arranged, and the second sub-display area (SDA2) is an area where first data connection holes (DCH1), to which the first data connection wires (DCL1) and the second data connection wires (DCL2) are respectively connected, are arranged.

[0133] A plurality of first data lines (DL1) and a plurality of first vertical power lines (VPL1) may be placed in a first sub-display area (SDA1), and a plurality of second data lines (DL2), first data connection lines (DCL1), and a plurality of first vertical dummy patterns (VDP1) may be placed in a second sub-display area (SDA2). Additionally, the second data connection lines (DCL2) and a plurality of first horizontal dummy patterns (HDP1) may be placed in the first sub-display area (SDA1) and the second sub-display area (SDA2).

[0134] In the first sub-display area (SDA1), a plurality of first data lines (DL1) and a plurality of first vertical power lines (VPL1) can be arranged alternately in the first direction (DR1). That is, a first vertical power line (VPL1) can be arranged between adjacent first data lines (DL1) in the first direction (DR1), and a first data line (DL1) can be arranged between adjacent first vertical power lines (VPL1) in the first direction (DR1).

[0135] In the second sub-display area (SDA2), a plurality of second data lines (DL2) and first data connection lines (DCL1) can be arranged alternately in the first direction (DR1). That is, a first data connection line (DCL1) can be arranged between adjacent second data lines (DL2) in the first direction (DR1), and a second data line (DL2) can be arranged between adjacent first data connection lines (DCL1) in the first direction (DR1).

[0136] Additionally, in the second sub-display area (SDA2), a plurality of second data lines (DL2) and a plurality of first vertical dummy patterns (VDP1) can be arranged alternately in the first direction (DR1). That is, a first vertical dummy pattern (VDP1) can be arranged between adjacent second data lines (DL2) in the first direction (DR1), and a second data line (DL2) can be arranged between adjacent first vertical dummy patterns (VDP1) in the first direction (DR1).

[0137] Each of the first data wiring (DL1), the first vertical power wiring (VPL1), the second data wiring (DL2), and the first data connection wiring (DCL1) may include a first wiring section having a first width and a second wiring section having a second width greater than the first width. The first wiring sections and the second wiring sections may be arranged alternately in the second direction (DR2). Some of the second wiring sections may overlap with the second data connection wiring (DCL2) or the first horizontal dummy pattern (HDP1), while the remainder may not overlap with the second data connection wiring (DCL2) and the first horizontal dummy pattern (HDP1).

[0138] A plurality of second horizontal power lines (HPL2) may be extended in a first direction (DR1) and arranged in a second direction (DR2). A second power voltage higher than the first power voltage may be applied to the plurality of second horizontal power lines (HPL2). The first power voltage may be a low potential voltage, and the second power voltage may be a high potential voltage.

[0139] Multiple second data connection lines (DCL2) may be extended in a first direction (DR1) and arranged in a second direction (DR2). In a first display area (DA1), multiple second horizontal power lines (HPL2) and multiple second data connection lines (DCL2) may be arranged alternately in the second direction (DR2). That is, a second data connection line (DCL2) may be arranged between adjacent second horizontal power lines (HPL2) in the second direction (DR2), and a second horizontal power line (HPL2) may be arranged between adjacent second data connection lines (DCL2) in the second direction (DR2).

[0140] Multiple first horizontal dummy patterns (HDP1) can be extended in a first direction (DR1) and arranged in a second direction (DR2). In a first display area (DA1), multiple second horizontal power lines (HPL2) and multiple first horizontal dummy patterns (HDP1) can be arranged alternately in the second direction (DR2). That is, a first horizontal dummy pattern (HDP1) can be arranged between adjacent second horizontal power lines (HPL2) in the second direction (DR2), and a second horizontal power line (HPL2) can be arranged between adjacent first horizontal dummy patterns (HDP1) in the second direction (DR2).

[0141] Each of the second data connection wiring (DCL2) and the first horizontal dummy pattern (HDP1) may include third wiring sections having a third width and fourth wiring sections having a fourth width greater than the third width. The third wiring sections and the fourth wiring sections may be arranged alternately in the first direction (DR1). Each of the fourth wiring sections may overlap with the first data wiring (DL1), the first vertical power wiring (VPL1), the second data wiring (DL2), or the first data connection wiring (DCL1).

[0142] Each of the first data connection wires (DCL1) can be connected to the second data connection wires (DCL2) through the first data connection hole (DCH1). Each of the plurality of first data wires (DL1) can be connected to the second data connection wires (DCL2) through the second data connection hole (DCH2). The first data connection holes (DCH1) can be arranged in the first diagonal direction (DD1) in the second sub-display area (SDA2). The second data connection holes (DCH2) can be arranged in the second diagonal direction (DD2) in the first sub-display area (SDA1).

[0143] Among the first data connection lines (DCL1), any one of the first data connection lines (DCL1) and the adjacent first vertical dummy pattern (VDP1) may be arranged apart from each other. The first separation (SU1) between the first data connection line (DCL1) and the adjacent first vertical dummy pattern (VDP1) may overlap with the second horizontal power line (HPL2). A description of the first separation (SU1) will be given later in conjunction with FIG. 10.

[0144] Additionally, among the first data connection lines (DCL1), another first data connection line (DCL1) and the adjacent first vertical dummy pattern (VDP1) may be arranged apart from each other. The second separation (SU2) between the other first data connection line (DCL1) and the adjacent first vertical dummy pattern (VDP1) may not overlap with the second horizontal power line (HPL2). A description of the second separation (SU2) will be given later in conjunction with FIGS. 11 and 12.

[0145] Additionally, the second data connection wiring (DCL2) and the adjacent first horizontal power wiring (HPL1) may be spaced apart from each other. The third separation portion (SU3) between the second data connection wiring (DCL2) and the adjacent first horizontal power wiring (HPL1) may be positioned between the adjacent first data wiring (DL1) and the first vertical power wiring (VPL1), or between the adjacent second data wiring (DL2) and the first data connection wiring (DCL1).

[0146] Additionally, the second data connection wiring (DCL2) and the adjacent first horizontal dummy pattern (HDP1) may be spaced apart from each other. The fourth separation portion (SU4) between the second data connection wiring (DCL2) and the adjacent first horizontal dummy pattern (HDP1) may be positioned between the adjacent first data wiring (DL1) and the first vertical power wiring (VPL1), or between the adjacent second data wiring (DL2) and the first data connection wiring (DCL1).

[0147] FIG. 10 is an enlarged layout diagram showing in detail an example of the first separation portion of FIG. 9.

[0148] Referring to FIG. 10, the first gap (SU1) is positioned between the first data connection wiring (DCL1) and the adjacent first vertical dummy pattern (VDP1), and indicates a gap that overlaps with the second horizontal power wiring (HPL2). The first gap (SU1) may be a gap between the first wiring section (WP1) having a first width (Wwp1) of the first data connection wiring (DCL1) and the first wiring section (WP1) having a first width (Wwp1) of the first vertical dummy pattern (VDP1).

[0149] The length (Lsu1) of the second direction (DR2) of the first separation portion (SU1) may be smaller than the width (Whpl2) of the second horizontal power wiring (HPL2). The width (Whpl2) of the second horizontal power wiring (HPL2) may be the length of the second direction (DR2) of the second horizontal power wiring (HPL2).

[0150] FIG. 11 is an enlarged layout diagram showing in detail an example of the second separation portion of FIG. 9.

[0151] Referring to FIG. 11, the second gap (SU2) is positioned between the first data connection wiring (DCL1) and the adjacent first vertical dummy pattern (VDP1) and indicates a gap that does not overlap with the second horizontal power wiring (HPL2). The second gap (SU2) may be a gap between a first wiring section (WP1) having a first width (Wwp1) of the first data connection wiring (DCL1) and a second wiring section (WP2) having a second width (Wwp2) of the first vertical dummy pattern (VDP1), but embodiments of the present specification are not limited thereto. The second gap (SU2) may be a gap between a second wiring section (WP2) having a second width (Wwp2) of the first data connection wiring (DCL1) and a first wiring section (WP2) having a first width (Wwp1) of the first vertical dummy pattern (VDP1).

[0152] The second gap (SU2) can be formed by removing the pattern connecting the first data connection wiring (DCL1) and the first vertical dummy pattern (VDP1) by an etching process. At this time, since the second wiring portion (WP2) of the first data connection wiring (DCL1) has a thicker width than the first wiring portion (WP1), if the second gap (SU2) is formed as a gap between the first wiring portion (WP1) of the first data connection wiring (DCL1) and the second wiring portion (WP2) of the first vertical dummy pattern (VDP1), it is possible to prevent over-etching compared to the original intention during the etching process. In addition, since the second wiring portion (WP2) of the first vertical dummy pattern (VDP1) also has a thicker width than the first wiring portion (WP1), if the second separation portion (SU2) is formed as a gap between the second wiring portion (WP2) of the first data connection wiring (DCL1) and the first wiring portion (WP1) of the first vertical dummy pattern (VDP1), it is possible to prevent over-etching compared to the original intention during the etching process.

[0153] FIG. 12 is an enlarged layout diagram showing in detail another example of the second separation portion of FIG. 9.

[0154] The second gap (SU2) shown in FIG. 12 differs from the embodiment of FIG. 11 in that it is a gap between the second wiring section (WP2) having the second width (Wwp2) of the first data connection wiring (DCL1) and the second wiring section (WP2) having the second width (Wwp2) of the first vertical dummy pattern (VDP1).

[0155] The second gap (SU2) can be formed by removing the pattern connecting the first data connection wiring (DCL1) and the first vertical dummy pattern (VDP1) by an etching process. At this time, the second wiring portion (WP2) of the first data connection wiring (DCL1) has a wider width than the first wiring portion (WP1), and the second wiring portion (WP2) of the first vertical dummy pattern (VDP1) also has a wider width than the first wiring portion (WP1). Therefore, if the second gap (SU2) is formed as a gap between the first wiring portion (WP1) of the first data connection wiring (DCL1) and the second wiring portion (WP2) of the first vertical dummy pattern (VDP1), it may be easy to prevent over-etching compared to the original intention during the etching process.

[0156] FIG. 13 is a cross-sectional view showing an example of a display panel cut along A-A' of FIG. 10. FIG. 14 is a cross-sectional view showing a first comparative example of a display panel. FIG. 15 is a cross-sectional view showing a second comparative example of a display panel. FIG. 16 is a cross-sectional view showing an example of a display panel cut along B-B' of FIG. 11.

[0157] Referring to FIGS. 13 to 15, a thin-film transistor layer (TFTL) is disposed on a substrate (SUB), a first planarization layer (160) is disposed on the thin-film transistor layer (TFTL), and a second horizontal power line (HPL2) may be disposed on the first planarization layer (160). A second planarization layer (161) may be disposed on the second horizontal power line (HPL2), and a first data connection line (DCL1) and a first vertical dummy pattern (VDP1) may be disposed on the second planarization layer (161). A third planarization layer (162) may be disposed on the first data connection line (DCL1) and the first vertical dummy pattern (VDP1), and a pixel electrode (171) may be disposed on the third planarization layer (162).

[0158] At this time, the flatness of the third flattening film (162) may be affected by the step difference of the second horizontal power line (HPL2) and the step difference between the first data connection line (DCL1) and the first vertical dummy pattern (VDP1). As a result, the pixel electrode (171) placed on the first separation portion (SU1) may also have a step difference.

[0159] As shown in FIG. 13, when the second horizontal power line (HPL2) overlaps with the first separation portion (SU1), the pixel electrode (171) may have a first step (h1). In contrast, as shown in FIG. 14, when the second horizontal power line (HPL2) partially overlaps with the first separation portion (SU1), the pixel electrode (171) may have a second step (h2) that is larger than the first step (h1). Additionally, as shown in FIG. 15, when the second horizontal power line (HPL2) does not overlap with the first separation portion (SU1) but is positioned adjacent to the first separation portion (SU1), the pixel electrode (171) may have a third step (h3) that is larger than the second step (h2).

[0160] As shown in FIG. 16, when the second horizontal power line (HPL2) does not overlap with the first separation portion (SU1), the pixel electrode (171) may have a fourth step (h4). The fourth step (h4) may be smaller than the second step (h2) or the third step (h3).

[0161] The greater the step difference of the pixel electrode (171), the more visible the pattern caused by the step difference of the pixel electrode (171) is to the user when external light is reflected from the display panel (100). By arranging the first separation portion (SU1) to overlap with the second horizontal power line (HPL2) as in FIG. 13, or by arranging the second separation portion (SU2) not to overlap with the second horizontal power line (HPL2) as in FIG. 16, the pattern caused by the step difference of the pixel electrode (171) can be prevented from being visible to the user.

[0162] FIG. 17 is a layout diagram showing in detail an example of the second display area of ​​FIG. 2.

[0163] Referring to FIG. 17, the second display area (DA2) is an area where the first vertical power lines (VPL1) are connected to the first horizontal dummy patterns (HDP1) through the first power holes (PH1).

[0164] The second data lines (DL2) and the first vertical power lines (VPL1) can be arranged alternately in the first direction (DR1). That is, the first vertical power lines (VPL1) can be arranged between adjacent second data lines (DL2) in the first direction (DR1), and the second data lines (DL2) can be arranged between adjacent first vertical power lines (VPL1) in the first direction (DR1).

[0165] Each of the second data wiring (DL2) and the first vertical power wiring (VPL1) may include first wiring sections having a first width and second wiring sections having a second width greater than the first width. The first wiring sections and the second wiring sections may be arranged alternately in the second direction (DR2). Some of the second wiring sections may overlap with the first horizontal dummy pattern (HDP1), and the remainder may not overlap with the first horizontal dummy pattern (HDP1).

[0166] A plurality of second horizontal power lines (HPL2) may be extended in a first direction (DR1) and arranged in a second direction (DR2). A second power voltage may be applied to the plurality of second horizontal power lines (HPL2).

[0167] Multiple first horizontal dummy patterns (HDP1) can be extended in a first direction (DR1) and arranged in a second direction (DR2). In a first display area (DA1), multiple second horizontal power lines (HPL2) and multiple first horizontal dummy patterns (HDP1) can be arranged alternately in the second direction (DR2). That is, a first horizontal dummy pattern (HDP1) can be arranged between adjacent second horizontal power lines (HPL2) in the second direction (DR2), and a second horizontal power line (HPL2) can be arranged between adjacent first horizontal dummy patterns (HDP1) in the second direction (DR2).

[0168] The first horizontal dummy pattern (HDP1) may include third wiring sections having a third width and fourth wiring sections having a fourth width greater than the third width. The third width may be substantially the same as the first width (Wwp1), and the fourth width may be substantially the same as the second width (Wwp2). The third wiring sections and the fourth wiring sections may be arranged alternately in the first direction (DR1). Each of the fourth wiring sections may overlap with the second data wiring (DL2) or the first vertical power wiring (VPL1).

[0169] Each of the plurality of first vertical power lines (VPL1) can be connected to the first horizontal dummy pattern (HDP1) through the first power hole (PH1). FIG. 17 illustrates the first power holes (PH1) being arranged in the first diagonal direction (DD1), but embodiments of the present specification are not limited thereto. For example, the first power holes (PH1) may be arranged in the second diagonal direction (DD2). Or, the first power holes (PH1) may be arranged in the first diagonal direction (DD1) and then arranged in the second diagonal direction (DD2). That is, the first power holes (PH1) may be arranged in a ">" shape. Or, the first power holes (PH1) may be arranged in the second diagonal direction (DD2) and then arranged in the first diagonal direction (DD1). That is, the first power holes (PH1) may be arranged in a "<" shape. Alternatively, the first power holes (PH1) may be arranged in a repeating pattern other than ">" and "<".

[0170] FIG. 18 is a layout diagram showing an example of the third display area of ​​FIG. 2.

[0171] Referring to FIG. 18, the third display area (DA3) includes a third sub-display area (SDA3) and a fourth sub-display area (SDA4). The third sub-display area (SDA3) is an area where second power holes (PH2), to which first horizontal power lines (HPL1) and first vertical power lines (VPL1) are respectively connected, are arranged, and the fourth sub-display area (SDA4) is an area where third power holes (PH3), to which first horizontal power lines (HPL1) and first vertical dummy patterns (VDP1) are respectively connected, are arranged.

[0172] A plurality of first data lines (DL1) and a plurality of first vertical power lines (VPL1) may be placed in a third sub-display area (SDA3), and a plurality of second data lines (DL2) and a plurality of first vertical dummy patterns (VDP1) may be placed in a fourth sub-display area (SDA4).

[0173] In the third sub-display area (SDA3), a plurality of first data lines (DL1) and a plurality of first vertical power lines (VPL1) can be arranged alternately in the first direction (DR1). That is, a first vertical power line (VPL1) can be arranged between adjacent first data lines (DL1) in the first direction (DR1), and a first data line (DL1) can be arranged between adjacent first vertical power lines (VPL1) in the first direction (DR1).

[0174] In the fourth sub-display area (SDA4), a plurality of second data lines (DL2) and a plurality of first vertical dummy patterns (VDP1) can be arranged alternately in the first direction (DR1). That is, a first vertical dummy pattern (VDP1) can be arranged between adjacent second data lines (DL2) in the first direction (DR1), and a second data line (DL2) can be arranged between adjacent first vertical dummy patterns (VDP1) in the first direction (DR1).

[0175] Each of the first data wiring (DL1), the first vertical power wiring (VPL1), and the second data wiring (DL2) may include a first wiring section having a first width and a second wiring section having a second width greater than the first width. The first wiring sections and the second wiring sections may be arranged alternately in the second direction (DR2). Some of the second wiring sections may overlap with the first horizontal power wiring (HPL1), and the remainder may not overlap with the first horizontal power wiring (HPL1).

[0176] A plurality of second horizontal power lines (HPL2) may be extended in a first direction (DR1) and arranged in a second direction (DR2). A second power voltage may be applied to the plurality of second horizontal power lines (HPL2).

[0177] The first horizontal power wiring (HPL1) may include third wiring sections having a third width and fourth wiring sections having a fourth width greater than the third width. The third wiring sections and the fourth wiring sections may be arranged alternately in the first direction (DR1). Each of the fourth wiring sections may overlap with the first data wiring (DL1), the first vertical power wiring (VPL1), or the second data wiring (DL2).

[0178] Each of the first vertical power lines (VPL1) can be connected to the first horizontal power lines (HPL1) through the second power hole (PH2). Each of the first vertical dummy patterns (VDP1) can be connected to the first horizontal power lines (HPL1) through the third power hole (PH3).

[0179] FIG. 18 illustrates a repeating arrangement of the second power holes (PH2) and the third power holes (PH3) in a "∨" shape by arranging the second power holes (PH2) in a second diagonal direction (DD2) and the third power holes (PH3) in a first diagonal direction (DD1). However, the embodiments of this specification are not limited thereto. For example, the second power holes (PH2) and the third power holes (PH3) may be repeatedly arranged in a "∧" shape by arranging the second power holes (PH2) in a first diagonal direction (DD1) and the third power holes (PH3) in a second diagonal direction (DD2). Alternatively, the second power holes (PH2) and the third power holes (PH3) may be arranged in a repeating pattern other than "∨" and "∧".

[0180] FIG. 19 is a layout diagram showing in detail a part of the fourth display area of ​​FIG. 2.

[0181] Referring to FIG. 19, the fourth display area (DA4) includes a fifth sub-display area (SDA5) and a sixth sub-display area (SDA6). The fifth sub-display area (SDA5) is an area where first data connection holes (DCH1) are arranged to which first data connection wires (DCL1) and second data connection wires (DCL2) are respectively connected, and the sixth sub-display area (SDA6) is an area where second data connection holes (DCH2) are arranged to which second data connection wires (DCL2) and first data wires (DL1) are respectively connected.

[0182] Since the fifth sub-display area (SDA5) is substantially identical to the second sub-display area (SDA2) described in conjunction with FIG. 7, the description of the fifth sub-display area (SDA5) is omitted. Also, since the sixth sub-display area (SDA6) is substantially identical to the first sub-display area (SDA1) described in conjunction with FIG. 7, the description of the sixth sub-display area (SDA6) is omitted.

[0183] FIG. 20 is a layout diagram showing in detail a part of the fifth display area of ​​FIG. 2.

[0184] Referring to FIG. 20, the fifth display area (DA5) includes a seventh sub-display area (SDA7) and an eighth sub-display area (SDA8). The seventh sub-display area (SDA7) is an area where third power holes (PH3), to which first horizontal power lines (HPL1) and first vertical dummy patterns (VDP1) are respectively connected, are arranged, and the eighth sub-display area (SDA8) is an area where second power holes (PH2), to which first horizontal power lines (HPL1) and first vertical power lines (VPL1) are respectively connected, are arranged.

[0185] Since the seventh sub-display area (SDA7) is substantially identical to the fifth sub-display area (SDA5) described in conjunction with FIG. 18, the description of the seventh sub-display area (SDA7) is omitted. Also, since the eighth sub-display area (SDA8) is substantially identical to the fourth sub-display area (SDA4) described in conjunction with FIG. 7, the description of the fourth sub-display area (SDA4) is omitted.

[0186] FIG. 21 is a layout diagram showing in detail an example of the sixth display area of ​​FIG. 2.

[0187] Referring to FIG. 21, the sixth display area (DA6) is an area where the first vertical power lines (VPL1) are connected to the first horizontal power lines (HPL1) through the fourth power holes (PH4).

[0188] The second data lines (DL2) and the first vertical power lines (VPL1) can be arranged alternately in the first direction (DR1). That is, the first vertical power lines (VPL1) can be arranged between adjacent second data lines (DL2) in the first direction (DR1), and the second data lines (DL2) can be arranged between adjacent first vertical power lines (VPL1) in the first direction (DR1).

[0189] Each of the second data wiring (DL2) and the first vertical power wiring (VPL1) may include a first wiring section having a first width and a second wiring section having a second width greater than the first width. The first wiring sections and the second wiring sections may be arranged alternately in the second direction (DR2). Some of the second wiring sections may overlap with the first vertical power wiring (VPL1), and the remainder may not overlap with the first vertical power wiring (VPL1).

[0190] A plurality of second horizontal power lines (HPL2) may be extended in a first direction (DR1) and arranged in a second direction (DR2). A second power voltage may be applied to the plurality of second horizontal power lines (HPL2).

[0191] Multiple first vertical power lines (VPL1) may be extended in a first direction (DR1) and arranged in a second direction (DR2). In the sixth display area (DA6), multiple first horizontal power lines (HPL1) and multiple second horizontal power lines (HPL2) may be arranged alternately in the second direction (DR2). That is, a first horizontal power line (HPL1) may be arranged between adjacent second horizontal power lines (HPL2) in the second direction (DR2), and a second horizontal power line (HPL2) may be arranged between adjacent first horizontal power lines (HPL1) in the second direction (DR2).

[0192] The first horizontal power wiring (HPL1) may include third wiring sections having a third width and fourth wiring sections having a fourth width greater than the third width. The third wiring sections and the fourth wiring sections may be arranged alternately in the first direction (DR1). Each of the fourth wiring sections may overlap with the second data wiring (DL2) or the first vertical power wiring (VPL1).

[0193] Each of the plurality of first vertical power lines (VPL1) can be connected to the first horizontal power line (HPL1) through the fourth power hole (PH4). FIG. 22 illustrates the fourth power holes (PH4) being arranged in the first diagonal direction (DD1), but embodiments of the present specification are not limited thereto. For example, the fourth power holes (PH4) may be arranged in the second diagonal direction (DD2). Or, the fourth power holes (PH4) may be arranged in the first diagonal direction (DD1) and then arranged in the second diagonal direction (DD2). That is, the fourth power holes (PH4) may be arranged in a ">" shape. Or, the fourth power holes (PH4) may be arranged in the second diagonal direction (DD2) and then arranged in the first diagonal direction (DD1). That is, the fourth power holes (PH4) may be arranged in a "<" shape. Alternatively, the fourth power holes (PH4) may be arranged in a repeating pattern other than ">" and "<".

[0194] FIG. 22 is a layout diagram showing in detail an example of the seventh display area of ​​FIG. 2. FIG. 23 is a layout diagram showing in detail a first area and a part of the third area of ​​the seventh display area of ​​FIG. 22. FIG. 24 is a layout diagram showing in detail a second area, a fourth area, and a part of the non-display area of ​​the seventh display area of ​​FIG. 22.

[0195] Referring to FIGS. 22 through 24, the seventh display area (DA7) may include a first area (A1), a second area (A2), a third area (A3), and a fourth area (A4). Each of the first area (A1) and the third area (A3) is an area where second data lines (DL2) disposed on one side of the hole (OH) are connected to bypass lines (DETL). Each of the second area (A2) and the fourth area (A4) is an area where third data lines (DL3) disposed on the other side of the hole (OH) are connected to bypass lines (DETL). One side of the hole (OH) may be the lower side of the hole (OH), and the other side of the hole (OH) may be the upper side of the hole (OH).

[0196] A plurality of second data lines (DL2), a plurality of third data lines (DL3), a plurality of first vertical power lines (VPL1), a plurality of second vertical power lines (VPL2), a plurality of first horizontal power lines (HPL1), a plurality of second horizontal power lines (HPL2), a plurality of second horizontal dummy patterns (HDP2), a plurality of third horizontal dummy patterns (HDP3), a plurality of second vertical dummy patterns (VDP2), and a plurality of bypass lines (DETL) can be placed in the seventh display area (DA7).

[0197] A plurality of second data lines (DL2) may be extended in a second direction (DR2) and arranged in a first direction (DR1). A plurality of third data lines (DL3) may be extended in a second direction (DR2) and arranged in a first direction (DR1).

[0198] A plurality of first vertical power lines (VPL1) may be extended in a second direction (DR2) and arranged in a first direction (DR1). A plurality of second vertical power lines (VPL2) may be extended in a second direction (DR2) and arranged in a first direction (DR1). A plurality of second vertical dummy patterns (VDP2) may be extended in a second direction (DR2) and arranged in a first direction (DR1).

[0199] The lengths of two adjacent second vertical pile patterns (VDP2) in the first direction (DR1) may differ. For example, among two adjacent second vertical pile patterns (VDP2) in the second region (A2), the length of the second vertical pile pattern (VDP2) placed on the right may be greater than the length of the second vertical pile pattern (VDP2) placed on the left.

[0200] Multiple second data lines (DL2) and multiple first vertical power lines (VPL1) can be arranged alternately in the first direction (DR1). Multiple third data lines (DL3) and multiple second vertical power lines (VPL2) can be arranged alternately in the first direction (DR1). Multiple third data lines (DL3) and multiple second vertical dummy patterns (VDP2) can be arranged alternately in the first direction (DR1).

[0201] A plurality of first horizontal power lines (HPL1) may be extended in a first direction (DR1) and arranged in a second direction (DR2). A plurality of second horizontal power lines (HPL2) may be extended in a first direction (DR1) and arranged in a second direction (DR2). A plurality of first horizontal power lines (HPL1) and a plurality of second horizontal power lines (HPL2) may be arranged alternately in the second direction (DR2). A first power voltage may be applied to a plurality of first horizontal power lines (HPL1), and a second power voltage higher than the first power voltage may be applied to a plurality of second horizontal power lines (HPL2).

[0202] Each of the plurality of bypass lines (DETL) may include a first sub-bypass line (DETL1), a second sub-bypass line (DETL2), and a third sub-bypass line (DETL3). The first sub-bypass line (DETL1) may extend in a first direction (DR1), the second sub-bypass line (DETL2) may extend in a second direction (DR2), and the third sub-bypass line (DETL3) may extend in a first direction (DR1).

[0203] The lengths of two adjacent first sub-bypass lines (DETL1) in the second direction (DR2) may differ. For example, the length of the first sub-bypass line (DETL1) may decrease as it approaches the hole (OH).

[0204] The lengths of two adjacent second sub-bypass lines (DETL2) in the first direction (DR1) may differ. For example, the length of the second sub-bypass line (DETL2) may decrease as it gets closer to the hole (OH).

[0205] The lengths of two adjacent third sub-bypass lines (DETL3) in the second direction (DR2) may differ. For example, the length of the third sub-bypass line (DETL3) may decrease as it gets closer to the hole (OH).

[0206] In each of the first area (A1) and the third area (A3), the second data wiring (DL2) can be connected to the first sub-bypass wiring (DETL1) through the first bypass connection hole (TCH1). In each of the first area (A1) and the third area (A3), the second sub-bypass wiring (DETL2) can be connected to the first sub-bypass wiring (DETL1) through the second bypass connection hole (TCH2).

[0207] The first bypass connection holes (TCH1) may be arranged in the second diagonal direction (DD2), and the second bypass connection holes (TCH2) may be arranged in the first diagonal direction (DD1). That is, the first bypass connection holes (TCH1) and the second bypass connection holes (TCH2) may be arranged in an "∧" shape, but the embodiments of this specification are not limited thereto.

[0208] In each of the second area (A2) and the fourth area (A4), the second sub-bypass wiring (DETL2) can be connected to the third sub-bypass wiring (DETL3) through the third bypass connection hole (TCH3). In each of the second area (A2) and the fourth area (A4), the third data wiring (DL3) can be connected to the third sub-bypass wiring (DETL3) through the fourth bypass connection hole (TCH4).

[0209] The third bypass connection holes (TCH3) may be arranged in the second diagonal direction (DD2), and the fourth bypass connection holes (TCH4) may be arranged in the first diagonal direction (DD1). That is, the third bypass connection holes (TCH3) and the fourth bypass connection holes (TCH4) may be arranged in a "∨" shape, but the embodiments of this specification are not limited thereto.

[0210] Multiple second horizontal pile patterns (HDP2) may be placed in the first area (A1) and the third area (A3). Multiple second horizontal pile patterns (HDP2) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Multiple second horizontal pile patterns (HDP2) and multiple second horizontal power lines (HPL2) may be arranged alternately in the second direction (DR2). The lengths of two adjacent second horizontal pile patterns (HDP2) in the second direction (DR2) may differ. For example, the length of the second horizontal pile pattern (HDP2) may increase as it approaches the hole (OH).

[0211] Each of the multiple second horizontal dummy patterns (HDP2) can be connected to the first vertical power wiring (VPL1) through the fifth power hole (PH5). The fifth power holes (PH5) can be arranged in the second direction (DR2). The fifth power holes (PH5) can be positioned adjacent to the boundary between the first area (A1) and the third area (A3). The fifth power holes (PH5) can overlap with the center (OHC) of the hole (OH) in the second direction (DR2).

[0212] Multiple third horizontal pile patterns (HDP3) may be placed in the second area (A2) and the fourth area (A4). Multiple third horizontal pile patterns (HDP3) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Multiple third horizontal pile patterns (HDP3) and multiple second horizontal power lines (HPL2) may be arranged alternately in the second direction (DR2). The lengths of two adjacent third horizontal pile patterns (HDP3) in the second direction (DR2) may differ. For example, the length of the third horizontal pile pattern (HDP3) may increase as it approaches the hole (OH).

[0213] Each of the plurality of third horizontal dummy patterns (HDP3) can be connected to the second vertical power wiring (VPL2) through the sixth power hole (PH6). The sixth power holes (PH6) can be arranged in the second direction (DR2). The sixth power holes (PH6) can be positioned adjacent to the boundary between the second area (A2) and the fourth area (A4). The sixth power holes (PH6) can overlap with the center (OHC) of the hole (OH) in the second direction (DR2). Each of the second data wiring (DL2), the third data wiring (DL3), the first vertical power wiring (VPL1), the second vertical power wiring (VPL2), and the second sub-bypass wiring (DETL2) may include a first wiring section having a first width and a second wiring section having a second width greater than the first width. The first wiring sections and the second wiring sections can be arranged alternately in the second direction (DR2). Some of the second wiring sections overlap with the first sub-bypass wiring (DETL1), the third sub-bypass wiring (DETL3), or the first horizontal dummy pattern (HDP1), while the remainder may not overlap with the first sub-bypass wiring (DETL1), the third sub-bypass wiring (DETL3), and the first horizontal dummy pattern (HDP1).

[0214] Each of the first sub-bypass wiring (DETL1), the third sub-bypass wiring (DETL3), the first horizontal power wiring (HPL1), and the second horizontal dummy pattern (HDP2) may include a third wiring section having a third width and a fourth wiring section having a fourth width greater than the third width. The third wiring sections and the fourth wiring sections may be arranged alternately in the first direction (DR1). Each of the fourth wiring sections may overlap with the second data wiring (DL2), the third data wiring (DL3), the first vertical power wiring (VPL1), the second vertical power wiring (VPL2), and the second sub-bypass wiring (DETL2).

[0215] One end of the second sub-bypass wiring (DETL2) may be positioned apart from the adjacent first vertical power wiring (VPL1). The fifth separation (SU5) between the end of the second sub-bypass wiring (DETL2) and the adjacent first vertical power wiring (VPL1) may overlap with the second horizontal power wiring (HPL2). The fifth separation (SU5) may be substantially identical to the first separation (SU1) in conjunction with FIG. 10.

[0216] Additionally, the other end of the second sub-bypass wiring (DETL2) may be positioned apart from the adjacent first vertical dummy pattern (VDP1). The sixth separation (SU6) between one end of the second sub-bypass wiring (DETL2) and the adjacent first vertical power wiring (VPL1) may not overlap with the first horizontal power wiring (HPL1) and the second horizontal power wiring (HPL2). The sixth separation (SU6) may be substantially the same as the second separation (SU2) described in conjunction with FIGS. 11 and 12.

[0217] The seventh separation (SU7) is positioned between one end of the first sub-bypass wiring (DETL1) and the first horizontal power wiring (HPL1). The seventh separation (SU7) may not overlap with other wiring or electrodes.

[0218] The eighth separation (SU8) is positioned between the other end of the first sub-bypass wiring (DETL1) and the second horizontal dummy pattern (HDP2). The eighth separation (SU8) may not overlap with other wiring or electrodes.

[0219] The ninth separation section (SU9) is positioned between the second sub-bypass wiring (DETL2) and the second vertical dummy pattern (VDP2), and can overlap with the second horizontal power wiring (HPL2).

[0220] The 10th separation section (SU10) is positioned between the second sub-bypass wiring (DETL2) and the second vertical dummy pattern (VDP2) and may not overlap with the first horizontal power wiring (HPL1) and the second horizontal power wiring (HPL2).

[0221] The eleventh separation (SU11) is positioned between one end of the third sub-bypass wiring (DETL3) and the first horizontal power wiring (HPL1). The eleventh separation (SU11) may not overlap with other wiring or electrodes.

[0222] The 12th separation (SU12) is positioned between the other end of the third sub-bypass wiring (DETL3) and the third horizontal dummy pattern (HDP3). The 12th separation (SU12) may not overlap with other wiring or electrodes. Additionally, one end of the first sub-bypass wiring (DETL1) and the adjacent first horizontal power wiring (HPL1) may be positioned apart from each other. The 7th separation (SU7) between one end of the first sub-bypass wiring (DETL1) and the adjacent first horizontal power wiring (HPL1) may be positioned between the adjacent second data wiring (DL2) and the second sub-bypass wiring (DETL2).

[0223] Additionally, the other end of the first sub-bypass wiring (DETL1) and the adjacent second horizontal dummy pattern (HDP2) may be spaced apart from each other. The eighth separation (SU8) between one end of the first sub-bypass wiring (DETL1) and the adjacent second horizontal dummy pattern (HDP2) may be positioned between the adjacent second data wiring (DL2) and the first vertical power wiring (VPL1).

[0224] Additionally, one end of the third sub-bypass wiring (DETL3) and the adjacent first horizontal power wiring (HPL1) may be spaced apart from each other. The eleventh separation (SU11) between one end of the third sub-bypass wiring (DETL3) and the adjacent first horizontal power wiring (HPL1) may be spaced between the adjacent third data wiring (DL3) and the second sub-bypass wiring (DETL2).

[0225] Additionally, the other end of the third sub-bypass wiring (DETL3) and the adjacent second horizontal dummy pattern (HDP2) may be spaced apart from each other. The twelfth separation (SU12) between the other end of the third sub-bypass wiring (DETL3) and the adjacent second horizontal dummy pattern (HDP2) may be positioned between the adjacent third data wiring (DL3) and the second vertical power wiring (VPL2).

[0226] A non-display area (NDA) may be placed on the upper side of the second area (A2) and the upper side of the fourth area (A4). A first power line (PL1) and a second power line (PL2) may be placed in the non-display area (NDA).

[0227] The second power wiring (PL2) can be extended from the non-display area (NDA) to the first direction (DR1). Each of the second vertical power wiring (VPL2) and the second vertical dummy pattern (VDP2) is connected to the power connection pattern (VCP1) through the second power connection hole (PCH2), and the power connection pattern (VCP) can be connected to the second power wiring (PL2) through the first power connection hole (PCH1). As a result, the second power voltage of the second power wiring (PL2) can be applied to each of the second vertical power wiring (VPL2) and the second vertical dummy pattern (VDP2).

[0228] In summary, as shown in FIG. 4 and FIG. 22, the first vertical power line (VPL1) and the first vertical dummy pattern (VDP1), which are positioned on one side of the hole (OH), are connected to the first power line (PL1) at the lower side of the non-display area (NDA) so that the first power voltage can be applied. In contrast, as shown in FIG. 22, the second vertical power line (VPL2) and the second vertical dummy pattern (VDP2), which are positioned on the other side of the hole (OH), are connected to the second power line (PL2) at the upper side of the non-display area (NDA) so that the second power voltage can be applied. That is, the power voltage applied to the first vertical power line (VPL1) and the first vertical dummy pattern (VDP1) may be different from the power voltage applied to the second vertical power line (VPL2) and the second vertical dummy pattern (VDP2).

[0229] The first power wiring (PL1) may be positioned outside the second power wiring (PL2). That is, in the non-display area (NDA) positioned above the second area (A2) and above the fourth area (A4), the first power wiring (PL1) may be positioned above the second power wiring (PL2).

[0230] Meanwhile, if the hole (OH) is positioned adjacent to the non-display area (NDA), some of the second sub-bypass wiring (DETL2) and the third sub-bypass wiring (DETL3) may be positioned in the second area (A2), and the remainder may be positioned in the non-display area (NDA). The second sub-bypass wiring (DETL2) and the third sub-bypass wiring (DETL3) positioned in the non-display area (NDA) may be positioned between the first power wiring (PL1) and the second power wiring (PL2).

[0231] To minimize the width of the non-display area (NDA), the second sub-bypass wiring (DETL2) and the third sub-bypass wiring (DETL3), which are adjacent to each other in the non-display area (NDA), may be placed on different layers. In this case, the second sub-bypass wiring (DETL2) may be connected to the third sub-bypass wiring (DETL3), which is placed on the same layer as the first sub-bypass wiring (DETL1), through the third bypass connection hole (TCH3). The third data wiring (DL3) may be connected to the third sub-bypass wiring (DETL3), which is placed on the same layer as the first sub-bypass wiring (DETL1), through the fourth bypass connection hole (TCH4).

[0232] In addition, since the second sub-bypass wiring (DETL2) and the third data wiring (DL3) are placed on the same layer, the second sub-bypass wiring (DETL2) can be connected to the third data wiring (DL3) without a separate connection hole.

[0233] Meanwhile, as shown in FIG. 24, the first vertical dummy pattern (VDP1) placed in the third display area (DA3) can be directly connected to the first power wiring (PL1) in the non-display area (NDA).

[0234] Figure 25 is a layout diagram showing a part of the hole in Figure 22 in detail.

[0235] Referring to FIG. 25, the seventh marked area (DA7) may include an inorganic encapsulation area (AED) surrounding the hole (OH).

[0236] The weapon bag area (AED) may include at least one dam (DAM) and a plurality of grooves (GR1 to GR4) formed on the inner and outer sides of the dam (DAM). First to third grooves (GR1 to GR3) may be arranged on the inner side of the dam (DAM) adjacent to the hole (OH), and a fourth groove (GR4) may be arranged on the outer side of the dam (DAM).

[0237] As shown in FIG. 33, an inorganic encapsulation structure can be realized by blocking the organic film of the encapsulation layer (TFE) by the dam (DAM) and arranging inorganic films inside the dam (DAM). The dam (DAM) may include a first dam (DAM1) formed by the same process with the same material as the second planarization film (161), a second dam (DAM2) formed by the same process with the same material as the third planarization film (162), a third dam (DAM3) formed by the same process with the same material as the bank (180), and a fourth dam (DAM4) formed by the same process with the same material as the spacer (SPC). The first to fourth grooves (GR1~GR4) may be formed by removing a portion of the upper surface of the substrate (SUB) and may have a groove shape.

[0238] In addition, due to the bypass wiring (DETL), the bypass section of the wiring that runs along the weapon encapsulation area (AED) can be omitted, allowing subpixels (SPX) to be placed immediately adjacent to the weapon encapsulation area (AED). Therefore, since the distance between the hole (OH) and the area where the subpixels (SPX) are placed can be minimized, the distance between the hole (OH) and the subpixels (SPX) can be improved so that it is not visible to the user as a non-display area.

[0239] Meanwhile, active patterns (ACP) may be disposed in the space between the subpixels (SPX) and the hole (OH). Additionally, as shown in FIG. 33, an exposed hole (H) may be formed to expose the active pattern (ACP) by penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). Due to the active patterns (ACP) and the exposed hole (H), the pattern density of the active layer formed on the subpixels (SPX) can be maintained uniformly, thereby preventing the active layer or contact hole formed on the subpixels (SPX) from being over-etched.

[0240] Additionally, a dummy pattern (DP) may be placed in the exposed hole (H). The dummy pattern (DP) may be placed away from the sidewalls of the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The dummy patterns (DP) may be remnants of the first data metal layer (DTL1). FIG. 33 illustrates that the dummy patterns (DP) are placed adjacent to both sidewalls of the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142) in the exposed hole (H), but embodiments of the present specification are not limited thereto. For example, the dummy pattern (DP) may be placed adjacent only to one sidewall of the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142) in the exposed hole (H), or may not be placed in the exposed hole (H).

[0241] Additionally, active patterns (ACPs) may be placed between the first power line (PL1) and the second power line (PL2) in the non-display area (NDA) as shown in FIG. 24. For example, active patterns (APs) may be placed adjacent to the second sub-bypass lines (DETL2) and the third sub-bypass lines (DETL3) placed in the non-display area (NDA).

[0242] Figures 26 and 27 are layout drawings showing in detail an example of area B of Figure 23.

[0243] FIG. 26 shows the active layer, first gate layer, second gate layer, and first source drain layer of the pixel driving unit (PDU), and FIG. 27 shows the active layer, first gate layer, second gate layer, first source drain layer, second source drain layer, and third source drain layer of the pixel driving unit (PDU).

[0244] Referring to FIGS. 26 and 27, scan write wires (GWL), scan initialization wires (GIL), scan bias wires (GBL), and light emission wires (EL) can be extended in a first direction (DR1). Additionally, first horizontal initialization wires (HVIL), second horizontal initialization wires (HVAIL), first horizontal power wires (HPL1), second horizontal power wires (HPL2), horizontal driving voltage wires (HVDL), and first sub-bypass wires (DETL1) can be extended in a first direction (DR1).

[0245] The first vertical initialization lines (VVIL), the second vertical initialization lines (VVAIL), and the vertical drive voltage lines (VVDL) can be extended in the second direction (DR2). Additionally, the second data lines (DL) and the first vertical power lines (VPL1) can be extended in the second direction (DR2).

[0246] The pixel driving unit (PDU) may include a driving transistor (DT), first to sixth transistors (ST1 to ST6), a capacitor (CST), and connecting electrodes (CE1 to CE6). The first transistor (ST1) may include a first-1 transistor (ST1-1) and a first-2 transistor (ST1-2). The third transistor (ST3) may include a third-1 transistor (ST3-1) and a third-2 transistor (ST3-2).

[0247] The driving transistor (DT) may include a channel layer (DTCH), a gate electrode (DTG), a first electrode (DTS), and a second electrode (DTD). The channel layer (DTCH) of the driving transistor (DT) may overlap with the gate electrode (DTG) of the driving transistor (DT). The gate electrode (DTG) of the driving transistor (DT) may be placed on the channel layer (DTCH) of the driving transistor (DT).

[0248] The gate electrode (DTG) of the driving transistor (DT) can be connected to the first connection electrode (CE1) through the first contact hole (CT1). The first connection electrode (BE1) can be connected to the second electrode (D2) of the first-second transistor (ST1-2) through the second contact hole (CT2). The first connection electrode (CE1) can intersect with the k-th scan control wiring (GCLk).

[0249] The first electrode (DTS) of the driving transistor (DT) can be connected to the second electrode (D2) of the second transistor (ST2) and the second electrode (D5) of the fifth transistor (ST5).

[0250] The second electrode (DTD) of the driving transistor (DT) can be connected to the first electrode (S1-1) of the first-1 transistor (ST1-1) and the first electrode (S6) of the sixth transistor (ST6).

[0251] The first-1 transistor (ST1-1) may include a channel layer (CH1-1), a gate electrode (G1-1), a first electrode (S1-1), and a second electrode (D1-1). The channel layer (CH1-1) of the first-1 transistor (ST1-1) may overlap with the gate electrode (G1-1) of the first-1 transistor (ST1-1). The gate electrode (G1-1) of the first-1 transistor (ST1-1) may be formed integrally with the scan write wiring (GWL). The gate electrode (G1-1) of the first-1 transistor (ST1-1) may be part of the scan write wiring (GWL). The first electrode (S1-1) of the first-1 transistor (ST1-1) may be connected to the second electrode (DTD) of the driving transistor (DT). The second electrode (D1-1) of the first-1 transistor (ST1-1) can be connected to the first electrode (S1-2) of the first-2 transistor (ST1-2).

[0252] The first-second transistor (ST1-2) may include a channel layer (CH1-2), a gate electrode (G1-2), a first electrode (S1-2), and a second electrode (D1-2). The channel layer (CH1-2) of the first-second transistor (ST1-2) may overlap with the gate electrode (G1-2) of the first-second transistor (ST1-2). The gate electrode (G1-2) of the first-second transistor (ST1-2) may be formed integrally with the scan write wiring (GWL). The gate electrode (G1-2) of the first-second transistor (ST1-2) may protrude in a second direction (DR2) from the scan write wiring (GWL). The first electrode (S1-2) of the first-second transistor (ST1-2) may be connected to the second electrode (D1-1) of the first-first transistor (ST1-1). The second electrode (D1-2) of the first-second transistor (ST1-2) can be connected to the first connection electrode (CE1).

[0253] The second transistor (ST2) may include a channel layer (CH2), a gate electrode (G2), a first electrode (S2), and a second electrode (D2). The channel layer (CH2) of the second transistor (ST2) may overlap with the gate electrode (G2) of the second transistor (ST2). The gate electrode (G2) of the second transistor (ST2) may be formed integrally with the scan write wiring (GWL). The gate electrode (G2) of the second transistor (ST2) may be part of the scan write wiring (GWL). The first electrode (S1) of the second transistor (ST2) may be connected to the second connection electrode (BE2) through the fourth contact hole (CT4). The second electrode (D2) of the second transistor (ST2) may be connected to the first electrode (DTS) of the driving transistor (DT).

[0254] The third-1 transistor (ST3-1) may include a channel layer (CH3-1), a gate electrode (G3-1), a first electrode (S3-1), and a second electrode (D3-1). The channel layer (CH3-1) of the third-1 transistor (ST3-1) may overlap with the gate electrode (G3-1) of the third-1 transistor (ST3-1). The gate electrode (G3-1) of the third-1 transistor (ST3-1) may be formed integrally with the scan initialization wiring (GIL). The gate electrode (G3-1) of the third-1 transistor (ST3-1) may be part of the scan initialization wiring (GIL). The first electrode (S3-1) of the third-1 transistor (ST3-1) may be connected to a first connection electrode (CE1). The second electrode (D3-1) of the third-1 transistor (ST3-1) can be connected to the first electrode (S3-2) of the third-2 transistor (ST3-2).

[0255] The third-2 transistor (ST3-2) may include a channel layer (CH3-2), a gate electrode (G3-2), a first electrode (S3-2), and a second electrode (D3-2). The channel layer (CH3-2) of the third-2 transistor (ST3-2) may overlap with the gate electrode (G3-2) of the third-2 transistor (ST3-2). The gate electrode (G3-2) of the third-2 transistor (ST3-2) may be formed integrally with the scan initialization wiring (GIL). The gate electrode (G3-2) of the third-2 transistor (ST3-2) may be part of the scan initialization wiring (GIL). The first electrode (S3-2) of the third-2 transistor (ST3-2) may be connected to the second electrode (D3-1) of the third-1 transistor (ST3-1). The second electrode (D3-2) of the third-2 transistor (ST3-2) can be connected to the first vertical initialization wiring (VVIL) through the second initialization contact hole (VICH2).

[0256] The fourth transistor (ST4) may include a channel layer (CH4), a gate electrode (G4), a first electrode (S4), and a second electrode (D4). The channel layer (CH4) of the fourth transistor (ST4) may overlap with the gate electrode (G4) of the fourth transistor (ST4). The gate electrode (G4) of the fourth transistor (ST4) may be formed integrally with the scan bias wiring (GBL). The gate electrode (G4) of the fourth transistor (ST4) may be part of the scan bias wiring (GBL). The k-th scan bias wiring may be the k+1-th scan initialization wiring. The first electrode (S4) of the fourth transistor (ST4) may be connected to the third connection electrode (CE3) through the seventh contact hole (CH7). The second electrode (D4) of the fourth transistor (ST4) may be connected to the second vertical initialization wiring (VVAIL) through the fourth initialization contact hole (VACH2).

[0257] The fifth transistor (ST5) may include a channel layer (CH5), a gate electrode (G5), a first electrode (S5), and a second electrode (D5). The channel layer (CH5) of the fifth transistor (ST5) may overlap with the gate electrode (G5) of the fifth transistor (ST5). The gate electrode (G5) of the fifth transistor (ST5) may be formed integrally with the light-emitting wiring (EML). The gate electrode (G5) of the fifth transistor (ST5) may be part of the light-emitting wiring (EML). The first electrode (S5) of the fifth transistor (ST5) may be connected to the vertical driving voltage wiring (VVDL) through the sixth contact hole (CT6). The second electrode (D5) of the fifth transistor (ST5) may be connected to the first electrode (DTS) of the driving transistor (DT).

[0258] The sixth transistor (ST6) may include a channel layer (CH6), a gate electrode (G6), a first electrode (S6), and a second electrode (D6). The channel layer (CH6) of the sixth transistor (ST6) may overlap with the gate electrode (G6) of the sixth transistor (ST6). The gate electrode (G6) of the sixth transistor (ST6) may be formed integrally with the light-emitting wiring (EML). The gate electrode (G6) of the sixth transistor (ST6) may be part of the light-emitting wiring. The first electrode (S6) of the sixth transistor (ST6) may be connected to the second electrode (DTD) of the driving transistor (DT). The second electrode (D6) of the sixth transistor (ST6) may be connected to the third connection electrode (CE3) through the seventh contact hole (CH7).

[0259] The first electrode (CAE1) of the capacitor (CST) can be formed integrally with the gate electrode (DTG) of the driving transistor (DT). The first electrode (CAE1) of the capacitor (CST) may be part of the gate electrode (DTG) of the driving transistor (DT). The second electrode (CAE2) of the capacitor (CST) can be formed integrally with the horizontal driving voltage wiring (HVDL). The second electrode (CAE2) of the capacitor (CST) may be part of the horizontal driving voltage wiring (HVDL). The second electrode (CAE2) of the capacitor (CST) may overlap with the first electrode (CAE1) of the capacitor (CST). The horizontal driving voltage wiring (HVDL) may be connected to the vertical driving voltage wiring (VVDL) through the fifth contact hole (CT5).

[0260] The first connecting electrode (CE1) is connected to the gate electrode (DTG) of the driving transistor (DT) through the first contact hole (CT1), and can be connected to the second electrode (D1-2) of the first-second transistor (ST1-2) and the first electrode (S3-1) of the third-first transistor (ST3-1) through the second contact hole (CT2). The first connecting electrode (CE1) can be extended in the second direction (DR2). The first connecting electrode (CE1) can overlap with the scan write wiring (GWL) and the horizontal driving voltage wiring (HVDL).

[0261] The second connection electrode (CE2) can be connected to the first electrode (S2) of the second transistor (ST2) through the fourth contact hole (CT4). The fourth connection electrode (CE4) can be connected to the second connection electrode (CE2) through the tenth contact hole (CT10). The second data wiring (DL2) can be connected to the fourth connection electrode (CE4) through the eleventh contact hole (CT11).

[0262] The third connecting electrode (CE3) can be connected to the second electrode (D6) of the sixth transistor (ST6) through the seventh contact hole (CT7). The fifth connecting electrode (CE5) can be connected to the third connecting electrode (CE3) through the eighth contact hole (CT8). The sixth connecting electrode (CE6) can be connected to the fifth connecting electrode (CE5) through the ninth contact hole (CT9).

[0263] The shielding electrode (SHE) can be connected to the vertical driving voltage wiring (VVDL) through the third contact hole (CT3). The shielding electrode (SHE) can overlap the second electrode (D1-2) of the first-1 transistor (ST1-1) and the first electrode (S1-2) of the first-2 transistor (ST1-2). Additionally, the shielding electrode (SHE) can overlap the first electrode (S3-1) of the third-1 transistor (ST3-1).

[0264] The first horizontal initialization wiring (HVIL) and the second horizontal initialization wiring (HVAIL) can be extended in the first direction (DR1). The first horizontal initialization wiring (HVIL) and the second horizontal initialization wiring (HVAIL) can be arranged alternately in the second direction (DR2).

[0265] The first vertical initialization wiring (VVIL) and the second vertical initialization wiring (VVAIL) can be extended in the second direction (DR2). The first vertical initialization wiring (VVIL) and the second vertical initialization wiring (VVAIL) can be arranged alternately in the second direction (DR2).

[0266] The first vertical initialization wire (VVIL) can be connected to the first horizontal initialization wire (HVIL) through the first initialization contact hole (VICH1). The first vertical initialization wire (VVIL) can be connected to the second electrode (D3-2) of the third transistor (ST3-2) through the second initialization contact hole (VICH2).

[0267] The second vertical initialization wire (VVAIL) can be connected to the second horizontal initialization wire (HVAIL) through the third initialization contact hole (VACH1). The second vertical initialization wire (VVAIL) can be connected to the second electrode (D4) of the fourth transistor (ST4) through the fourth initialization contact hole (VICH4).

[0268] A first initialization voltage may be applied to the first horizontal initialization wiring (HVIL) and the first vertical initialization wiring (VVIL), and a second initialization voltage may be applied to the second horizontal initialization wiring (HVAIL) and the second vertical initialization wiring (VVAIL).

[0269] The first sub-bypass wiring (DETL1) can be connected to the second sub-bypass wiring (DETL2) through the second bypass connection hole (TCH2).

[0270] The fifth separation portion (SU5) is positioned between the second sub-bypass wiring (DETL2) and the first vertical power pattern (VPL1) and may overlap with the second horizontal power wiring (HPL2). Additionally, the fifth separation portion (SU5) may overlap with the horizontal driving voltage wiring (HVDL) and the second electrode (DTD) of the driving transistor (DT).

[0271] The sixth separation section (SU6) is positioned between the second sub-bypass wiring (DETL2) and the first vertical power pattern (VPL1) and can overlap with the scan bias wiring (GBL).

[0272] Each of the seventh separation sections (SU7) is positioned between one end of the first sub-bypass wiring (DETL1) and the first horizontal power wiring (HPL1). The seventh separation sections (SU7) may not overlap with other wiring or electrodes.

[0273] FIG. 28 is a cross-sectional view showing an example of a display panel cut along C-C' of FIG. 26 and FIG. 27. FIG. 29 is a cross-sectional view showing an example of a display panel cut along D-D' of FIG. 27. FIG. 30 is a cross-sectional view showing an example of a display panel cut along E-E' of FIG. 27. FIG. 31 is a cross-sectional view showing an example of a display panel cut along F-F' of FIG. 27.

[0274] Referring to FIGS. 28 to 31, a thin-film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin-film transistor layer (TFTL) may be a layer on which the driving transistor (DT) of each pixel driving unit (PDU1 to PDU4), the first to sixth transistors (ST1 to ST6), and the capacitor (CST) are formed.

[0275] The display panel (100) includes a substrate (SUB), an active layer (ACT), a first gate layer (GTL1), a second gate layer (GTL2), a first data metal layer (DTL1), a second data metal layer (DTL2), and a third data metal layer (DTL3). Additionally, the display panel (100) includes a buffer film (BF), a gate insulating film (130), a first interlayer insulating film (141), a second interlayer insulating film (142), a first planarization film (160), a second planarization film (161), and a third planarization film (162).

[0276] A buffer film (BF) may be disposed on one side of the substrate (SUB). The buffer film (BF) may be formed on one side of the substrate (SUB) to protect the thin-film transistors and the organic light-emitting layer (172) of the light-emitting element layer (EML) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability. The buffer film (BF) may be composed of a plurality of inorganic films that are alternately stacked. For example, the buffer film (BF) may be formed as a multilayer in which one or more inorganic films selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The buffer film (BF) may be omitted.

[0277] An active layer (ACT) may be disposed on the buffer film (BF). The active layer (ACT) may include a silicon semiconductor such as polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, and amorphous silicon.

[0278] The active layer (ACT) may include a channel layer (DTCH), a first electrode (DTS), and a second electrode (DTD) of the driving transistor (DT). The channel layer (DTCH) of the driving transistor (DT) may be a region that overlaps with the gate electrode (DTG) of the driving transistor (DT) in a third direction (DR3), which is the thickness direction of the substrate (SUB). The first electrode (DTS) of the driving transistor (DT) may be disposed on one side of the channel layer (DTCH), and the second electrode (DTD) may be disposed on the other side of the channel layer (DTCH). The first electrode (DTS) and the second electrode (DTD) of the driving transistor (DT) may be regions that do not overlap with the gate electrode (DTG) in the third direction (DR3). The first electrode (DTS) and the second electrode (DTD) of the driving transistor (DT) may be regions that have conductivity by doping ions or impurities into a silicon semiconductor.

[0279] Additionally, the active layer (ACT) may further include channel layers (CH1, CH4~CH6) of the first and fourth to sixth transistors (ST1, ST4~ST6), first electrodes (S1, S4~S6), and second electrodes (D1, D4~D6). Each of the channel layers (CH1, CH4~CH6) of the first to sixth transistors (ST1, ST4~ST6) may overlap with the corresponding gate electrode among the gate electrodes (G1, G4~G6) in the third direction (DR3). The first electrodes (S1, S4~S6) and second electrodes (D1, D4~D6) of the first to sixth transistors (ST1~ST6) may be regions that have conductivity by doping ions or impurities into a silicon semiconductor.

[0280] A gate insulating film (130) may be disposed on the active layer (ACT). The gate insulating film (130) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0281] A first gate layer (GTL1) may be disposed on the gate insulating film (130). The first gate layer (GTL1) may include a gate electrode (DTG) of a driving transistor (DT). Additionally, the first gate layer (GTL1) may further include gate electrodes (G1 to G6) of the first to sixth transistors (ST1 to ST6), a first capacitor electrode (CAE1), scan write wires (GWL), scan initialization wires (GIL), scan bias wires (GBL), and light-emitting wires (EL). The first gate layer (GTL1) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0282] A first interlayer insulating film (141) may be disposed on the first gate layer (GTL1). The first interlayer insulating film (141) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0283] A second gate layer (GTL2) may be disposed on the first interlayer insulating film (141). The second gate layer (GTL2) may include a second capacitor electrode (CAE2), a shielding electrode (SHE), a horizontal driving voltage wiring (HVDL), a first horizontal initialization wiring (HVIL), and a second horizontal initialization wiring (HVAIL). The second gate layer (GTL2) may be formed as a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0284] A second interlayer insulating film (142) may be disposed on the second gate layer (GTL2). The second interlayer insulating film (142) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0285] A first data metal layer (DTL1) comprising first to third connecting electrodes (CE1, CE2, CE3), a vertical driving voltage wiring (VVDL), a first vertical initialization wiring (VVIL), and a second vertical initialization wiring (VVAIL) may be disposed on the second interlayer insulating film (142). The first data metal layer (DTL1) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0286] The first connecting electrode (CE1) can be connected to the gate electrode (DTG) of the driving transistor (DT) through a first contact hole (CT1) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The first connecting electrode (CE1) can be connected to the second electrode (D1-2) of the first-second transistor (ST1-2) and the first electrode (S3-1) of the third-first transistor (ST3-1) through a second contact hole (CT2) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). The second connecting electrode (CE2) can be connected to the first electrode (S2) of the second transistor (ST2) through a fourth contact hole (CT4) penetrating the first interlayer insulating film (141) and the second interlayer insulating film (142). The third connecting electrode (CE3) can be connected to the second electrode (D6) of the sixth transistor (ST6) through a seventh contact hole (CT7) that penetrates the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142).

[0287] The vertical driving voltage wiring (VVDL) can be connected to the shielding electrode (SHE) through a third contact hole (CT3) penetrating the second interlayer insulating film (142). The vertical driving voltage wiring (VVDL) can be connected to the horizontal driving voltage wiring (HVIL) through a fifth contact hole (CT5) penetrating the second interlayer insulating film (142). The vertical driving voltage wiring (VVDL) can be connected to the first electrode (S5) of the fifth transistor (ST5) through a sixth contact hole (CT6) penetrating the gate insulating film (130), the first interlayer insulating film (141), and the second interlayer insulating film (142). As a result, a second power supply voltage can be applied to the shielding electrode (SHE), the horizontal driving voltage wiring (HVIL), and the first electrode (S5) of the fifth transistor (ST5).

[0288] A first planarization film (160) may be formed on the first data metal layer (DTL1) to flatten the step difference caused by the active layer (ACT), the first gate layer (GTL1), the second gate layer (GTL2), and the first data metal layer (DTL1). The first planarization film (160) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0289] A second data metal layer (DTL2) may be formed on the first planarization film (160). The second data metal layer (DTL2) may include a fourth connection electrode (CE4), a fifth connection electrode (CE5), first sub-bypass wiring (DETL1), first horizontal power wiring (HPL1), and second horizontal power wiring (HPL2). Additionally, the second data metal layer (DTL2) may further include second data connection wiring (DCL2), first horizontal dummy patterns (HDP1), and second horizontal dummy patterns (HDP2). The second data metal layer (DTL2) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0290] The fourth connecting electrode (CE4) can be connected to the second connecting electrode (CE2) through the tenth contact hole (CT10) penetrating the first flattening film (160). The fifth connecting electrode (CE5) can be connected to the third connecting electrode (CE3) through the eighth contact hole (CT8) penetrating the first flattening film (160). The first horizontal power wiring (HPL1) can be connected to the vertical driving voltage wiring (VVDL) through the twelfth contact hole (CT12) penetrating the first flattening film (160).

[0291] A second flattening film (161) for flattening the step difference may be formed on the second data metal layer (DTL2). The second flattening film (161) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0292] A third data metal layer (DTL3) may be formed on the second planarization film (161). The third data metal layer (DTL3) may include a sixth connection electrode (CE6), second data wiring (DL2), second sub-bypass wiring (DETL2), and first vertical power wiring (VPL1). Additionally, the third data metal layer (DTL3) may further include first data wiring (DL1), third data wiring (DL3), second vertical power wiring (VPL2), first vertical power patterns (VDP1), and second vertical power patterns (VDP2). The third data metal layer (DTL3) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0293] The sixth connecting electrode (CE6) can be connected to the fifth connecting electrode (CE5) through a ninth contact hole (CT9) penetrating the second flattening film (161). The second data wiring (DL2) can be connected to the fourth connecting electrode (CE4) through an eleventh contact hole (CT11) penetrating the second flattening film (161).

[0294] The second sub-bypass wiring (DETL2) can be connected to the first sub-bypass wiring (DETL1) through a second bypass connection hole (TCH2) penetrating the second flattening film (161). Similarly, the second data wiring (DL2) can be connected to the first sub-bypass wiring (DETL1) through a first bypass connection hole (TCH1) penetrating the second flattening film (161).

[0295] Additionally, the second sub-bypass wiring (DETL2) can be connected to the third sub-bypass wiring (DETL3) placed in the seventh display area (DA7) through a third bypass connection hole (TCH3) penetrating the second flattening film (161). The third data wiring (DL3) can be connected to the third sub-bypass wiring (DETL3) placed in the seventh display area (DA7) through a fourth bypass connection hole (TCH4) penetrating the second flattening film (161). The connection between the second sub-bypass wiring (DETL2) and the third sub-bypass wiring (DETL3) placed in the non-display area (NDA), and the connection between the third data wiring (DL3) and the third sub-bypass wiring (DETL3) placed in the non-display area (NDA), will be explained in detail in conjunction with FIG. 32.

[0296] A third flattening film (162) for flattening the step difference may be formed on the third data metal layer (DTL3). The third flattening film (162) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0297] Light-emitting elements (170) and a bank (180) may be disposed on the third planarization film (162). Each of the light-emitting elements (170) may include a pixel electrode (171), an organic light-emitting layer (172), and a common electrode (173). The light-emitting elements (LE) may share the common electrode (173).

[0298] Each pixel electrode (171) of each light-emitting element (170) can be formed on the third planarization film (162). Each pixel electrode (171) of each light-emitting element (LE) can be connected to the sixth connection electrode (CE6) through a pixel contact hole (ANCT) penetrating the third planarization film (162). Each pixel electrode (171) of each light-emitting element (170) can be formed from a highly reflective metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, and a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0299] The bank (180) may be a pixel defining film or a light-emitting part defining film that defines light-emitting parts (EA). The bank (180) may partition the light-emitting parts (EA). Each of the light-emitting parts (EA) represents a region in which a pixel electrode (171), an organic light-emitting layer (172), and a common electrode (173) are sequentially stacked so that holes from the pixel electrode (171) and electrons from the common electrode (173) recombine in the organic light-emitting layer (172) to emit light.

[0300] The bank (180) can be formed to cover the edges of each pixel electrode (171) of the light-emitting elements (170). The bank (180) can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0301] A spacer (SPC) for mounting a mask during the manufacturing process may be placed on the bank (180). The spacer (SPC) may be formed from an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0302] An organic light-emitting layer (172) is formed on the pixel electrode (171) of each of the light-emitting elements (170). The organic light-emitting layer (172) may include an organic material and emit a predetermined color. For example, the organic light-emitting layer (172) may include a hole transporting layer, an organic material layer, and an electron transporting layer.

[0303] A common electrode (173) can be disposed on an organic light-emitting layer (172) and a bank (180). The common electrode (173) can be formed to cover the organic light-emitting layer (172). The common electrode (173) can be formed commonly on the light-emitting parts (EA). A capping layer can be formed on the common electrode (173).

[0304] In the upper light-emitting structure, the common electrode (173) can be formed from a transparent conductive material (TCO) such as ITO or IZO that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode (173) is formed from a semi-transmissive conductive material, the light emission efficiency of each of the light-emitting parts (ELU1, ELU2, ELU3, ELU4) can be increased by the micro cavity.

[0305] An encapsulation layer (TFE) may be formed on the light-emitting elements (170). The encapsulation layer (TFE) may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light-emitting element layer (EML). Additionally, the encapsulation layer (TFE) may include at least one organic film to protect the light-emitting element layer (EML) from foreign substances such as dust.

[0306] Meanwhile, in the embodiments of FIGS. 28 to 31, the display panel (100) is illustrated as including a third data metal layer (DTL3), but the third data metal layer (DTL3) in the display panel (100) may be omitted. In this case, the second data connection lines (DCL2), the first sub-bypass lines (DETL1), the first horizontal power lines (HPL1), the second horizontal power lines (HPL2), the first horizontal dummy patterns (HDP1), or the second horizontal dummy patterns (HDP2) may be included in or omitted from the first data metal layer (DTL1). Additionally, the first data lines (DL1), the second data lines (DL2), the third data lines (DL3), the first data connection lines (DCL1), the second sub-bypass lines (DETL2), the first vertical power lines (VPL1), the second vertical power lines (VPL2), the first vertical dummy patterns (VDP1), and the second vertical dummy patterns (VDP2) can be formed to be included in the second data metal layer (DTL2).

[0307] FIG. 32 is a cross-sectional view showing an example of a display panel cut along GG' and H-H' of FIG. 24.

[0308] Referring to FIG. 32, the first power wiring (PL1) may include a first sub-power wiring (SPL1), a second sub-power wiring (SPL2), and a third sub-power wiring (SPL3).

[0310] The first data metal layer (DTL1) may include a first sub-power wiring (SPL1) and a second power wiring (PL2). The second data metal layer (DTL2) may further include a second sub-power wiring (SPL2), third sub-bypass wirings (DETL3), and a power connection pattern (VCP1). The third data metal layer (DTL3) may further include a third sub-power wiring (SPL3), second sub-bypass wirings (DETL2), a third data wiring (DL3), and a second vertical power wiring (VPL2).

[0311] The power connection pattern (VCP1) can be connected to the second power wiring (VDP2) through the first power connection hole (PCH1) penetrating the first flattening film (160).

[0313] The second sub-bypass wiring (DETL2) can be connected to the third sub-bypass wiring (DETL3) through a third bypass connection hole (TCH3) penetrating the second flattening film (162). Similarly, the third data wiring (DL3) can be connected to the third sub-bypass wiring (DETL3) through a fourth bypass connection hole (TCH4) penetrating the second flattening film (162).

[0314] The second vertical dummy pattern (VDP2) can be connected to the power connection pattern (VCP1) through a second power connection hole (PCH3) penetrating the second flattening film (161). Similarly, the second vertical power wiring (VPL2) can be connected to the power connection pattern (VCP1) through a second power connection hole (PCH2) penetrating the second flattening film (161).

[0315] The adjacent second sub-bypass wiring (DETL2) and third sub-bypass wiring (DETL3) may not overlap each other in the third direction (DR3). That is, by alternately arranging the second sub-bypass wiring (DETL2) and the third sub-bypass wiring (DETL3) in the non-display area (NDA), the width of the non-display area (NDA) can be minimized.

[0316] FIG. 34 is a layout diagram showing a display device according to another embodiment.

[0317] The embodiment of FIG. 34 differs from the embodiment of FIG. 2 only in that the length of the first direction (DR1) of the seventh display area (DA7) is substantially the same as the length of the first direction (DR1) of the second display area (DA2), and the power holes (PH) in the second display area (DA2) and the sixth display area (DA6) are arranged in a Z shape; therefore, a detailed description of the embodiment of FIG. 34 is omitted.

[0318] FIG. 35 is a layout diagram showing a display device according to another embodiment.

[0319] The embodiment of FIG. 35 differs from the embodiment of FIG. 2 only in that power holes (PH) are not placed in the second display area (DA2), and power holes (PH) of the third display area (DA3) and the sixth display area (DA6) are arranged together in a "∨" shape, so a detailed description of the embodiment of FIG. 35 is omitted.

[0320] FIG. 36 is a layout diagram showing a display device according to another embodiment.

[0321] The embodiment of FIG. 36 differs from the embodiment of FIG. 2 only in that the length of the first direction (DR1) of the second display area (DA2) and the length of the first direction (DR1) of the sixth display area (DA6) are increased, power holes (PH) are not placed in the second display area (DA2), and power holes (PH) are arranged repeatedly in an "∧" shape in the sixth display area (DA6). Therefore, a detailed description of the embodiment of FIG. 36 is omitted.

[0322] FIG. 37 is a layout diagram showing a display device according to another embodiment.

[0323] The embodiment of FIG. 37 differs from the embodiment of FIG. 2 only in that the length of the first direction (DR1) of the second display area (DA2) and the length of the first direction (DR1) of the sixth display area (DA6) are increased, and power holes (PH) are not placed in the second display area (DA2) and the sixth display area (DA6); therefore, a detailed description of the embodiment of FIG. 37 is omitted.

[0324] FIG. 38 is a layout diagram showing a display device according to another embodiment.

[0325] The embodiment of FIG. 38 is substantially identical to the length of the first direction (DR1) of the second display area (DA2) and the length of the first direction (DR1) of the sixth display area (DA6), respectively, as well as the length of the first direction (DR1) of the first display area (DA1), the length of the first direction (DR1) of the third display area (DA3), the length of the first direction (DR1) of the fourth display area (DA5), and the length of the first direction (DR1) of the sixth display area (DA6), and differs from the embodiment of FIG. 2 only in that the power holes (PH) in the second display area (DA2), the third display area (DA3), the fifth display area (DA5), and the sixth display area (DA6) are arranged in a "∨" shape, so a detailed description of the embodiment of FIG. 38 is omitted.

[0326] Meanwhile, in FIGS. 34 to 38, the power holes (PH) may be arranged in shapes other than "∨" within the designable range of those skilled in the art.

[0327] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0328] 10: Display device 100: Display panel 200: Display driving circuit 300: Circuit board

Claims

Claim 1 delete Claim 2 A display area including subpixels that display a hole and an image; a plurality of first data lines located in the display area, disposed on one side of the hole in a first direction, and extending in a second direction intersecting the first direction; a plurality of second data lines located in the display area, disposed on the other side of the hole in the first direction, and extending in the second direction; and a plurality of bypass lines that bypass the hole in the display area and respectively connect the first data lines and the second data lines, wherein each of the plurality of bypass lines comprises: a first sub-bypass line extending in the first direction and connected to one of the first data lines among the plurality of first data lines; and a second sub-bypass line extending in the second direction and connected to the first sub-bypass line. A display device further comprising: a third sub-bypass wiring extending in the first direction and connecting the second sub-bypass wiring and one of the plurality of second data wirings; a plurality of first horizontal power wirings extending in the first direction in the display area and to which a first power voltage is applied; a plurality of second horizontal power wirings extending in the first direction in the display area and to which a second power voltage higher than the first power voltage is applied; and a first vertical power wiring extending in the second direction in the display area and disposed apart from one end of the second sub-bypass wiring. Claim 3 In claim 2, the first vertical power wiring is a display device connected to any one of the plurality of first horizontal power wirings. Claim 4 In claim 2, the first separation portion in which the second sub-bypass wiring of the first bypass wiring and the first vertical power wiring are separated among the plurality of bypass wirings overlaps with one of the second horizontal power wirings among the plurality of second horizontal power wirings. Claim 5 A display device according to claim 4, wherein the second sub-bypass wiring of the first bypass wiring and the first vertical power wiring comprise a first wiring portion having a first width; and a second wiring portion having a second width greater than the first width, and the first separation portion is defined as a gap between the first wiring portion of the second sub-bypass wiring of the first bypass wiring and the first wiring portion of the first vertical power wiring. Claim 6 In claim 4, the second separation portion in which the second sub-bypass wiring of the second bypass wiring and the first vertical power wiring are separated among the plurality of bypass wirings does not overlap with the plurality of second horizontal power wirings. Claim 7 In claim 6, the second sub-bypass wiring of the second bypass wiring and the first vertical power wiring comprise a first wiring section having a first width; and a second wiring section having a second width greater than the first width, in a display device. Claim 8 A display device according to claim 7, wherein the second separation portion is defined as a gap between the first wiring portion of the second sub-bypass wiring of the second bypass wiring and the second wiring portion of the first vertical power wiring, or a gap between the second wiring portion of the second sub-bypass wiring and the first wiring portion of the first vertical power wiring. Claim 9 In claim 7, the second separation portion is a display device defined as a gap between the second wiring portion of the second sub-bypass wiring of the second bypass wiring and the second wiring portion of the first vertical power wiring. Claim 10 A display device according to claim 2, further comprising a vertical dummy pattern extending in the second direction from the display area and positioned apart from the other end of the second sub-bypass wiring. Claim 11 A display device according to claim 10, further comprising a second power line disposed in a non-display area surrounding the display area and to which the second power voltage is applied, wherein the vertical dummy pattern is connected to the second power line in the non-display area. Claim 12 A display device according to claim 11, wherein the second sub-bypass lines and third sub-bypass lines of some of the bypass lines among the plurality of bypass lines are placed in the display area, and the second sub-bypass lines and third sub-bypass lines of the remaining bypass lines are placed in the non-display area. Claim 13 A display device according to claim 12, further comprising a first power line to which the first power voltage is applied, which is disposed in a non-display area disposed around the display area, and the second sub-bypass lines and third sub-bypass lines of the remaining bypass lines are disposed between the first power line and the second power line. Claim 14 In claim 12, among the second sub-bypass lines and third sub-bypass lines of the remaining bypass lines, the second sub-bypass line and the third sub-bypass line that are adjacent to each other are a display device placed on different layers. Claim 15 A display device according to claim 2, further comprising an optical device disposed in the hole and detecting light incident through the hole. Claim 16 A display device according to claim 2, further comprising a plurality of first horizontal dummy patterns extending in the first direction from the display area and positioned apart from one end of the first sub-bypass wiring. Claim 17 In claim 16, the first horizontal dummy patterns are each connected to the first vertical power wiring through the first power holes. Claim 18 In claim 17, the first power holes are a display device arranged in the second direction. Claim 19 In claim 17, the first power holes are a display device that overlaps with the center of the hole in the second direction. Claim 20 A display device according to claim 2, further comprising a plurality of second horizontal dummy patterns extending in the first direction from the display area and positioned apart from one end of the third sub-bypass wiring. Claim 21 A display device according to claim 20, further comprising a second vertical power line extending in the second direction in the display area, wherein the second horizontal dummy patterns are connected to the second vertical power line through second power holes. Claim 22 In claim 21, the second power holes are a display device arranged in the second direction. Claim 23 In claim 21, the second power holes are a display device that overlaps with the center of the hole in the second direction. Claim 24 A display device according to claim 21, wherein the first vertical power wiring receives a first power voltage, and the second vertical power wiring receives a second power voltage higher than the first power voltage. Claim 25 A display area including subpixels that display a hole and an image; a plurality of first data lines located in the display area, disposed on one side of the hole in a first direction, and extending in a second direction intersecting the first direction; a plurality of second data lines located in the display area, disposed on the other side of the hole in the first direction, and extending in the second direction; and a plurality of bypass lines that bypass the hole in the display area and respectively connect the first data lines and the second data lines, wherein each of the plurality of bypass lines includes: a first sub-bypass line extending in the first direction and connected to one of the first data lines among the plurality of first data lines; a second sub-bypass line extending in the second direction and connected to the first sub-bypass line; and a third sub-bypass line extending in the first direction and connecting the second sub-bypass line and one of the second data lines among the plurality of second data lines, and a plurality of active patterns; and at least one insulating film disposed on the plurality of active patterns. A display device further comprising an exposure hole that penetrates at least one insulating film to expose one of the plurality of active patterns. Claim 26 In claim 25, a display device further comprising a dummy pattern disposed on the active pattern in the exposure hole. Claim 27 In claim 26, the dummy pattern is a display device positioned apart from the sidewall of the at least one insulating film in the exposed hole. Claim 28 In claim 26, the active pattern is a display device disposed between the hole and the subpixel. Claim 29 In claim 26, the active pattern is a display device placed in a non-display area surrounding the display area. Claim 30 In claim 29, a display device wherein some of the bypass lines among the plurality of bypass lines have second sub-bypass lines and third sub-bypass lines placed in the display area, and the remaining bypass lines have second sub-bypass lines and third sub-bypass lines placed in the non-display area, and the active pattern is placed between adjacent second sub-bypass lines and third sub-bypass lines among the remaining bypass lines. Claim 31 A plurality of first data lines extending in a second direction intersecting a first direction; a plurality of second data lines extending in the second direction; a plurality of bypass lines connecting the first data lines and the second data lines, respectively; a plurality of first horizontal power lines extending in the first direction and to which a first power voltage is applied; and a plurality of vertical power lines extending in the second direction and to which a second power voltage is applied, wherein each of the plurality of bypass lines comprises: a first sub-bypass line extending in the first direction and connected to one of the first data lines among the plurality of first data lines; and a second sub-bypass line extending in the second direction and connected to the first sub-bypass line. A display device that includes a third sub-bypass wiring extending in the first direction and connecting the second sub-bypass wiring and one of the second data wirings, wherein the first separation portion in which the second sub-bypass wiring of the first bypass wiring among the plurality of bypass wirings and one of the vertical power wirings are separated overlaps with one of the first horizontal power wirings among the plurality of first horizontal power wirings. Claim 32 In claim 31, a display device in which the second sub-bypass wiring of the second bypass wiring among the plurality of bypass wirings and another vertical power wiring among the vertical power wirings are spaced apart, such that the second separation portion does not overlap with the plurality of first horizontal power wirings. Claim 33 A display device according to claim 31, further comprising a plurality of second horizontal power lines extending in the first direction and to which a second power voltage lower than the first power voltage is applied, wherein the vertical power line is connected to any one of the plurality of second horizontal power lines. Claim 34 A display device comprising: a plurality of first data lines extending in a second direction intersecting a first direction; a plurality of second data lines extending in the second direction; a plurality of bypass lines connecting the first data lines and the second data lines, respectively; a plurality of horizontal power lines extending in the first direction and to which a first power voltage is applied; and a plurality of vertical power lines extending in the second direction and to which a second power voltage is applied, wherein each of the plurality of bypass lines includes: a first sub-bypass line extending in the first direction and connected to one of the first data lines among the plurality of first data lines; a second sub-bypass line extending in the second direction and connected to the first sub-bypass line; and a third sub-bypass line extending in the first direction and connecting the second sub-bypass line and one of the second data lines among the plurality of second data lines, wherein a first separation portion in which the second sub-bypass line of the first bypass line among the plurality of bypass lines and one of the vertical power lines among the vertical power lines are separated does not overlap with the plurality of horizontal power lines. Claim 35 In claim 34, the second separation portion in which the second sub-bypass wiring of the second bypass wiring among the plurality of bypass wirings and another vertical power wiring among the vertical power wirings are spaced apart overlaps with one of the horizontal power wirings among the plurality of horizontal power wirings.

Images