A photoelectronic semiconductor component and a method for manufacturing one or more photoelectronic semiconductor components

Abstract

The present invention relates to an optoelectronic semiconductor component (16), wherein the optoelectronic semiconductor component is - A layer stack (9) comprising one or more side surfaces (9A), a first main surface (9B) and a second main surface (9C), - A first contact means (12) disposed on the first main surface (9B), provided for electrical contact of the first semiconductor region (4) of the layer stack (9), - A second contact means (17) disposed on the second main surface (9C), which is provided for electrical contact of the second semiconductor region (5) of the layer stack (9) and is radiation-transmittable, - An electrically conductive edge layer (11) disposed on the layer stack (9), extending from the second contact means (17) across the side surface (9A) to the first main surface (9B), and - Includes a first dielectric layer (10) disposed between the edge layer (11) and the layer stack (9), wherein the second main surface (9C) is not covered by the first dielectric layer (10). In addition, the present invention relates to a method for manufacturing one or more optoelectronic semiconductor components.

Description

Technology Field

[0001] The present invention relates to an optoelectronic semiconductor component and a method for manufacturing the same. For example, a flip chip is considered as an optoelectronic semiconductor component. Background Technology

[0002] In the case of flip chips, charge carriers of the first and second conductivity types are typically supplied and distributed beneath the semiconductor layer rather than on the outer surface of the flip chip. In this case, rewiring within the component is required to make contact of the semiconductor layer over the active area. Flip chips using etched blind holes to make the semiconductor layer electrically accessible are known. However, this causes a reduction in the area efficiency of the flip chip. The problem to be solved

[0003] The objective of the present invention is to provide an area-optimized optoelectronic semiconductor component. Another objective of the present invention is to provide a method for manufacturing an area-optimized optoelectronic semiconductor component. means of solving the problem

[0004] These problems are solved particularly by an optoelectronic semiconductor component having the features of the independent claims and a method for manufacturing the optoelectronic semiconductor component.

[0005] According to one or more embodiments of an optoelectronic semiconductor component, such an optoelectronic semiconductor component comprises a layer stack including a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type, and an active region disposed between the first semiconductor region and the second semiconductor region. For example, the first semiconductor region may be considered a p-doped region, and the second semiconductor region may be considered an n-doped region. Furthermore, the active region is preferably provided to generate electromagnetic radiation.

[0006] Furthermore, the layer stack comprises one or more side surfaces that restrict the layer stack in a lateral direction, a first main surface, and a second main surface facing the first main surface, wherein the first and second main surfaces are each positioned in a transverse direction, which is preferably neither parallel nor perpendicular to the side surface. In particular, the first main surface is considered to be a surface of the layer stack positioned on the side of a first semiconductor region, and the second main surface is considered to be a surface of the layer stack positioned on the side of a second semiconductor region. Preferably, most of the generated radiation is emitted from the semiconductor component on the side of the second main surface.

[0007] The thickest layer of the optoelectronic semiconductor component can be considered as a layer stack. For example, the layer stack may account for 50% of the thickness of the optoelectronic semiconductor component. In this case, the thickness refers to the length in the direction perpendicular to, for example, the main extension plane of the semiconductor component.

[0008] Additionally, the optoelectronic semiconductor component comprises a first contact means disposed on a first main surface provided for electrical contact of a first semiconductor region, a second contact means disposed on a second main surface provided for electrical contact of a second semiconductor region and having radiation transparency, and an electrically conductive edge layer disposed on a layer stack extending from the second contact means to the first main surface across a side surface.

[0009] The edge layer can be positioned in a lateral direction, that is, on one or more lateral surfaces, at least locally behind the layer stack.

[0010] Furthermore, the edge layer may include an end region disposed on the second main surface, said end region having a lateral length corresponding to the thickness of the electrically conductive edge layer. In this case, the lateral length corresponding to the thickness is understood not only as an equal value, but also as a value up to twice as large, particularly up to 1.5 times larger. For example, the equal value is achieved when the edge layer and the second main surface are at a right angle, whereas larger values ​​are taken at smaller angles, particularly at angles greater than 30° and less than 90°.

[0011] For example, the edge layer can be formed on the second main surface without kink or curvature. In other words, the edge layer can be positioned to conform to one or more side surfaces.

[0012] In particular, the edge layer enables electrical contact of the second semiconductor region on the side of the first main surface.

[0013] Preferably, the second semiconductor region is positioned on the front of the optoelectronic semiconductor component provided for radiation emission, and the first semiconductor region is positioned on the rear of the optoelectronic semiconductor component facing the front.

[0014] Furthermore, the optoelectronic semiconductor component includes a first dielectric layer disposed between an edge layer and a layer stack, wherein the second main surface is not covered by the first dielectric layer. The first dielectric layer is used, in particular, for electrical insulation of the pn-transition region of the active region. The first dielectric layer may consist of only a single layer. Alternatively, the first dielectric layer may include a plurality of layers, in particular, with alternating refractive indices. In such a case, the first dielectric layer may additionally have a mirror function.

[0015] For the materials of the first dielectric layer, oxide and nitride compounds such as AlxOy, SiOx, SixNy, NbOx, TiOx, HfOx, TaOx, AlxNy, and TixNy, and organic polymers such as parylene, BCB, silicone, siloxane, photoresist, spin-on glass, organic-inorganic hybrid material, epoxide, and acrylic are considered.

[0016] The first dielectric layer can be positioned in a lateral direction, that is, on one or more lateral surfaces, at least locally behind the layer stack.

[0017] Furthermore, the first dielectric layer may include an end region disposed on the second main surface, said end region having a lateral length corresponding to the thickness of the first dielectric layer. In this case, the lateral length corresponding to the thickness is understood not only as an equal value but also as a value up to twice as large, particularly up to 1.5 times larger. For example, the equal value is achieved when the first dielectric layer and the second main surface are perpendicular, whereas larger values ​​are taken at smaller angles, particularly at angles greater than 30° and less than 90°.

[0018] For example, the first dielectric layer can be formed on the second main surface without kink or curvature. In other words, the first dielectric layer can be positioned to conform to one or more side surfaces.

[0019] According to one or more embodiments, the second contact means contacts the first dielectric layer.

[0020] The active region may include a sequence of single layers, wherein a quantum well structure, in particular a single quantum well (SQW) or a multiple quantum well (MQW) structure, is formed by said single layers.

[0021] Furthermore, the first and second semiconductor regions may include one or more semiconductor layers. For the semiconductor layers of the semiconductor regions, materials based on nitride-, phosphide-, or arsenide-compound semiconductors are considered. In this context, “based on nitride-, phosphide-, or arsenide-compound semiconductors” means that the semiconductor layers are Al n Ga m In 1-n-m N, Al n Ga m In 1-n-m P or Al n Ga m In 1-n-m This implies that it contains As, wherein 0 ≤ n ≤ 1, 0 ≤ m ≤ 1, and n+m ≤ 1. In this case, such a material does not necessarily have to have a mathematically precise composition according to the above chemical formula. Rather, the material comprises one or more dopants and Al n Ga m In 1-n-m N- , Al n Ga m In 1-n-m P- or Al n Ga m In 1-n-mIt may include additional components that do not substantially alter the characteristic physical properties of the As-material. However, for the sake of simplification, even where the major components may be partially replaced by small amounts of other materials, the above formula contains only the major components of the crystal lattice (Al, Ga, In, P, or As).

[0022] According to one or more embodiments, the second main surface is not substantially covered by the edge layer, that is, within the range of ordinary manufacturing tolerances. Preferably, the edge layer does not protrude over the second main surface on the side of the second main surface facing away from the layer stack. In other words, the edge layer preferably does not protrude over the second main surface in a vertical direction. Particularly preferably, the edge layer terminates coplanar with the second main surface. This may be caused by manufacturing in cases where the edge layer is provided onto the layer stack prior to the exposure of the second main surface and is removed together upon exposure.

[0023] According to one or more embodiments, the second semiconductor region comprises a contact layer formed from a semiconductor material disposed on a second main surface, and a second contact means is at least partially directly disposed on the contact layer. In particular, a highly doped semiconductor layer is considered as the contact layer.

[0024] In one preferred design example, the second contact means comprises one or more of the following materials, or is composed of one or more of the following materials: TCO, metal, semiconductor, graphene.

[0025] “TCO” is understood as transparent conductive oxide (abbreviated as “TCO”). TCOs are transparent conductive materials, generally metal oxides such as, for example, zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide, and / or indium tin oxide (ITO). Along with binary metal-oxygen compounds such as, for example, ZnO, SnO2, or In2O3, there are, for example, Zn2SnO4, CdSnO3, ZnSnO3, MgIn2O4, GaInO3, Zn2In2O5, or In4Sn3O. 12 Ternary metal-oxygen compounds such as those mentioned above, or mixtures of different transparent conductive oxides, also belong to the group of TCOs. Furthermore, TCOs do not necessarily correspond to stoichiometric compositions and may be p- or n-doped.

[0026] Preferably, a layer provided on the second main surface is considered as the second contact means. The second contact means may be a uniform layer, particularly if formed from TCO, or a structured layer, for example, if formed from a metal. For example, the second contact means may be designed as a metal mesh or an inverted metal mesh.

[0027] In particular, the second main surface is covered by the second contact means by at least 20%, preferably at least 50%, and particularly preferably at least 80%.

[0028] According to one or more embodiments, one or more side surfaces of a layer stack are covered by at least most of an edge layer. Preferably, all side surfaces of the layer stack are completely covered by an edge layer.

[0029] In one preferred design example, the edge layer forms a mirror coating of the layer stack. This allows radiation generated by the active zone to preferably be deflected toward the second main surface. In this case, the edge layer may include a metal or be composed of a metal, wherein Rh, Al, Cr, Ti, Pt, W, Au, and Ni are particularly considered as metals.

[0030] According to one or more embodiments, the edge layer comprises one or more of the following materials or is composed of one or more of the following materials: TCO, metal, graphene.

[0031] According to one or more embodiments, an optoelectronic semiconductor component can be electrically connected from the outside by a first contact means and an edge layer on the side of a first main surface. In this case, the first main surface is partially covered by an edge layer, wherein the edge layer is used as a second conductive type contact pad. In this case, the edge layer and the second contact means may be formed from different materials. In particular, the first contact means comprises a metal or a metal compound, or is composed of a metal or a metal compound.

[0032] Additionally, the optoelectronic semiconductor component may include a third contact means disposed on a first main surface. The third contact means is preferably used as a second conductive type contact pad and is electrically conductively connected to an edge layer. The edge layer and the third contact means may be formed from different materials. In particular, the third contact means may include a metal or a metal compound, or be composed of a metal or a metal compound. By means of the first contact means and the third contact means, the optoelectronic semiconductor component can be electrically connected from the outside on the side of the first main surface.

[0033] Since the means for electrical contact between the first and second semiconductor regions are positioned outside the layer stack, area is not “consumed” for the contact, and thus area efficiency can be improved. Furthermore, the semiconductor component becomes scalable through contact on the outer side. In particular, the semiconductor component does not include plated-through holes.

[0034] Furthermore, semiconductor components may not contain carriers.

[0035] In one possible variant, the optoelectronic semiconductor component comprises a second dielectric layer disposed on an edge layer, wherein the second dielectric layer electrically insulates the edge layer from the outside at a first main surface. Furthermore, the edge layer may be electrically insulated from the outside by the second dielectric layer at one or more side surfaces. For the second dielectric layer, materials mentioned particularly for the first dielectric layer are considered.

[0036] According to one or more embodiments, the optoelectronic semiconductor component can be electrically connected from the outside on two sides facing each other by first and second contact means. In this case, the second contact means is used as a second conductive type contact pad.

[0037] According to one preferred embodiment, the layer stack is formed in a mesa-like shape, wherein the second main surface is larger than the first main surface. In this case, radiation emission occurs particularly on the side of the larger main surface.

[0038] The second main surface may be formed flat. Alternatively, the second semiconductor region may include structural elements on the second main surface, for example, to increase radiation decoupling, or may be roughened. Furthermore, the semiconductor component may include a decoupling structure disposed on the second main surface, particularly to increase radiation decoupling.

[0039] Various design examples are considered for the first contact means used as a first conductive type contact pad, and for the edge layer or third contact means used as a second conductive type contact pad.

[0040] For example, the first contact means may be positioned centrally on the first main surface and surrounded on all sides by the edge layer or the third contact means. Additionally, it is possible for the first contact means to be positioned on the edge side and surrounded only partially on the periphery side by the edge layer or the third contact means. Furthermore, it is possible for the first and third contact means to be positioned side by side on the first main surface. At least a first dielectric layer is located between them for electrical insulation. Additionally, a first and second dielectric layer may be located between them for electrical insulation.

[0041] The method described below is suitable for manufacturing one or multiple optoelectronic semiconductor components of the type mentioned above. Accordingly, features described in relation to the semiconductor component can also be used for the above method, and conversely, features described in relation to the above method can also be used for the semiconductor component.

[0042] According to one or more embodiments of a method for manufacturing one or more optoelectronic semiconductor components of the type mentioned above, such a method is:

[0043] - A step of providing a semiconductor wafer comprising a carrier and a semiconductor layer sequence disposed on the carrier,

[0044] - A step of manufacturing one or more layer stacks by creating one or more recesses within the semiconductor wafer, starting from the side of the semiconductor layer sequence facing away from the carrier,

[0045] - A step of providing a first dielectric layer on the semiconductor wafer such that the layer stack is covered by the first dielectric layer,

[0046] - A step of providing an electrically conductive layer provided to form an edge layer on the first dielectric layer,

[0047] - Includes the step of exposing the second main surface of the layer stack (wherein the regions of the first dielectric layer and the second semiconductor region are removed in the same step).

[0048] Preferably, the method steps are carried out in the order presented. This means, in particular, that the edge layer is provided on the first dielectric layer prior to the exposure of the second main surface. Subsequently, regions of the edge layer are removed upon the exposure of the second main surface. In particular, regions of the edge layer may be removed upon the exposure of the second main surface such that the edge layer does not protrude above the second main surface on the side of the second main surface facing away from the layer stack, or terminates coplanar with such second main surface.

[0049] Preferably, as a carrier, a growth substrate upon which a semiconductor layer sequence is epitaxially grown is considered. In this case, a second semiconductor region is grown particularly on the carrier, and a first semiconductor region is grown on the second semiconductor region. When the second main surface is exposed, regions of the second semiconductor region are removed particularly.

[0050] In one preferred design embodiment of the method according to the present invention, a plurality of layer stacks are individualized by a second main surface exposure step. This occurs particularly by a semiconductor wafer thinning from a carrier side to one or more recesses.

[0051] Preferably, the exposure of the second main surface is carried out by a polishing and / or etching and / or laser lift-off method.

[0052] The method or structure of the semiconductor component according to the present invention provides contact of a second semiconductor region without using conventional photolithography process steps.

[0053] Optoelectronic semiconductor components are particularly suitable for video walls, projectors, and high-performance components. Brief explanation of the drawing

[0054] Other advantages, preferred embodiments, and improvements are given from the embodiments described below in conjunction with the drawings. FIGS. 1 to 4 and FIGS. 7 to 11a are schematic cross-sectional views of different steps of a method for manufacturing an optoelectronic semiconductor component according to a first embodiment, and FIG. 11b is a schematic cross-sectional view of an optoelectronic semiconductor component according to a first embodiment, and FIG. 5 is a schematic cross-sectional view of one step of a method for manufacturing an optoelectronic semiconductor component according to a second embodiment, and FIG. 6 is a schematic cross-sectional view of one step of a method for manufacturing an optoelectronic semiconductor component according to a third embodiment, and FIG. 12 is a schematic cross-sectional view of one step of a method for manufacturing an optoelectronic semiconductor component according to a fourth embodiment and a schematic cross-sectional view of an optoelectronic semiconductor component according to a fourth embodiment, and FIG. 13 is a schematic cross-sectional view of one step of a method for manufacturing an optoelectronic semiconductor component according to a fifth embodiment and a schematic cross-sectional view of an optoelectronic semiconductor component according to a fifth embodiment. FIGS. 14 to 16 are schematic plan views looking at the rear of optoelectronic semiconductor components according to different embodiments, and FIG. 17a is a schematic cross-sectional view of one step of a method for manufacturing an optoelectronic semiconductor component according to a sixth embodiment and a schematic cross-sectional view of an optoelectronic semiconductor component according to a sixth embodiment, and FIG. 17b is a schematic plan view looking at the rear of an optoelectronic semiconductor component according to a sixth embodiment, and FIG. 18a is a schematic cross-sectional view of one step of a method for manufacturing a photoelectronic semiconductor component according to the seventh embodiment and a schematic cross-sectional view of a photoelectronic semiconductor component according to the seventh embodiment, and FIG. 18b is a schematic plan view looking at the bottom surface of a photoelectronic semiconductor component according to the seventh embodiment. Specific details for implementing the invention

[0055] In the embodiments and drawings, identical, identical types, or identically functioning elements may be provided with the same reference numerals. The illustrated elements and their relative sizes are not necessarily considered to be in scale; rather, individual elements may be depicted larger for better illustration and / or better understanding.

[0056] FIG. 1 illustrates the starting step of a method for manufacturing an optoelectronic semiconductor component according to a first embodiment, wherein a semiconductor wafer (1) is provided, comprising a semiconductor layer sequence (2) and a carrier (3) on which the semiconductor layer sequence (2) is provided. The semiconductor layer sequence (2) includes a first semiconductor region (4) of a first conductive type, a second semiconductor region (5) of a second conductive type, and an active region (6) disposed between the first semiconductor region (4) and the second semiconductor region (5). The first semiconductor region (4) is disposed behind the second semiconductor region (5) in a vertical direction (V). For example, the first semiconductor region (4) is considered to be a p-doped region, and the second semiconductor region (5) is considered to be an n-doped region. Furthermore, the carrier (3) is preferably a growth substrate upon which the semiconductor layer sequence (2) is epitaxially grown. Additionally, the semiconductor wafer (1) includes a contact layer (7) for electrical contact of the first semiconductor region (4), said contact layer is disposed on the first semiconductor region (4). The contact layer (7) may be formed from TCO and / or metal.

[0057] With respect to the semiconductor regions (4, 5) and active region (6) and the semiconductor layers contained therein, metals based on nitride-, phosphide-, or arsenide-compound semiconductors are considered, as already mentioned further above. In this context, “based on nitride-, phosphide-, or arsenide-compound semiconductors” means that the semiconductor regions (4, 5) and active region (6) or the semiconductor layers contained therein are Al n Ga m In 1-n-m N, Al n Ga m In 1-n-m P or Al n Ga m In 1-n-mIt means that As is included, where 0 ≤ n ≤ 1, 0 ≤ m ≤ 1 and n+m ≤ 1.

[0058] FIG. 2 illustrates the next method step in which the semiconductor wafer (1) is structured to create layer stacks (9). In particular, to manufacture the layer stack (9), a recess (8) is inserted into the semiconductor wafer (1) starting from the side of the semiconductor layer sequence (2) facing away from the carrier (3). In a plan view facing the semiconductor layer sequence (2), the recess (8) may be formed in a frame-shaped manner. Additionally, the recess (8) may have a cross-section that tapers in the direction of the carrier (3). Thus, the layer stack (9) preferably has a mesa-shaped shape. The recess (8) preferably extends at least into the contact layer (5A) of the second semiconductor region (5).

[0059] FIG. 3 illustrates the next method step in which a first dielectric layer (10) is provided on the semiconductor wafer (1) on the side of the semiconductor layer sequence (2) facing away from the carrier (3), wherein the layer stack (9) is covered by the first dielectric layer (10). Preferably, the first dielectric layer (10) is provided over the entire surface area of ​​the semiconductor wafer (1), so that the first dielectric layer restricts the semiconductor wafer (1) to the outside on the side of the semiconductor layer sequence (2) facing away from the carrier (3).

[0060] In particular, the side surfaces (9A) of the layer stack (9) that limit the layer stack (9) in a lateral direction are completely covered by the first dielectric layer (10). In this case, “lateral direction” refers to the lateral directions (L) arranged in a transverse direction with respect to the vertical direction (V), particularly in the vertical direction. Furthermore, the first main surface (9B) of the layer stack (9) arranged transversely with respect to the side surfaces (9A) is completely covered by the first dielectric layer (10).

[0061] Furthermore, the dielectric layer (10) is placed on the bottom surface (8A) of the recess (9).

[0062] FIG. 4a illustrates another method step in which an electrically conductive layer (11A) is provided on the first dielectric layer (10). In particular, the electrically conductive layer (11A) is provided over the entire area of ​​the dielectric layer (10) and subsequently opened, thereby forming an edge layer (11) disposed on the side surfaces (9A) and partially on the first main surface (9B).

[0063] As illustrated in FIG. 4b, the dielectric layer (10) is also opened, so that consequently the first main surface (9B) includes an uncovered area. Within the uncovered area, a first contact means (12) provided for electrical contact of the first semiconductor region (4) is disposed. In particular, the first contact means (12) is formed from a metal or a metal compound and is used as a first conductive type contact pad.

[0064] FIG. 5 illustrates a method step of a method according to a second embodiment in which the dielectric layer (10) is opened prior to the provision of the electrically conductive layer (11A). The electrically conductive layer (11A) is provided over the entire area on the semiconductor wafer (1) and is placed directly on the first main surface (9B) within the open area. Subsequently, the electrically conductive layer (11A) is structured so that an edge layer (11) placed on the side surfaces (9A) of the layer stack (9) and a first contact means (12) placed on the first main surface (9B) are formed from the electrically conductive layer.

[0065] The electrically conductive layer (11A) may be formed as a single layer or a multilayer and may include TCO and / or metal and / or graphene. Correspondingly, the edge layer (11) and the first contact means (12) may also be formed as a single layer or a multilayer and may include TCO and / or metal and / or graphene.

[0066] FIG. 6 shows a method step of a method according to a third embodiment in which a filler (13) for stabilizing the semiconductor wafer (1) is placed within the recesses (8) after the manufacture of the edge layer (11). For the filler (13), for example, a plastic material is considered.

[0067] FIG. 7 illustrates another method step in which an intermediate carrier (14), such as a plastic carrier, is disposed on the side of a composite material comprising the semiconductor wafer (1) and additionally provided layers (10, 11, 12) facing the carrier side, and the intermediate carrier is fixed to the composite material by a connecting layer (15), such as a film that can be released by UV radiation or heat. After the intermediate carrier (14) is provided, the carrier (3) can be removed.

[0068] FIG. 8 illustrates the next method step in which the second main surface (9C) of the layer stack (9) facing the first main surface (9B) is exposed. In this case, particularly, regions of the second semiconductor region (5) are removed up to the contact layer (5A). In this case, regions of the first dielectric layer (10) and the edge layer (11) disposed within the recess (8) are also removed together, so that, in particular, the first dielectric layer (10) and the edge layer (11) end in the same plane as the second main surface (9C), or consequently, the edge layer (11) does not protrude above the second main surface (9C) from the side of the second main surface (9C) facing away from the layer stack (9).

[0069] The semiconductor wafer (1) is thinned in the vertical direction (V) to at least the bottom surface (8A) of the recess (8) (see FIG. 3 in relation thereto), so that, as a result, the layer stacks (9) connected by the second semiconductor region (5) are separated from each other or individualized.

[0070] Preferably, the exposure of the second main surface (9C) is carried out by polishing and / or etching and / or laser lift-off methods.

[0071] FIG. 9 illustrates another method step in which a second contact means (17) is provided for electrical contact of the second semiconductor region (5) on the second main surface (9C). In this case, the second contact means (17) protrudes laterally over the second main surface (9C), so that the second contact means (17) consequently contacts the first dielectric layer (10) and the edge layer (11).

[0072] The second contact means (17) may include one or more of the following materials, or is composed of one or more of the following materials: TCO, metal, semiconductor, graphene. Preferably, the second contact means (17) is considered to be a uniform layer or a structured layer provided on the second main surface (9C). In particular, the second main surface is covered by the second contact means (9C) by at least 20%, preferably at least 50%, and particularly preferably at least 80%.

[0073] FIG. 10 shows another method step in which the intermediate carrier (14) is partially or completely released by the action of, for example, UV radiation or heat (indicated by arrows), so that as a result, at least some of the optoelectronic semiconductor components (16) are no longer attached to the intermediate carrier (14) or are only weakly attached.

[0074] FIG. 11a shows another method step in which the optoelectronic semiconductor components (16) are transported by a transport device (18), for example, a suction nozzle or a stamp.

[0075] FIG. 11b shows an optoelectronic semiconductor component (16) that can be manufactured by the method according to the first or third embodiment. Accordingly, the features described in relation to the method can also be used for the optoelectronic semiconductor component (16), and conversely, the features described in relation to the optoelectronic semiconductor component (16) can also be used for the method.

[0076] The above-described optoelectronic semiconductor component (16) comprises a layer stack (9) including a first semiconductor region (4) of a first conductive type, a second semiconductor region (5) of a second conductive type, and an active region (6) disposed between the first semiconductor region and the second semiconductor region, wherein the active region is provided to emit electromagnetic radiation, particularly within the visible light, ultraviolet or infrared spectral range. Furthermore, the layer stack (9) comprises a plurality of side surfaces (9A) that limit the layer stack (9) in a lateral direction, a first main surface (9B), and a second main surface (9C) facing the first main surface (9B), wherein the first and second main surfaces (9B, 9C) are each disposed with respect to the side surface (9A), particularly in a lateral direction rather than a vertical direction.

[0077] Additionally, the optoelectronic semiconductor component (16) includes a first contact means (12) disposed adjacent to or on the first main surface (9B) provided for electrical contact of the first semiconductor region (4), and a second contact means (17) disposed adjacent to or on the second main surface (9C) provided for electrical contact of the second semiconductor region (5) and having radiation transparency.

[0078] Furthermore, the optoelectronic semiconductor component (16) comprises an electrically conductive edge layer (11) disposed on the layer stack (9), extending from the second contact means (17) across the side surfaces (9A) to the first main surface (9B). The edge layer (11) comprises an end region (11B) disposed on the second main surface (9C), and the end region has a lateral length (b1) corresponding to the thickness (d1) of the electrically conductive edge layer (11). In this case, the lateral length (b1) corresponding to the thickness (d1) is understood not only as the same value but also as a value up to twice as large, particularly up to 1.5 times larger. For example, the same value is achieved when the edge layer (11) and the second main surface (9C) are at a right angle, whereas larger values ​​are taken at smaller angles, particularly at angles greater than 30° and less than 90°.

[0079] For example, the edge layer (11) can be formed on the second main surface (9C) without kink or curvature. In other words, the edge layer (11) can be positioned to conform to the side surfaces (9A).

[0080] Preferably, the edge layer (11) forms a mirror coating of the layer stack (9). This allows radiation generated by the active zone (6) to be preferably deflected toward the second main surface (9C). In this case, the edge layer (11) may preferably contain a metal or be composed of a metal, wherein Rh, Al, Cr, Ti, Pt, W, Au, and Ni are particularly considered as metals.

[0081] Furthermore, the above-described optoelectronic semiconductor component (16) includes a first dielectric layer (10) disposed between the edge layer (11) and the layer stack (9), wherein the second main surface (9C) is not covered by the first dielectric layer (10).

[0082] Preferably, all side surfaces (9A) of the layer stack (9) are completely covered by the dielectric layer (10) and the edge layer (11).

[0083] The first dielectric layer (10) comprises an end region (10A) disposed on the second main surface (9C), and the end region has a lateral length (b2) corresponding to the thickness (d2) of the first dielectric layer (10). In this case, the lateral length (b2) corresponding to the thickness (d2) is understood not only as the same value, but also as a value up to twice as large, particularly up to 1.5 times larger. For example, the same value is achieved when the dielectric layer and the second main surface (9C) are perpendicular, whereas larger values ​​are taken at smaller angles, particularly at angles greater than 30° and less than 90°.

[0084] For example, the first dielectric layer (10) can be formed on the second main surface (9C) without kink or curvature. In other words, the first dielectric layer (10) can be positioned to conform to one or more side surfaces (9C).

[0085] Although the second contact means (17) is positioned on the front surface (16B) of the semiconductor component (16), the edge layer (11) enables electrical contact of the second semiconductor region (5) or the semiconductor component (16) on the rear surface (16A) of the semiconductor component. Since the first contact means (12) is also positioned on the rear surface (16A), consequently, the optoelectronic semiconductor component (16) can be electrically connected from the outside by the first contact means (12) and the edge layer (11) on the side of the first main surface (9B) or on its own rear surface (16A). This is because the first main surface (9B) is partially covered by the edge layer (11), and the edge layer (11) is used as a second conductive type contact pad.

[0086] A flip chip is considered as the optoelectronic semiconductor component (16) illustrated in FIG. 11b. In this case, means (11, 12) for electrical contact of the first and second semiconductor regions (4, 5) are placed outside the layer stack (9), so that, consequently, no area is “consumed” for contact, and thus area efficiency can be improved compared to conventional flip chips. Furthermore, the semiconductor component (16) is scalable by contact on the outer side.

[0087] FIG. 12 shows one method step or optoelectronic semiconductor component (16) according to a fourth embodiment. Unlike the embodiment illustrated in FIG. 11b, the second main surface (9C) is not formed flat. Rather, the second semiconductor region (5) includes structural elements (19), particularly to increase radiation decoupling. To create the structural elements (19), a recess (8) is formed to a depth that reaches into the interior of the second semiconductor region (5) placed between the contact layer (5A) and the carrier (3) (see FIG. 2 in this regard), so that the region to be structured consequently has sufficient thickness for structuring.

[0088] FIG. 13 shows one method step or optoelectronic semiconductor component (16) according to a fifth embodiment. In this case, the optoelectronic semiconductor component (16) includes a decoupling structure (20) disposed on a second main surface (9C) in particular to increase radiation decoupling.

[0089] The above decoupling structure (20) can be manufactured by structuring a radiation-transmitting layer, for example, composed of a refractive index-modified dielectric material, for example Nb2O5, having a thickness of 0.5 μm to 1.5 μm, onto the second main surface (9C) or the second contact means (17), so that the radiation-transmitting layer comprises a plurality of structural elements (19).

[0090] For example, a filler (13) may be placed in a recess (8) to stabilize the semiconductor wafer (1), and the filler is likewise removed when the semiconductor wafer (1) becomes thin.

[0091] Various possibilities for designing the first contact means (12) and the edge layer (11) on the rear surface are described by FIGS. 14 to 16.

[0092] For example, the first contact means (12) may be positioned centrally on the first main surface and surrounded by edge layers (11) on all sides, wherein the dielectric layer (10) is positioned between them as an electrical insulator (see FIG. 14). In this case, the first contact means (12) may be formed, for example, in a circular shape. In this case, the dielectric layer (10) may have a ring shape.

[0093] Additionally, it is possible for the first contact means (12) to be positioned on the edge side and, accordingly, outside the center, so that it is surrounded only partially by the edge layer (11) on the periphery side (see FIG. 15). In this case, the first contact means (12) may be formed, for example, in an elliptical shape. In this case, the dielectric layer (10) may have a parabolic shape.

[0094] In particular, when manufacturing within the composite material, the first contact means (12) of two adjacent components (16) may be positioned on a side edge (16C) facing each adjacent component (16). Accordingly, preferably, when the first contact means (12) are formed, the electrically conductive layers of the two adjacent components (16) may be opened in a single step. Additionally, the positioning of the contact means (12) on the edge side facilitates the serial connection of the two semiconductor components (16).

[0095] As shown in FIG. 16, the opening in the electrically conductive layer does not need to end at the side edge (16C) of the component (16) as in the embodiment shown in FIG. 15, but rather can extend into the electrically conductive layer of an adjacent component (16), so that, as a result, the edge layer (11) of one component (16) is retracted from the two side edges (16C) facing each other.

[0096] While flip chips are considered as optoelectronic semiconductor components (16) as illustrated in FIG. 11b, FIG. 12, and FIG. 13, in relation to FIG. 17, optoelectronic semiconductor components (16) that can be electrically connected from the outside on two sides facing each other by first and second contact means (12, 17) are described. In this case, the second contact means (17) is used as a second conductive type contact pad.

[0097] The optoelectronic semiconductor component (16) comprises a second dielectric layer (22) disposed on an edge layer (11), and the second dielectric layer electrically insulates the edge layer (11) from the outside on the first main surface (9B) or the back surface (16A), so that, as a result, the edge layer (11) is not exposed on the back surface (16A). Furthermore, the edge layer (11) is electrically insulated from the outside by the second dielectric layer (22) on the side surfaces (9A).

[0098] In such an embodiment (see FIG. 17b), the first contact means (12) covers most of the first main surface (9B) and preferably forms a mirror coating on the rear surface (16A).

[0099] FIG. 18 shows another embodiment in which the optoelectronic semiconductor component (16) includes a second dielectric layer (22) disposed on the edge layer (11) as in FIG. 17, and the second dielectric layer electrically insulates the edge layer (11) from the outside on the first main surface (9B) or the back surface (16A). Furthermore, the edge layer (11) is electrically insulated from the outside by the second dielectric layer (22) on the side surfaces (9A). In such an embodiment, a flip chip is considered as the optoelectronic semiconductor component (16).

[0100] Unlike the embodiment illustrated in FIG. 17, the second dielectric layer (22) includes an opening in which a third contact means (21) for electrical contact with the edge layer (11) is disposed on the rear side (16A). The edge layer (11) and the third contact means (21) are preferably produced in two separate steps and can be formed from different materials accordingly.

[0101] The first contact means (12) and the third contact means (21) are arranged side by side on the first main surface (9B). Accordingly, the optoelectronic semiconductor component (16) can be electrically connected from the outside by the first contact means (12) and the third contact means (21) on the side of the first main surface (9B) or the rear surface (16A).

[0102] The present invention is not limited by the description with reference to the embodiments. Rather, the present invention includes each novel feature and each combination of features, which means that each combination of features is included in the claims, in particular, even if such feature or such combination itself is not explicitly presented in the claims or embodiments.

[0103] This patent application claims priority to German patent application 102020124258.1, and accordingly, the disclosures of said application are incorporated into this application by reference. Explanation of the symbols

[0104] 1 Semiconductor wafer 2 Semiconductor layer sequence 3 Carrier 4 First semiconductor region of the first conductive type 5 Second semiconductor region of the second conductive type 5A Contact layer of the second semiconductor region 6 Active zone 7 Contact layer 8 Recess 8A Bottom surface of the recess 9 Layer stack 9A Side surface 9B First main surface 9C Second main surface 10 First dielectric layer 10A End region 11 Edge layer 11A Electrically conductive layer 11B End region 12 First contact means 13 Filler 14 Intermediate carrier 15 Connecting layer 16 Optoelectronic semiconductor component 16A Rear side 16B Front side 16C Side edge 17 Second contact means 18 Carrier 19 Structural element 20 Decoupling structure 21 Third contact means 22 Second dielectric layer L Side direction V Vertical direction b1, b2 Side length d1, d2 Thickness

Claims

Claim 1 delete Claim 2 delete Claim 3 delete Claim 4 delete Claim 5 delete Claim 6 delete Claim 7 delete Claim 8 delete Claim 9 delete Claim 10 delete Claim 11 delete Claim 12 delete Claim 13 delete Claim 14 delete Claim 15 delete Claim 16 delete Claim 17 A method for manufacturing one or more optoelectronic semiconductor components (16), wherein the one or more optoelectronic semiconductor components comprise: - a layer stack (9) — the layer stack comprises a first semiconductor region (4) of a first conductivity type, a second semiconductor region (5) of a second conductivity type, an active zone (6) disposed between the first semiconductor region (4) and the second semiconductor region (5), one or more side surfaces (9A) that limit the layer stack (9) in a lateral direction, a first main surface (9B), and a second main surface (9C) facing the first main surface (9B), wherein the first and second main surfaces (9B, 9C) are each disposed transversely with respect to the side surface (9A) — a first contact means (12) disposed on the first main surface (9B) provided for electrical contact of the first semiconductor region (4), and the second main surface (9B) provided for electrical contact of the second semiconductor region (5) and being radiation-transmittable A second contact means (17) disposed on a surface (9C), - an electrically conductive edge layer (11) disposed on the layer stack (9) — the electrically conductive edge layer extends from the second contact means (17) through the side surface (9A) to the first main surface (9B) and has an end region (11B) disposed on the second main surface (9C), the end region (11B) having a lateral length (b1) corresponding to the thickness (d1) of the electrically conductive edge layer (11) —, - comprising a first dielectric layer (10) disposed between the edge layer (11) and the layer stack (9), the second main surface (9C) is not covered by the first dielectric layer (10), the optoelectronic semiconductor component (16) does not include plated-through holes, and the second semiconductor region (5) is the second main It includes a high-concentration doping contact layer (5A) formed of a semiconductor material disposed on a surface (9C), andThe second contact means (17) is disposed at least partially directly on the contact layer (5A), and the method comprises: - providing a semiconductor wafer (1) comprising a carrier (3) and a semiconductor layer sequence (2) disposed on the carrier (3) — the semiconductor layer sequence (2) has a first semiconductor region (4) of a first conductive type, a second semiconductor region (5) of a second conductive type, and an active region (6) disposed between the first and second semiconductor regions (4, 5) —, - manufacturing one or more layer stacks (9) by creating one or more recesses (8) in the semiconductor wafer (1) starting from the side of the semiconductor layer sequence (2) facing away from the carrier (3) — the recesses (8) extend to a high-concentration doping contact layer (5A) formed of at least the semiconductor material of the second semiconductor region (5) —, - the layer stack (9) is a first dielectric A method for manufacturing one or more optoelectronic semiconductor components, comprising: providing the first dielectric layer (10) on the semiconductor wafer (1) so as to be covered by the layer (10); providing an electrically conductive layer (11A) provided to form an edge layer (11) on the first dielectric layer (10); exposing the second main surface (9C) of the layer stack (9) — in which regions of the first dielectric layer (10) and regions of the second semiconductor region (5) disposed in the at least one recess are removed up to the contact layer (5A) in the same step — and providing a second radiation-transmitting contact means (17) on the second main surface (9C) for electrical contact of the second semiconductor region (5) — wherein the second contact means (17) is disposed at least partially directly on the contact layer (5A). Claim 18 A method for manufacturing one or more optoelectronic semiconductor components (16), wherein the one or more optoelectronic semiconductor components comprise: - a layer stack (9) — the layer stack comprises a first semiconductor region (4) of a first conductive type, a second semiconductor region (5) of a second conductive type, an active area (6) disposed between the first semiconductor region (4) and the second semiconductor region (5), one or more side surfaces (9A) that limit the layer stack (9) in a lateral direction, a first main surface (9B), and a second main surface (9C) facing the first main surface (9B), wherein the first and second main surfaces (9B, 9C) are each disposed transversely with respect to the side surface (9A) — a first contact means (12) disposed on the first main surface (9B) provided for electrical contact of the first semiconductor region (4), - a second main surface (9C) disposed on the second main surface (9C) provided for electrical contact of the second semiconductor region (5) and being radiation-transparent A second contact means (17), - an electrically conductive edge layer (11) disposed on the layer stack (9) — the electrically conductive edge layer (11) extends from the second contact means (17) across the side surface (9A) to the first main surface (9B) — - comprising a first dielectric layer (10) disposed between the edge layer (11) and the layer stack (9), wherein the second main surface (9C) is not covered by the first dielectric layer (10), and the first dielectric layer (10) terminates coplanarally with the second main surface (9C), and the one or more side surfaces (9A) are at least mostly covered by the edge layer (11), and the second semiconductor region (5) comprises a high-concentration doping contact layer (5A) formed of a semiconductor material disposed on the second main surface (9C), and the second contact means (17) is at least partially on the contact layer (5A). Directly placed, and the above method,- A step of providing a semiconductor wafer (1) comprising a carrier (3) and a semiconductor layer sequence (2) disposed on the carrier (3) — wherein the semiconductor layer sequence (2) has a first semiconductor region (4) of a first conductive type, a second semiconductor region (5) of a second conductive type, and an active region (6) disposed between the first and second semiconductor regions (4, 5) —, - A step of manufacturing one or more layer stacks (9) by creating one or more recesses (8) in the semiconductor wafer (1) starting from the side of the semiconductor layer sequence (2) facing away from the carrier (3) — wherein the recesses (8) extend to a high-concentration doping contact layer (5A) formed of a semiconductor material of at least the second semiconductor region (5) —, - A step of providing the first dielectric layer (10) on the semiconductor wafer (1) such that the layer stack (9) is covered by the first dielectric layer (10). A method for manufacturing one or more optoelectronic semiconductor components, comprising: a step of providing an electrically conductive layer (11A) provided to form an edge layer (11) on the first dielectric layer (10); a step of exposing a second main surface (9C) of the layer stack (9) — in which regions of the first dielectric layer (10) disposed in the at least one recess and regions of the second semiconductor region (5) are removed up to the contact layer (5A) in the same step — and a step of providing a second radiation-transmitting contact means (17) on the second main surface (9C) for electrical contact of the second semiconductor region (5) — wherein the second contact means (17) is disposed at least partially directly on the contact layer (5A). Claim 19 A method for manufacturing one or more optoelectronic semiconductor components, wherein, in claim 17 or 18, a plurality of layer stacks (9) are individualized by the step of exposing the second main surface (9C). Claim 20 A method for manufacturing one or more optoelectronic semiconductor components, wherein, in claim 17 or 18, when the second main surface (9C) is exposed, regions of the edge layer (11) disposed in the at least one recess (8) are removed. Claim 21 A method for manufacturing one or more optoelectronic semiconductor components, wherein, in claim 17 or 18, the exposure of the second main surface (9C) is carried out by polishing and / or etching and / or laser lift-off methods.

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