Ultraviolet light-emitting device and method of manufacturing the same

Abstract

The present invention provides an ultraviolet light-emitting device capable of obtaining a large light output at a center wavelength of light emission greater than 320 nm and less than 350 nm, and a method for manufacturing the same. The light-emitting element (100) comprises, in this order, an n-type semiconductor layer (3) made of AlxGa1-xN having an Al composition ratio x, a quantum well-type light-emitting layer (4), a p-type electron block layer (6) made of AllyGa1-yN having an Al composition ratio y, a p-type clad layer (7) made of AlzGa1-zN having an Al composition ratio z, and a p-type GaN contact layer (8). The p-type electron block layer (6) has an Al composition ratio y of 0.35 or more and 0.45 or less, and its thickness is 11 nm or more and 70 nm or less, the total thickness of the p-type electron block layer (6) and the p-type clad layer (7) is 73 nm or more and 100 nm or less, and the thickness of the p-type GaN contact layer (8) is 5 nm or more and 15 nm or less.

Description

Technology Field

[0001] The present invention relates to an ultraviolet light-emitting element and a method for manufacturing the same. Background Technology

[0002] Light-emitting devices composed mainly of gallium aluminum nitride (AlGaN) can emit light of approximately 250 to 360 nm. Since ultraviolet light-emitting devices with emission center wavelengths of UVC (~280 nm) or UVB (280 to 320 nm) are used for sterilization and the like, the development of deep ultraviolet light-emitting devices in these wavelength ranges is particularly active.

[0003] Patent Document 1 describes a light-emitting element that emits deep ultraviolet light of 240 to 320 nm. In this light-emitting element, the electron block layer is preferably 1 to 10 nm thick, the p-type clad layer is preferably 10 to 100 nm thick, and the p-type contact layer is preferably more than 500 nm thick. It is also described that the flatness of the p-type contact layer can be improved by making the p-type contact layer thicker.

[0004] Patent Document 2 describes a nitride semiconductor ultraviolet light-emitting device. In this light-emitting device, it is described that the output is improved when the surface of the active layer is rough enough to have an average roughness greater than the thickness of the well layer. Additionally, examples are provided in which the electron block layer is 15 to 30 nm, the p-type clad layer is 500 to 600 nm, and the p-type contact layer is 100 to 300 nm.

[0005] Patent Document 3 describes an ultraviolet light-emitting device and a method for manufacturing the same. In this ultraviolet light-emitting device, when the wavelength is shorter than 350 nm, the electronic block layer has a thickness of 1 to 50 nm and has an Al composition of 50% or more. Prior art literature

[0006] Japanese Patent No. 06814902, International Publication No. 2017 / 013729, Japanese Patent Publication No. 2017-050439 The problem to be solved

[0007] As mentioned above, while there are numerous reports of ultraviolet light-emitting devices having emission center wavelengths of UVC (~280 nm) or UVB (280 to 320 nm), there are few reports regarding ultraviolet light-emitting devices of UVA (320 nm~). Ultraviolet light-emitting devices of UVA (320 nm~) are sometimes used for resin curing, medical applications, or analysis. Therefore, it is desired to provide an ultraviolet light-emitting device suitable for UVA. In particular, it is desired to provide an ultraviolet light-emitting device capable of obtaining a large emission output at an emission center wavelength greater than 330 nm and less than 350 nm.

[0008] The present invention has been made in consideration of these facts, and its purpose is to provide an ultraviolet light-emitting device capable of obtaining a large light output at a center wavelength of light emission greater than 320 nm and less than 350 nm, particularly greater than 330 nm and less than 350 nm, and a method for manufacturing the same. means of solving the problem

[0009] The ultraviolet light-emitting element according to the present invention for achieving the above objective is as follows.

[0010] (1) Al having Al composition ratio x x Ga 1-x n-type semiconductor layer composed of N,

[0011] Quantum well-type light-emitting layer,

[0012] Al having Al composition ratio y y Ga 1-y p-type electronic block layer composed of N,

[0013] Al having Al composition ratio z z Ga 1-z A p-type clad layer composed of N, and

[0014] p-type GaN contact layers are provided in this order, and

[0015] The above p-type electronic block layer is,

[0016] The above Al composition ratio y is 0.35 or higher and 0.45 or lower, and

[0017] Its thickness is 11 nm or more and 70 nm or less, and

[0018] The total thickness of the p-type electronic block layer and the p-type clad layer is 73 nm or more and 100 nm or less, and

[0019] The above-mentioned p-type GaN contact layer thickness is 5 nm or more and 15 nm or less, in an ultraviolet light-emitting device.

[0020] (2) The surface of the above p-type GaN contact layer is,

[0021] The maximum surface roughness is 9 nm or less, and

[0022] An ultraviolet light-emitting device described in (1) having an average surface roughness of 1 nm or less.

[0023] (3) The above p-type clad layer is an ultraviolet light-emitting element described in (1) or (2) in which the Al composition ratio z is 0.17 or more and 0.27 or less.

[0024] (4) An ultraviolet light-emitting device described in any one of (1) to (3) in which the value obtained by dividing the thickness of the p-type clad layer by the thickness of the p-type electronic block layer is 0.4 or greater.

[0025] (5) The surface of the n-type semiconductor layer is an ultraviolet light-emitting device described in any one of (1) to (4) having an average surface roughness of 1 nm or less.

[0026] (6) An ultraviolet light-emitting device described in any one of (1) to (5) having a half-width of X-ray diffraction of the (10-12) plane of the n-type semiconductor layer of 350 seconds or less.

[0027] (7) The n-type semiconductor layer above is,

[0028] The above Al composition ratio x is 0.2 or higher and 0.35 or lower, and

[0029] An ultraviolet light-emitting device described in any one of (1) to (6), wherein the Al composition ratio z of the p-type clad layer is less than or equal to the Al composition ratio x of the n-type semiconductor layer.

[0030] (8) Further equipped with a reflective electrode,

[0031] The above-mentioned reflective electrode is an ultraviolet light-emitting element described in any one of (1) to (7) which is disposed on a side opposite to the side facing the p-type clad layer in the above-mentioned p-type GaN contact layer.

[0032] (9) An ultraviolet light-emitting device described in any one of (1) to (8) having a central wavelength of light emission of 331 nm or more and 349 nm or less.

[0033] In addition, the method for manufacturing an ultraviolet light-emitting element according to the present invention to achieve the above objective is as follows.

[0034] (10) Al having Al composition ratio x x Ga 1-x n-type semiconductor layer formation process for forming an n-type semiconductor layer composed of N,

[0035] Light-emitting layer formation process for forming a quantum well-type light-emitting layer,

[0036] Al having Al composition ratio y y Ga 1-y p-type electronic block layer formation process for forming a p-type electronic block layer composed of N,

[0037] Al having Al composition ratio z z Ga 1-z A p-type clad layer formation process for forming a p-type clad layer composed of N, and

[0038] The method includes a process for forming a p-type GaN contact layer, and

[0039] The above n-type semiconductor layer formation process, the above light-emitting layer formation process, the above p-type electronic block layer formation process, the above p-type clad layer formation process, and the above p-type GaN contact layer formation process are performed in this order, and

[0040] The above p-type electronic block layer formation process is,

[0041] The above Al composition ratio y is set to 0.35 or higher and 0.45 or lower, and

[0042] The thickness of the above p-type electronic block layer is 11 nm or more and 70 nm or less, and

[0043] The above p-type electronic block layer formation process and p-type clad layer formation process make the total thickness of the p-type electronic block layer and the p-type clad layer 73 nm or more and 100 nm or less, and

[0044] The above p-type GaN contact layer formation process is a method for manufacturing an ultraviolet light-emitting device in which the thickness of the p-type GaN contact layer is 5 nm or more and 15 nm or less.

[0045] (11) The above p-type GaN contact layer formation process is,

[0046] The maximum surface roughness of the surface of the above p-type GaN contact layer is 9 nm or less, and

[0047] A method for manufacturing an ultraviolet light-emitting device as described in (10), wherein the average surface roughness of the surface of the p-type GaN contact layer is 1 nm or less.

[0048] (12) A method for manufacturing an ultraviolet light-emitting device as described in (9) or (10), further comprising a p-side electrode forming process for forming a p-side electrode on the p-type GaN contact layer. Effects of the invention

[0049] It is possible to provide an ultraviolet light-emitting device capable of obtaining a large light output at a center wavelength of light emission greater than 320 nm and less than 350 nm, particularly greater than 330 nm and less than 350 nm, and a method for manufacturing the same. Brief explanation of the drawing

[0050] FIG. 1 is a diagram showing the layer structure of an ultraviolet light-emitting element according to the present embodiment. Figure 2 is a diagram illustrating the process of forming a substrate of an ultraviolet light-emitting device. Figure 3 is a diagram illustrating the process of forming the layer structure of an ultraviolet light-emitting device. Figure 4 is a diagram illustrating a process of exposing a portion of an n-type semiconductor layer by etching. Figure 5 is a diagram showing the thicknesses of each example and comparative example, with the vertical axis representing the thickness of the p-type clad layer and the horizontal axis representing the thickness of the p-type electron block layer. Specific details for implementing the invention

[0051] First, the circumstances of the development of the ultraviolet light-emitting device according to the embodiment of the present invention will be explained. Within the scope of prior art knowledge, it is thought that increasing the thickness of the light-transmitting electron block layer or clad layer increases light extraction and thus improves output. However, the inventors discovered that when the Al composition ratio and thickness of the p-type electron block layer are set within a specific range, and the combination of the thicknesses of the p-type electron block layer and the p-type clad layer is also set within a specific range, the output of the ultraviolet light-emitting device is improved, contrary to expectations based on prior art knowledge. Furthermore, by setting the thickness of these p-type layers within the aforementioned specific range, thickness control becomes easier, non-uniformity between lots is reduced, and the light emission output within the wafer plane becomes more stable and the yield is improved compared to using thicker p-type layers. In addition, it was discovered that when the Al composition ratio and thickness of the p-type electron block layer are set within a specific range, and the combination of the thicknesses of the p-type electron block layer and the p-type clad layer is also set within a specific range, the flatness of the surface of the p-type contact layer forming the electrode can be secured even if the thickness of the p-type contact layer is thin.

[0052] Hereinafter, based on the drawings, an ultraviolet light-emitting element according to an embodiment of the present invention and a method for manufacturing the same will be described.

[0053] FIG. 1 shows an ultraviolet light-emitting element (100) according to the present embodiment (hereinafter referred to as the light-emitting element (100)). The light-emitting element (100) has an AlN layer (11), a buffer layer (2), and an Al composition ratio x on a substrate (1). x Ga 1-x An n-type semiconductor layer (3) made of N, an n-type guide layer (31), a quantum well-type light-emitting layer (4) (hereinafter referred to as the light-emitting layer (4)), an i-type guide layer (5), and Al having an Al composition ratio y. y Ga 1-y p-type electron block layer (6) made of N, Al having an Al composition ratio z z Ga 1-z A p-type clad layer (7) made of N and a p-type GaN contact layer (8) (hereinafter referred to as the contact layer (8)) are provided in this order. Also, for convenience of explanation, the thickness of each layer in the drawing of the light-emitting element (100) shown in FIG. 1 is displayed by changing the ratio of the thicknesses between each layer so that it is easy to see in the drawing. The ratio of the thicknesses of each layer in the drawing shown in FIG. 1 is different from the actual ratio of the thicknesses of each layer in the light-emitting element (100).

[0054] And, the light-emitting element (100) has a p-side electrode (91) (as a reflective electrode) on a side opposite to the side facing the p-type clad layer (7) in the contact layer (8), and has an n-side electrode (92) on the same side as the light-emitting layer (4) in the n-type semiconductor layer (3).

[0055] In this light-emitting element (100), a large light output can be obtained at a light emission center wavelength greater than 320 nm and less than 350 nm. The light emission center wavelength suitable for the light-emitting element (100) is 331 nm or more and 349 nm or less.

[0056] This light-emitting element (100) can be manufactured, for example, by the following manufacturing method. That is, an example of a manufacturing method for the light-emitting element (100) includes an n-type semiconductor layer forming process for forming an n-type semiconductor layer (3), a light-emitting layer forming process for forming a light-emitting layer (4), a p-type electronic block layer forming process for forming a p-type electronic block layer (6), a p-type clad layer forming process for forming a p-type clad layer (7), and a p-type GaN contact layer forming process for forming a contact layer (8).

[0057] In the method for manufacturing the above-mentioned light-emitting element (100), the n-type semiconductor layer formation process, the light-emitting layer formation process, the p-type electronic block layer formation process, the p-type clad layer formation process, and the p-type GaN contact layer formation process are performed in this order.

[0058] The p-type electronic block layer formation process sets the Al composition ratio y to 0.35 or higher and 0.45 or lower, and the thickness of the p-type electronic block layer (6) to 11 nm or higher and 70 nm or lower, the p-type electronic block layer formation process and the p-type clad layer formation process set the total thickness of the p-type electronic block layer (6) and the p-type clad layer (7) to 73 nm or higher and 100 nm or lower, and the p-type GaN contact layer formation process sets the thickness of the contact layer (8) to 5 nm or higher and 15 nm or lower.

[0059] Below, details of the light-emitting element (100) and the method of manufacturing the same are described.

[0060] Layer Thickness

[0061] In this embodiment, the thickness of each layer of the light-emitting element (100) is measured based on an image taken with a TEM-EDS (transmission electron microscope). That is, the thickness of each layer is determined by using the average value of the thickness of each layer in an image taken of a cross-section of the light-emitting element (100). Also, the thickness of the substrate (1) is determined by using a value measured by an SEM (scanning electron microscope).

[0062] <Al 조성비의 측정>

[0063] In this embodiment, "AlGaN" is Al when the Al composition ratio is α. α Ga 1-α It means that it is N. The value of the Al composition ratio α of the AlGaN in this embodiment is determined from the wavelength observed by photoluminescence measurements performed on the surface of each layer when each layer is grown. Unless otherwise specified, the Al composition ratio α is within the range of 0 to 1. As a method for determining the Al composition from the cross-section of the light-emitting element (100), for example, EDS (Energy Dispersive X-ray Spectroscopy) can be used.

[0064] In addition, when "GaN" or "AlN" is indicated in this embodiment, it means that the composition ratio of Ga and Al is 1.0, respectively. "GaN", "AlN", and "AlGaN" are allowed to contain trace amounts of other unlisted Group III elements, including indium, with a composition ratio of 0.04 or less (4% or less in mole fraction).

[0065] Measurement of Surface Roughness

[0066] The surface roughness value in this embodiment is obtained by performing AFM (Atomic Force Microscope) measurements on a rectangular shape range of 5 μm × 5 μm. The average arithmetic roughness (Ra) and maximum surface roughness (Rmax) are obtained in accordance with the specifications of JIS (B0601-2001) based on the surface profile obtained by AFM measurement. The average arithmetic roughness (Ra) and maximum surface roughness (Rmax) may also be obtained by automatically calculating them using application software attached to the AFM device.

[0067] Measurement of Crystallinity

[0068] In this embodiment, the crystallinity is evaluated based on the arcsec value of the X-ray rocking curve obtained by an X-ray diffraction device. The arcsec value may be obtained by automatically calculating it using application software attached to the X-ray diffraction device. In this embodiment, X-rays are irradiated onto each of the (0001) plane and the (10-12) plane of the subject to evaluation, and the diffraction profiles are evaluated. In particular, the measurement results from the (10-12) plane serve as an indicator of the penetration dislocation density (mixed dislocations on spirals and blades) within the crystal.

[0069] <Measurement of Dopant Concentration>

[0070] The dopant concentration in the present invention utilizes values ​​measured by SIMS (Secondary Ion Mass Spectrometry). Furthermore, "undoped" refers to intentionally not supplying source gases for specific dopants, such as Mg or Si, during MOCVD growth, and may include unavoidable impurities such as C, H, and O from the manufacturing process. Additionally, "Type i" in the present invention refers to the undoped form, having a carrier density of 4 × 10⁻⁶ 16 cm -3 It refers to the following.

[0071] The substrate (1) may be a known substrate capable of epitaxially growing a group III nitride. For example, a sapphire substrate, an AlN substrate, a GaN substrate, a SiC substrate, etc. In this embodiment, the case where the substrate (1) is a sapphire substrate is described below as an example.

[0072] When using a sapphire substrate as the substrate (1), as shown in FIG. 2, it is more preferable to use an AlN template substrate in which an AlN layer (11) is formed on the substrate (1) and the AlN layer (11) is heat-treated at a high temperature to lower the half-width of the X-ray rocking curve of the (10-12) plane of the AlN layer (11) to 400 seconds or less. Hereinafter, the substrate (1) having an AlN layer (11) formed on it is referred to as an AlN template substrate.

[0073] Buffer layer

[0074] Next, as shown in FIGS. 1 and 3, a buffer layer (2) is formed on an AlN template substrate. The buffer layer (2) is located between the AlN layer (11) and the n-type semiconductor layer (3) on the substrate (1), and is a layer that alleviates the lattice constant difference between the substrate (1), the AlN layer (11), and the n-type semiconductor layer (3). It is preferable that the buffer layer (2) be composed of a layer formed by stacking multiple AlGaN layers with different Al compositions, or by an Al composition gradient layer. Additionally, it is preferable that the buffer layer (2) be undoped. The thickness of the buffer layer (2) is, for example, 500 nm or more and 2000 nm or less.

[0075] In FIGS. 1 and 3, the buffer layer (2) is shown as a layer formed by stacking a first buffer layer (21) and a second buffer layer (22), each of which is an AlGaN layer with a different Al composition.

[0076] <n형 반도체층>

[0077] The n-type semiconductor layer (3) is an Al having an Al composition ratio x. x Ga 1-x It is a layer that functions as an n-type semiconductor by containing n-type dopants such as Si in N. The concentration of the n-type dopant is 1 × 10⁻⁶ 18 cm -3 Up to 5 × 10 19 cm -3It is desirable that the n-type semiconductor layer (3) is formed on the side opposite to the side facing the AlN template substrate in the buffer layer (2) after the buffer layer (2) is formed (an example of the n-type semiconductor layer formation process).

[0078] It is preferable that the average surface roughness (Ra) of the surface of the n-type semiconductor layer (3) in the 5㎛ angle range be 1 nm or less. Since the surface of the n-type semiconductor layer (3) is flat, the layer grown thereon can also maintain flatness.

[0079] In addition, it is preferable that the half-width in the X-ray diffraction of the (10-12) plane of the n-type semiconductor layer (3) is 350 seconds or less, and more preferable that it is 300 seconds or less. It is preferable that the Al composition ratio x of the n-type semiconductor layer (3) is 0.2 or more and 0.35 or less. The Al composition ratio x is greater than the Al composition ratio w of the well layer (41) described later, so w < x.

[0080] The thickness of the n-type semiconductor layer (3) should be sufficient to supply carriers, and for example, it is preferably 300 nm or more and 3000 nm or less.

[0081] As described below, an n-side electrode (92) is formed on a portion of the exposed n-type semiconductor layer (3). As a variation, an AlGaN layer with an Al composition of 0 or more and 0.2 or less may be provided between the n-type semiconductor layer (3) and the n-side electrode (92), where the Al composition is lower than that of the n-type semiconductor layer (3).

[0082] On the n-type semiconductor layer (3), an n-type guide layer (31) thinner than the n-type semiconductor layer (3) may be formed as a layer that functions as an n-type semiconductor by containing an n-type dopant such as Si in AlGaN having the same Al composition ratio as the n-type semiconductor layer (3).

[0083] <Luminous layer>

[0084] The light-emitting layer (4) is a layer comprising a layer made of AlGaN. The light-emitting layer (4) has a plurality of well layers (41) and a plurality of barrier layers (42) (barrier layers), and is a layer in which these are alternately stacked. That is, the light-emitting layer (4) has a well layer (41) having an Al composition ratio according to the center wavelength of light emission, and a barrier layer (42) placed between the well layers (41, 41), and has a configuration in which the combination of the well layer (41) and the barrier layer (42) is repeated one or more times. Both sides of the light-emitting layer (4) are barrier layers (42). The light-emitting layer (4) is formed on the side opposite to the side facing the AlN template substrate in the n-type semiconductor layer (3) after the n-type semiconductor layer (3) is formed (an example of a light-emitting layer formation process).

[0085] The well layer (41) of the present embodiment is an Al having an Al composition ratio w. w Ga 1-w It is a layer made of N. For example, when the center wavelength of emission is greater than 320 nm, it is preferable that the Al composition ratio w be < 0.3. Also, when the center wavelength of emission is 331 nm or more, it is preferable that w be ≤ 0.15. Also, when the center wavelength of emission is 349 nm or less, it is preferable that 0.07 be ≤ w. The thickness of the well layer (41) is preferably 1 nm or more and 5 nm or less. The well layer (41) is preferably undoped.

[0086] The barrier layer (42) is an Al having an Al composition ratio b. b Ga 1-b It is a layer made of N. It is preferable that the Al composition ratio b of the barrier layer (42) be within the range of w + 0.05 ≤ b ≤ w + 0.3. It is preferable that the thickness of the barrier layer (42) be 3 nm or more and 20 nm or less. The barrier layer (42) may be n-type, containing an n-type dopant such as undope or Si.

[0087] <i형 가이드층>

[0088] The i-type guide layer (5) is an i-type layer having a higher Al composition ratio than the barrier layer (42) and a thickness of 0.7 nm or more and 1.3 nm or less. The Al composition ratio of the i-type guide layer (5) is preferably higher than the Al composition ratio y of the p-type electron block layer (6) described later, and most preferably is AlN. The i-type guide layer (5) is formed on the side opposite to the side facing the AlN template substrate in the light-emitting layer (4) after the light-emitting layer (4) is formed (an example of a light-emitting layer formation process).

[0089] There are two types of methods for manufacturing the i-type guide layer (5). One is a method of directly forming the i-type guide layer (5) having the above thickness and Al composition. The other is a method of forming an AlGaN layer having a thickness greater than the above thickness, and then, in the process of changing the carrier gas from nitrogen to hydrogen, the Ga in the AlGaN layer volatilizes due to the decrease in nitrogen partial pressure, thereby increasing the Al composition and consequently forming the i-type guide layer (5) having the above thickness and Al composition. In this embodiment, either method may be adopted.

[0090] <p형 전자 블록층>

[0091] The p-type electron block layer (6) is an Al having an Al composition ratio y. y Ga 1-y It is a layer that functions as a p-type semiconductor made of N. The p-type dopant (p-type impurity) doped into the p-type electron block layer (6) is, for example, Mg. The concentration of the p-type dopant is 1 × 10⁻⁶ 18 cm -3 Up to 5 × 10 19 cm -3 It is sufficient to be of this extent. The p-type electronic block layer (6) is formed on the side opposite to the side facing the AlN template substrate in the i-type guide layer (5) after the i-type guide layer (5) is formed.

[0092] The Al composition ratio y is 0.35 or higher and 0.45 or lower. The p-type electron block layer (6) has a thickness of 11 nm or higher and 70 nm or lower. By having such an Al composition ratio y and thickness, the p-type electron block layer (6) suppresses the deterioration of its surface roughness and acts as an electron block layer to realize an improvement in light emission output. For an improvement in light emission output, it is more preferable to make it 60 nm or lower.

[0093] If the Al composition ratio y exceeds 0.45 or the thickness of the p-type electron block layer (6) exceeds 70 nm, there is a risk that the surface roughness (especially the maximum surface roughness) of the p-type electron block layer (6) and the contact layer (8) will increase significantly. If the Al composition ratio y is less than 0.35 or the thickness of the p-type electron block layer (6) is 10 nm or less or more than 70 nm, there is a risk that reliability will deteriorate or the light emission output will decrease.

[0094] The p-type electron block layer (6) may be composed of a single layer or multiple layers. When the p-type electron block layer (6) is composed of multiple layers, it may have layers with different Al compositions, layers with different dopant concentrations, a Si dope layer, or a joint dope layer of Si and Mg.

[0095] <p형 클래드층>

[0096] The p-type clad layer (7) is an Al having an Al composition ratio z. z Ga 1-z It is a layer that functions as a p-type semiconductor composed of N. It is preferable that the Al composition ratio z be 0.17 or higher and 0.27 or lower. The p-type dopant doped into the p-type clad layer (7) is, for example, Mg. The concentration of the p-type dopant is 1 × 10⁻⁶ 18 cm -3 Up to 5 × 10 19 cm -3It is sufficient to have this amount. The p-type clad layer (7) is formed on the side opposite to the side facing the AlN template substrate in the p-type electron block layer (6) after the p-type electron block layer (6) is formed (an example of a p-type clad layer formation process).

[0097] Regarding the relationship between the Al composition ratio z of the p-type clad layer (7) and the Al composition ratio of another layer, the Al composition ratio z of the p-type clad layer (7) is less than the Al composition ratio y of the p-type electron block layer (6) (z < y). It is preferable that the Al composition ratio z of the p-type clad layer (7) be 0.48 times or more and 0.60 times or less the Al composition ratio y of the p-type electron block layer (6). Hereinafter, the ratio of the Al composition ratio z of the p-type clad layer (7) to the Al composition ratio y of the p-type electron block layer (6) may be referred to as the Al ratio. Furthermore, it is also preferable that the Al composition ratio z is less than or equal to the Al composition ratio x of the n-type semiconductor layer (3) (z ≤ x). The Al composition ratio z is greater than the Al composition ratio w of the well layer (41) described above (w < z).

[0098] It is preferable to adjust the thickness of the p-type clad layer (7) according to the thickness of the p-type electronic block layer (6) as follows.

[0099] In determining the thickness of the p-type clad layer (7), the total thickness of the p-type electronic block layer (6) and the p-type clad layer (7) is 73 nm or more and 100 nm or less. By keeping it within this range, light emission output and flatness can be achieved. For improved light emission output, it is more preferable to make the total thickness of the p-type electronic block layer (6) and the p-type clad layer (7) 79 nm or more.

[0100] In addition, when the thickness of the electronic block layer is 60 nm or less, since the total thickness tends to be thicker when the thickness of the electronic block layer is constant, the range in which the output enhancement effect becomes significant is such that the thickness of the electronic block layer is 11 nm or more and 60 nm or less, and also it is more preferable to make the total thickness of the p-type electronic block layer (6) and the p-type clad layer (7) 79 nm or more and less than 100 nm.

[0101] The value obtained by dividing the thickness of the p-type clad layer (7) by the thickness of the p-type electronic block layer (6) (hereinafter referred to as the layer thickness ratio) should be at least 0.1. In order to suppress the maximum surface roughness (Rmax) of the contact layer (8), the layer thickness ratio is preferably 0.4 or higher, and more preferably 0.55 or higher. The upper limit of the layer thickness ratio can be 6.0 or lower. If the layer thickness ratio is less than 0.4, the surface flatness of the p-type clad layer (7) deteriorates, and the Rmax of the contact layer (8) tends to increase.

[0102] <Contact Layer>

[0103] The contact layer (8) is a layer that functions as a p-type semiconductor, made of GaN. The p-type dopant doped into the contact layer (8) is, for example, Mg. The concentration of the p-type dopant is 1 × 10⁻⁶ 19 cm -3 Up to 5 × 10 21 cm -3 It is sufficient to have this much. The contact layer (8) is formed on the side opposite to the side facing the AlN template substrate in the p-type clad layer (7) after the p-type clad layer (7) is formed (an example of a p-type GaN contact layer formation process).

[0104] The thickness of the contact layer (8) is 5 nm or more and 15 nm or less. More preferably, the thickness of the contact layer (8) is 5 nm or more and 10 nm or less. By making the p-type electron block layer (6) and the p-type clad layer (7) as described above, the surface of the contact layer (8) can be made flat even if the contact layer (8) is made such a thin layer.

[0105] The maximum surface roughness (Rmax) of a rectangular shape of 5㎛ × 5㎛ on the surface of the contact layer (8) is 9 nm or less, preferably 8 nm or less, and more preferably less than 6.5 nm. By setting the range of the Al composition ratio of the p-type electron block layer (6) to 0.35 or more and 0.45 or less, and also setting the above layer thickness ratio to 0.4 or more, the maximum surface roughness on the surface of the contact layer (8) can be 8 nm or less. Furthermore, by setting the range of the Al composition ratio of the p-type electron block layer (6) to 0.35 or more and 0.45 or less, and also setting the above layer thickness ratio to 0.55 or more, the maximum surface roughness on the surface of the contact layer (8) can be less than 6.5 nm. If the maximum surface roughness (Rmax) is large, the reliability of the p-side electrode (91) may be compromised when the p-side electrode (91) is formed on the surface having the maximum surface roughness. Accordingly, when current is applied to the light-emitting element (100), the p-side electrode (91) is destroyed, and the light-emitting element (100) suddenly stops emitting light.

[0106] The average surface roughness (Ra) of a rectangular shape of 5㎛ × 5㎛ on the surface of the contact layer (8) is preferably 1 nm or less, and more preferably 0.01 or more and 0.6 nm or less.

[0107] The contact layer (8) may be composed of a single layer or multiple layers. In the case of being composed of multiple layers, it may have layers with different Al compositions, layers with different dopant concentrations, a Si dope layer, or a joint dope layer of Si and Mg. On the outermost surface of the side forming the p-side electrode (91) of the contact layer (8), the concentration of a p-type dopant is 1 × 10 20 cm -3 ~ 5 × 10 21 cm -3 It is also desirable to have a high range.

[0108] When the light-emitting element (100) is a Philip chip type element, as shown in FIG. 4, a portion of the n-type guide layer (31) located above the n-type semiconductor layer (3) and the portion from the light-emitting layer (4) to the contact layer (8) is removed by a dry etching method to expose a portion of the n-type semiconductor layer (3), and then, as shown in FIG. 1, an n-side electrode (92) is formed on a portion of the exposed n-type semiconductor layer (3) (in this embodiment, on the same side as the light-emitting layer (4)). In addition, a p-side electrode (91) is formed on a portion of the contact layer (8) (on the side opposite to the side facing the AlN template substrate in the contact layer (8)) (an example of a p-side electrode formation process). In addition, as a variation, after exposing a part of the n-type semiconductor layer (3), a layer made of AlGaN having an Al composition ratio lower than that of the n-type semiconductor layer (3) and an Al composition ratio of 0 or more and 0.2 or less may be formed on the exposed n-type semiconductor layer (3), and an n-side electrode (92) may be formed thereon.

[0109] As for the p-side electrode (91), a known electrode that can be used in the contact layer (8) may be selected. It is preferable that the p-side electrode (91) be a reflective electrode having a reflectance of 50% or more of the center wavelength of light emission. For example, as the p-side electrode (91), a combination of a first metal (Ni) and a second metal (Au, Rh) or a conductive metal nitride may be used. When the p-side electrode (91) is a reflective electrode, it is preferable to include Rh in the p-side electrode (91).

[0110] As for the n-side electrode (92), a known electrode that can be used in the contact layer (8) may be selected. For example, as the n-side electrode (92), a combination of the first metal (Ti) and the second metal (Al, Rh) or a conductive metal nitride may be used.

[0111] In the process of reorganizing the wafer into individual light-emitting element (100) chips, it is preferable to remove each layer on the substrate at the separation location using dry etching or the like. At that time, a mesa (slanted portion) may be formed on the side of each layer. The chip size of the light-emitting element (100) can be square, rectangular, or hexagonal with a side length of 200 μm to 2000 μm. Scribing or laser dicing may be used for the reorganization of the substrate. The thickness of the substrate may be adjusted by grinding or the like before reorganization.

[0112] As another embodiment of the light-emitting element (100), it may be a vertical element. It may be made into a vertical element by using a conductive substrate as a substrate for epitaxial growth or by removing the substrate used during epitaxial growth. In the case of removing the substrate used during epitaxial growth, a p-side electrode (91) is formed on the contact layer (8), and a conductive support having a thickness sufficient to be handled as a light-emitting element (100) is formed thereon, and then the growth substrate (sapphire substrate) is removed according to a known method to form an n-side electrode (92) on a part of the exposed n-type semiconductor layer (3).

[0113] MOCVD may be employed as the method for epitaxial growth of each layer. For the epitaxial growth of each layer, it is preferable to use a source gas consisting of trimethylaluminum gas (TMA gas), trimethylgallium gas (TMG gas), and ammonia gas (NH3 gas). As for the growth temperature for epitaxial growth, it is preferable to be between 1000°C and 1400°C, although this varies depending on the Al composition ratio. In addition, the growth pressure inside the chamber where epitaxial growth is performed can be, for example, 10 Torr to 760 Torr. Furthermore, since there exists an optimal molar ratio of Group V elements to Group III elements (V / III ratio) depending on the growth temperature and growth pressure, it is desirable to appropriately set the flow rate of the source gas.

[0114] Hereinafter, a light-emitting element (100) according to the present embodiment will be described by way of an example.

[0115] (Example 1)

[0116] A sapphire substrate (diameter 2 inches, thickness 430 μm, plane orientation (0001), m-axis direction off-angle θ: 0.5 degrees) was prepared, and an AlN layer with a center film thickness of 600 nm was grown on the sapphire substrate by the MOCVD method. Then, an AlN template substrate was obtained by heating at 1650°C for 4 hours in a nitrogen gas atmosphere using a heat treatment furnace.

[0117] The half-width of the X-ray rocking curve of (10-12) by X-ray diffraction device (D8 DISCOVER AUTOWAFS; manufactured by Bruker AXS, CuKα1 line) of the AlN layer of the AlN template substrate was 288 seconds and less than 300 seconds.

[0118] Using an AFM (atomic force microscope), the surface roughness of the AlN template substrate was measured in a rectangular area of ​​5 µm × 5 µm with respect to the center of the wafer, and the average surface roughness (Ra) was 0.23 nm and the maximum surface roughness (Rmax) was 3 nm.

[0119] After obtaining an AlN template substrate, undoped Al is applied on the AlN template substrate by the MOCVD method. 0.4 Ga 0.6 A first buffer layer with a thickness of 30 nm made of N is formed, and next, Al of the undoped is formed. 0.25 Ga 0.75 A second buffer layer with a thickness of 1000 nm made of N was formed.

[0120] Next, a Si-doped n-type semiconductor layer with a thickness of 2400 nm was formed on the second buffer layer. Also, when the n-type semiconductor layer was removed from the MOCVD furnace at this point, the crystallinity of the layer was measured by X-ray diffraction in the same manner as above, and the half-width of the X-ray rocking curve of the (10-12) plane was 270 seconds and 300 seconds or less.

[0121] Using an AFM, the surface roughness of the n-type semiconductor layer was measured within a rectangular area of ​​5 µm × 5 µm relative to the center of the wafer; the average surface roughness (Ra) was 0.5 nm, and the maximum surface roughness (Rmax) was 7.4 nm. As a result of SIMS analysis, the Si concentration of the n-type semiconductor layer was 1.0 × 10⁻⁶ 19 It was atoms / cm³.

[0122] Subsequently, after changing the growth temperature from 1200℃ to 1100℃, Si-doped Al on the n-type semiconductor layer 0.25 Ga 0.75 After forming an n-type guide layer with a thickness of 25 nm made of N, as a light-emitting layer, Si-doped Al 0.25 Ga 0.75 A 12 nm thick barrier layer composed of N, and Al of the undoped 0.10 Ga 0.90 A quantum well structure was formed by repeating the formation of a well layer with a thickness of 2.4 nm made of N three times.

[0123] After that, on the emissive layer (on the 3rd well layer), Undoff's Al 0.25 Ga 0.75 After forming an i-type guide layer with a thickness of 3 nm made of N, the supply of the Group III source gas is stopped while the supply of the Group V source gas continues, the nitrogen gas used as the carrier gas is stopped and the carrier gas is changed to hydrogen gas, and the supply of the Group III source gas is started 1 minute after the start of the hydrogen gas supply, thereby the Al of the Mg dope 0.4 Ga 0.6 A 54 nm thick p-type electronic block layer composed of N is formed, and Mg-doped Al is formed. 0.22 Ga 0.78A p-type clad layer with a thickness of 29 nm made of N was formed, and a p-type contact layer (p-type GaN contact layer) with a thickness of 8 nm made of Mg-doped GaN was formed. With the change of the carrier gas above, the i-type guide layer was decomposed as the Ga component volatilized, and was transformed into an i-type guide layer with a thickness of 1.0 nm and an Al composition ratio of approximately 1.

[0124] Using an AFM, the surface roughness of the p-type contact layer was measured within a rectangular area of ​​5 µm × 5 µm at the center of the wafer immediately after epitaxial formation; the average surface roughness (Ra) of the p-type contact layer was 0.39 nm, and the maximum surface roughness (Rmax) was 7.4 nm. As a result of SIMS analysis, the Mg concentrations of the p-type electron block layer, p-type clad layer, and p-type contact layer were 1.0 × 10⁻⁶, respectively. 19 atoms / cm³, 5.0 × 10⁻⁶ 19 atoms / cm³, 2.0 × 10⁻⁶ 20 It was atoms / cm³.

[0125] The Al composition ratio, type of dopant, and thickness of each layer of Example 1 are shown in Table 1. The measured thickness values ​​listed in Table 1 are based on measurement results obtained by TEM. The Al composition of each layer is determined from the wavelength observed by photoluminescence measurement.

[0126] [Table 1]

[0127]

[0128] In addition, a mask was formed on the p-type contact layer, and mesa etching was performed by dry etching to expose a portion of the n-type semiconductor layer. After that, the mask on the p-type contact layer was removed.

[0129] Next, a Ni layer with a thickness of 7 nm and a Rh layer with a thickness of 50 nm were formed on the p-type contact layer to serve as the p-side electrode for the reflection electrode.

[0130] In addition, on an exposed portion of the above n-type semiconductor layer, a Ti layer with a thickness of 20 nm and an Al layer with a thickness of 150 nm were formed as n-type electrodes and used as n-type electrodes.

[0131] Sputtering was used for stacking the p-side electrode and the n-type electrode. A lift-off method using a resist was used for forming the electrode patterns of the p-side electrode and the n-type electrode.

[0132] In addition, contact annealing was performed at 550°C for 10 minutes using an infrared lamp annealing device, and then separated into individual rectangular elements with chip sizes of 1000 μm × 1000 μm using a laser scriber to fabricate an ultraviolet light-emitting element according to Example 1 (hereinafter simply referred to as a light-emitting element). The thickness of the sapphire substrate after separation was 430 μm.

[0133] (Examples 2 to 16, Comparative Examples 1 to 6 and Conventional Examples)

[0134] Light-emitting devices according to Examples 2 to 16, Comparative Examples 1 to 6, and the Conventional Example were prepared in the same manner as Example 1, except that the Al composition ratio and the thickness of the p-type electronic block layer and the p-type clad layer in Example 1 were changed as described in Tables 2 and 3.

[0135] Specifically, Example 2 is identical to Example 1 except that the thickness of the p-type clad layer is 35 nm. Example 3 is identical to Example 1 except that the thickness of the p-type clad layer is 41 nm. Example 4 is identical to Example 1 except that the thickness of the p-type block layer is 22 nm and the thickness of the p-type clad layer is 64 nm. Example 5 is identical to Example 1 except that the thickness of the p-type block layer is 38 nm and the thickness of the p-type clad layer is 41 nm. Example 6 is identical to Example 1 except that the thickness of the p-type block layer is 38 nm and the thickness of the p-type clad layer is 35 nm. Example 7 is identical to Example 1 except that the thickness of the p-type block layer is 11 nm and the thickness of the p-type clad layer is 64 nm. Example 8 is identical to Example 1 except that the thickness of the p-type block layer is 54 nm and the thickness of the p-type clad layer is 23 nm. Example 9 is identical to Example 1 except that the thickness of the p-type block layer is 70 nm and the thickness of the p-type clad layer is 29 nm. Example 10 is identical to Example 1 except that the thickness of the p-type block layer is 70 nm and the thickness of the p-type clad layer is 12 nm.

[0136] Example 11 is identical to Example 1 except that the thickness of the p-type block layer is 11 nm and the thickness of the p-type clad layer is 76 nm. Example 12 is identical to Example 1 except that the thickness of the p-type block layer is 11 nm and the thickness of the p-type clad layer is 70 nm. Example 13 is identical to Example 1 except that the thickness of the p-type block layer is 11 nm and the thickness of the p-type clad layer is 89 nm. Example 14 is identical to Example 1 except that the thickness of the p-type block layer is 22 nm and the thickness of the p-type clad layer is 78 nm. Example 15 is identical to Example 1 except that the thickness of the p-type block layer is 38 nm and the thickness of the p-type clad layer is 62 nm. Example 16 is identical to Example 1 except that the thickness of the p-type block layer is 70 nm and the thickness of the p-type clad layer is 3 nm.

[0137] In addition, Comparative Example 1 is identical to Example 1 except that the thickness of the p-type clad layer is 18 nm. Comparative Example 2 is identical to Example 1 except that the thickness of the p-type block layer is 38 nm and the thickness of the p-type clad layer is 29 nm. Comparative Example 3 is identical to Example 1 except that the thickness of the p-type block layer is 86 nm and the thickness of the p-type clad layer is 29 nm. Comparative Example 4 is identical to Example 1 except that the thickness of the p-type block layer is 22 nm and the thickness of the p-type clad layer is 41 nm. Comparative Example 5 is identical to Example 1 except that the thickness of the p-type block layer is 11 nm and the thickness of the p-type clad layer is 53 nm. Comparative Example 6 is identical to Example 1 except that the thickness of the p-type block layer is 5 nm and the thickness of the p-type clad layer is 64 nm. The conventional example is identical to Example 1 except that the thickness of the p-type clad layer is 350 nm.

[0138] Also, in Tables 2 and 3, "BL" and "CL" are abbreviations for the p-type electron block layer and the p-type clad layer, respectively. Also, "Al ratio" is the ratio of the Al composition ratio of the p-type clad layer to the Al composition ratio of the p-type electron block layer. Also, "layer thickness ratio CL / BL" is the value obtained by dividing the thickness of the p-type clad layer by the thickness of the p-type electron block layer. Also, "total thickness BL + CL" is the total thickness of the p-type electron block layer and the p-type clad layer. In addition, the light-emitting devices of the conventional example and comparative example all have the thicknesses of the p-type electron block layer and the p-type clad layer set so that the total thickness of the p-type electron block layer and the p-type clad layer falls outside the range of 73 nm or more and 100 nm or less. In the following description, the light-emitting element constituting a conventional example is merely referred to as a conventional example for the convenience of explanation when the total thickness of the p-type electronic block layer and the p-type clad layer is very thick, and the embodiment according to the present embodiment is positioned as a comparative example.

[0139] [Table 2]

[0140]

[0141] [Table 3]

[0142]

[0143] Each of the light-emitting elements of the example, comparative example, and conventional example was mounted on an AlN submount (size 2 mm × 2 mm, thickness 0.2 mm) using spherical Au bumps in a flip-chip manner. In addition, with an Al heat sink connected to the AlN submount, a current of 350 mA was applied using a constant current power supply, and the forward voltage (Vf) at that time was measured, and the total luminous flux output (Po) was measured using an integrating sphere placed on the sapphire substrate side.

[0144] In particular, regarding the luminescence output (Po), random measurements were performed by sampling five light-emitting elements from the center portion of each wafer of the examples, comparative examples, and conventional examples, and the average value was calculated. The measurement results are shown as the "Po average" in "chip measurement" in Tables 2 and 3. In addition, the measurement results of Examples 1 to 10, Comparative Examples 1 to 5, and the conventional example are shown in Table 2, and the measurement results of Examples 11 to 16 and Comparative Example 6 are shown in Table 3.

[0145] For the center of the wafer immediately after epitaxial formation in Examples 1 to 10, Comparative Examples 1 to 5, and Conventional Examples, the surface roughness (Ra and Rmax) of the surface of the p-type contact layer was measured using an AFM. The results of these measurements are described in the item below "Contact Layer AFM" in Table 2. In addition, for Examples 11 to 16 and Comparative Example 6, surface roughness measurements using an AFM were not performed.

[0146] In addition, the emission center wavelength (λp) of the chips of the example, comparative example, and conventional example was measured by a spectrometer, and the emission center wavelength of any chip was within the range of 340 nm ± 5 nm.

[0147] In addition, the light-emitting devices of each embodiment all have a higher average light-emitting output compared to the light-emitting devices of the conventional and comparative examples. That is, in the case where the thickness of the p-type electron block layer is 11 nm or more and 70 nm or less, as in the present embodiment, and the total thickness of the p-type AlGaN electron block layer and the p-type AlGaN clad layer is 73 nm or more and 100 nm or less, the light-emitting device has a higher light-emitting output compared to the light-emitting device in the case where this is not the case. Figure 5 illustrates the embodiment and the comparative example with the vertical axis representing the thickness of the p-type clad layer and the horizontal axis representing the thickness of the p-type electron block layer. The values ​​in the figure are the values ​​of the average Po (mW). Also, in Comparative Example 6, since the thickness of the p-type electron block layer is thin, the initial light-emitting output is higher than that of Example 7, but the rate of degradation of the light-emitting output due to 500 hours of operation at 600 mA is 80% or less, and the reliability is lower compared to the embodiment, so it is indicated as "deterioration of reliability" in Table 2.

[0148] In this way, according to the present embodiment, it is possible to provide an ultraviolet light-emitting device capable of obtaining a large light output at a center wavelength of light emission greater than 320 nm and less than 350 nm, particularly greater than 330 nm and less than 350 nm.

[0149] In addition, in the comparison between the examples, the average surface roughness (Ra) of the p-type contact layer is preferably 1 nm or less, and more preferably 0.01 or more and 0.6 nm or less. Even more preferably, it is 0.3 or more and 0.6 nm or less. Furthermore, the maximum surface roughness (Rmax) of the p-type contact layer is preferably 8 nm or less.

[0150] In this way, an ultraviolet light-emitting device capable of obtaining a large light output at a center wavelength of light emission greater than 320 nm and less than 350 nm, and a method for manufacturing the same can be provided.

[0151] For the conventional example and Example 1, a chip sorter was used to measure chips manufactured from all light-emitting elements obtained within the wafer (i.e., a full count measurement was performed). This full count measurement was performed on 20 lots. The average and non-uniformity between lots of the full count results performed on these 20 lots were as follows: in the conventional example, the average output was 77.9 mW and the standard deviation was 16.0 mW, whereas in Example 1, the average output was 89.1 mW and the standard deviation was 12.2 mW. It can be seen that the light-emitting element of Example 1, which has a thinner p-type layer thickness compared to the conventional example, has a higher average light-emitting output and a smaller standard deviation value (non-uniformity) between lots.

[0152] Furthermore, the embodiments disclosed in this specification are examples, and the embodiments of the present invention are not limited thereto, and appropriate modifications are possible within the scope that does not deviate from the purpose of the present invention. Industrial applicability

[0153] The present invention can be applied to a light-emitting element and a method for manufacturing the same. Explanation of the symbols

[0154] 1: Substrate 11: AlN layer 100: Light-emitting element (ultraviolet light-emitting element) 2: Buffer layer 21: First buffer layer 22: Second buffer layer 3: n-type semiconductor layer 31: n-type guide layer 4: Emitting layer (quantum well type emitting layer) 41: Well layer 42: Barrier layer 5: I-shaped guide layer 6: p-type electron block layer 7: p-type clad layer 8: p-type contact layer (p-type GaN contact layer) 91: p-side electrode 92: n-side electrode

Claims

Claim 1 Al having Al composition ratio x x Ga 1-x n-type semiconductor layer composed of N, quantum well-type light-emitting layer, Al having Al composition ratio y y Ga 1-y p-type electron block layer composed of N, Al having Al composition ratio z z Ga 1-z A UV light-emitting device comprising a p-type clad layer made of N and a p-type GaN contact layer in that order, wherein the p-type electronic block layer has an Al composition ratio y of 0.35 or more and 0.45 or less and a thickness of 11 nm or more and 70 nm or less, the total thickness of the p-type electronic block layer and the p-type clad layer is 73 nm or more and 100 nm or less, the thickness of the p-type GaN contact layer is 5 nm or more and 15 nm or less, and the p-type clad layer has an Al composition ratio z of 0.17 or more and 0.27 or less. Claim 2 Al having Al composition ratio x x Ga 1-x n-type semiconductor layer composed of N, quantum well-type light-emitting layer, Al having Al composition ratio y y Ga 1-y p-type electron block layer composed of N, Al having Al composition ratio z z Ga 1-z A UV light-emitting device comprising a p-type clad layer made of N and a p-type GaN contact layer in that order, wherein the p-type electronic block layer has an Al composition ratio y of 0.35 or more and 0.45 or less and a thickness of 11 nm or more and 70 nm or less, the total thickness of the p-type electronic block layer and the p-type clad layer is 73 nm or more and 100 nm or less, the thickness of the p-type GaN contact layer is 5 nm or more and 15 nm or less, and the Al composition ratio z of the p-type clad layer is less than or equal to the Al composition ratio x of the n-type semiconductor layer. Claim 3 A UV light-emitting device according to claim 1 or 2, wherein the surface of the p-type GaN contact layer has a maximum surface roughness of 9 nm or less and an average surface roughness of 1 nm or less. Claim 4 An ultraviolet light-emitting device according to claim 1 or 2, wherein the value obtained by dividing the thickness of the p-type clad layer by the thickness of the p-type electronic block layer is 0.4 or greater. Claim 5 A UV light-emitting device according to claim 1 or 2, wherein the surface of the n-type semiconductor layer has an average surface roughness of 1 nm or less. Claim 6 An ultraviolet light-emitting device according to claim 1 or 2, wherein the half-width of the X-ray diffraction of the (10-12) plane of the n-type semiconductor layer is 350 seconds or less. Claim 7 In claim 1 or 2, the n-type semiconductor layer is an ultraviolet light-emitting device in which the Al composition ratio x is 0.2 or more and 0.35 or less. Claim 8 An ultraviolet light-emitting device according to claim 1 or 2, further comprising a reflective electrode, wherein the reflective electrode is disposed on a side opposite to the side facing the p-type clad layer in the p-type GaN contact layer. Claim 9 An ultraviolet light-emitting device according to claim 1 or 2, wherein the center wavelength of the light emission is 331 nm or more and 349 nm or less. Claim 10 Al having Al composition ratio x x Ga 1-x An n-type semiconductor layer formation process for forming an n-type semiconductor layer composed of N, a light-emitting layer formation process for forming a quantum well-type light-emitting layer, and Al having an Al composition ratio y y Ga 1-y A process for forming a p-type electron block layer composed of N, and Al having an Al composition ratio z. z Ga 1-z The method comprises a p-type clad layer formation process for forming a p-type clad layer composed of N, and a p-type GaN contact layer formation process for forming a p-type GaN contact layer, wherein the n-type semiconductor layer formation process, the light-emitting layer formation process, the p-type electronic block layer formation process, the p-type clad layer formation process, and the p-type GaN contact layer formation process are performed in this order, wherein the p-type electronic block layer formation process sets the Al composition ratio y to be 0.35 or more and 0.45 or less, and the thickness of the p-type electronic block layer is 11 nm or more and 70 nm or less, wherein the p-type electronic block layer formation process and the p-type clad layer formation process set the total thickness of the p-type electronic block layer and the p-type clad layer to be 73 nm or more and 100 nm or less, wherein the p-type GaN contact layer formation process sets the thickness of the p-type GaN contact layer to be 5 nm or more and 15 nm or less, and the p-type clad layer is the Al composition ratio A method for manufacturing an ultraviolet light-emitting device in which z is 0.17 or more and 0.27 or less. Claim 11 Al having Al composition ratio x x Ga 1-x An n-type semiconductor layer formation process for forming an n-type semiconductor layer composed of N, a light-emitting layer formation process for forming a quantum well-type light-emitting layer, and Al having an Al composition ratio y y Ga 1-y A process for forming a p-type electron block layer composed of N, and Al having an Al composition ratio z. z Ga 1-z The method comprises a p-type clad layer formation process for forming a p-type clad layer composed of N, and a p-type GaN contact layer formation process for forming a p-type GaN contact layer, wherein the n-type semiconductor layer formation process, the light-emitting layer formation process, the p-type electronic block layer formation process, the p-type clad layer formation process, and the p-type GaN contact layer formation process are performed in this order, wherein the p-type electronic block layer formation process sets the Al composition ratio y to be 0.35 or more and 0.45 or less, and the thickness of the p-type electronic block layer is 11 nm or more and 70 nm or less, wherein the p-type electronic block layer formation process and the p-type clad layer formation process set the total thickness of the p-type electronic block layer and the p-type clad layer to be 73 nm or more and 100 nm or less, wherein the p-type GaN contact layer formation process sets the thickness of the p-type GaN contact layer to be 5 nm or more and 15 nm or less, and the Al composition ratio z of the p-type clad layer A method for manufacturing an ultraviolet light-emitting device in which the Al composition ratio of the n-type semiconductor layer is less than or equal to x. Claim 12 A method for manufacturing an ultraviolet light-emitting device according to claim 10 or 11, wherein the p-type GaN contact layer formation process has a maximum surface roughness of the surface of the p-type GaN contact layer of 9 nm or less and an average surface roughness of the surface of the p-type GaN contact layer of 1 nm or less. Claim 13 A method for manufacturing an ultraviolet light-emitting device, wherein, in claim 10 or 11, a p-side electrode forming process for forming a p-side electrode on the p-type GaN contact layer is further included.

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